2 * Amlogic Meson8b and GXBB DWMAC glue layer
4 * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/device.h>
17 #include <linux/ethtool.h>
19 #include <linux/ioport.h>
20 #include <linux/module.h>
21 #include <linux/of_net.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/platform_device.h>
24 #include <linux/stmmac.h>
26 #include "stmmac_platform.h"
30 #define PRG_ETH0_RGMII_MODE BIT(0)
32 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
33 #define PRG_ETH0_CLK_M250_SEL_SHIFT 4
34 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
36 #define PRG_ETH0_TXDLY_SHIFT 5
37 #define PRG_ETH0_TXDLY_MASK GENMASK(6, 5)
39 /* divider for the result of m250_sel */
40 #define PRG_ETH0_CLK_M250_DIV_SHIFT 7
41 #define PRG_ETH0_CLK_M250_DIV_WIDTH 3
43 /* divides the result of m25_sel by either 5 (bit unset) or 10 (bit set) */
44 #define PRG_ETH0_CLK_M25_DIV_SHIFT 10
45 #define PRG_ETH0_CLK_M25_DIV_WIDTH 1
47 #define PRG_ETH0_INVERTED_RMII_CLK BIT(11)
48 #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12)
50 #define MUX_CLK_NUM_PARENTS 2
52 struct meson8b_dwmac
{
53 struct platform_device
*pdev
;
57 phy_interface_t phy_mode
;
59 struct clk_mux m250_mux
;
60 struct clk
*m250_mux_clk
;
61 struct clk
*m250_mux_parent
[MUX_CLK_NUM_PARENTS
];
63 struct clk_divider m250_div
;
64 struct clk
*m250_div_clk
;
66 struct clk_divider m25_div
;
67 struct clk
*m25_div_clk
;
72 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac
*dwmac
, u32 reg
,
77 data
= readl(dwmac
->regs
+ reg
);
79 data
|= (value
& mask
);
81 writel(data
, dwmac
->regs
+ reg
);
84 static int meson8b_init_clk(struct meson8b_dwmac
*dwmac
)
86 struct clk_init_data init
;
88 struct device
*dev
= &dwmac
->pdev
->dev
;
90 const char *clk_div_parents
[1];
91 const char *mux_parent_names
[MUX_CLK_NUM_PARENTS
];
92 static struct clk_div_table clk_25m_div_table
[] = {
93 { .val
= 0, .div
= 5 },
94 { .val
= 1, .div
= 10 },
98 /* get the mux parents from DT */
99 for (i
= 0; i
< MUX_CLK_NUM_PARENTS
; i
++) {
102 snprintf(name
, sizeof(name
), "clkin%d", i
);
103 dwmac
->m250_mux_parent
[i
] = devm_clk_get(dev
, name
);
104 if (IS_ERR(dwmac
->m250_mux_parent
[i
])) {
105 ret
= PTR_ERR(dwmac
->m250_mux_parent
[i
]);
106 if (ret
!= -EPROBE_DEFER
)
107 dev_err(dev
, "Missing clock %s\n", name
);
111 mux_parent_names
[i
] =
112 __clk_get_name(dwmac
->m250_mux_parent
[i
]);
115 /* create the m250_mux */
116 snprintf(clk_name
, sizeof(clk_name
), "%s#m250_sel", dev_name(dev
));
117 init
.name
= clk_name
;
118 init
.ops
= &clk_mux_ops
;
120 init
.parent_names
= mux_parent_names
;
121 init
.num_parents
= MUX_CLK_NUM_PARENTS
;
123 dwmac
->m250_mux
.reg
= dwmac
->regs
+ PRG_ETH0
;
124 dwmac
->m250_mux
.shift
= PRG_ETH0_CLK_M250_SEL_SHIFT
;
125 dwmac
->m250_mux
.mask
= PRG_ETH0_CLK_M250_SEL_MASK
;
126 dwmac
->m250_mux
.flags
= 0;
127 dwmac
->m250_mux
.table
= NULL
;
128 dwmac
->m250_mux
.hw
.init
= &init
;
130 dwmac
->m250_mux_clk
= devm_clk_register(dev
, &dwmac
->m250_mux
.hw
);
131 if (WARN_ON(IS_ERR(dwmac
->m250_mux_clk
)))
132 return PTR_ERR(dwmac
->m250_mux_clk
);
134 /* create the m250_div */
135 snprintf(clk_name
, sizeof(clk_name
), "%s#m250_div", dev_name(dev
));
136 init
.name
= devm_kstrdup(dev
, clk_name
, GFP_KERNEL
);
137 init
.ops
= &clk_divider_ops
;
138 init
.flags
= CLK_SET_RATE_PARENT
;
139 clk_div_parents
[0] = __clk_get_name(dwmac
->m250_mux_clk
);
140 init
.parent_names
= clk_div_parents
;
141 init
.num_parents
= ARRAY_SIZE(clk_div_parents
);
143 dwmac
->m250_div
.reg
= dwmac
->regs
+ PRG_ETH0
;
144 dwmac
->m250_div
.shift
= PRG_ETH0_CLK_M250_DIV_SHIFT
;
145 dwmac
->m250_div
.width
= PRG_ETH0_CLK_M250_DIV_WIDTH
;
146 dwmac
->m250_div
.hw
.init
= &init
;
147 dwmac
->m250_div
.flags
= CLK_DIVIDER_ONE_BASED
| CLK_DIVIDER_ALLOW_ZERO
;
149 dwmac
->m250_div_clk
= devm_clk_register(dev
, &dwmac
->m250_div
.hw
);
150 if (WARN_ON(IS_ERR(dwmac
->m250_div_clk
)))
151 return PTR_ERR(dwmac
->m250_div_clk
);
153 /* create the m25_div */
154 snprintf(clk_name
, sizeof(clk_name
), "%s#m25_div", dev_name(dev
));
155 init
.name
= devm_kstrdup(dev
, clk_name
, GFP_KERNEL
);
156 init
.ops
= &clk_divider_ops
;
157 init
.flags
= CLK_IS_BASIC
| CLK_SET_RATE_PARENT
;
158 clk_div_parents
[0] = __clk_get_name(dwmac
->m250_div_clk
);
159 init
.parent_names
= clk_div_parents
;
160 init
.num_parents
= ARRAY_SIZE(clk_div_parents
);
162 dwmac
->m25_div
.reg
= dwmac
->regs
+ PRG_ETH0
;
163 dwmac
->m25_div
.shift
= PRG_ETH0_CLK_M25_DIV_SHIFT
;
164 dwmac
->m25_div
.width
= PRG_ETH0_CLK_M25_DIV_WIDTH
;
165 dwmac
->m25_div
.table
= clk_25m_div_table
;
166 dwmac
->m25_div
.hw
.init
= &init
;
167 dwmac
->m25_div
.flags
= CLK_DIVIDER_ALLOW_ZERO
;
169 dwmac
->m25_div_clk
= devm_clk_register(dev
, &dwmac
->m25_div
.hw
);
170 if (WARN_ON(IS_ERR(dwmac
->m25_div_clk
)))
171 return PTR_ERR(dwmac
->m25_div_clk
);
176 static int meson8b_init_prg_eth(struct meson8b_dwmac
*dwmac
)
179 unsigned long clk_rate
;
182 switch (dwmac
->phy_mode
) {
183 case PHY_INTERFACE_MODE_RGMII
:
184 case PHY_INTERFACE_MODE_RGMII_ID
:
185 case PHY_INTERFACE_MODE_RGMII_RXID
:
186 case PHY_INTERFACE_MODE_RGMII_TXID
:
187 /* Generate a 25MHz clock for the PHY */
188 clk_rate
= 25 * 1000 * 1000;
190 /* enable RGMII mode */
191 meson8b_dwmac_mask_bits(dwmac
, PRG_ETH0
, PRG_ETH0_RGMII_MODE
,
192 PRG_ETH0_RGMII_MODE
);
194 /* only relevant for RMII mode -> disable in RGMII mode */
195 meson8b_dwmac_mask_bits(dwmac
, PRG_ETH0
,
196 PRG_ETH0_INVERTED_RMII_CLK
, 0);
198 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where
199 * 8ns are exactly one cycle of the 125MHz RGMII TX clock):
200 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
202 tx_dly_val
= dwmac
->tx_delay_ns
>> 1;
203 meson8b_dwmac_mask_bits(dwmac
, PRG_ETH0
, PRG_ETH0_TXDLY_MASK
,
204 tx_dly_val
<< PRG_ETH0_TXDLY_SHIFT
);
207 case PHY_INTERFACE_MODE_RMII
:
208 /* Use the rate of the mux clock for the internal RMII PHY */
209 clk_rate
= clk_get_rate(dwmac
->m250_mux_clk
);
211 /* disable RGMII mode -> enables RMII mode */
212 meson8b_dwmac_mask_bits(dwmac
, PRG_ETH0
, PRG_ETH0_RGMII_MODE
,
215 /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
216 meson8b_dwmac_mask_bits(dwmac
, PRG_ETH0
,
217 PRG_ETH0_INVERTED_RMII_CLK
,
218 PRG_ETH0_INVERTED_RMII_CLK
);
220 /* TX clock delay cannot be configured in RMII mode */
221 meson8b_dwmac_mask_bits(dwmac
, PRG_ETH0
, PRG_ETH0_TXDLY_MASK
,
227 dev_err(&dwmac
->pdev
->dev
, "unsupported phy-mode %s\n",
228 phy_modes(dwmac
->phy_mode
));
232 ret
= clk_prepare_enable(dwmac
->m25_div_clk
);
234 dev_err(&dwmac
->pdev
->dev
, "failed to enable the PHY clock\n");
238 ret
= clk_set_rate(dwmac
->m25_div_clk
, clk_rate
);
240 clk_disable_unprepare(dwmac
->m25_div_clk
);
242 dev_err(&dwmac
->pdev
->dev
, "failed to set PHY clock\n");
246 /* enable TX_CLK and PHY_REF_CLK generator */
247 meson8b_dwmac_mask_bits(dwmac
, PRG_ETH0
, PRG_ETH0_TX_AND_PHY_REF_CLK
,
248 PRG_ETH0_TX_AND_PHY_REF_CLK
);
253 static int meson8b_dwmac_probe(struct platform_device
*pdev
)
255 struct plat_stmmacenet_data
*plat_dat
;
256 struct stmmac_resources stmmac_res
;
257 struct resource
*res
;
258 struct meson8b_dwmac
*dwmac
;
261 ret
= stmmac_get_platform_resources(pdev
, &stmmac_res
);
265 plat_dat
= stmmac_probe_config_dt(pdev
, &stmmac_res
.mac
);
266 if (IS_ERR(plat_dat
))
267 return PTR_ERR(plat_dat
);
269 dwmac
= devm_kzalloc(&pdev
->dev
, sizeof(*dwmac
), GFP_KERNEL
);
272 goto err_remove_config_dt
;
275 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
276 dwmac
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
277 if (IS_ERR(dwmac
->regs
)) {
278 ret
= PTR_ERR(dwmac
->regs
);
279 goto err_remove_config_dt
;
283 dwmac
->phy_mode
= of_get_phy_mode(pdev
->dev
.of_node
);
284 if (dwmac
->phy_mode
< 0) {
285 dev_err(&pdev
->dev
, "missing phy-mode property\n");
287 goto err_remove_config_dt
;
290 /* use 2ns as fallback since this value was previously hardcoded */
291 if (of_property_read_u32(pdev
->dev
.of_node
, "amlogic,tx-delay-ns",
292 &dwmac
->tx_delay_ns
))
293 dwmac
->tx_delay_ns
= 2;
295 ret
= meson8b_init_clk(dwmac
);
297 goto err_remove_config_dt
;
299 ret
= meson8b_init_prg_eth(dwmac
);
301 goto err_remove_config_dt
;
303 plat_dat
->bsp_priv
= dwmac
;
305 ret
= stmmac_dvr_probe(&pdev
->dev
, plat_dat
, &stmmac_res
);
307 goto err_clk_disable
;
312 clk_disable_unprepare(dwmac
->m25_div_clk
);
313 err_remove_config_dt
:
314 stmmac_remove_config_dt(pdev
, plat_dat
);
319 static int meson8b_dwmac_remove(struct platform_device
*pdev
)
321 struct meson8b_dwmac
*dwmac
= get_stmmac_bsp_priv(&pdev
->dev
);
323 clk_disable_unprepare(dwmac
->m25_div_clk
);
325 return stmmac_pltfr_remove(pdev
);
328 static const struct of_device_id meson8b_dwmac_match
[] = {
329 { .compatible
= "amlogic,meson8b-dwmac" },
330 { .compatible
= "amlogic,meson-gxbb-dwmac" },
333 MODULE_DEVICE_TABLE(of
, meson8b_dwmac_match
);
335 static struct platform_driver meson8b_dwmac_driver
= {
336 .probe
= meson8b_dwmac_probe
,
337 .remove
= meson8b_dwmac_remove
,
339 .name
= "meson8b-dwmac",
340 .pm
= &stmmac_pltfr_pm_ops
,
341 .of_match_table
= meson8b_dwmac_match
,
344 module_platform_driver(meson8b_dwmac_driver
);
346 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
347 MODULE_DESCRIPTION("Amlogic Meson8b and GXBB DWMAC glue layer");
348 MODULE_LICENSE("GPL v2");