drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

   1 /*******************************************************************************
   2   Copyright (C) 2007-2009  STMicroelectronics Ltd
   3
   4   This program is free software; you can redistribute it and/or modify it
   5   under the terms and conditions of the GNU General Public License,
   6   version 2, as published by the Free Software Foundation.
   7
   8   This program is distributed in the hope it will be useful, but WITHOUT
   9   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11   more details.
  12
  13   You should have received a copy of the GNU General Public License along with
  14   this program; if not, write to the Free Software Foundation, Inc.,
  15   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16
  17   The full GNU General Public License is included in this distribution in
  18   the file called "COPYING".
  19
  20   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  21 *******************************************************************************/
  22
  23 #include <linux/phy.h>
  24 #include "common.h"
  25
  26 #define GMAC_CONTROL            0x00000000      /* Configuration */
  27 #define GMAC_FRAME_FILTER       0x00000004      /* Frame Filter */
  28 #define GMAC_HASH_HIGH          0x00000008      /* Multicast Hash Table High */
  29 #define GMAC_HASH_LOW           0x0000000c      /* Multicast Hash Table Low */
  30 #define GMAC_MII_ADDR           0x00000010      /* MII Address */
  31 #define GMAC_MII_DATA           0x00000014      /* MII Data */
  32 #define GMAC_FLOW_CTRL          0x00000018      /* Flow Control */
  33 #define GMAC_VLAN_TAG           0x0000001c      /* VLAN Tag */
  34 #define GMAC_VERSION            0x00000020      /* GMAC CORE Version */
  35 #define GMAC_WAKEUP_FILTER      0x00000028      /* Wake-up Frame Filter */
  36
  37 #define GMAC_INT_STATUS         0x00000038      /* interrupt status register */
  38 enum dwmac1000_irq_status {
  39         time_stamp_irq = 0x0200,
  40         mmc_rx_csum_offload_irq = 0x0080,
  41         mmc_tx_irq = 0x0040,
  42         mmc_rx_irq = 0x0020,
  43         mmc_irq = 0x0010,
  44         pmt_irq = 0x0008,
  45         pcs_ane_irq = 0x0004,
  46         pcs_link_irq = 0x0002,
  47         rgmii_irq = 0x0001,
  48 };
  49 #define GMAC_INT_MASK           0x0000003c      /* interrupt mask register */
  50
  51 /* PMT Control and Status */
  52 #define GMAC_PMT                0x0000002c
  53 enum power_event {
  54         pointer_reset = 0x80000000,
  55         global_unicast = 0x00000200,
  56         wake_up_rx_frame = 0x00000040,
  57         magic_frame = 0x00000020,
  58         wake_up_frame_en = 0x00000004,
  59         magic_pkt_en = 0x00000002,
  60         power_down = 0x00000001,
  61 };
  62
  63 /* GMAC HW ADDR regs */
  64 #define GMAC_ADDR_HIGH(reg)     (((reg > 15) ? 0x00000800 : 0x00000040) + \
  65                                 (reg * 8))
  66 #define GMAC_ADDR_LOW(reg)      (((reg > 15) ? 0x00000804 : 0x00000044) + \
  67                                 (reg * 8))
  68 #define GMAC_MAX_PERFECT_ADDRESSES      32
  69
  70 #define GMAC_AN_CTRL    0x000000c0      /* AN control */
  71 #define GMAC_AN_STATUS  0x000000c4      /* AN status */
  72 #define GMAC_ANE_ADV    0x000000c8      /* Auto-Neg. Advertisement */
  73 #define GMAC_ANE_LINK   0x000000cc      /* Auto-Neg. link partener ability */
  74 #define GMAC_ANE_EXP    0x000000d0      /* ANE expansion */
  75 #define GMAC_TBI        0x000000d4      /* TBI extend status */
  76 #define GMAC_GMII_STATUS 0x000000d8     /* S/R-GMII status */
  77
  78 /* GMAC Configuration defines */
  79 #define GMAC_CONTROL_TC 0x01000000      /* Transmit Conf. in RGMII/SGMII */
  80 #define GMAC_CONTROL_WD 0x00800000      /* Disable Watchdog on receive */
  81 #define GMAC_CONTROL_JD 0x00400000      /* Jabber disable */
  82 #define GMAC_CONTROL_BE 0x00200000      /* Frame Burst Enable */
  83 #define GMAC_CONTROL_JE 0x00100000      /* Jumbo frame */
  84 enum inter_frame_gap {
  85         GMAC_CONTROL_IFG_88 = 0x00040000,
  86         GMAC_CONTROL_IFG_80 = 0x00020000,
  87         GMAC_CONTROL_IFG_40 = 0x000e0000,
  88 };
  89 #define GMAC_CONTROL_DCRS       0x00010000 /* Disable carrier sense during tx */
  90 #define GMAC_CONTROL_PS         0x00008000 /* Port Select 0:GMI 1:MII */
  91 #define GMAC_CONTROL_FES        0x00004000 /* Speed 0:10 1:100 */
  92 #define GMAC_CONTROL_DO         0x00002000 /* Disable Rx Own */
  93 #define GMAC_CONTROL_LM         0x00001000 /* Loop-back mode */
  94 #define GMAC_CONTROL_DM         0x00000800 /* Duplex Mode */
  95 #define GMAC_CONTROL_IPC        0x00000400 /* Checksum Offload */
  96 #define GMAC_CONTROL_DR         0x00000200 /* Disable Retry */
  97 #define GMAC_CONTROL_LUD        0x00000100 /* Link up/down */
  98 #define GMAC_CONTROL_ACS        0x00000080 /* Automatic Pad/FCS Stripping */
  99 #define GMAC_CONTROL_DC         0x00000010 /* Deferral Check */
 100 #define GMAC_CONTROL_TE         0x00000008 /* Transmitter Enable */
 101 #define GMAC_CONTROL_RE         0x00000004 /* Receiver Enable */
 102
 103 #define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \
 104                         GMAC_CONTROL_JE | GMAC_CONTROL_BE)
 105
 106 /* GMAC Frame Filter defines */
 107 #define GMAC_FRAME_FILTER_PR    0x00000001      /* Promiscuous Mode */
 108 #define GMAC_FRAME_FILTER_HUC   0x00000002      /* Hash Unicast */
 109 #define GMAC_FRAME_FILTER_HMC   0x00000004      /* Hash Multicast */
 110 #define GMAC_FRAME_FILTER_DAIF  0x00000008      /* DA Inverse Filtering */
 111 #define GMAC_FRAME_FILTER_PM    0x00000010      /* Pass all multicast */
 112 #define GMAC_FRAME_FILTER_DBF   0x00000020      /* Disable Broadcast frames */
 113 #define GMAC_FRAME_FILTER_SAIF  0x00000100      /* Inverse Filtering */
 114 #define GMAC_FRAME_FILTER_SAF   0x00000200      /* Source Address Filter */
 115 #define GMAC_FRAME_FILTER_HPF   0x00000400      /* Hash or perfect Filter */
 116 #define GMAC_FRAME_FILTER_RA    0x80000000      /* Receive all mode */
 117 /* GMII ADDR  defines */
 118 #define GMAC_MII_ADDR_WRITE     0x00000002      /* MII Write */
 119 #define GMAC_MII_ADDR_BUSY      0x00000001      /* MII Busy */
 120 /* GMAC FLOW CTRL defines */
 121 #define GMAC_FLOW_CTRL_PT_MASK  0xffff0000      /* Pause Time Mask */
 122 #define GMAC_FLOW_CTRL_PT_SHIFT 16
 123 #define GMAC_FLOW_CTRL_RFE      0x00000004      /* Rx Flow Control Enable */
 124 #define GMAC_FLOW_CTRL_TFE      0x00000002      /* Tx Flow Control Enable */
 125 #define GMAC_FLOW_CTRL_FCB_BPA  0x00000001      /* Flow Control Busy ... */
 126
 127 /*--- DMA BLOCK defines ---*/
 128 /* DMA Bus Mode register defines */
 129 #define DMA_BUS_MODE_SFT_RESET  0x00000001      /* Software Reset */
 130 #define DMA_BUS_MODE_DA         0x00000002      /* Arbitration scheme */
 131 #define DMA_BUS_MODE_DSL_MASK   0x0000007c      /* Descriptor Skip Length */
 132 #define DMA_BUS_MODE_DSL_SHIFT  2       /*   (in DWORDS)      */
 133 /* Programmable burst length (passed thorugh platform)*/
 134 #define DMA_BUS_MODE_PBL_MASK   0x00003f00      /* Programmable Burst Len */
 135 #define DMA_BUS_MODE_PBL_SHIFT  8
 136
 137 enum rx_tx_priority_ratio {
 138         double_ratio = 0x00004000,      /*2:1 */
 139         triple_ratio = 0x00008000,      /*3:1 */
 140         quadruple_ratio = 0x0000c000,   /*4:1 */
 141 };
 142
 143 #define DMA_BUS_MODE_FB         0x00010000      /* Fixed burst */
 144 #define DMA_BUS_MODE_MB         0x04000000      /* Mixed burst */
 145 #define DMA_BUS_MODE_RPBL_MASK  0x003e0000      /* Rx-Programmable Burst Len */
 146 #define DMA_BUS_MODE_RPBL_SHIFT 17
 147 #define DMA_BUS_MODE_USP        0x00800000
 148 #define DMA_BUS_MODE_PBL        0x01000000
 149 #define DMA_BUS_MODE_AAL        0x02000000
 150
 151 /* DMA CRS Control and Status Register Mapping */
 152 #define DMA_HOST_TX_DESC          0x00001048    /* Current Host Tx descriptor */
 153 #define DMA_HOST_RX_DESC          0x0000104c    /* Current Host Rx descriptor */
 154 /*  DMA Bus Mode register defines */
 155 #define DMA_BUS_PR_RATIO_MASK     0x0000c000    /* Rx/Tx priority ratio */
 156 #define DMA_BUS_PR_RATIO_SHIFT    14
 157 #define DMA_BUS_FB                0x00010000    /* Fixed Burst */
 158
 159 /* DMA operation mode defines (start/stop tx/rx are placed in common header)*/
 160 #define DMA_CONTROL_DT          0x04000000 /* Disable Drop TCP/IP csum error */
 161 #define DMA_CONTROL_RSF         0x02000000 /* Receive Store and Forward */
 162 #define DMA_CONTROL_DFF         0x01000000 /* Disaable flushing */
 163 /* Threshold for Activating the FC */
 164 enum rfa {
 165         act_full_minus_1 = 0x00800000,
 166         act_full_minus_2 = 0x00800200,
 167         act_full_minus_3 = 0x00800400,
 168         act_full_minus_4 = 0x00800600,
 169 };
 170 /* Threshold for Deactivating the FC */
 171 enum rfd {
 172         deac_full_minus_1 = 0x00400000,
 173         deac_full_minus_2 = 0x00400800,
 174         deac_full_minus_3 = 0x00401000,
 175         deac_full_minus_4 = 0x00401800,
 176 };
 177 #define DMA_CONTROL_TSF         0x00200000 /* Transmit  Store and Forward */
 178
 179 enum ttc_control {
 180         DMA_CONTROL_TTC_64 = 0x00000000,
 181         DMA_CONTROL_TTC_128 = 0x00004000,
 182         DMA_CONTROL_TTC_192 = 0x00008000,
 183         DMA_CONTROL_TTC_256 = 0x0000c000,
 184         DMA_CONTROL_TTC_40 = 0x00010000,
 185         DMA_CONTROL_TTC_32 = 0x00014000,
 186         DMA_CONTROL_TTC_24 = 0x00018000,
 187         DMA_CONTROL_TTC_16 = 0x0001c000,
 188 };
 189 #define DMA_CONTROL_TC_TX_MASK  0xfffe3fff
 190
 191 #define DMA_CONTROL_EFC         0x00000100
 192 #define DMA_CONTROL_FEF         0x00000080
 193 #define DMA_CONTROL_FUF         0x00000040
 194
 195 enum rtc_control {
 196         DMA_CONTROL_RTC_64 = 0x00000000,
 197         DMA_CONTROL_RTC_32 = 0x00000008,
 198         DMA_CONTROL_RTC_96 = 0x00000010,
 199         DMA_CONTROL_RTC_128 = 0x00000018,
 200 };
 201 #define DMA_CONTROL_TC_RX_MASK  0xffffffe7
 202
 203 #define DMA_CONTROL_OSF 0x00000004      /* Operate on second frame */
 204
 205 /* MMC registers offset */
 206 #define GMAC_MMC_CTRL      0x100
 207 #define GMAC_MMC_RX_INTR   0x104
 208 #define GMAC_MMC_TX_INTR   0x108
 209 #define GMAC_MMC_RX_CSUM_OFFLOAD   0x208
 210
 211 /* Synopsys Core versions */
 212 #define DWMAC_CORE_3_40 34
 213
 214 extern const struct stmmac_dma_ops dwmac1000_dma_ops;