drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c

   1 /*******************************************************************************
   2   This is the driver for the MAC 10/100 on-chip Ethernet controller
   3   currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
   4
   5   DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
   6   this code.
   7
   8   This only implements the mac core functions for this chip.
   9
  10   Copyright (C) 2007-2009  STMicroelectronics Ltd
  11
  12   This program is free software; you can redistribute it and/or modify it
  13   under the terms and conditions of the GNU General Public License,
  14   version 2, as published by the Free Software Foundation.
  15
  16   This program is distributed in the hope it will be useful, but WITHOUT
  17   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19   more details.
  20
  21   The full GNU General Public License is included in this distribution in
  22   the file called "COPYING".
  23
  24   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  25 *******************************************************************************/
  26
  27 #include <linux/crc32.h>
  28 #include <asm/io.h>
  29 #include "dwmac100.h"
  30
  31 static void dwmac100_core_init(struct mac_device_info *hw, int mtu)
  32 {
  33         void __iomem *ioaddr = hw->pcsr;
  34         u32 value = readl(ioaddr + MAC_CONTROL);
  35
  36         writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL);
  37
  38 #ifdef STMMAC_VLAN_TAG_USED
  39         writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
  40 #endif
  41 }
  42
  43 static void dwmac100_dump_mac_regs(struct mac_device_info *hw, u32 *reg_space)
  44 {
  45         void __iomem *ioaddr = hw->pcsr;
  46
  47         reg_space[MAC_CONTROL / 4] = readl(ioaddr + MAC_CONTROL);
  48         reg_space[MAC_ADDR_HIGH / 4] = readl(ioaddr + MAC_ADDR_HIGH);
  49         reg_space[MAC_ADDR_LOW / 4] = readl(ioaddr + MAC_ADDR_LOW);
  50         reg_space[MAC_HASH_HIGH / 4] = readl(ioaddr + MAC_HASH_HIGH);
  51         reg_space[MAC_HASH_LOW / 4] = readl(ioaddr + MAC_HASH_LOW);
  52         reg_space[MAC_FLOW_CTRL / 4] = readl(ioaddr + MAC_FLOW_CTRL);
  53         reg_space[MAC_VLAN1 / 4] = readl(ioaddr + MAC_VLAN1);
  54         reg_space[MAC_VLAN2 / 4] = readl(ioaddr + MAC_VLAN2);
  55 }
  56
  57 static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)
  58 {
  59         return 0;
  60 }
  61
  62 static int dwmac100_irq_status(struct mac_device_info *hw,
  63                                struct stmmac_extra_stats *x)
  64 {
  65         return 0;
  66 }
  67
  68 static void dwmac100_set_umac_addr(struct mac_device_info *hw,
  69                                    unsigned char *addr,
  70                                    unsigned int reg_n)
  71 {
  72         void __iomem *ioaddr = hw->pcsr;
  73         stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
  74 }
  75
  76 static void dwmac100_get_umac_addr(struct mac_device_info *hw,
  77                                    unsigned char *addr,
  78                                    unsigned int reg_n)
  79 {
  80         void __iomem *ioaddr = hw->pcsr;
  81         stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
  82 }
  83
  84 static void dwmac100_set_filter(struct mac_device_info *hw,
  85                                 struct net_device *dev)
  86 {
  87         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
  88         u32 value = readl(ioaddr + MAC_CONTROL);
  89
  90         if (dev->flags & IFF_PROMISC) {
  91                 value |= MAC_CONTROL_PR;
  92                 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
  93                            MAC_CONTROL_HP);
  94         } else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
  95                    || (dev->flags & IFF_ALLMULTI)) {
  96                 value |= MAC_CONTROL_PM;
  97                 value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
  98                 writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
  99                 writel(0xffffffff, ioaddr + MAC_HASH_LOW);
 100         } else if (netdev_mc_empty(dev)) {      /* no multicast */
 101                 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
 102                            MAC_CONTROL_HO | MAC_CONTROL_HP);
 103         } else {
 104                 u32 mc_filter[2];
 105                 struct netdev_hw_addr *ha;
 106
 107                 /* Perfect filter mode for physical address and Hash
 108                  * filter for multicast
 109                  */
 110                 value |= MAC_CONTROL_HP;
 111                 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
 112                            MAC_CONTROL_IF | MAC_CONTROL_HO);
 113
 114                 memset(mc_filter, 0, sizeof(mc_filter));
 115                 netdev_for_each_mc_addr(ha, dev) {
 116                         /* The upper 6 bits of the calculated CRC are used to
 117                          * index the contens of the hash table
 118                          */
 119                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
 120                         /* The most significant bit determines the register to
 121                          * use (H/L) while the other 5 bits determine the bit
 122                          * within the register.
 123                          */
 124                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 125                 }
 126                 writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
 127                 writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
 128         }
 129
 130         writel(value, ioaddr + MAC_CONTROL);
 131 }
 132
 133 static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 134                                unsigned int fc, unsigned int pause_time)
 135 {
 136         void __iomem *ioaddr = hw->pcsr;
 137         unsigned int flow = MAC_FLOW_CTRL_ENABLE;
 138
 139         if (duplex)
 140                 flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
 141         writel(flow, ioaddr + MAC_FLOW_CTRL);
 142 }
 143
 144 /* No PMT module supported on ST boards with this Eth chip. */
 145 static void dwmac100_pmt(struct mac_device_info *hw, unsigned long mode)
 146 {
 147         return;
 148 }
 149
 150 static const struct stmmac_ops dwmac100_ops = {
 151         .core_init = dwmac100_core_init,
 152         .rx_ipc = dwmac100_rx_ipc_enable,
 153         .dump_regs = dwmac100_dump_mac_regs,
 154         .host_irq_status = dwmac100_irq_status,
 155         .set_filter = dwmac100_set_filter,
 156         .flow_ctrl = dwmac100_flow_ctrl,
 157         .pmt = dwmac100_pmt,
 158         .set_umac_addr = dwmac100_set_umac_addr,
 159         .get_umac_addr = dwmac100_get_umac_addr,
 160 };
 161
 162 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id)
 163 {
 164         struct mac_device_info *mac;
 165
 166         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 167         if (!mac)
 168                 return NULL;
 169
 170         pr_info("\tDWMAC100\n");
 171
 172         mac->pcsr = ioaddr;
 173         mac->mac = &dwmac100_ops;
 174         mac->dma = &dwmac100_dma_ops;
 175
 176         mac->link.port = MAC_CONTROL_PS;
 177         mac->link.duplex = MAC_CONTROL_F;
 178         mac->link.speed = 0;
 179         mac->mii.addr = MAC_MII_ADDR;
 180         mac->mii.data = MAC_MII_DATA;
 181         mac->mii.addr_shift = 11;
 182         mac->mii.addr_mask = 0x0000F800;
 183         mac->mii.reg_shift = 6;
 184         mac->mii.reg_mask = 0x000007C0;
 185         mac->mii.clk_csr_shift = 2;
 186         mac->mii.clk_csr_mask = GENMASK(5, 2);
 187
 188         /* Synopsys Id is not available on old chips */
 189         *synopsys_id = 0;
 190
 191         return mac;
 192 }