drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c

   1 /*******************************************************************************
   2   This is the driver for the MAC 10/100 on-chip Ethernet controller
   3   currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
   4
   5   DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
   6   this code.
   7
   8   This only implements the mac core functions for this chip.
   9
  10   Copyright (C) 2007-2009  STMicroelectronics Ltd
  11
  12   This program is free software; you can redistribute it and/or modify it
  13   under the terms and conditions of the GNU General Public License,
  14   version 2, as published by the Free Software Foundation.
  15
  16   This program is distributed in the hope it will be useful, but WITHOUT
  17   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19   more details.
  20
  21   The full GNU General Public License is included in this distribution in
  22   the file called "COPYING".
  23
  24   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  25 *******************************************************************************/
  26
  27 #include <linux/crc32.h>
  28 #include <asm/io.h>
  29 #include "dwmac100.h"
  30
  31 static void dwmac100_core_init(struct mac_device_info *hw, int mtu)
  32 {
  33         void __iomem *ioaddr = hw->pcsr;
  34         u32 value = readl(ioaddr + MAC_CONTROL);
  35
  36         writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL);
  37
  38 #ifdef STMMAC_VLAN_TAG_USED
  39         writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
  40 #endif
  41 }
  42
  43 static void dwmac100_dump_mac_regs(struct mac_device_info *hw)
  44 {
  45         void __iomem *ioaddr = hw->pcsr;
  46         pr_info("\t----------------------------------------------\n"
  47                 "\t  DWMAC 100 CSR (base addr = 0x%p)\n"
  48                 "\t----------------------------------------------\n", ioaddr);
  49         pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
  50                 readl(ioaddr + MAC_CONTROL));
  51         pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
  52                 readl(ioaddr + MAC_ADDR_HIGH));
  53         pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
  54                 readl(ioaddr + MAC_ADDR_LOW));
  55         pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
  56                 MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
  57         pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
  58                 MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
  59         pr_info("\tflow control (offset 0x%x): 0x%08x\n",
  60                 MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
  61         pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
  62                 readl(ioaddr + MAC_VLAN1));
  63         pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
  64                 readl(ioaddr + MAC_VLAN2));
  65 }
  66
  67 static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)
  68 {
  69         return 0;
  70 }
  71
  72 static int dwmac100_irq_status(struct mac_device_info *hw,
  73                                struct stmmac_extra_stats *x)
  74 {
  75         return 0;
  76 }
  77
  78 static void dwmac100_set_umac_addr(struct mac_device_info *hw,
  79                                    unsigned char *addr,
  80                                    unsigned int reg_n)
  81 {
  82         void __iomem *ioaddr = hw->pcsr;
  83         stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
  84 }
  85
  86 static void dwmac100_get_umac_addr(struct mac_device_info *hw,
  87                                    unsigned char *addr,
  88                                    unsigned int reg_n)
  89 {
  90         void __iomem *ioaddr = hw->pcsr;
  91         stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
  92 }
  93
  94 static void dwmac100_set_filter(struct mac_device_info *hw,
  95                                 struct net_device *dev)
  96 {
  97         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
  98         u32 value = readl(ioaddr + MAC_CONTROL);
  99
 100         if (dev->flags & IFF_PROMISC) {
 101                 value |= MAC_CONTROL_PR;
 102                 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
 103                            MAC_CONTROL_HP);
 104         } else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
 105                    || (dev->flags & IFF_ALLMULTI)) {
 106                 value |= MAC_CONTROL_PM;
 107                 value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
 108                 writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
 109                 writel(0xffffffff, ioaddr + MAC_HASH_LOW);
 110         } else if (netdev_mc_empty(dev)) {      /* no multicast */
 111                 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
 112                            MAC_CONTROL_HO | MAC_CONTROL_HP);
 113         } else {
 114                 u32 mc_filter[2];
 115                 struct netdev_hw_addr *ha;
 116
 117                 /* Perfect filter mode for physical address and Hash
 118                  * filter for multicast
 119                  */
 120                 value |= MAC_CONTROL_HP;
 121                 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
 122                            MAC_CONTROL_IF | MAC_CONTROL_HO);
 123
 124                 memset(mc_filter, 0, sizeof(mc_filter));
 125                 netdev_for_each_mc_addr(ha, dev) {
 126                         /* The upper 6 bits of the calculated CRC are used to
 127                          * index the contens of the hash table
 128                          */
 129                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
 130                         /* The most significant bit determines the register to
 131                          * use (H/L) while the other 5 bits determine the bit
 132                          * within the register.
 133                          */
 134                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 135                 }
 136                 writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
 137                 writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
 138         }
 139
 140         writel(value, ioaddr + MAC_CONTROL);
 141 }
 142
 143 static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 144                                unsigned int fc, unsigned int pause_time)
 145 {
 146         void __iomem *ioaddr = hw->pcsr;
 147         unsigned int flow = MAC_FLOW_CTRL_ENABLE;
 148
 149         if (duplex)
 150                 flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
 151         writel(flow, ioaddr + MAC_FLOW_CTRL);
 152 }
 153
 154 /* No PMT module supported on ST boards with this Eth chip. */
 155 static void dwmac100_pmt(struct mac_device_info *hw, unsigned long mode)
 156 {
 157         return;
 158 }
 159
 160 static const struct stmmac_ops dwmac100_ops = {
 161         .core_init = dwmac100_core_init,
 162         .rx_ipc = dwmac100_rx_ipc_enable,
 163         .dump_regs = dwmac100_dump_mac_regs,
 164         .host_irq_status = dwmac100_irq_status,
 165         .set_filter = dwmac100_set_filter,
 166         .flow_ctrl = dwmac100_flow_ctrl,
 167         .pmt = dwmac100_pmt,
 168         .set_umac_addr = dwmac100_set_umac_addr,
 169         .get_umac_addr = dwmac100_get_umac_addr,
 170 };
 171
 172 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id)
 173 {
 174         struct mac_device_info *mac;
 175
 176         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 177         if (!mac)
 178                 return NULL;
 179
 180         pr_info("\tDWMAC100\n");
 181
 182         mac->pcsr = ioaddr;
 183         mac->mac = &dwmac100_ops;
 184         mac->dma = &dwmac100_dma_ops;
 185
 186         mac->link.port = MAC_CONTROL_PS;
 187         mac->link.duplex = MAC_CONTROL_F;
 188         mac->link.speed = 0;
 189         mac->mii.addr = MAC_MII_ADDR;
 190         mac->mii.data = MAC_MII_DATA;
 191         mac->mii.addr_shift = 11;
 192         mac->mii.addr_mask = 0x0000F800;
 193         mac->mii.reg_shift = 6;
 194         mac->mii.reg_mask = 0x000007C0;
 195         mac->mii.clk_csr_shift = 2;
 196         mac->mii.clk_csr_mask = GENMASK(5, 2);
 197
 198         /* Synopsys Id is not available on old chips */
 199         *synopsys_id = 0;
 200
 201         return mac;
 202 }