1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_STMMAC_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_STMMAC_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
54 #include <linux/reset.h>
56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
58 /* Module parameters */
60 static int watchdog
= TX_TIMEO
;
61 module_param(watchdog
, int, S_IRUGO
| S_IWUSR
);
62 MODULE_PARM_DESC(watchdog
, "Transmit timeout in milliseconds (default 5s)");
64 static int debug
= -1;
65 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
66 MODULE_PARM_DESC(debug
, "Message Level (-1: default, 0: no output, 16: all)");
68 static int phyaddr
= -1;
69 module_param(phyaddr
, int, S_IRUGO
);
70 MODULE_PARM_DESC(phyaddr
, "Physical device address");
72 #define DMA_TX_SIZE 256
73 static int dma_txsize
= DMA_TX_SIZE
;
74 module_param(dma_txsize
, int, S_IRUGO
| S_IWUSR
);
75 MODULE_PARM_DESC(dma_txsize
, "Number of descriptors in the TX list");
77 #define DMA_RX_SIZE 256
78 static int dma_rxsize
= DMA_RX_SIZE
;
79 module_param(dma_rxsize
, int, S_IRUGO
| S_IWUSR
);
80 MODULE_PARM_DESC(dma_rxsize
, "Number of descriptors in the RX list");
82 static int flow_ctrl
= FLOW_OFF
;
83 module_param(flow_ctrl
, int, S_IRUGO
| S_IWUSR
);
84 MODULE_PARM_DESC(flow_ctrl
, "Flow control ability [on/off]");
86 static int pause
= PAUSE_TIME
;
87 module_param(pause
, int, S_IRUGO
| S_IWUSR
);
88 MODULE_PARM_DESC(pause
, "Flow Control Pause Time");
91 static int tc
= TC_DEFAULT
;
92 module_param(tc
, int, S_IRUGO
| S_IWUSR
);
93 MODULE_PARM_DESC(tc
, "DMA threshold control value");
95 #define DEFAULT_BUFSIZE 1536
96 static int buf_sz
= DEFAULT_BUFSIZE
;
97 module_param(buf_sz
, int, S_IRUGO
| S_IWUSR
);
98 MODULE_PARM_DESC(buf_sz
, "DMA buffer size");
100 static const u32 default_msg_level
= (NETIF_MSG_DRV
| NETIF_MSG_PROBE
|
101 NETIF_MSG_LINK
| NETIF_MSG_IFUP
|
102 NETIF_MSG_IFDOWN
| NETIF_MSG_TIMER
);
104 #define STMMAC_DEFAULT_LPI_TIMER 1000
105 static int eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
106 module_param(eee_timer
, int, S_IRUGO
| S_IWUSR
);
107 MODULE_PARM_DESC(eee_timer
, "LPI tx expiration time in msec");
108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
110 /* By default the driver will use the ring mode to manage tx and rx descriptors
111 * but passing this value so user can force to use the chain instead of the ring
113 static unsigned int chain_mode
;
114 module_param(chain_mode
, int, S_IRUGO
);
115 MODULE_PARM_DESC(chain_mode
, "To use chain instead of ring mode");
117 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
);
119 #ifdef CONFIG_STMMAC_DEBUG_FS
120 static int stmmac_init_fs(struct net_device
*dev
);
121 static void stmmac_exit_fs(void);
124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
127 * stmmac_verify_args - verify the driver parameters.
128 * Description: it verifies if some wrong parameter is passed to the driver.
129 * Note that wrong parameters are replaced with the default values.
131 static void stmmac_verify_args(void)
133 if (unlikely(watchdog
< 0))
135 if (unlikely(dma_rxsize
< 0))
136 dma_rxsize
= DMA_RX_SIZE
;
137 if (unlikely(dma_txsize
< 0))
138 dma_txsize
= DMA_TX_SIZE
;
139 if (unlikely((buf_sz
< DEFAULT_BUFSIZE
) || (buf_sz
> BUF_SIZE_16KiB
)))
140 buf_sz
= DEFAULT_BUFSIZE
;
141 if (unlikely(flow_ctrl
> 1))
142 flow_ctrl
= FLOW_AUTO
;
143 else if (likely(flow_ctrl
< 0))
144 flow_ctrl
= FLOW_OFF
;
145 if (unlikely((pause
< 0) || (pause
> 0xffff)))
148 eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
152 * stmmac_clk_csr_set - dynamically set the MDC clock
153 * @priv: driver private structure
154 * Description: this is to dynamically set the MDC clock according to the csr
157 * If a specific clk_csr value is passed from the platform
158 * this means that the CSR Clock Range selection cannot be
159 * changed at run-time and it is fixed (as reported in the driver
160 * documentation). Viceversa the driver will try to set the MDC
161 * clock dynamically according to the actual clock input.
163 static void stmmac_clk_csr_set(struct stmmac_priv
*priv
)
167 clk_rate
= clk_get_rate(priv
->stmmac_clk
);
169 /* Platform provided default clk_csr would be assumed valid
170 * for all other cases except for the below mentioned ones.
171 * For values higher than the IEEE 802.3 specified frequency
172 * we can not estimate the proper divider as it is not known
173 * the frequency of clk_csr_i. So we do not change the default
176 if (!(priv
->clk_csr
& MAC_CSR_H_FRQ_MASK
)) {
177 if (clk_rate
< CSR_F_35M
)
178 priv
->clk_csr
= STMMAC_CSR_20_35M
;
179 else if ((clk_rate
>= CSR_F_35M
) && (clk_rate
< CSR_F_60M
))
180 priv
->clk_csr
= STMMAC_CSR_35_60M
;
181 else if ((clk_rate
>= CSR_F_60M
) && (clk_rate
< CSR_F_100M
))
182 priv
->clk_csr
= STMMAC_CSR_60_100M
;
183 else if ((clk_rate
>= CSR_F_100M
) && (clk_rate
< CSR_F_150M
))
184 priv
->clk_csr
= STMMAC_CSR_100_150M
;
185 else if ((clk_rate
>= CSR_F_150M
) && (clk_rate
< CSR_F_250M
))
186 priv
->clk_csr
= STMMAC_CSR_150_250M
;
187 else if ((clk_rate
>= CSR_F_250M
) && (clk_rate
< CSR_F_300M
))
188 priv
->clk_csr
= STMMAC_CSR_250_300M
;
192 static void print_pkt(unsigned char *buf
, int len
)
195 pr_debug("len = %d byte, buf addr: 0x%p", len
, buf
);
196 for (j
= 0; j
< len
; j
++) {
198 pr_debug("\n %03x:", j
);
199 pr_debug(" %02x", buf
[j
]);
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
207 static inline u32
stmmac_tx_avail(struct stmmac_priv
*priv
)
209 return priv
->dirty_tx
+ priv
->dma_tx_size
- priv
->cur_tx
- 1;
213 * stmmac_hw_fix_mac_speed: callback for speed selection
214 * @priv: driver private structure
215 * Description: on some platforms (e.g. ST), some HW system configuraton
216 * registers have to be set according to the link speed negotiated.
218 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv
*priv
)
220 struct phy_device
*phydev
= priv
->phydev
;
222 if (likely(priv
->plat
->fix_mac_speed
))
223 priv
->plat
->fix_mac_speed(priv
->plat
->bsp_priv
, phydev
->speed
);
227 * stmmac_enable_eee_mode: Check and enter in LPI mode
228 * @priv: driver private structure
229 * Description: this function is to verify and enter in LPI mode for EEE.
231 static void stmmac_enable_eee_mode(struct stmmac_priv
*priv
)
233 /* Check and enter in LPI mode */
234 if ((priv
->dirty_tx
== priv
->cur_tx
) &&
235 (priv
->tx_path_in_lpi_mode
== false))
236 priv
->hw
->mac
->set_eee_mode(priv
->ioaddr
);
240 * stmmac_disable_eee_mode: disable/exit from EEE
241 * @priv: driver private structure
242 * Description: this function is to exit and disable EEE in case of
243 * LPI state is true. This is called by the xmit.
245 void stmmac_disable_eee_mode(struct stmmac_priv
*priv
)
247 priv
->hw
->mac
->reset_eee_mode(priv
->ioaddr
);
248 del_timer_sync(&priv
->eee_ctrl_timer
);
249 priv
->tx_path_in_lpi_mode
= false;
253 * stmmac_eee_ctrl_timer: EEE TX SW timer.
256 * if there is no data transfer and if we are not in LPI state,
257 * then MAC Transmitter can be moved to LPI state.
259 static void stmmac_eee_ctrl_timer(unsigned long arg
)
261 struct stmmac_priv
*priv
= (struct stmmac_priv
*)arg
;
263 stmmac_enable_eee_mode(priv
);
264 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
268 * stmmac_eee_init: init EEE
269 * @priv: driver private structure
271 * If the EEE support has been enabled while configuring the driver,
272 * if the GMAC actually supports the EEE (from the HW cap reg) and the
273 * phy can also manage EEE, so enable the LPI state and start the timer
274 * to verify if the tx path can enter in LPI state.
276 bool stmmac_eee_init(struct stmmac_priv
*priv
)
280 /* Using PCS we cannot dial with the phy registers at this stage
281 * so we do not support extra feature like EEE.
283 if ((priv
->pcs
== STMMAC_PCS_RGMII
) || (priv
->pcs
== STMMAC_PCS_TBI
) ||
284 (priv
->pcs
== STMMAC_PCS_RTBI
))
287 /* MAC core supports the EEE feature. */
288 if (priv
->dma_cap
.eee
) {
289 int tx_lpi_timer
= priv
->tx_lpi_timer
;
291 /* Check if the PHY supports EEE */
292 if (phy_init_eee(priv
->phydev
, 1)) {
293 /* To manage at run-time if the EEE cannot be supported
294 * anymore (for example because the lp caps have been
296 * In that case the driver disable own timers.
298 if (priv
->eee_active
) {
299 pr_debug("stmmac: disable EEE\n");
300 del_timer_sync(&priv
->eee_ctrl_timer
);
301 priv
->hw
->mac
->set_eee_timer(priv
->ioaddr
, 0,
304 priv
->eee_active
= 0;
307 /* Activate the EEE and start timers */
308 if (!priv
->eee_active
) {
309 priv
->eee_active
= 1;
310 init_timer(&priv
->eee_ctrl_timer
);
311 priv
->eee_ctrl_timer
.function
= stmmac_eee_ctrl_timer
;
312 priv
->eee_ctrl_timer
.data
= (unsigned long)priv
;
313 priv
->eee_ctrl_timer
.expires
= STMMAC_LPI_T(eee_timer
);
314 add_timer(&priv
->eee_ctrl_timer
);
316 priv
->hw
->mac
->set_eee_timer(priv
->ioaddr
,
317 STMMAC_DEFAULT_LIT_LS
,
320 /* Set HW EEE according to the speed */
321 priv
->hw
->mac
->set_eee_pls(priv
->ioaddr
,
324 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
332 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
333 * @priv: driver private structure
334 * @entry : descriptor index to be used.
335 * @skb : the socket buffer
337 * This function will read timestamp from the descriptor & pass it to stack.
338 * and also perform some sanity checks.
340 static void stmmac_get_tx_hwtstamp(struct stmmac_priv
*priv
,
341 unsigned int entry
, struct sk_buff
*skb
)
343 struct skb_shared_hwtstamps shhwtstamp
;
347 if (!priv
->hwts_tx_en
)
350 /* exit if skb doesn't support hw tstamp */
351 if (likely(!skb
|| !(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)))
355 desc
= (priv
->dma_etx
+ entry
);
357 desc
= (priv
->dma_tx
+ entry
);
359 /* check tx tstamp status */
360 if (!priv
->hw
->desc
->get_tx_timestamp_status((struct dma_desc
*)desc
))
363 /* get the valid tstamp */
364 ns
= priv
->hw
->desc
->get_timestamp(desc
, priv
->adv_ts
);
366 memset(&shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
367 shhwtstamp
.hwtstamp
= ns_to_ktime(ns
);
368 /* pass tstamp to stack */
369 skb_tstamp_tx(skb
, &shhwtstamp
);
374 /* stmmac_get_rx_hwtstamp: get HW RX timestamps
375 * @priv: driver private structure
376 * @entry : descriptor index to be used.
377 * @skb : the socket buffer
379 * This function will read received packet's timestamp from the descriptor
380 * and pass it to stack. It also perform some sanity checks.
382 static void stmmac_get_rx_hwtstamp(struct stmmac_priv
*priv
,
383 unsigned int entry
, struct sk_buff
*skb
)
385 struct skb_shared_hwtstamps
*shhwtstamp
= NULL
;
389 if (!priv
->hwts_rx_en
)
393 desc
= (priv
->dma_erx
+ entry
);
395 desc
= (priv
->dma_rx
+ entry
);
397 /* exit if rx tstamp is not valid */
398 if (!priv
->hw
->desc
->get_rx_timestamp_status(desc
, priv
->adv_ts
))
401 /* get valid tstamp */
402 ns
= priv
->hw
->desc
->get_timestamp(desc
, priv
->adv_ts
);
403 shhwtstamp
= skb_hwtstamps(skb
);
404 memset(shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
405 shhwtstamp
->hwtstamp
= ns_to_ktime(ns
);
409 * stmmac_hwtstamp_ioctl - control hardware timestamping.
410 * @dev: device pointer.
411 * @ifr: An IOCTL specefic structure, that can contain a pointer to
412 * a proprietary structure used to pass information to the driver.
414 * This function configures the MAC to enable/disable both outgoing(TX)
415 * and incoming(RX) packets time stamping based on user input.
417 * 0 on success and an appropriate -ve integer on failure.
419 static int stmmac_hwtstamp_ioctl(struct net_device
*dev
, struct ifreq
*ifr
)
421 struct stmmac_priv
*priv
= netdev_priv(dev
);
422 struct hwtstamp_config config
;
427 u32 ptp_over_ipv4_udp
= 0;
428 u32 ptp_over_ipv6_udp
= 0;
429 u32 ptp_over_ethernet
= 0;
430 u32 snap_type_sel
= 0;
431 u32 ts_master_en
= 0;
435 if (!(priv
->dma_cap
.time_stamp
|| priv
->adv_ts
)) {
436 netdev_alert(priv
->dev
, "No support for HW time stamping\n");
437 priv
->hwts_tx_en
= 0;
438 priv
->hwts_rx_en
= 0;
443 if (copy_from_user(&config
, ifr
->ifr_data
,
444 sizeof(struct hwtstamp_config
)))
447 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
448 __func__
, config
.flags
, config
.tx_type
, config
.rx_filter
);
450 /* reserved for future extensions */
454 if (config
.tx_type
!= HWTSTAMP_TX_OFF
&&
455 config
.tx_type
!= HWTSTAMP_TX_ON
)
459 switch (config
.rx_filter
) {
460 case HWTSTAMP_FILTER_NONE
:
461 /* time stamp no incoming packet at all */
462 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
465 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
466 /* PTP v1, UDP, any kind of event packet */
467 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
468 /* take time stamp for all event messages */
469 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
471 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
472 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
475 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
476 /* PTP v1, UDP, Sync packet */
477 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_SYNC
;
478 /* take time stamp for SYNC messages only */
479 ts_event_en
= PTP_TCR_TSEVNTENA
;
481 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
482 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
485 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
486 /* PTP v1, UDP, Delay_req packet */
487 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
;
488 /* take time stamp for Delay_Req messages only */
489 ts_master_en
= PTP_TCR_TSMSTRENA
;
490 ts_event_en
= PTP_TCR_TSEVNTENA
;
492 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
493 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
496 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
497 /* PTP v2, UDP, any kind of event packet */
498 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_EVENT
;
499 ptp_v2
= PTP_TCR_TSVER2ENA
;
500 /* take time stamp for all event messages */
501 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
503 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
504 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
507 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
508 /* PTP v2, UDP, Sync packet */
509 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_SYNC
;
510 ptp_v2
= PTP_TCR_TSVER2ENA
;
511 /* take time stamp for SYNC messages only */
512 ts_event_en
= PTP_TCR_TSEVNTENA
;
514 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
515 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
518 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
519 /* PTP v2, UDP, Delay_req packet */
520 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
;
521 ptp_v2
= PTP_TCR_TSVER2ENA
;
522 /* take time stamp for Delay_Req messages only */
523 ts_master_en
= PTP_TCR_TSMSTRENA
;
524 ts_event_en
= PTP_TCR_TSEVNTENA
;
526 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
527 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
530 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
531 /* PTP v2/802.AS1 any layer, any kind of event packet */
532 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
533 ptp_v2
= PTP_TCR_TSVER2ENA
;
534 /* take time stamp for all event messages */
535 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
537 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
538 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
539 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
542 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
543 /* PTP v2/802.AS1, any layer, Sync packet */
544 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_SYNC
;
545 ptp_v2
= PTP_TCR_TSVER2ENA
;
546 /* take time stamp for SYNC messages only */
547 ts_event_en
= PTP_TCR_TSEVNTENA
;
549 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
550 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
551 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
554 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
555 /* PTP v2/802.AS1, any layer, Delay_req packet */
556 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
;
557 ptp_v2
= PTP_TCR_TSVER2ENA
;
558 /* take time stamp for Delay_Req messages only */
559 ts_master_en
= PTP_TCR_TSMSTRENA
;
560 ts_event_en
= PTP_TCR_TSEVNTENA
;
562 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
563 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
564 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
567 case HWTSTAMP_FILTER_ALL
:
568 /* time stamp any incoming packet */
569 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
570 tstamp_all
= PTP_TCR_TSENALL
;
577 switch (config
.rx_filter
) {
578 case HWTSTAMP_FILTER_NONE
:
579 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
582 /* PTP v1, UDP, any kind of event packet */
583 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
587 priv
->hwts_rx_en
= ((config
.rx_filter
== HWTSTAMP_FILTER_NONE
) ? 0 : 1);
588 priv
->hwts_tx_en
= config
.tx_type
== HWTSTAMP_TX_ON
;
590 if (!priv
->hwts_tx_en
&& !priv
->hwts_rx_en
)
591 priv
->hw
->ptp
->config_hw_tstamping(priv
->ioaddr
, 0);
593 value
= (PTP_TCR_TSENA
| PTP_TCR_TSCFUPDT
| PTP_TCR_TSCTRLSSR
|
594 tstamp_all
| ptp_v2
| ptp_over_ethernet
|
595 ptp_over_ipv6_udp
| ptp_over_ipv4_udp
| ts_event_en
|
596 ts_master_en
| snap_type_sel
);
598 priv
->hw
->ptp
->config_hw_tstamping(priv
->ioaddr
, value
);
600 /* program Sub Second Increment reg */
601 priv
->hw
->ptp
->config_sub_second_increment(priv
->ioaddr
);
603 /* calculate default added value:
605 * addend = (2^32)/freq_div_ratio;
606 * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
607 * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
608 * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
609 * achive 20ns accuracy.
611 * 2^x * y == (y << x), hence
612 * 2^32 * 50000000 ==> (50000000 << 32)
614 temp
= (u64
) (50000000ULL << 32);
615 priv
->default_addend
= div_u64(temp
, STMMAC_SYSCLOCK
);
616 priv
->hw
->ptp
->config_addend(priv
->ioaddr
,
617 priv
->default_addend
);
619 /* initialize system time */
620 getnstimeofday(&now
);
621 priv
->hw
->ptp
->init_systime(priv
->ioaddr
, now
.tv_sec
,
625 return copy_to_user(ifr
->ifr_data
, &config
,
626 sizeof(struct hwtstamp_config
)) ? -EFAULT
: 0;
630 * stmmac_init_ptp: init PTP
631 * @priv: driver private structure
632 * Description: this is to verify if the HW supports the PTPv1 or v2.
633 * This is done by looking at the HW cap. register.
634 * Also it registers the ptp driver.
636 static int stmmac_init_ptp(struct stmmac_priv
*priv
)
638 if (!(priv
->dma_cap
.time_stamp
|| priv
->dma_cap
.atime_stamp
))
642 if (priv
->dma_cap
.atime_stamp
&& priv
->extend_desc
)
645 if (netif_msg_hw(priv
) && priv
->dma_cap
.time_stamp
)
646 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
648 if (netif_msg_hw(priv
) && priv
->adv_ts
)
649 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
651 priv
->hw
->ptp
= &stmmac_ptp
;
652 priv
->hwts_tx_en
= 0;
653 priv
->hwts_rx_en
= 0;
655 return stmmac_ptp_register(priv
);
658 static void stmmac_release_ptp(struct stmmac_priv
*priv
)
660 stmmac_ptp_unregister(priv
);
665 * @dev: net device structure
666 * Description: it adjusts the link parameters.
668 static void stmmac_adjust_link(struct net_device
*dev
)
670 struct stmmac_priv
*priv
= netdev_priv(dev
);
671 struct phy_device
*phydev
= priv
->phydev
;
674 unsigned int fc
= priv
->flow_ctrl
, pause_time
= priv
->pause
;
679 spin_lock_irqsave(&priv
->lock
, flags
);
682 u32 ctrl
= readl(priv
->ioaddr
+ MAC_CTRL_REG
);
684 /* Now we make sure that we can be in full duplex mode.
685 * If not, we operate in half-duplex mode. */
686 if (phydev
->duplex
!= priv
->oldduplex
) {
688 if (!(phydev
->duplex
))
689 ctrl
&= ~priv
->hw
->link
.duplex
;
691 ctrl
|= priv
->hw
->link
.duplex
;
692 priv
->oldduplex
= phydev
->duplex
;
694 /* Flow Control operation */
696 priv
->hw
->mac
->flow_ctrl(priv
->ioaddr
, phydev
->duplex
,
699 if (phydev
->speed
!= priv
->speed
) {
701 switch (phydev
->speed
) {
703 if (likely(priv
->plat
->has_gmac
))
704 ctrl
&= ~priv
->hw
->link
.port
;
705 stmmac_hw_fix_mac_speed(priv
);
709 if (priv
->plat
->has_gmac
) {
710 ctrl
|= priv
->hw
->link
.port
;
711 if (phydev
->speed
== SPEED_100
) {
712 ctrl
|= priv
->hw
->link
.speed
;
714 ctrl
&= ~(priv
->hw
->link
.speed
);
717 ctrl
&= ~priv
->hw
->link
.port
;
719 stmmac_hw_fix_mac_speed(priv
);
722 if (netif_msg_link(priv
))
723 pr_warn("%s: Speed (%d) not 10/100\n",
724 dev
->name
, phydev
->speed
);
728 priv
->speed
= phydev
->speed
;
731 writel(ctrl
, priv
->ioaddr
+ MAC_CTRL_REG
);
733 if (!priv
->oldlink
) {
737 } else if (priv
->oldlink
) {
741 priv
->oldduplex
= -1;
744 if (new_state
&& netif_msg_link(priv
))
745 phy_print_status(phydev
);
747 /* At this stage, it could be needed to setup the EEE or adjust some
748 * MAC related HW registers.
750 priv
->eee_enabled
= stmmac_eee_init(priv
);
752 spin_unlock_irqrestore(&priv
->lock
, flags
);
756 * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
757 * @priv: driver private structure
758 * Description: this is to verify if the HW supports the PCS.
759 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
760 * configured for the TBI, RTBI, or SGMII PHY interface.
762 static void stmmac_check_pcs_mode(struct stmmac_priv
*priv
)
764 int interface
= priv
->plat
->interface
;
766 if (priv
->dma_cap
.pcs
) {
767 if ((interface
== PHY_INTERFACE_MODE_RGMII
) ||
768 (interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
769 (interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
770 (interface
== PHY_INTERFACE_MODE_RGMII_TXID
)) {
771 pr_debug("STMMAC: PCS RGMII support enable\n");
772 priv
->pcs
= STMMAC_PCS_RGMII
;
773 } else if (interface
== PHY_INTERFACE_MODE_SGMII
) {
774 pr_debug("STMMAC: PCS SGMII support enable\n");
775 priv
->pcs
= STMMAC_PCS_SGMII
;
781 * stmmac_init_phy - PHY initialization
782 * @dev: net device structure
783 * Description: it initializes the driver's PHY state, and attaches the PHY
788 static int stmmac_init_phy(struct net_device
*dev
)
790 struct stmmac_priv
*priv
= netdev_priv(dev
);
791 struct phy_device
*phydev
;
792 char phy_id_fmt
[MII_BUS_ID_SIZE
+ 3];
793 char bus_id
[MII_BUS_ID_SIZE
];
794 int interface
= priv
->plat
->interface
;
795 int max_speed
= priv
->plat
->max_speed
;
798 priv
->oldduplex
= -1;
800 if (priv
->plat
->phy_bus_name
)
801 snprintf(bus_id
, MII_BUS_ID_SIZE
, "%s-%x",
802 priv
->plat
->phy_bus_name
, priv
->plat
->bus_id
);
804 snprintf(bus_id
, MII_BUS_ID_SIZE
, "stmmac-%x",
807 snprintf(phy_id_fmt
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, bus_id
,
808 priv
->plat
->phy_addr
);
809 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt
);
811 phydev
= phy_connect(dev
, phy_id_fmt
, &stmmac_adjust_link
, interface
);
813 if (IS_ERR(phydev
)) {
814 pr_err("%s: Could not attach to PHY\n", dev
->name
);
815 return PTR_ERR(phydev
);
818 /* Stop Advertising 1000BASE Capability if interface is not GMII */
819 if ((interface
== PHY_INTERFACE_MODE_MII
) ||
820 (interface
== PHY_INTERFACE_MODE_RMII
) ||
821 (max_speed
< 1000 && max_speed
> 0))
822 phydev
->advertising
&= ~(SUPPORTED_1000baseT_Half
|
823 SUPPORTED_1000baseT_Full
);
826 * Broken HW is sometimes missing the pull-up resistor on the
827 * MDIO line, which results in reads to non-existent devices returning
828 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
830 * Note: phydev->phy_id is the result of reading the UID PHY registers.
832 if (phydev
->phy_id
== 0) {
833 phy_disconnect(phydev
);
836 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
837 " Link = %d\n", dev
->name
, phydev
->phy_id
, phydev
->link
);
839 priv
->phydev
= phydev
;
845 * stmmac_display_ring: display ring
846 * @head: pointer to the head of the ring passed.
847 * @size: size of the ring.
848 * @extend_desc: to verify if extended descriptors are used.
849 * Description: display the control/status and buffer descriptors.
851 static void stmmac_display_ring(void *head
, int size
, int extend_desc
)
854 struct dma_extended_desc
*ep
= (struct dma_extended_desc
*)head
;
855 struct dma_desc
*p
= (struct dma_desc
*)head
;
857 for (i
= 0; i
< size
; i
++) {
861 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
862 i
, (unsigned int)virt_to_phys(ep
),
863 (unsigned int)x
, (unsigned int)(x
>> 32),
864 ep
->basic
.des2
, ep
->basic
.des3
);
868 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
869 i
, (unsigned int)virt_to_phys(p
),
870 (unsigned int)x
, (unsigned int)(x
>> 32),
878 static void stmmac_display_rings(struct stmmac_priv
*priv
)
880 unsigned int txsize
= priv
->dma_tx_size
;
881 unsigned int rxsize
= priv
->dma_rx_size
;
883 if (priv
->extend_desc
) {
884 pr_info("Extended RX descriptor ring:\n");
885 stmmac_display_ring((void *)priv
->dma_erx
, rxsize
, 1);
886 pr_info("Extended TX descriptor ring:\n");
887 stmmac_display_ring((void *)priv
->dma_etx
, txsize
, 1);
889 pr_info("RX descriptor ring:\n");
890 stmmac_display_ring((void *)priv
->dma_rx
, rxsize
, 0);
891 pr_info("TX descriptor ring:\n");
892 stmmac_display_ring((void *)priv
->dma_tx
, txsize
, 0);
896 static int stmmac_set_bfsize(int mtu
, int bufsize
)
900 if (mtu
>= BUF_SIZE_4KiB
)
902 else if (mtu
>= BUF_SIZE_2KiB
)
904 else if (mtu
> DEFAULT_BUFSIZE
)
907 ret
= DEFAULT_BUFSIZE
;
913 * stmmac_clear_descriptors: clear descriptors
914 * @priv: driver private structure
915 * Description: this function is called to clear the tx and rx descriptors
916 * in case of both basic and extended descriptors are used.
918 static void stmmac_clear_descriptors(struct stmmac_priv
*priv
)
921 unsigned int txsize
= priv
->dma_tx_size
;
922 unsigned int rxsize
= priv
->dma_rx_size
;
924 /* Clear the Rx/Tx descriptors */
925 for (i
= 0; i
< rxsize
; i
++)
926 if (priv
->extend_desc
)
927 priv
->hw
->desc
->init_rx_desc(&priv
->dma_erx
[i
].basic
,
928 priv
->use_riwt
, priv
->mode
,
931 priv
->hw
->desc
->init_rx_desc(&priv
->dma_rx
[i
],
932 priv
->use_riwt
, priv
->mode
,
934 for (i
= 0; i
< txsize
; i
++)
935 if (priv
->extend_desc
)
936 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
940 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
945 static int stmmac_init_rx_buffers(struct stmmac_priv
*priv
, struct dma_desc
*p
,
950 skb
= __netdev_alloc_skb(priv
->dev
, priv
->dma_buf_sz
+ NET_IP_ALIGN
,
953 pr_err("%s: Rx init fails; skb is NULL\n", __func__
);
956 skb_reserve(skb
, NET_IP_ALIGN
);
957 priv
->rx_skbuff
[i
] = skb
;
958 priv
->rx_skbuff_dma
[i
] = dma_map_single(priv
->device
, skb
->data
,
961 if (dma_mapping_error(priv
->device
, priv
->rx_skbuff_dma
[i
])) {
962 pr_err("%s: DMA mapping error\n", __func__
);
963 dev_kfree_skb_any(skb
);
967 p
->des2
= priv
->rx_skbuff_dma
[i
];
969 if ((priv
->hw
->mode
->init_desc3
) &&
970 (priv
->dma_buf_sz
== BUF_SIZE_16KiB
))
971 priv
->hw
->mode
->init_desc3(p
);
976 static void stmmac_free_rx_buffers(struct stmmac_priv
*priv
, int i
)
978 if (priv
->rx_skbuff
[i
]) {
979 dma_unmap_single(priv
->device
, priv
->rx_skbuff_dma
[i
],
980 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
981 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
983 priv
->rx_skbuff
[i
] = NULL
;
987 * init_dma_desc_rings - init the RX/TX descriptor rings
988 * @dev: net device structure
989 * Description: this function initializes the DMA RX/TX descriptors
990 * and allocates the socket buffers. It suppors the chained and ring
993 static int init_dma_desc_rings(struct net_device
*dev
)
996 struct stmmac_priv
*priv
= netdev_priv(dev
);
997 unsigned int txsize
= priv
->dma_tx_size
;
998 unsigned int rxsize
= priv
->dma_rx_size
;
999 unsigned int bfsize
= 0;
1002 if (priv
->hw
->mode
->set_16kib_bfsize
)
1003 bfsize
= priv
->hw
->mode
->set_16kib_bfsize(dev
->mtu
);
1005 if (bfsize
< BUF_SIZE_16KiB
)
1006 bfsize
= stmmac_set_bfsize(dev
->mtu
, priv
->dma_buf_sz
);
1008 priv
->dma_buf_sz
= bfsize
;
1010 if (netif_msg_probe(priv
))
1011 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__
,
1012 txsize
, rxsize
, bfsize
);
1014 if (netif_msg_probe(priv
)) {
1015 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__
,
1016 (u32
) priv
->dma_rx_phy
, (u32
) priv
->dma_tx_phy
);
1018 /* RX INITIALIZATION */
1019 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1021 for (i
= 0; i
< rxsize
; i
++) {
1023 if (priv
->extend_desc
)
1024 p
= &((priv
->dma_erx
+ i
)->basic
);
1026 p
= priv
->dma_rx
+ i
;
1028 ret
= stmmac_init_rx_buffers(priv
, p
, i
);
1030 goto err_init_rx_buffers
;
1032 if (netif_msg_probe(priv
))
1033 pr_debug("[%p]\t[%p]\t[%x]\n", priv
->rx_skbuff
[i
],
1034 priv
->rx_skbuff
[i
]->data
,
1035 (unsigned int)priv
->rx_skbuff_dma
[i
]);
1038 priv
->dirty_rx
= (unsigned int)(i
- rxsize
);
1041 /* Setup the chained descriptor addresses */
1042 if (priv
->mode
== STMMAC_CHAIN_MODE
) {
1043 if (priv
->extend_desc
) {
1044 priv
->hw
->mode
->init(priv
->dma_erx
, priv
->dma_rx_phy
,
1046 priv
->hw
->mode
->init(priv
->dma_etx
, priv
->dma_tx_phy
,
1049 priv
->hw
->mode
->init(priv
->dma_rx
, priv
->dma_rx_phy
,
1051 priv
->hw
->mode
->init(priv
->dma_tx
, priv
->dma_tx_phy
,
1056 /* TX INITIALIZATION */
1057 for (i
= 0; i
< txsize
; i
++) {
1059 if (priv
->extend_desc
)
1060 p
= &((priv
->dma_etx
+ i
)->basic
);
1062 p
= priv
->dma_tx
+ i
;
1064 priv
->tx_skbuff_dma
[i
] = 0;
1065 priv
->tx_skbuff
[i
] = NULL
;
1071 stmmac_clear_descriptors(priv
);
1073 if (netif_msg_hw(priv
))
1074 stmmac_display_rings(priv
);
1077 err_init_rx_buffers
:
1079 stmmac_free_rx_buffers(priv
, i
);
1083 static void dma_free_rx_skbufs(struct stmmac_priv
*priv
)
1087 for (i
= 0; i
< priv
->dma_rx_size
; i
++)
1088 stmmac_free_rx_buffers(priv
, i
);
1091 static void dma_free_tx_skbufs(struct stmmac_priv
*priv
)
1095 for (i
= 0; i
< priv
->dma_tx_size
; i
++) {
1098 if (priv
->extend_desc
)
1099 p
= &((priv
->dma_etx
+ i
)->basic
);
1101 p
= priv
->dma_tx
+ i
;
1103 if (priv
->tx_skbuff_dma
[i
]) {
1104 dma_unmap_single(priv
->device
,
1105 priv
->tx_skbuff_dma
[i
],
1106 priv
->hw
->desc
->get_tx_len(p
),
1108 priv
->tx_skbuff_dma
[i
] = 0;
1111 if (priv
->tx_skbuff
[i
] != NULL
) {
1112 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
1113 priv
->tx_skbuff
[i
] = NULL
;
1118 static int alloc_dma_desc_resources(struct stmmac_priv
*priv
)
1120 unsigned int txsize
= priv
->dma_tx_size
;
1121 unsigned int rxsize
= priv
->dma_rx_size
;
1124 priv
->rx_skbuff_dma
= kmalloc_array(rxsize
, sizeof(dma_addr_t
),
1126 if (!priv
->rx_skbuff_dma
)
1129 priv
->rx_skbuff
= kmalloc_array(rxsize
, sizeof(struct sk_buff
*),
1131 if (!priv
->rx_skbuff
)
1134 priv
->tx_skbuff_dma
= kmalloc_array(txsize
, sizeof(dma_addr_t
),
1136 if (!priv
->tx_skbuff_dma
)
1137 goto err_tx_skbuff_dma
;
1139 priv
->tx_skbuff
= kmalloc_array(txsize
, sizeof(struct sk_buff
*),
1141 if (!priv
->tx_skbuff
)
1144 if (priv
->extend_desc
) {
1145 priv
->dma_erx
= dma_alloc_coherent(priv
->device
, rxsize
*
1153 priv
->dma_etx
= dma_alloc_coherent(priv
->device
, txsize
*
1158 if (!priv
->dma_etx
) {
1159 dma_free_coherent(priv
->device
, priv
->dma_rx_size
*
1160 sizeof(struct dma_extended_desc
),
1161 priv
->dma_erx
, priv
->dma_rx_phy
);
1165 priv
->dma_rx
= dma_alloc_coherent(priv
->device
, rxsize
*
1166 sizeof(struct dma_desc
),
1172 priv
->dma_tx
= dma_alloc_coherent(priv
->device
, txsize
*
1173 sizeof(struct dma_desc
),
1176 if (!priv
->dma_tx
) {
1177 dma_free_coherent(priv
->device
, priv
->dma_rx_size
*
1178 sizeof(struct dma_desc
),
1179 priv
->dma_rx
, priv
->dma_rx_phy
);
1187 kfree(priv
->tx_skbuff
);
1189 kfree(priv
->tx_skbuff_dma
);
1191 kfree(priv
->rx_skbuff
);
1193 kfree(priv
->rx_skbuff_dma
);
1197 static void free_dma_desc_resources(struct stmmac_priv
*priv
)
1199 /* Release the DMA TX/RX socket buffers */
1200 dma_free_rx_skbufs(priv
);
1201 dma_free_tx_skbufs(priv
);
1203 /* Free DMA regions of consistent memory previously allocated */
1204 if (!priv
->extend_desc
) {
1205 dma_free_coherent(priv
->device
,
1206 priv
->dma_tx_size
* sizeof(struct dma_desc
),
1207 priv
->dma_tx
, priv
->dma_tx_phy
);
1208 dma_free_coherent(priv
->device
,
1209 priv
->dma_rx_size
* sizeof(struct dma_desc
),
1210 priv
->dma_rx
, priv
->dma_rx_phy
);
1212 dma_free_coherent(priv
->device
, priv
->dma_tx_size
*
1213 sizeof(struct dma_extended_desc
),
1214 priv
->dma_etx
, priv
->dma_tx_phy
);
1215 dma_free_coherent(priv
->device
, priv
->dma_rx_size
*
1216 sizeof(struct dma_extended_desc
),
1217 priv
->dma_erx
, priv
->dma_rx_phy
);
1219 kfree(priv
->rx_skbuff_dma
);
1220 kfree(priv
->rx_skbuff
);
1221 kfree(priv
->tx_skbuff_dma
);
1222 kfree(priv
->tx_skbuff
);
1226 * stmmac_dma_operation_mode - HW DMA operation mode
1227 * @priv: driver private structure
1228 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
1229 * or Store-And-Forward capability.
1231 static void stmmac_dma_operation_mode(struct stmmac_priv
*priv
)
1233 if (priv
->plat
->force_thresh_dma_mode
)
1234 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, tc
);
1235 else if (priv
->plat
->force_sf_dma_mode
|| priv
->plat
->tx_coe
) {
1237 * In case of GMAC, SF mode can be enabled
1238 * to perform the TX COE in HW. This depends on:
1239 * 1) TX COE if actually supported
1240 * 2) There is no bugged Jumbo frame support
1241 * that needs to not insert csum in the TDES.
1243 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, SF_DMA_MODE
, SF_DMA_MODE
);
1246 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, SF_DMA_MODE
);
1251 * @priv: driver private structure
1252 * Description: it reclaims resources after transmission completes.
1254 static void stmmac_tx_clean(struct stmmac_priv
*priv
)
1256 unsigned int txsize
= priv
->dma_tx_size
;
1258 spin_lock(&priv
->tx_lock
);
1260 priv
->xstats
.tx_clean
++;
1262 while (priv
->dirty_tx
!= priv
->cur_tx
) {
1264 unsigned int entry
= priv
->dirty_tx
% txsize
;
1265 struct sk_buff
*skb
= priv
->tx_skbuff
[entry
];
1268 if (priv
->extend_desc
)
1269 p
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1271 p
= priv
->dma_tx
+ entry
;
1273 /* Check if the descriptor is owned by the DMA. */
1274 if (priv
->hw
->desc
->get_tx_owner(p
))
1277 /* Verify tx error by looking at the last segment. */
1278 last
= priv
->hw
->desc
->get_tx_ls(p
);
1281 priv
->hw
->desc
->tx_status(&priv
->dev
->stats
,
1284 if (likely(tx_error
== 0)) {
1285 priv
->dev
->stats
.tx_packets
++;
1286 priv
->xstats
.tx_pkt_n
++;
1288 priv
->dev
->stats
.tx_errors
++;
1290 stmmac_get_tx_hwtstamp(priv
, entry
, skb
);
1292 if (netif_msg_tx_done(priv
))
1293 pr_debug("%s: curr %d, dirty %d\n", __func__
,
1294 priv
->cur_tx
, priv
->dirty_tx
);
1296 if (likely(priv
->tx_skbuff_dma
[entry
])) {
1297 dma_unmap_single(priv
->device
,
1298 priv
->tx_skbuff_dma
[entry
],
1299 priv
->hw
->desc
->get_tx_len(p
),
1301 priv
->tx_skbuff_dma
[entry
] = 0;
1303 priv
->hw
->mode
->clean_desc3(priv
, p
);
1305 if (likely(skb
!= NULL
)) {
1306 dev_consume_skb_any(skb
);
1307 priv
->tx_skbuff
[entry
] = NULL
;
1310 priv
->hw
->desc
->release_tx_desc(p
, priv
->mode
);
1314 if (unlikely(netif_queue_stopped(priv
->dev
) &&
1315 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH(priv
))) {
1316 netif_tx_lock(priv
->dev
);
1317 if (netif_queue_stopped(priv
->dev
) &&
1318 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH(priv
)) {
1319 if (netif_msg_tx_done(priv
))
1320 pr_debug("%s: restart transmit\n", __func__
);
1321 netif_wake_queue(priv
->dev
);
1323 netif_tx_unlock(priv
->dev
);
1326 if ((priv
->eee_enabled
) && (!priv
->tx_path_in_lpi_mode
)) {
1327 stmmac_enable_eee_mode(priv
);
1328 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
1330 spin_unlock(&priv
->tx_lock
);
1333 static inline void stmmac_enable_dma_irq(struct stmmac_priv
*priv
)
1335 priv
->hw
->dma
->enable_dma_irq(priv
->ioaddr
);
1338 static inline void stmmac_disable_dma_irq(struct stmmac_priv
*priv
)
1340 priv
->hw
->dma
->disable_dma_irq(priv
->ioaddr
);
1344 * stmmac_tx_err: irq tx error mng function
1345 * @priv: driver private structure
1346 * Description: it cleans the descriptors and restarts the transmission
1347 * in case of errors.
1349 static void stmmac_tx_err(struct stmmac_priv
*priv
)
1352 int txsize
= priv
->dma_tx_size
;
1353 netif_stop_queue(priv
->dev
);
1355 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1356 dma_free_tx_skbufs(priv
);
1357 for (i
= 0; i
< txsize
; i
++)
1358 if (priv
->extend_desc
)
1359 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
1363 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
1368 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1370 priv
->dev
->stats
.tx_errors
++;
1371 netif_wake_queue(priv
->dev
);
1375 * stmmac_dma_interrupt: DMA ISR
1376 * @priv: driver private structure
1377 * Description: this is the DMA ISR. It is called by the main ISR.
1378 * It calls the dwmac dma routine to understand which type of interrupt
1379 * happened. In case of there is a Normal interrupt and either TX or RX
1380 * interrupt happened so the NAPI is scheduled.
1382 static void stmmac_dma_interrupt(struct stmmac_priv
*priv
)
1386 status
= priv
->hw
->dma
->dma_interrupt(priv
->ioaddr
, &priv
->xstats
);
1387 if (likely((status
& handle_rx
)) || (status
& handle_tx
)) {
1388 if (likely(napi_schedule_prep(&priv
->napi
))) {
1389 stmmac_disable_dma_irq(priv
);
1390 __napi_schedule(&priv
->napi
);
1393 if (unlikely(status
& tx_hard_error_bump_tc
)) {
1394 /* Try to bump up the dma threshold on this failure */
1395 if (unlikely(tc
!= SF_DMA_MODE
) && (tc
<= 256)) {
1397 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, SF_DMA_MODE
);
1398 priv
->xstats
.threshold
= tc
;
1400 } else if (unlikely(status
== tx_hard_error
))
1401 stmmac_tx_err(priv
);
1405 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1406 * @priv: driver private structure
1407 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1409 static void stmmac_mmc_setup(struct stmmac_priv
*priv
)
1411 unsigned int mode
= MMC_CNTRL_RESET_ON_READ
| MMC_CNTRL_COUNTER_RESET
|
1412 MMC_CNTRL_PRESET
| MMC_CNTRL_FULL_HALF_PRESET
;
1414 dwmac_mmc_intr_all_mask(priv
->ioaddr
);
1416 if (priv
->dma_cap
.rmon
) {
1417 dwmac_mmc_ctrl(priv
->ioaddr
, mode
);
1418 memset(&priv
->mmc
, 0, sizeof(struct stmmac_counters
));
1420 pr_info(" No MAC Management Counters available\n");
1423 static u32
stmmac_get_synopsys_id(struct stmmac_priv
*priv
)
1425 u32 hwid
= priv
->hw
->synopsys_uid
;
1427 /* Check Synopsys Id (not available on old chips) */
1429 u32 uid
= ((hwid
& 0x0000ff00) >> 8);
1430 u32 synid
= (hwid
& 0x000000ff);
1432 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1441 * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1442 * @priv: driver private structure
1443 * Description: select the Enhanced/Alternate or Normal descriptors.
1444 * In case of Enhanced/Alternate, it looks at the extended descriptors are
1445 * supported by the HW cap. register.
1447 static void stmmac_selec_desc_mode(struct stmmac_priv
*priv
)
1449 if (priv
->plat
->enh_desc
) {
1450 pr_info(" Enhanced/Alternate descriptors\n");
1452 /* GMAC older than 3.50 has no extended descriptors */
1453 if (priv
->synopsys_id
>= DWMAC_CORE_3_50
) {
1454 pr_info("\tEnabled extended descriptors\n");
1455 priv
->extend_desc
= 1;
1457 pr_warn("Extended descriptors not supported\n");
1459 priv
->hw
->desc
= &enh_desc_ops
;
1461 pr_info(" Normal descriptors\n");
1462 priv
->hw
->desc
= &ndesc_ops
;
1467 * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1468 * @priv: driver private structure
1470 * new GMAC chip generations have a new register to indicate the
1471 * presence of the optional feature/functions.
1472 * This can be also used to override the value passed through the
1473 * platform and necessary for old MAC10/100 and GMAC chips.
1475 static int stmmac_get_hw_features(struct stmmac_priv
*priv
)
1479 if (priv
->hw
->dma
->get_hw_feature
) {
1480 hw_cap
= priv
->hw
->dma
->get_hw_feature(priv
->ioaddr
);
1482 priv
->dma_cap
.mbps_10_100
= (hw_cap
& DMA_HW_FEAT_MIISEL
);
1483 priv
->dma_cap
.mbps_1000
= (hw_cap
& DMA_HW_FEAT_GMIISEL
) >> 1;
1484 priv
->dma_cap
.half_duplex
= (hw_cap
& DMA_HW_FEAT_HDSEL
) >> 2;
1485 priv
->dma_cap
.hash_filter
= (hw_cap
& DMA_HW_FEAT_HASHSEL
) >> 4;
1486 priv
->dma_cap
.multi_addr
= (hw_cap
& DMA_HW_FEAT_ADDMAC
) >> 5;
1487 priv
->dma_cap
.pcs
= (hw_cap
& DMA_HW_FEAT_PCSSEL
) >> 6;
1488 priv
->dma_cap
.sma_mdio
= (hw_cap
& DMA_HW_FEAT_SMASEL
) >> 8;
1489 priv
->dma_cap
.pmt_remote_wake_up
=
1490 (hw_cap
& DMA_HW_FEAT_RWKSEL
) >> 9;
1491 priv
->dma_cap
.pmt_magic_frame
=
1492 (hw_cap
& DMA_HW_FEAT_MGKSEL
) >> 10;
1494 priv
->dma_cap
.rmon
= (hw_cap
& DMA_HW_FEAT_MMCSEL
) >> 11;
1495 /* IEEE 1588-2002 */
1496 priv
->dma_cap
.time_stamp
=
1497 (hw_cap
& DMA_HW_FEAT_TSVER1SEL
) >> 12;
1498 /* IEEE 1588-2008 */
1499 priv
->dma_cap
.atime_stamp
=
1500 (hw_cap
& DMA_HW_FEAT_TSVER2SEL
) >> 13;
1501 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1502 priv
->dma_cap
.eee
= (hw_cap
& DMA_HW_FEAT_EEESEL
) >> 14;
1503 priv
->dma_cap
.av
= (hw_cap
& DMA_HW_FEAT_AVSEL
) >> 15;
1504 /* TX and RX csum */
1505 priv
->dma_cap
.tx_coe
= (hw_cap
& DMA_HW_FEAT_TXCOESEL
) >> 16;
1506 priv
->dma_cap
.rx_coe_type1
=
1507 (hw_cap
& DMA_HW_FEAT_RXTYP1COE
) >> 17;
1508 priv
->dma_cap
.rx_coe_type2
=
1509 (hw_cap
& DMA_HW_FEAT_RXTYP2COE
) >> 18;
1510 priv
->dma_cap
.rxfifo_over_2048
=
1511 (hw_cap
& DMA_HW_FEAT_RXFIFOSIZE
) >> 19;
1512 /* TX and RX number of channels */
1513 priv
->dma_cap
.number_rx_channel
=
1514 (hw_cap
& DMA_HW_FEAT_RXCHCNT
) >> 20;
1515 priv
->dma_cap
.number_tx_channel
=
1516 (hw_cap
& DMA_HW_FEAT_TXCHCNT
) >> 22;
1517 /* Alternate (enhanced) DESC mode */
1518 priv
->dma_cap
.enh_desc
= (hw_cap
& DMA_HW_FEAT_ENHDESSEL
) >> 24;
1525 * stmmac_check_ether_addr: check if the MAC addr is valid
1526 * @priv: driver private structure
1528 * it is to verify if the MAC address is valid, in case of failures it
1529 * generates a random MAC address
1531 static void stmmac_check_ether_addr(struct stmmac_priv
*priv
)
1533 if (!is_valid_ether_addr(priv
->dev
->dev_addr
)) {
1534 priv
->hw
->mac
->get_umac_addr((void __iomem
*)
1535 priv
->dev
->base_addr
,
1536 priv
->dev
->dev_addr
, 0);
1537 if (!is_valid_ether_addr(priv
->dev
->dev_addr
))
1538 eth_hw_addr_random(priv
->dev
);
1539 pr_info("%s: device MAC address %pM\n", priv
->dev
->name
,
1540 priv
->dev
->dev_addr
);
1545 * stmmac_init_dma_engine: DMA init.
1546 * @priv: driver private structure
1548 * It inits the DMA invoking the specific MAC/GMAC callback.
1549 * Some DMA parameters can be passed from the platform;
1550 * in case of these are not passed a default is kept for the MAC or GMAC.
1552 static int stmmac_init_dma_engine(struct stmmac_priv
*priv
)
1554 int pbl
= DEFAULT_DMA_PBL
, fixed_burst
= 0, burst_len
= 0;
1555 int mixed_burst
= 0;
1558 if (priv
->plat
->dma_cfg
) {
1559 pbl
= priv
->plat
->dma_cfg
->pbl
;
1560 fixed_burst
= priv
->plat
->dma_cfg
->fixed_burst
;
1561 mixed_burst
= priv
->plat
->dma_cfg
->mixed_burst
;
1562 burst_len
= priv
->plat
->dma_cfg
->burst_len
;
1565 if (priv
->extend_desc
&& (priv
->mode
== STMMAC_RING_MODE
))
1568 return priv
->hw
->dma
->init(priv
->ioaddr
, pbl
, fixed_burst
, mixed_burst
,
1569 burst_len
, priv
->dma_tx_phy
,
1570 priv
->dma_rx_phy
, atds
);
1574 * stmmac_tx_timer: mitigation sw timer for tx.
1575 * @data: data pointer
1577 * This is the timer handler to directly invoke the stmmac_tx_clean.
1579 static void stmmac_tx_timer(unsigned long data
)
1581 struct stmmac_priv
*priv
= (struct stmmac_priv
*)data
;
1583 stmmac_tx_clean(priv
);
1587 * stmmac_init_tx_coalesce: init tx mitigation options.
1588 * @priv: driver private structure
1590 * This inits the transmit coalesce parameters: i.e. timer rate,
1591 * timer handler and default threshold used for enabling the
1592 * interrupt on completion bit.
1594 static void stmmac_init_tx_coalesce(struct stmmac_priv
*priv
)
1596 priv
->tx_coal_frames
= STMMAC_TX_FRAMES
;
1597 priv
->tx_coal_timer
= STMMAC_COAL_TX_TIMER
;
1598 init_timer(&priv
->txtimer
);
1599 priv
->txtimer
.expires
= STMMAC_COAL_TIMER(priv
->tx_coal_timer
);
1600 priv
->txtimer
.data
= (unsigned long)priv
;
1601 priv
->txtimer
.function
= stmmac_tx_timer
;
1602 add_timer(&priv
->txtimer
);
1606 * stmmac_hw_setup: setup mac in a usable state.
1607 * @dev : pointer to the device structure.
1609 * This function sets up the ip in a usable state.
1611 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1614 static int stmmac_hw_setup(struct net_device
*dev
)
1616 struct stmmac_priv
*priv
= netdev_priv(dev
);
1619 ret
= init_dma_desc_rings(dev
);
1621 pr_err("%s: DMA descriptors initialization failed\n", __func__
);
1624 /* DMA initialization and SW reset */
1625 ret
= stmmac_init_dma_engine(priv
);
1627 pr_err("%s: DMA engine initialization failed\n", __func__
);
1631 /* Copy the MAC addr into the HW */
1632 priv
->hw
->mac
->set_umac_addr(priv
->ioaddr
, dev
->dev_addr
, 0);
1634 /* If required, perform hw setup of the bus. */
1635 if (priv
->plat
->bus_setup
)
1636 priv
->plat
->bus_setup(priv
->ioaddr
);
1638 /* Initialize the MAC Core */
1639 priv
->hw
->mac
->core_init(priv
->ioaddr
, dev
->mtu
);
1641 /* Enable the MAC Rx/Tx */
1642 stmmac_set_mac(priv
->ioaddr
, true);
1644 /* Set the HW DMA mode and the COE */
1645 stmmac_dma_operation_mode(priv
);
1647 stmmac_mmc_setup(priv
);
1649 ret
= stmmac_init_ptp(priv
);
1650 if (ret
&& ret
!= -EOPNOTSUPP
)
1651 pr_warn("%s: failed PTP initialisation\n", __func__
);
1653 #ifdef CONFIG_STMMAC_DEBUG_FS
1654 ret
= stmmac_init_fs(dev
);
1656 pr_warn("%s: failed debugFS registration\n", __func__
);
1658 /* Start the ball rolling... */
1659 pr_debug("%s: DMA RX/TX processes started...\n", dev
->name
);
1660 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1661 priv
->hw
->dma
->start_rx(priv
->ioaddr
);
1663 /* Dump DMA/MAC registers */
1664 if (netif_msg_hw(priv
)) {
1665 priv
->hw
->mac
->dump_regs(priv
->ioaddr
);
1666 priv
->hw
->dma
->dump_regs(priv
->ioaddr
);
1668 priv
->tx_lpi_timer
= STMMAC_DEFAULT_TWT_LS
;
1670 priv
->eee_enabled
= stmmac_eee_init(priv
);
1672 stmmac_init_tx_coalesce(priv
);
1674 if ((priv
->use_riwt
) && (priv
->hw
->dma
->rx_watchdog
)) {
1675 priv
->rx_riwt
= MAX_DMA_RIWT
;
1676 priv
->hw
->dma
->rx_watchdog(priv
->ioaddr
, MAX_DMA_RIWT
);
1679 if (priv
->pcs
&& priv
->hw
->mac
->ctrl_ane
)
1680 priv
->hw
->mac
->ctrl_ane(priv
->ioaddr
, 0);
1686 * stmmac_open - open entry point of the driver
1687 * @dev : pointer to the device structure.
1689 * This function is the open entry point of the driver.
1691 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1694 static int stmmac_open(struct net_device
*dev
)
1696 struct stmmac_priv
*priv
= netdev_priv(dev
);
1699 stmmac_check_ether_addr(priv
);
1701 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
1702 priv
->pcs
!= STMMAC_PCS_RTBI
) {
1703 ret
= stmmac_init_phy(dev
);
1705 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1711 /* Extra statistics */
1712 memset(&priv
->xstats
, 0, sizeof(struct stmmac_extra_stats
));
1713 priv
->xstats
.threshold
= tc
;
1715 /* Create and initialize the TX/RX descriptors chains. */
1716 priv
->dma_tx_size
= STMMAC_ALIGN(dma_txsize
);
1717 priv
->dma_rx_size
= STMMAC_ALIGN(dma_rxsize
);
1718 priv
->dma_buf_sz
= STMMAC_ALIGN(buf_sz
);
1720 ret
= alloc_dma_desc_resources(priv
);
1722 pr_err("%s: DMA descriptors allocation failed\n", __func__
);
1723 goto dma_desc_error
;
1726 ret
= stmmac_hw_setup(dev
);
1728 pr_err("%s: Hw setup failed\n", __func__
);
1733 phy_start(priv
->phydev
);
1735 /* Request the IRQ lines */
1736 ret
= request_irq(dev
->irq
, stmmac_interrupt
,
1737 IRQF_SHARED
, dev
->name
, dev
);
1738 if (unlikely(ret
< 0)) {
1739 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1740 __func__
, dev
->irq
, ret
);
1744 /* Request the Wake IRQ in case of another line is used for WoL */
1745 if (priv
->wol_irq
!= dev
->irq
) {
1746 ret
= request_irq(priv
->wol_irq
, stmmac_interrupt
,
1747 IRQF_SHARED
, dev
->name
, dev
);
1748 if (unlikely(ret
< 0)) {
1749 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1750 __func__
, priv
->wol_irq
, ret
);
1755 /* Request the IRQ lines */
1756 if (priv
->lpi_irq
> 0) {
1757 ret
= request_irq(priv
->lpi_irq
, stmmac_interrupt
, IRQF_SHARED
,
1759 if (unlikely(ret
< 0)) {
1760 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1761 __func__
, priv
->lpi_irq
, ret
);
1766 napi_enable(&priv
->napi
);
1767 netif_start_queue(dev
);
1772 if (priv
->wol_irq
!= dev
->irq
)
1773 free_irq(priv
->wol_irq
, dev
);
1775 free_irq(dev
->irq
, dev
);
1778 free_dma_desc_resources(priv
);
1781 phy_disconnect(priv
->phydev
);
1787 * stmmac_release - close entry point of the driver
1788 * @dev : device pointer.
1790 * This is the stop entry point of the driver.
1792 static int stmmac_release(struct net_device
*dev
)
1794 struct stmmac_priv
*priv
= netdev_priv(dev
);
1796 if (priv
->eee_enabled
)
1797 del_timer_sync(&priv
->eee_ctrl_timer
);
1799 /* Stop and disconnect the PHY */
1801 phy_stop(priv
->phydev
);
1802 phy_disconnect(priv
->phydev
);
1803 priv
->phydev
= NULL
;
1806 netif_stop_queue(dev
);
1808 napi_disable(&priv
->napi
);
1810 del_timer_sync(&priv
->txtimer
);
1812 /* Free the IRQ lines */
1813 free_irq(dev
->irq
, dev
);
1814 if (priv
->wol_irq
!= dev
->irq
)
1815 free_irq(priv
->wol_irq
, dev
);
1816 if (priv
->lpi_irq
> 0)
1817 free_irq(priv
->lpi_irq
, dev
);
1819 /* Stop TX/RX DMA and clear the descriptors */
1820 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1821 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
1823 /* Release and free the Rx/Tx resources */
1824 free_dma_desc_resources(priv
);
1826 /* Disable the MAC Rx/Tx */
1827 stmmac_set_mac(priv
->ioaddr
, false);
1829 netif_carrier_off(dev
);
1831 #ifdef CONFIG_STMMAC_DEBUG_FS
1835 stmmac_release_ptp(priv
);
1841 * stmmac_xmit: Tx entry point of the driver
1842 * @skb : the socket buffer
1843 * @dev : device pointer
1844 * Description : this is the tx entry point of the driver.
1845 * It programs the chain or the ring and supports oversized frames
1848 static netdev_tx_t
stmmac_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1850 struct stmmac_priv
*priv
= netdev_priv(dev
);
1851 unsigned int txsize
= priv
->dma_tx_size
;
1853 int i
, csum_insertion
= 0, is_jumbo
= 0;
1854 int nfrags
= skb_shinfo(skb
)->nr_frags
;
1855 struct dma_desc
*desc
, *first
;
1856 unsigned int nopaged_len
= skb_headlen(skb
);
1857 unsigned int enh_desc
= priv
->plat
->enh_desc
;
1859 if (unlikely(stmmac_tx_avail(priv
) < nfrags
+ 1)) {
1860 if (!netif_queue_stopped(dev
)) {
1861 netif_stop_queue(dev
);
1862 /* This is a hard error, log it. */
1863 pr_err("%s: Tx Ring full when queue awake\n", __func__
);
1865 return NETDEV_TX_BUSY
;
1868 spin_lock(&priv
->tx_lock
);
1870 if (priv
->tx_path_in_lpi_mode
)
1871 stmmac_disable_eee_mode(priv
);
1873 entry
= priv
->cur_tx
% txsize
;
1875 csum_insertion
= (skb
->ip_summed
== CHECKSUM_PARTIAL
);
1877 if (priv
->extend_desc
)
1878 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1880 desc
= priv
->dma_tx
+ entry
;
1884 /* To program the descriptors according to the size of the frame */
1886 is_jumbo
= priv
->hw
->mode
->is_jumbo_frm(skb
->len
, enh_desc
);
1888 if (likely(!is_jumbo
)) {
1889 desc
->des2
= dma_map_single(priv
->device
, skb
->data
,
1890 nopaged_len
, DMA_TO_DEVICE
);
1891 priv
->tx_skbuff_dma
[entry
] = desc
->des2
;
1892 priv
->hw
->desc
->prepare_tx_desc(desc
, 1, nopaged_len
,
1893 csum_insertion
, priv
->mode
);
1896 entry
= priv
->hw
->mode
->jumbo_frm(priv
, skb
, csum_insertion
);
1899 for (i
= 0; i
< nfrags
; i
++) {
1900 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1901 int len
= skb_frag_size(frag
);
1903 priv
->tx_skbuff
[entry
] = NULL
;
1904 entry
= (++priv
->cur_tx
) % txsize
;
1905 if (priv
->extend_desc
)
1906 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1908 desc
= priv
->dma_tx
+ entry
;
1910 desc
->des2
= skb_frag_dma_map(priv
->device
, frag
, 0, len
,
1912 priv
->tx_skbuff_dma
[entry
] = desc
->des2
;
1913 priv
->hw
->desc
->prepare_tx_desc(desc
, 0, len
, csum_insertion
,
1916 priv
->hw
->desc
->set_tx_owner(desc
);
1920 priv
->tx_skbuff
[entry
] = skb
;
1922 /* Finalize the latest segment. */
1923 priv
->hw
->desc
->close_tx_desc(desc
);
1926 /* According to the coalesce parameter the IC bit for the latest
1927 * segment could be reset and the timer re-started to invoke the
1928 * stmmac_tx function. This approach takes care about the fragments.
1930 priv
->tx_count_frames
+= nfrags
+ 1;
1931 if (priv
->tx_coal_frames
> priv
->tx_count_frames
) {
1932 priv
->hw
->desc
->clear_tx_ic(desc
);
1933 priv
->xstats
.tx_reset_ic_bit
++;
1934 mod_timer(&priv
->txtimer
,
1935 STMMAC_COAL_TIMER(priv
->tx_coal_timer
));
1937 priv
->tx_count_frames
= 0;
1939 /* To avoid raise condition */
1940 priv
->hw
->desc
->set_tx_owner(first
);
1945 if (netif_msg_pktdata(priv
)) {
1946 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
1947 __func__
, (priv
->cur_tx
% txsize
),
1948 (priv
->dirty_tx
% txsize
), entry
, first
, nfrags
);
1950 if (priv
->extend_desc
)
1951 stmmac_display_ring((void *)priv
->dma_etx
, txsize
, 1);
1953 stmmac_display_ring((void *)priv
->dma_tx
, txsize
, 0);
1955 pr_debug(">>> frame to be transmitted: ");
1956 print_pkt(skb
->data
, skb
->len
);
1958 if (unlikely(stmmac_tx_avail(priv
) <= (MAX_SKB_FRAGS
+ 1))) {
1959 if (netif_msg_hw(priv
))
1960 pr_debug("%s: stop transmitted packets\n", __func__
);
1961 netif_stop_queue(dev
);
1964 dev
->stats
.tx_bytes
+= skb
->len
;
1966 if (unlikely((skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) &&
1967 priv
->hwts_tx_en
)) {
1968 /* declare that device is doing timestamping */
1969 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
1970 priv
->hw
->desc
->enable_tx_timestamp(first
);
1973 if (!priv
->hwts_tx_en
)
1974 skb_tx_timestamp(skb
);
1976 priv
->hw
->dma
->enable_dma_transmission(priv
->ioaddr
);
1978 spin_unlock(&priv
->tx_lock
);
1980 return NETDEV_TX_OK
;
1983 static void stmmac_rx_vlan(struct net_device
*dev
, struct sk_buff
*skb
)
1985 struct ethhdr
*ehdr
;
1988 if ((dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) ==
1989 NETIF_F_HW_VLAN_CTAG_RX
&&
1990 !__vlan_get_tag(skb
, &vlanid
)) {
1991 /* pop the vlan tag */
1992 ehdr
= (struct ethhdr
*)skb
->data
;
1993 memmove(skb
->data
+ VLAN_HLEN
, ehdr
, ETH_ALEN
* 2);
1994 skb_pull(skb
, VLAN_HLEN
);
1995 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vlanid
);
2001 * stmmac_rx_refill: refill used skb preallocated buffers
2002 * @priv: driver private structure
2003 * Description : this is to reallocate the skb for the reception process
2004 * that is based on zero-copy.
2006 static inline void stmmac_rx_refill(struct stmmac_priv
*priv
)
2008 unsigned int rxsize
= priv
->dma_rx_size
;
2009 int bfsize
= priv
->dma_buf_sz
;
2011 for (; priv
->cur_rx
- priv
->dirty_rx
> 0; priv
->dirty_rx
++) {
2012 unsigned int entry
= priv
->dirty_rx
% rxsize
;
2015 if (priv
->extend_desc
)
2016 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2018 p
= priv
->dma_rx
+ entry
;
2020 if (likely(priv
->rx_skbuff
[entry
] == NULL
)) {
2021 struct sk_buff
*skb
;
2023 skb
= netdev_alloc_skb_ip_align(priv
->dev
, bfsize
);
2025 if (unlikely(skb
== NULL
))
2028 priv
->rx_skbuff
[entry
] = skb
;
2029 priv
->rx_skbuff_dma
[entry
] =
2030 dma_map_single(priv
->device
, skb
->data
, bfsize
,
2033 p
->des2
= priv
->rx_skbuff_dma
[entry
];
2035 priv
->hw
->mode
->refill_desc3(priv
, p
);
2037 if (netif_msg_rx_status(priv
))
2038 pr_debug("\trefill entry #%d\n", entry
);
2041 priv
->hw
->desc
->set_rx_owner(p
);
2047 * stmmac_rx_refill: refill used skb preallocated buffers
2048 * @priv: driver private structure
2049 * @limit: napi bugget.
2050 * Description : this the function called by the napi poll method.
2051 * It gets all the frames inside the ring.
2053 static int stmmac_rx(struct stmmac_priv
*priv
, int limit
)
2055 unsigned int rxsize
= priv
->dma_rx_size
;
2056 unsigned int entry
= priv
->cur_rx
% rxsize
;
2057 unsigned int next_entry
;
2058 unsigned int count
= 0;
2059 int coe
= priv
->plat
->rx_coe
;
2061 if (netif_msg_rx_status(priv
)) {
2062 pr_debug("%s: descriptor ring:\n", __func__
);
2063 if (priv
->extend_desc
)
2064 stmmac_display_ring((void *)priv
->dma_erx
, rxsize
, 1);
2066 stmmac_display_ring((void *)priv
->dma_rx
, rxsize
, 0);
2068 while (count
< limit
) {
2072 if (priv
->extend_desc
)
2073 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2075 p
= priv
->dma_rx
+ entry
;
2077 if (priv
->hw
->desc
->get_rx_owner(p
))
2082 next_entry
= (++priv
->cur_rx
) % rxsize
;
2083 if (priv
->extend_desc
)
2084 prefetch(priv
->dma_erx
+ next_entry
);
2086 prefetch(priv
->dma_rx
+ next_entry
);
2088 /* read the status of the incoming frame */
2089 status
= priv
->hw
->desc
->rx_status(&priv
->dev
->stats
,
2091 if ((priv
->extend_desc
) && (priv
->hw
->desc
->rx_extended_status
))
2092 priv
->hw
->desc
->rx_extended_status(&priv
->dev
->stats
,
2096 if (unlikely(status
== discard_frame
)) {
2097 priv
->dev
->stats
.rx_errors
++;
2098 if (priv
->hwts_rx_en
&& !priv
->extend_desc
) {
2099 /* DESC2 & DESC3 will be overwitten by device
2100 * with timestamp value, hence reinitialize
2101 * them in stmmac_rx_refill() function so that
2102 * device can reuse it.
2104 priv
->rx_skbuff
[entry
] = NULL
;
2105 dma_unmap_single(priv
->device
,
2106 priv
->rx_skbuff_dma
[entry
],
2111 struct sk_buff
*skb
;
2114 frame_len
= priv
->hw
->desc
->get_rx_frame_len(p
, coe
);
2116 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2117 * Type frames (LLC/LLC-SNAP)
2119 if (unlikely(status
!= llc_snap
))
2120 frame_len
-= ETH_FCS_LEN
;
2122 if (netif_msg_rx_status(priv
)) {
2123 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2125 if (frame_len
> ETH_FRAME_LEN
)
2126 pr_debug("\tframe size %d, COE: %d\n",
2129 skb
= priv
->rx_skbuff
[entry
];
2130 if (unlikely(!skb
)) {
2131 pr_err("%s: Inconsistent Rx descriptor chain\n",
2133 priv
->dev
->stats
.rx_dropped
++;
2136 prefetch(skb
->data
- NET_IP_ALIGN
);
2137 priv
->rx_skbuff
[entry
] = NULL
;
2139 stmmac_get_rx_hwtstamp(priv
, entry
, skb
);
2141 skb_put(skb
, frame_len
);
2142 dma_unmap_single(priv
->device
,
2143 priv
->rx_skbuff_dma
[entry
],
2144 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
2146 if (netif_msg_pktdata(priv
)) {
2147 pr_debug("frame received (%dbytes)", frame_len
);
2148 print_pkt(skb
->data
, frame_len
);
2151 stmmac_rx_vlan(priv
->dev
, skb
);
2153 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
2156 skb_checksum_none_assert(skb
);
2158 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2160 napi_gro_receive(&priv
->napi
, skb
);
2162 priv
->dev
->stats
.rx_packets
++;
2163 priv
->dev
->stats
.rx_bytes
+= frame_len
;
2168 stmmac_rx_refill(priv
);
2170 priv
->xstats
.rx_pkt_n
+= count
;
2176 * stmmac_poll - stmmac poll method (NAPI)
2177 * @napi : pointer to the napi structure.
2178 * @budget : maximum number of packets that the current CPU can receive from
2181 * To look at the incoming frames and clear the tx resources.
2183 static int stmmac_poll(struct napi_struct
*napi
, int budget
)
2185 struct stmmac_priv
*priv
= container_of(napi
, struct stmmac_priv
, napi
);
2188 priv
->xstats
.napi_poll
++;
2189 stmmac_tx_clean(priv
);
2191 work_done
= stmmac_rx(priv
, budget
);
2192 if (work_done
< budget
) {
2193 napi_complete(napi
);
2194 stmmac_enable_dma_irq(priv
);
2201 * @dev : Pointer to net device structure
2202 * Description: this function is called when a packet transmission fails to
2203 * complete within a reasonable time. The driver will mark the error in the
2204 * netdev structure and arrange for the device to be reset to a sane state
2205 * in order to transmit a new packet.
2207 static void stmmac_tx_timeout(struct net_device
*dev
)
2209 struct stmmac_priv
*priv
= netdev_priv(dev
);
2211 /* Clear Tx resources and restart transmitting again */
2212 stmmac_tx_err(priv
);
2216 * stmmac_set_rx_mode - entry point for multicast addressing
2217 * @dev : pointer to the device structure
2219 * This function is a driver entry point which gets called by the kernel
2220 * whenever multicast addresses must be enabled/disabled.
2224 static void stmmac_set_rx_mode(struct net_device
*dev
)
2226 struct stmmac_priv
*priv
= netdev_priv(dev
);
2228 spin_lock(&priv
->lock
);
2229 priv
->hw
->mac
->set_filter(dev
, priv
->synopsys_id
);
2230 spin_unlock(&priv
->lock
);
2234 * stmmac_change_mtu - entry point to change MTU size for the device.
2235 * @dev : device pointer.
2236 * @new_mtu : the new MTU size for the device.
2237 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2238 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2239 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2241 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2244 static int stmmac_change_mtu(struct net_device
*dev
, int new_mtu
)
2246 struct stmmac_priv
*priv
= netdev_priv(dev
);
2249 if (netif_running(dev
)) {
2250 pr_err("%s: must be stopped to change its MTU\n", dev
->name
);
2254 if (priv
->plat
->enh_desc
)
2255 max_mtu
= JUMBO_LEN
;
2257 max_mtu
= SKB_MAX_HEAD(NET_SKB_PAD
+ NET_IP_ALIGN
);
2259 if (priv
->plat
->maxmtu
< max_mtu
)
2260 max_mtu
= priv
->plat
->maxmtu
;
2262 if ((new_mtu
< 46) || (new_mtu
> max_mtu
)) {
2263 pr_err("%s: invalid MTU, max MTU is: %d\n", dev
->name
, max_mtu
);
2268 netdev_update_features(dev
);
2273 static netdev_features_t
stmmac_fix_features(struct net_device
*dev
,
2274 netdev_features_t features
)
2276 struct stmmac_priv
*priv
= netdev_priv(dev
);
2278 if (priv
->plat
->rx_coe
== STMMAC_RX_COE_NONE
)
2279 features
&= ~NETIF_F_RXCSUM
;
2280 else if (priv
->plat
->rx_coe
== STMMAC_RX_COE_TYPE1
)
2281 features
&= ~NETIF_F_IPV6_CSUM
;
2282 if (!priv
->plat
->tx_coe
)
2283 features
&= ~NETIF_F_ALL_CSUM
;
2285 /* Some GMAC devices have a bugged Jumbo frame support that
2286 * needs to have the Tx COE disabled for oversized frames
2287 * (due to limited buffer sizes). In this case we disable
2288 * the TX csum insertionin the TDES and not use SF.
2290 if (priv
->plat
->bugged_jumbo
&& (dev
->mtu
> ETH_DATA_LEN
))
2291 features
&= ~NETIF_F_ALL_CSUM
;
2297 * stmmac_interrupt - main ISR
2298 * @irq: interrupt number.
2299 * @dev_id: to pass the net device pointer.
2300 * Description: this is the main driver interrupt service routine.
2301 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2304 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
)
2306 struct net_device
*dev
= (struct net_device
*)dev_id
;
2307 struct stmmac_priv
*priv
= netdev_priv(dev
);
2310 pm_wakeup_event(priv
->device
, 0);
2312 if (unlikely(!dev
)) {
2313 pr_err("%s: invalid dev pointer\n", __func__
);
2317 /* To handle GMAC own interrupts */
2318 if (priv
->plat
->has_gmac
) {
2319 int status
= priv
->hw
->mac
->host_irq_status((void __iomem
*)
2322 if (unlikely(status
)) {
2323 /* For LPI we need to save the tx status */
2324 if (status
& CORE_IRQ_TX_PATH_IN_LPI_MODE
)
2325 priv
->tx_path_in_lpi_mode
= true;
2326 if (status
& CORE_IRQ_TX_PATH_EXIT_LPI_MODE
)
2327 priv
->tx_path_in_lpi_mode
= false;
2331 /* To handle DMA interrupts */
2332 stmmac_dma_interrupt(priv
);
2337 #ifdef CONFIG_NET_POLL_CONTROLLER
2338 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2339 * to allow network I/O with interrupts disabled.
2341 static void stmmac_poll_controller(struct net_device
*dev
)
2343 disable_irq(dev
->irq
);
2344 stmmac_interrupt(dev
->irq
, dev
);
2345 enable_irq(dev
->irq
);
2350 * stmmac_ioctl - Entry point for the Ioctl
2351 * @dev: Device pointer.
2352 * @rq: An IOCTL specefic structure, that can contain a pointer to
2353 * a proprietary structure used to pass information to the driver.
2354 * @cmd: IOCTL command
2356 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2358 static int stmmac_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2360 struct stmmac_priv
*priv
= netdev_priv(dev
);
2361 int ret
= -EOPNOTSUPP
;
2363 if (!netif_running(dev
))
2372 ret
= phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
2375 ret
= stmmac_hwtstamp_ioctl(dev
, rq
);
2384 #ifdef CONFIG_STMMAC_DEBUG_FS
2385 static struct dentry
*stmmac_fs_dir
;
2386 static struct dentry
*stmmac_rings_status
;
2387 static struct dentry
*stmmac_dma_cap
;
2389 static void sysfs_display_ring(void *head
, int size
, int extend_desc
,
2390 struct seq_file
*seq
)
2393 struct dma_extended_desc
*ep
= (struct dma_extended_desc
*)head
;
2394 struct dma_desc
*p
= (struct dma_desc
*)head
;
2396 for (i
= 0; i
< size
; i
++) {
2400 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2401 i
, (unsigned int)virt_to_phys(ep
),
2402 (unsigned int)x
, (unsigned int)(x
>> 32),
2403 ep
->basic
.des2
, ep
->basic
.des3
);
2407 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2408 i
, (unsigned int)virt_to_phys(ep
),
2409 (unsigned int)x
, (unsigned int)(x
>> 32),
2413 seq_printf(seq
, "\n");
2417 static int stmmac_sysfs_ring_read(struct seq_file
*seq
, void *v
)
2419 struct net_device
*dev
= seq
->private;
2420 struct stmmac_priv
*priv
= netdev_priv(dev
);
2421 unsigned int txsize
= priv
->dma_tx_size
;
2422 unsigned int rxsize
= priv
->dma_rx_size
;
2424 if (priv
->extend_desc
) {
2425 seq_printf(seq
, "Extended RX descriptor ring:\n");
2426 sysfs_display_ring((void *)priv
->dma_erx
, rxsize
, 1, seq
);
2427 seq_printf(seq
, "Extended TX descriptor ring:\n");
2428 sysfs_display_ring((void *)priv
->dma_etx
, txsize
, 1, seq
);
2430 seq_printf(seq
, "RX descriptor ring:\n");
2431 sysfs_display_ring((void *)priv
->dma_rx
, rxsize
, 0, seq
);
2432 seq_printf(seq
, "TX descriptor ring:\n");
2433 sysfs_display_ring((void *)priv
->dma_tx
, txsize
, 0, seq
);
2439 static int stmmac_sysfs_ring_open(struct inode
*inode
, struct file
*file
)
2441 return single_open(file
, stmmac_sysfs_ring_read
, inode
->i_private
);
2444 static const struct file_operations stmmac_rings_status_fops
= {
2445 .owner
= THIS_MODULE
,
2446 .open
= stmmac_sysfs_ring_open
,
2448 .llseek
= seq_lseek
,
2449 .release
= single_release
,
2452 static int stmmac_sysfs_dma_cap_read(struct seq_file
*seq
, void *v
)
2454 struct net_device
*dev
= seq
->private;
2455 struct stmmac_priv
*priv
= netdev_priv(dev
);
2457 if (!priv
->hw_cap_support
) {
2458 seq_printf(seq
, "DMA HW features not supported\n");
2462 seq_printf(seq
, "==============================\n");
2463 seq_printf(seq
, "\tDMA HW features\n");
2464 seq_printf(seq
, "==============================\n");
2466 seq_printf(seq
, "\t10/100 Mbps %s\n",
2467 (priv
->dma_cap
.mbps_10_100
) ? "Y" : "N");
2468 seq_printf(seq
, "\t1000 Mbps %s\n",
2469 (priv
->dma_cap
.mbps_1000
) ? "Y" : "N");
2470 seq_printf(seq
, "\tHalf duple %s\n",
2471 (priv
->dma_cap
.half_duplex
) ? "Y" : "N");
2472 seq_printf(seq
, "\tHash Filter: %s\n",
2473 (priv
->dma_cap
.hash_filter
) ? "Y" : "N");
2474 seq_printf(seq
, "\tMultiple MAC address registers: %s\n",
2475 (priv
->dma_cap
.multi_addr
) ? "Y" : "N");
2476 seq_printf(seq
, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2477 (priv
->dma_cap
.pcs
) ? "Y" : "N");
2478 seq_printf(seq
, "\tSMA (MDIO) Interface: %s\n",
2479 (priv
->dma_cap
.sma_mdio
) ? "Y" : "N");
2480 seq_printf(seq
, "\tPMT Remote wake up: %s\n",
2481 (priv
->dma_cap
.pmt_remote_wake_up
) ? "Y" : "N");
2482 seq_printf(seq
, "\tPMT Magic Frame: %s\n",
2483 (priv
->dma_cap
.pmt_magic_frame
) ? "Y" : "N");
2484 seq_printf(seq
, "\tRMON module: %s\n",
2485 (priv
->dma_cap
.rmon
) ? "Y" : "N");
2486 seq_printf(seq
, "\tIEEE 1588-2002 Time Stamp: %s\n",
2487 (priv
->dma_cap
.time_stamp
) ? "Y" : "N");
2488 seq_printf(seq
, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2489 (priv
->dma_cap
.atime_stamp
) ? "Y" : "N");
2490 seq_printf(seq
, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2491 (priv
->dma_cap
.eee
) ? "Y" : "N");
2492 seq_printf(seq
, "\tAV features: %s\n", (priv
->dma_cap
.av
) ? "Y" : "N");
2493 seq_printf(seq
, "\tChecksum Offload in TX: %s\n",
2494 (priv
->dma_cap
.tx_coe
) ? "Y" : "N");
2495 seq_printf(seq
, "\tIP Checksum Offload (type1) in RX: %s\n",
2496 (priv
->dma_cap
.rx_coe_type1
) ? "Y" : "N");
2497 seq_printf(seq
, "\tIP Checksum Offload (type2) in RX: %s\n",
2498 (priv
->dma_cap
.rx_coe_type2
) ? "Y" : "N");
2499 seq_printf(seq
, "\tRXFIFO > 2048bytes: %s\n",
2500 (priv
->dma_cap
.rxfifo_over_2048
) ? "Y" : "N");
2501 seq_printf(seq
, "\tNumber of Additional RX channel: %d\n",
2502 priv
->dma_cap
.number_rx_channel
);
2503 seq_printf(seq
, "\tNumber of Additional TX channel: %d\n",
2504 priv
->dma_cap
.number_tx_channel
);
2505 seq_printf(seq
, "\tEnhanced descriptors: %s\n",
2506 (priv
->dma_cap
.enh_desc
) ? "Y" : "N");
2511 static int stmmac_sysfs_dma_cap_open(struct inode
*inode
, struct file
*file
)
2513 return single_open(file
, stmmac_sysfs_dma_cap_read
, inode
->i_private
);
2516 static const struct file_operations stmmac_dma_cap_fops
= {
2517 .owner
= THIS_MODULE
,
2518 .open
= stmmac_sysfs_dma_cap_open
,
2520 .llseek
= seq_lseek
,
2521 .release
= single_release
,
2524 static int stmmac_init_fs(struct net_device
*dev
)
2526 /* Create debugfs entries */
2527 stmmac_fs_dir
= debugfs_create_dir(STMMAC_RESOURCE_NAME
, NULL
);
2529 if (!stmmac_fs_dir
|| IS_ERR(stmmac_fs_dir
)) {
2530 pr_err("ERROR %s, debugfs create directory failed\n",
2531 STMMAC_RESOURCE_NAME
);
2536 /* Entry to report DMA RX/TX rings */
2537 stmmac_rings_status
= debugfs_create_file("descriptors_status",
2538 S_IRUGO
, stmmac_fs_dir
, dev
,
2539 &stmmac_rings_status_fops
);
2541 if (!stmmac_rings_status
|| IS_ERR(stmmac_rings_status
)) {
2542 pr_info("ERROR creating stmmac ring debugfs file\n");
2543 debugfs_remove(stmmac_fs_dir
);
2548 /* Entry to report the DMA HW features */
2549 stmmac_dma_cap
= debugfs_create_file("dma_cap", S_IRUGO
, stmmac_fs_dir
,
2550 dev
, &stmmac_dma_cap_fops
);
2552 if (!stmmac_dma_cap
|| IS_ERR(stmmac_dma_cap
)) {
2553 pr_info("ERROR creating stmmac MMC debugfs file\n");
2554 debugfs_remove(stmmac_rings_status
);
2555 debugfs_remove(stmmac_fs_dir
);
2563 static void stmmac_exit_fs(void)
2565 debugfs_remove(stmmac_rings_status
);
2566 debugfs_remove(stmmac_dma_cap
);
2567 debugfs_remove(stmmac_fs_dir
);
2569 #endif /* CONFIG_STMMAC_DEBUG_FS */
2571 static const struct net_device_ops stmmac_netdev_ops
= {
2572 .ndo_open
= stmmac_open
,
2573 .ndo_start_xmit
= stmmac_xmit
,
2574 .ndo_stop
= stmmac_release
,
2575 .ndo_change_mtu
= stmmac_change_mtu
,
2576 .ndo_fix_features
= stmmac_fix_features
,
2577 .ndo_set_rx_mode
= stmmac_set_rx_mode
,
2578 .ndo_tx_timeout
= stmmac_tx_timeout
,
2579 .ndo_do_ioctl
= stmmac_ioctl
,
2580 #ifdef CONFIG_NET_POLL_CONTROLLER
2581 .ndo_poll_controller
= stmmac_poll_controller
,
2583 .ndo_set_mac_address
= eth_mac_addr
,
2587 * stmmac_hw_init - Init the MAC device
2588 * @priv: driver private structure
2589 * Description: this function detects which MAC device
2590 * (GMAC/MAC10-100) has to attached, checks the HW capability
2591 * (if supported) and sets the driver's features (for example
2592 * to use the ring or chaine mode or support the normal/enh
2593 * descriptor structure).
2595 static int stmmac_hw_init(struct stmmac_priv
*priv
)
2598 struct mac_device_info
*mac
;
2600 /* Identify the MAC HW device */
2601 if (priv
->plat
->has_gmac
) {
2602 priv
->dev
->priv_flags
|= IFF_UNICAST_FLT
;
2603 mac
= dwmac1000_setup(priv
->ioaddr
);
2605 mac
= dwmac100_setup(priv
->ioaddr
);
2612 /* Get and dump the chip ID */
2613 priv
->synopsys_id
= stmmac_get_synopsys_id(priv
);
2615 /* To use the chained or ring mode */
2617 priv
->hw
->mode
= &chain_mode_ops
;
2618 pr_info(" Chain mode enabled\n");
2619 priv
->mode
= STMMAC_CHAIN_MODE
;
2621 priv
->hw
->mode
= &ring_mode_ops
;
2622 pr_info(" Ring mode enabled\n");
2623 priv
->mode
= STMMAC_RING_MODE
;
2626 /* Get the HW capability (new GMAC newer than 3.50a) */
2627 priv
->hw_cap_support
= stmmac_get_hw_features(priv
);
2628 if (priv
->hw_cap_support
) {
2629 pr_info(" DMA HW capability register supported");
2631 /* We can override some gmac/dma configuration fields: e.g.
2632 * enh_desc, tx_coe (e.g. that are passed through the
2633 * platform) with the values from the HW capability
2634 * register (if supported).
2636 priv
->plat
->enh_desc
= priv
->dma_cap
.enh_desc
;
2637 priv
->plat
->pmt
= priv
->dma_cap
.pmt_remote_wake_up
;
2639 priv
->plat
->tx_coe
= priv
->dma_cap
.tx_coe
;
2641 if (priv
->dma_cap
.rx_coe_type2
)
2642 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE2
;
2643 else if (priv
->dma_cap
.rx_coe_type1
)
2644 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE1
;
2647 pr_info(" No HW DMA feature register supported");
2649 /* To use alternate (extended) or normal descriptor structures */
2650 stmmac_selec_desc_mode(priv
);
2652 ret
= priv
->hw
->mac
->rx_ipc(priv
->ioaddr
);
2654 pr_warn(" RX IPC Checksum Offload not configured.\n");
2655 priv
->plat
->rx_coe
= STMMAC_RX_COE_NONE
;
2658 if (priv
->plat
->rx_coe
)
2659 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2660 priv
->plat
->rx_coe
);
2661 if (priv
->plat
->tx_coe
)
2662 pr_info(" TX Checksum insertion supported\n");
2664 if (priv
->plat
->pmt
) {
2665 pr_info(" Wake-Up On Lan supported\n");
2666 device_set_wakeup_capable(priv
->device
, 1);
2674 * @device: device pointer
2675 * @plat_dat: platform data pointer
2676 * @addr: iobase memory address
2677 * Description: this is the main probe function used to
2678 * call the alloc_etherdev, allocate the priv structure.
2680 struct stmmac_priv
*stmmac_dvr_probe(struct device
*device
,
2681 struct plat_stmmacenet_data
*plat_dat
,
2685 struct net_device
*ndev
= NULL
;
2686 struct stmmac_priv
*priv
;
2688 ndev
= alloc_etherdev(sizeof(struct stmmac_priv
));
2692 SET_NETDEV_DEV(ndev
, device
);
2694 priv
= netdev_priv(ndev
);
2695 priv
->device
= device
;
2700 stmmac_set_ethtool_ops(ndev
);
2701 priv
->pause
= pause
;
2702 priv
->plat
= plat_dat
;
2703 priv
->ioaddr
= addr
;
2704 priv
->dev
->base_addr
= (unsigned long)addr
;
2706 /* Verify driver arguments */
2707 stmmac_verify_args();
2709 /* Override with kernel parameters if supplied XXX CRS XXX
2710 * this needs to have multiple instances
2712 if ((phyaddr
>= 0) && (phyaddr
<= 31))
2713 priv
->plat
->phy_addr
= phyaddr
;
2715 priv
->stmmac_clk
= devm_clk_get(priv
->device
, STMMAC_RESOURCE_NAME
);
2716 if (IS_ERR(priv
->stmmac_clk
)) {
2717 dev_warn(priv
->device
, "%s: warning: cannot get CSR clock\n",
2719 ret
= PTR_ERR(priv
->stmmac_clk
);
2722 clk_prepare_enable(priv
->stmmac_clk
);
2724 priv
->stmmac_rst
= devm_reset_control_get(priv
->device
,
2725 STMMAC_RESOURCE_NAME
);
2726 if (IS_ERR(priv
->stmmac_rst
)) {
2727 if (PTR_ERR(priv
->stmmac_rst
) == -EPROBE_DEFER
) {
2728 ret
= -EPROBE_DEFER
;
2731 dev_info(priv
->device
, "no reset control found\n");
2732 priv
->stmmac_rst
= NULL
;
2734 if (priv
->stmmac_rst
)
2735 reset_control_deassert(priv
->stmmac_rst
);
2737 /* Init MAC and get the capabilities */
2738 ret
= stmmac_hw_init(priv
);
2742 ndev
->netdev_ops
= &stmmac_netdev_ops
;
2744 ndev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
2746 ndev
->features
|= ndev
->hw_features
| NETIF_F_HIGHDMA
;
2747 ndev
->watchdog_timeo
= msecs_to_jiffies(watchdog
);
2748 #ifdef STMMAC_VLAN_TAG_USED
2749 /* Both mac100 and gmac support receive VLAN tag detection */
2750 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_RX
;
2752 priv
->msg_enable
= netif_msg_init(debug
, default_msg_level
);
2755 priv
->flow_ctrl
= FLOW_AUTO
; /* RX/TX pause on */
2757 /* Rx Watchdog is available in the COREs newer than the 3.40.
2758 * In some case, for example on bugged HW this feature
2759 * has to be disable and this can be done by passing the
2760 * riwt_off field from the platform.
2762 if ((priv
->synopsys_id
>= DWMAC_CORE_3_50
) && (!priv
->plat
->riwt_off
)) {
2764 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2767 netif_napi_add(ndev
, &priv
->napi
, stmmac_poll
, 64);
2769 spin_lock_init(&priv
->lock
);
2770 spin_lock_init(&priv
->tx_lock
);
2772 ret
= register_netdev(ndev
);
2774 pr_err("%s: ERROR %i registering the device\n", __func__
, ret
);
2775 goto error_netdev_register
;
2778 /* If a specific clk_csr value is passed from the platform
2779 * this means that the CSR Clock Range selection cannot be
2780 * changed at run-time and it is fixed. Viceversa the driver'll try to
2781 * set the MDC clock dynamically according to the csr actual
2784 if (!priv
->plat
->clk_csr
)
2785 stmmac_clk_csr_set(priv
);
2787 priv
->clk_csr
= priv
->plat
->clk_csr
;
2789 stmmac_check_pcs_mode(priv
);
2791 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
2792 priv
->pcs
!= STMMAC_PCS_RTBI
) {
2793 /* MDIO bus Registration */
2794 ret
= stmmac_mdio_register(ndev
);
2796 pr_debug("%s: MDIO bus (id: %d) registration failed",
2797 __func__
, priv
->plat
->bus_id
);
2798 goto error_mdio_register
;
2804 error_mdio_register
:
2805 unregister_netdev(ndev
);
2806 error_netdev_register
:
2807 netif_napi_del(&priv
->napi
);
2809 clk_disable_unprepare(priv
->stmmac_clk
);
2813 return ERR_PTR(ret
);
2818 * @ndev: net device pointer
2819 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2820 * changes the link status, releases the DMA descriptor rings.
2822 int stmmac_dvr_remove(struct net_device
*ndev
)
2824 struct stmmac_priv
*priv
= netdev_priv(ndev
);
2826 pr_info("%s:\n\tremoving driver", __func__
);
2828 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
2829 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
2831 stmmac_set_mac(priv
->ioaddr
, false);
2832 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
2833 priv
->pcs
!= STMMAC_PCS_RTBI
)
2834 stmmac_mdio_unregister(ndev
);
2835 netif_carrier_off(ndev
);
2836 unregister_netdev(ndev
);
2837 if (priv
->stmmac_rst
)
2838 reset_control_assert(priv
->stmmac_rst
);
2839 clk_disable_unprepare(priv
->stmmac_clk
);
2846 int stmmac_suspend(struct net_device
*ndev
)
2848 struct stmmac_priv
*priv
= netdev_priv(ndev
);
2849 unsigned long flags
;
2851 if (!ndev
|| !netif_running(ndev
))
2855 phy_stop(priv
->phydev
);
2857 spin_lock_irqsave(&priv
->lock
, flags
);
2859 netif_device_detach(ndev
);
2860 netif_stop_queue(ndev
);
2862 napi_disable(&priv
->napi
);
2864 /* Stop TX/RX DMA */
2865 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
2866 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
2868 stmmac_clear_descriptors(priv
);
2870 /* Enable Power down mode by programming the PMT regs */
2871 if (device_may_wakeup(priv
->device
)) {
2872 priv
->hw
->mac
->pmt(priv
->ioaddr
, priv
->wolopts
);
2875 stmmac_set_mac(priv
->ioaddr
, false);
2876 pinctrl_pm_select_sleep_state(priv
->device
);
2877 /* Disable clock in case of PWM is off */
2878 clk_disable_unprepare(priv
->stmmac_clk
);
2880 spin_unlock_irqrestore(&priv
->lock
, flags
);
2884 int stmmac_resume(struct net_device
*ndev
)
2886 struct stmmac_priv
*priv
= netdev_priv(ndev
);
2887 unsigned long flags
;
2889 if (!netif_running(ndev
))
2892 spin_lock_irqsave(&priv
->lock
, flags
);
2894 /* Power Down bit, into the PM register, is cleared
2895 * automatically as soon as a magic packet or a Wake-up frame
2896 * is received. Anyway, it's better to manually clear
2897 * this bit because it can generate problems while resuming
2898 * from another devices (e.g. serial console).
2900 if (device_may_wakeup(priv
->device
)) {
2901 priv
->hw
->mac
->pmt(priv
->ioaddr
, 0);
2904 pinctrl_pm_select_default_state(priv
->device
);
2905 /* enable the clk prevously disabled */
2906 clk_prepare_enable(priv
->stmmac_clk
);
2907 /* reset the phy so that it's ready */
2909 stmmac_mdio_reset(priv
->mii
);
2912 netif_device_attach(ndev
);
2914 stmmac_hw_setup(ndev
);
2916 napi_enable(&priv
->napi
);
2918 netif_start_queue(ndev
);
2920 spin_unlock_irqrestore(&priv
->lock
, flags
);
2923 phy_start(priv
->phydev
);
2927 #endif /* CONFIG_PM */
2929 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2930 * depending on the configuration selected.
2932 static int __init
stmmac_init(void)
2936 ret
= stmmac_register_platform();
2939 ret
= stmmac_register_pci();
2944 stmmac_unregister_platform();
2946 pr_err("stmmac: driver registration failed\n");
2950 static void __exit
stmmac_exit(void)
2952 stmmac_unregister_platform();
2953 stmmac_unregister_pci();
2956 module_init(stmmac_init
);
2957 module_exit(stmmac_exit
);
2960 static int __init
stmmac_cmdline_opt(char *str
)
2966 while ((opt
= strsep(&str
, ",")) != NULL
) {
2967 if (!strncmp(opt
, "debug:", 6)) {
2968 if (kstrtoint(opt
+ 6, 0, &debug
))
2970 } else if (!strncmp(opt
, "phyaddr:", 8)) {
2971 if (kstrtoint(opt
+ 8, 0, &phyaddr
))
2973 } else if (!strncmp(opt
, "dma_txsize:", 11)) {
2974 if (kstrtoint(opt
+ 11, 0, &dma_txsize
))
2976 } else if (!strncmp(opt
, "dma_rxsize:", 11)) {
2977 if (kstrtoint(opt
+ 11, 0, &dma_rxsize
))
2979 } else if (!strncmp(opt
, "buf_sz:", 7)) {
2980 if (kstrtoint(opt
+ 7, 0, &buf_sz
))
2982 } else if (!strncmp(opt
, "tc:", 3)) {
2983 if (kstrtoint(opt
+ 3, 0, &tc
))
2985 } else if (!strncmp(opt
, "watchdog:", 9)) {
2986 if (kstrtoint(opt
+ 9, 0, &watchdog
))
2988 } else if (!strncmp(opt
, "flow_ctrl:", 10)) {
2989 if (kstrtoint(opt
+ 10, 0, &flow_ctrl
))
2991 } else if (!strncmp(opt
, "pause:", 6)) {
2992 if (kstrtoint(opt
+ 6, 0, &pause
))
2994 } else if (!strncmp(opt
, "eee_timer:", 10)) {
2995 if (kstrtoint(opt
+ 10, 0, &eee_timer
))
2997 } else if (!strncmp(opt
, "chain_mode:", 11)) {
2998 if (kstrtoint(opt
+ 11, 0, &chain_mode
))
3005 pr_err("%s: ERROR broken module parameter conversion", __func__
);
3009 __setup("stmmaceth=", stmmac_cmdline_opt
);
3012 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3013 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3014 MODULE_LICENSE("GPL");