1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/kernel.h>
32 #include <linux/interrupt.h>
34 #include <linux/tcp.h>
35 #include <linux/skbuff.h>
36 #include <linux/ethtool.h>
37 #include <linux/if_ether.h>
38 #include <linux/crc32.h>
39 #include <linux/mii.h>
41 #include <linux/if_vlan.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/slab.h>
44 #include <linux/prefetch.h>
45 #ifdef CONFIG_STMMAC_DEBUG_FS
46 #include <linux/debugfs.h>
47 #include <linux/seq_file.h>
52 /*#define STMMAC_DEBUG*/
54 #define DBG(nlevel, klevel, fmt, args...) \
55 ((void)(netif_msg_##nlevel(priv) && \
56 printk(KERN_##klevel fmt, ## args)))
58 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
61 #undef STMMAC_RX_DEBUG
62 /*#define STMMAC_RX_DEBUG*/
63 #ifdef STMMAC_RX_DEBUG
64 #define RX_DBG(fmt, args...) printk(fmt, ## args)
66 #define RX_DBG(fmt, args...) do { } while (0)
69 #undef STMMAC_XMIT_DEBUG
70 /*#define STMMAC_XMIT_DEBUG*/
71 #ifdef STMMAC_TX_DEBUG
72 #define TX_DBG(fmt, args...) printk(fmt, ## args)
74 #define TX_DBG(fmt, args...) do { } while (0)
77 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
78 #define JUMBO_LEN 9000
80 /* Module parameters */
81 #define TX_TIMEO 5000 /* default 5 seconds */
82 static int watchdog
= TX_TIMEO
;
83 module_param(watchdog
, int, S_IRUGO
| S_IWUSR
);
84 MODULE_PARM_DESC(watchdog
, "Transmit timeout in milliseconds");
86 static int debug
= -1; /* -1: default, 0: no output, 16: all */
87 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
88 MODULE_PARM_DESC(debug
, "Message Level (0: no output, 16: all)");
91 module_param(phyaddr
, int, S_IRUGO
);
92 MODULE_PARM_DESC(phyaddr
, "Physical device address");
94 #define DMA_TX_SIZE 256
95 static int dma_txsize
= DMA_TX_SIZE
;
96 module_param(dma_txsize
, int, S_IRUGO
| S_IWUSR
);
97 MODULE_PARM_DESC(dma_txsize
, "Number of descriptors in the TX list");
99 #define DMA_RX_SIZE 256
100 static int dma_rxsize
= DMA_RX_SIZE
;
101 module_param(dma_rxsize
, int, S_IRUGO
| S_IWUSR
);
102 MODULE_PARM_DESC(dma_rxsize
, "Number of descriptors in the RX list");
104 static int flow_ctrl
= FLOW_OFF
;
105 module_param(flow_ctrl
, int, S_IRUGO
| S_IWUSR
);
106 MODULE_PARM_DESC(flow_ctrl
, "Flow control ability [on/off]");
108 static int pause
= PAUSE_TIME
;
109 module_param(pause
, int, S_IRUGO
| S_IWUSR
);
110 MODULE_PARM_DESC(pause
, "Flow Control Pause Time");
112 #define TC_DEFAULT 64
113 static int tc
= TC_DEFAULT
;
114 module_param(tc
, int, S_IRUGO
| S_IWUSR
);
115 MODULE_PARM_DESC(tc
, "DMA threshold control value");
117 /* Pay attention to tune this parameter; take care of both
118 * hardware capability and network stabitily/performance impact.
119 * Many tests showed that ~4ms latency seems to be good enough. */
120 #ifdef CONFIG_STMMAC_TIMER
121 #define DEFAULT_PERIODIC_RATE 256
122 static int tmrate
= DEFAULT_PERIODIC_RATE
;
123 module_param(tmrate
, int, S_IRUGO
| S_IWUSR
);
124 MODULE_PARM_DESC(tmrate
, "External timer freq. (default: 256Hz)");
127 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
128 static int buf_sz
= DMA_BUFFER_SIZE
;
129 module_param(buf_sz
, int, S_IRUGO
| S_IWUSR
);
130 MODULE_PARM_DESC(buf_sz
, "DMA buffer size");
132 static const u32 default_msg_level
= (NETIF_MSG_DRV
| NETIF_MSG_PROBE
|
133 NETIF_MSG_LINK
| NETIF_MSG_IFUP
|
134 NETIF_MSG_IFDOWN
| NETIF_MSG_TIMER
);
136 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
);
138 #ifdef CONFIG_STMMAC_DEBUG_FS
139 static int stmmac_init_fs(struct net_device
*dev
);
140 static void stmmac_exit_fs(void);
144 * stmmac_verify_args - verify the driver parameters.
145 * Description: it verifies if some wrong parameter is passed to the driver.
146 * Note that wrong parameters are replaced with the default values.
148 static void stmmac_verify_args(void)
150 if (unlikely(watchdog
< 0))
152 if (unlikely(dma_rxsize
< 0))
153 dma_rxsize
= DMA_RX_SIZE
;
154 if (unlikely(dma_txsize
< 0))
155 dma_txsize
= DMA_TX_SIZE
;
156 if (unlikely((buf_sz
< DMA_BUFFER_SIZE
) || (buf_sz
> BUF_SIZE_16KiB
)))
157 buf_sz
= DMA_BUFFER_SIZE
;
158 if (unlikely(flow_ctrl
> 1))
159 flow_ctrl
= FLOW_AUTO
;
160 else if (likely(flow_ctrl
< 0))
161 flow_ctrl
= FLOW_OFF
;
162 if (unlikely((pause
< 0) || (pause
> 0xffff)))
166 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
167 static void print_pkt(unsigned char *buf
, int len
)
170 pr_info("len = %d byte, buf addr: 0x%p", len
, buf
);
171 for (j
= 0; j
< len
; j
++) {
173 pr_info("\n %03x:", j
);
174 pr_info(" %02x", buf
[j
]);
180 /* minimum number of free TX descriptors required to wake up TX process */
181 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
183 static inline u32
stmmac_tx_avail(struct stmmac_priv
*priv
)
185 return priv
->dirty_tx
+ priv
->dma_tx_size
- priv
->cur_tx
- 1;
188 /* On some ST platforms, some HW system configuraton registers have to be
189 * set according to the link speed negotiated.
191 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv
*priv
)
193 struct phy_device
*phydev
= priv
->phydev
;
195 if (likely(priv
->plat
->fix_mac_speed
))
196 priv
->plat
->fix_mac_speed(priv
->plat
->bsp_priv
,
202 * @dev: net device structure
203 * Description: it adjusts the link parameters.
205 static void stmmac_adjust_link(struct net_device
*dev
)
207 struct stmmac_priv
*priv
= netdev_priv(dev
);
208 struct phy_device
*phydev
= priv
->phydev
;
211 unsigned int fc
= priv
->flow_ctrl
, pause_time
= priv
->pause
;
216 DBG(probe
, DEBUG
, "stmmac_adjust_link: called. address %d link %d\n",
217 phydev
->addr
, phydev
->link
);
219 spin_lock_irqsave(&priv
->lock
, flags
);
221 u32 ctrl
= readl(priv
->ioaddr
+ MAC_CTRL_REG
);
223 /* Now we make sure that we can be in full duplex mode.
224 * If not, we operate in half-duplex mode. */
225 if (phydev
->duplex
!= priv
->oldduplex
) {
227 if (!(phydev
->duplex
))
228 ctrl
&= ~priv
->hw
->link
.duplex
;
230 ctrl
|= priv
->hw
->link
.duplex
;
231 priv
->oldduplex
= phydev
->duplex
;
233 /* Flow Control operation */
235 priv
->hw
->mac
->flow_ctrl(priv
->ioaddr
, phydev
->duplex
,
238 if (phydev
->speed
!= priv
->speed
) {
240 switch (phydev
->speed
) {
242 if (likely(priv
->plat
->has_gmac
))
243 ctrl
&= ~priv
->hw
->link
.port
;
244 stmmac_hw_fix_mac_speed(priv
);
248 if (priv
->plat
->has_gmac
) {
249 ctrl
|= priv
->hw
->link
.port
;
250 if (phydev
->speed
== SPEED_100
) {
251 ctrl
|= priv
->hw
->link
.speed
;
253 ctrl
&= ~(priv
->hw
->link
.speed
);
256 ctrl
&= ~priv
->hw
->link
.port
;
258 stmmac_hw_fix_mac_speed(priv
);
261 if (netif_msg_link(priv
))
262 pr_warning("%s: Speed (%d) is not 10"
263 " or 100!\n", dev
->name
, phydev
->speed
);
267 priv
->speed
= phydev
->speed
;
270 writel(ctrl
, priv
->ioaddr
+ MAC_CTRL_REG
);
272 if (!priv
->oldlink
) {
276 } else if (priv
->oldlink
) {
280 priv
->oldduplex
= -1;
283 if (new_state
&& netif_msg_link(priv
))
284 phy_print_status(phydev
);
286 spin_unlock_irqrestore(&priv
->lock
, flags
);
288 DBG(probe
, DEBUG
, "stmmac_adjust_link: exiting\n");
292 * stmmac_init_phy - PHY initialization
293 * @dev: net device structure
294 * Description: it initializes the driver's PHY state, and attaches the PHY
299 static int stmmac_init_phy(struct net_device
*dev
)
301 struct stmmac_priv
*priv
= netdev_priv(dev
);
302 struct phy_device
*phydev
;
303 char phy_id
[MII_BUS_ID_SIZE
+ 3];
304 char bus_id
[MII_BUS_ID_SIZE
];
305 int interface
= priv
->plat
->interface
;
308 priv
->oldduplex
= -1;
310 if (priv
->plat
->phy_bus_name
)
311 snprintf(bus_id
, MII_BUS_ID_SIZE
, "%s-%x",
312 priv
->plat
->phy_bus_name
, priv
->plat
->bus_id
);
314 snprintf(bus_id
, MII_BUS_ID_SIZE
, "stmmac-%x",
317 snprintf(phy_id
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, bus_id
,
318 priv
->plat
->phy_addr
);
319 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id
);
321 phydev
= phy_connect(dev
, phy_id
, &stmmac_adjust_link
, 0, interface
);
323 if (IS_ERR(phydev
)) {
324 pr_err("%s: Could not attach to PHY\n", dev
->name
);
325 return PTR_ERR(phydev
);
328 /* Stop Advertising 1000BASE Capability if interface is not GMII */
329 if ((interface
== PHY_INTERFACE_MODE_MII
) ||
330 (interface
== PHY_INTERFACE_MODE_RMII
))
331 phydev
->advertising
&= ~(SUPPORTED_1000baseT_Half
|
332 SUPPORTED_1000baseT_Full
);
335 * Broken HW is sometimes missing the pull-up resistor on the
336 * MDIO line, which results in reads to non-existent devices returning
337 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
339 * Note: phydev->phy_id is the result of reading the UID PHY registers.
341 if (phydev
->phy_id
== 0) {
342 phy_disconnect(phydev
);
345 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
346 " Link = %d\n", dev
->name
, phydev
->phy_id
, phydev
->link
);
348 priv
->phydev
= phydev
;
355 * @p: pointer to the ring.
356 * @size: size of the ring.
357 * Description: display all the descriptors within the ring.
359 static void display_ring(struct dma_desc
*p
, int size
)
367 for (i
= 0; i
< size
; i
++) {
368 struct tmp_s
*x
= (struct tmp_s
*)(p
+ i
);
369 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
370 i
, (unsigned int)virt_to_phys(&p
[i
]),
371 (unsigned int)(x
->a
), (unsigned int)((x
->a
) >> 32),
377 static int stmmac_set_bfsize(int mtu
, int bufsize
)
381 if (mtu
>= BUF_SIZE_4KiB
)
383 else if (mtu
>= BUF_SIZE_2KiB
)
385 else if (mtu
>= DMA_BUFFER_SIZE
)
388 ret
= DMA_BUFFER_SIZE
;
394 * init_dma_desc_rings - init the RX/TX descriptor rings
395 * @dev: net device structure
396 * Description: this function initializes the DMA RX/TX descriptors
397 * and allocates the socket buffers. It suppors the chained and ring
400 static void init_dma_desc_rings(struct net_device
*dev
)
403 struct stmmac_priv
*priv
= netdev_priv(dev
);
405 unsigned int txsize
= priv
->dma_tx_size
;
406 unsigned int rxsize
= priv
->dma_rx_size
;
409 int des3_as_data_buf
= 0;
411 /* Set the max buffer size according to the DESC mode
412 * and the MTU. Note that RING mode allows 16KiB bsize. */
413 bfsize
= priv
->hw
->ring
->set_16kib_bfsize(dev
->mtu
);
415 if (bfsize
== BUF_SIZE_16KiB
)
416 des3_as_data_buf
= 1;
418 bfsize
= stmmac_set_bfsize(dev
->mtu
, priv
->dma_buf_sz
);
420 #ifdef CONFIG_STMMAC_TIMER
421 /* Disable interrupts on completion for the reception if timer is on */
422 if (likely(priv
->tm
->enable
))
426 DBG(probe
, INFO
, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
427 txsize
, rxsize
, bfsize
);
429 priv
->rx_skbuff_dma
= kmalloc(rxsize
* sizeof(dma_addr_t
), GFP_KERNEL
);
431 kmalloc(sizeof(struct sk_buff
*) * rxsize
, GFP_KERNEL
);
433 (struct dma_desc
*)dma_alloc_coherent(priv
->device
,
435 sizeof(struct dma_desc
),
438 priv
->tx_skbuff
= kmalloc(sizeof(struct sk_buff
*) * txsize
,
441 (struct dma_desc
*)dma_alloc_coherent(priv
->device
,
443 sizeof(struct dma_desc
),
447 if ((priv
->dma_rx
== NULL
) || (priv
->dma_tx
== NULL
)) {
448 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__
);
452 DBG(probe
, INFO
, "stmmac (%s) DMA desc: virt addr (Rx %p, "
453 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
454 dev
->name
, priv
->dma_rx
, priv
->dma_tx
,
455 (unsigned int)priv
->dma_rx_phy
, (unsigned int)priv
->dma_tx_phy
);
457 /* RX INITIALIZATION */
458 DBG(probe
, INFO
, "stmmac: SKB addresses:\n"
459 "skb\t\tskb data\tdma data\n");
461 for (i
= 0; i
< rxsize
; i
++) {
462 struct dma_desc
*p
= priv
->dma_rx
+ i
;
464 skb
= __netdev_alloc_skb(dev
, bfsize
+ NET_IP_ALIGN
,
466 if (unlikely(skb
== NULL
)) {
467 pr_err("%s: Rx init fails; skb is NULL\n", __func__
);
470 skb_reserve(skb
, NET_IP_ALIGN
);
471 priv
->rx_skbuff
[i
] = skb
;
472 priv
->rx_skbuff_dma
[i
] = dma_map_single(priv
->device
, skb
->data
,
473 bfsize
, DMA_FROM_DEVICE
);
475 p
->des2
= priv
->rx_skbuff_dma
[i
];
477 priv
->hw
->ring
->init_desc3(des3_as_data_buf
, p
);
479 DBG(probe
, INFO
, "[%p]\t[%p]\t[%x]\n", priv
->rx_skbuff
[i
],
480 priv
->rx_skbuff
[i
]->data
, priv
->rx_skbuff_dma
[i
]);
483 priv
->dirty_rx
= (unsigned int)(i
- rxsize
);
484 priv
->dma_buf_sz
= bfsize
;
487 /* TX INITIALIZATION */
488 for (i
= 0; i
< txsize
; i
++) {
489 priv
->tx_skbuff
[i
] = NULL
;
490 priv
->dma_tx
[i
].des2
= 0;
493 /* In case of Chained mode this sets the des3 to the next
494 * element in the chain */
495 priv
->hw
->ring
->init_dma_chain(priv
->dma_rx
, priv
->dma_rx_phy
, rxsize
);
496 priv
->hw
->ring
->init_dma_chain(priv
->dma_tx
, priv
->dma_tx_phy
, txsize
);
501 /* Clear the Rx/Tx descriptors */
502 priv
->hw
->desc
->init_rx_desc(priv
->dma_rx
, rxsize
, dis_ic
);
503 priv
->hw
->desc
->init_tx_desc(priv
->dma_tx
, txsize
);
505 if (netif_msg_hw(priv
)) {
506 pr_info("RX descriptor ring:\n");
507 display_ring(priv
->dma_rx
, rxsize
);
508 pr_info("TX descriptor ring:\n");
509 display_ring(priv
->dma_tx
, txsize
);
513 static void dma_free_rx_skbufs(struct stmmac_priv
*priv
)
517 for (i
= 0; i
< priv
->dma_rx_size
; i
++) {
518 if (priv
->rx_skbuff
[i
]) {
519 dma_unmap_single(priv
->device
, priv
->rx_skbuff_dma
[i
],
520 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
521 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
523 priv
->rx_skbuff
[i
] = NULL
;
527 static void dma_free_tx_skbufs(struct stmmac_priv
*priv
)
531 for (i
= 0; i
< priv
->dma_tx_size
; i
++) {
532 if (priv
->tx_skbuff
[i
] != NULL
) {
533 struct dma_desc
*p
= priv
->dma_tx
+ i
;
535 dma_unmap_single(priv
->device
, p
->des2
,
536 priv
->hw
->desc
->get_tx_len(p
),
538 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
539 priv
->tx_skbuff
[i
] = NULL
;
544 static void free_dma_desc_resources(struct stmmac_priv
*priv
)
546 /* Release the DMA TX/RX socket buffers */
547 dma_free_rx_skbufs(priv
);
548 dma_free_tx_skbufs(priv
);
550 /* Free the region of consistent memory previously allocated for
552 dma_free_coherent(priv
->device
,
553 priv
->dma_tx_size
* sizeof(struct dma_desc
),
554 priv
->dma_tx
, priv
->dma_tx_phy
);
555 dma_free_coherent(priv
->device
,
556 priv
->dma_rx_size
* sizeof(struct dma_desc
),
557 priv
->dma_rx
, priv
->dma_rx_phy
);
558 kfree(priv
->rx_skbuff_dma
);
559 kfree(priv
->rx_skbuff
);
560 kfree(priv
->tx_skbuff
);
564 * stmmac_dma_operation_mode - HW DMA operation mode
565 * @priv : pointer to the private device structure.
566 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
567 * or Store-And-Forward capability.
569 static void stmmac_dma_operation_mode(struct stmmac_priv
*priv
)
571 if (likely(priv
->plat
->force_sf_dma_mode
||
572 ((priv
->plat
->tx_coe
) && (!priv
->no_csum_insertion
)))) {
574 * In case of GMAC, SF mode can be enabled
575 * to perform the TX COE in HW. This depends on:
576 * 1) TX COE if actually supported
577 * 2) There is no bugged Jumbo frame support
578 * that needs to not insert csum in the TDES.
580 priv
->hw
->dma
->dma_mode(priv
->ioaddr
,
581 SF_DMA_MODE
, SF_DMA_MODE
);
584 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, SF_DMA_MODE
);
589 * @priv: private driver structure
590 * Description: it reclaims resources after transmission completes.
592 static void stmmac_tx(struct stmmac_priv
*priv
)
594 unsigned int txsize
= priv
->dma_tx_size
;
596 spin_lock(&priv
->tx_lock
);
598 while (priv
->dirty_tx
!= priv
->cur_tx
) {
600 unsigned int entry
= priv
->dirty_tx
% txsize
;
601 struct sk_buff
*skb
= priv
->tx_skbuff
[entry
];
602 struct dma_desc
*p
= priv
->dma_tx
+ entry
;
604 /* Check if the descriptor is owned by the DMA. */
605 if (priv
->hw
->desc
->get_tx_owner(p
))
608 /* Verify tx error by looking at the last segment */
609 last
= priv
->hw
->desc
->get_tx_ls(p
);
612 priv
->hw
->desc
->tx_status(&priv
->dev
->stats
,
615 if (likely(tx_error
== 0)) {
616 priv
->dev
->stats
.tx_packets
++;
617 priv
->xstats
.tx_pkt_n
++;
619 priv
->dev
->stats
.tx_errors
++;
621 TX_DBG("%s: curr %d, dirty %d\n", __func__
,
622 priv
->cur_tx
, priv
->dirty_tx
);
625 dma_unmap_single(priv
->device
, p
->des2
,
626 priv
->hw
->desc
->get_tx_len(p
),
628 priv
->hw
->ring
->clean_desc3(p
);
630 if (likely(skb
!= NULL
)) {
632 * If there's room in the queue (limit it to size)
633 * we add this skb back into the pool,
634 * if it's the right size.
636 if ((skb_queue_len(&priv
->rx_recycle
) <
637 priv
->dma_rx_size
) &&
638 skb_recycle_check(skb
, priv
->dma_buf_sz
))
639 __skb_queue_head(&priv
->rx_recycle
, skb
);
643 priv
->tx_skbuff
[entry
] = NULL
;
646 priv
->hw
->desc
->release_tx_desc(p
);
648 entry
= (++priv
->dirty_tx
) % txsize
;
650 if (unlikely(netif_queue_stopped(priv
->dev
) &&
651 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH(priv
))) {
652 netif_tx_lock(priv
->dev
);
653 if (netif_queue_stopped(priv
->dev
) &&
654 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH(priv
)) {
655 TX_DBG("%s: restart transmit\n", __func__
);
656 netif_wake_queue(priv
->dev
);
658 netif_tx_unlock(priv
->dev
);
660 spin_unlock(&priv
->tx_lock
);
663 static inline void stmmac_enable_irq(struct stmmac_priv
*priv
)
665 #ifdef CONFIG_STMMAC_TIMER
666 if (likely(priv
->tm
->enable
))
667 priv
->tm
->timer_start(tmrate
);
670 priv
->hw
->dma
->enable_dma_irq(priv
->ioaddr
);
673 static inline void stmmac_disable_irq(struct stmmac_priv
*priv
)
675 #ifdef CONFIG_STMMAC_TIMER
676 if (likely(priv
->tm
->enable
))
677 priv
->tm
->timer_stop();
680 priv
->hw
->dma
->disable_dma_irq(priv
->ioaddr
);
683 static int stmmac_has_work(struct stmmac_priv
*priv
)
685 unsigned int has_work
= 0;
686 int rxret
, tx_work
= 0;
688 rxret
= priv
->hw
->desc
->get_rx_owner(priv
->dma_rx
+
689 (priv
->cur_rx
% priv
->dma_rx_size
));
691 if (priv
->dirty_tx
!= priv
->cur_tx
)
694 if (likely(!rxret
|| tx_work
))
700 static inline void _stmmac_schedule(struct stmmac_priv
*priv
)
702 if (likely(stmmac_has_work(priv
))) {
703 stmmac_disable_irq(priv
);
704 napi_schedule(&priv
->napi
);
708 #ifdef CONFIG_STMMAC_TIMER
709 void stmmac_schedule(struct net_device
*dev
)
711 struct stmmac_priv
*priv
= netdev_priv(dev
);
713 priv
->xstats
.sched_timer_n
++;
715 _stmmac_schedule(priv
);
718 static void stmmac_no_timer_started(unsigned int x
)
722 static void stmmac_no_timer_stopped(void)
729 * @priv: pointer to the private device structure
730 * Description: it cleans the descriptors and restarts the transmission
733 static void stmmac_tx_err(struct stmmac_priv
*priv
)
735 netif_stop_queue(priv
->dev
);
737 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
738 dma_free_tx_skbufs(priv
);
739 priv
->hw
->desc
->init_tx_desc(priv
->dma_tx
, priv
->dma_tx_size
);
742 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
744 priv
->dev
->stats
.tx_errors
++;
745 netif_wake_queue(priv
->dev
);
749 static void stmmac_dma_interrupt(struct stmmac_priv
*priv
)
753 status
= priv
->hw
->dma
->dma_interrupt(priv
->ioaddr
, &priv
->xstats
);
754 if (likely(status
== handle_tx_rx
))
755 _stmmac_schedule(priv
);
757 else if (unlikely(status
== tx_hard_error_bump_tc
)) {
758 /* Try to bump up the dma threshold on this failure */
759 if (unlikely(tc
!= SF_DMA_MODE
) && (tc
<= 256)) {
761 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, SF_DMA_MODE
);
762 priv
->xstats
.threshold
= tc
;
764 } else if (unlikely(status
== tx_hard_error
))
768 static void stmmac_mmc_setup(struct stmmac_priv
*priv
)
770 unsigned int mode
= MMC_CNTRL_RESET_ON_READ
| MMC_CNTRL_COUNTER_RESET
|
771 MMC_CNTRL_PRESET
| MMC_CNTRL_FULL_HALF_PRESET
;
773 /* Mask MMC irq, counters are managed in SW and registers
774 * are cleared on each READ eventually. */
775 dwmac_mmc_intr_all_mask(priv
->ioaddr
);
777 if (priv
->dma_cap
.rmon
) {
778 dwmac_mmc_ctrl(priv
->ioaddr
, mode
);
779 memset(&priv
->mmc
, 0, sizeof(struct stmmac_counters
));
781 pr_info(" No MAC Management Counters available\n");
784 static u32
stmmac_get_synopsys_id(struct stmmac_priv
*priv
)
786 u32 hwid
= priv
->hw
->synopsys_uid
;
788 /* Only check valid Synopsys Id because old MAC chips
789 * have no HW registers where get the ID */
791 u32 uid
= ((hwid
& 0x0000ff00) >> 8);
792 u32 synid
= (hwid
& 0x000000ff);
794 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
803 * stmmac_selec_desc_mode
804 * @dev : device pointer
805 * Description: select the Enhanced/Alternate or Normal descriptors */
806 static void stmmac_selec_desc_mode(struct stmmac_priv
*priv
)
808 if (priv
->plat
->enh_desc
) {
809 pr_info(" Enhanced/Alternate descriptors\n");
810 priv
->hw
->desc
= &enh_desc_ops
;
812 pr_info(" Normal descriptors\n");
813 priv
->hw
->desc
= &ndesc_ops
;
818 * stmmac_get_hw_features
819 * @priv : private device pointer
821 * new GMAC chip generations have a new register to indicate the
822 * presence of the optional feature/functions.
823 * This can be also used to override the value passed through the
824 * platform and necessary for old MAC10/100 and GMAC chips.
826 static int stmmac_get_hw_features(struct stmmac_priv
*priv
)
830 if (priv
->hw
->dma
->get_hw_feature
) {
831 hw_cap
= priv
->hw
->dma
->get_hw_feature(priv
->ioaddr
);
833 priv
->dma_cap
.mbps_10_100
= (hw_cap
& DMA_HW_FEAT_MIISEL
);
834 priv
->dma_cap
.mbps_1000
= (hw_cap
& DMA_HW_FEAT_GMIISEL
) >> 1;
835 priv
->dma_cap
.half_duplex
= (hw_cap
& DMA_HW_FEAT_HDSEL
) >> 2;
836 priv
->dma_cap
.hash_filter
= (hw_cap
& DMA_HW_FEAT_HASHSEL
) >> 4;
837 priv
->dma_cap
.multi_addr
=
838 (hw_cap
& DMA_HW_FEAT_ADDMACADRSEL
) >> 5;
839 priv
->dma_cap
.pcs
= (hw_cap
& DMA_HW_FEAT_PCSSEL
) >> 6;
840 priv
->dma_cap
.sma_mdio
= (hw_cap
& DMA_HW_FEAT_SMASEL
) >> 8;
841 priv
->dma_cap
.pmt_remote_wake_up
=
842 (hw_cap
& DMA_HW_FEAT_RWKSEL
) >> 9;
843 priv
->dma_cap
.pmt_magic_frame
=
844 (hw_cap
& DMA_HW_FEAT_MGKSEL
) >> 10;
846 priv
->dma_cap
.rmon
= (hw_cap
& DMA_HW_FEAT_MMCSEL
) >> 11;
848 priv
->dma_cap
.time_stamp
=
849 (hw_cap
& DMA_HW_FEAT_TSVER1SEL
) >> 12;
851 priv
->dma_cap
.atime_stamp
=
852 (hw_cap
& DMA_HW_FEAT_TSVER2SEL
) >> 13;
853 /* 802.3az - Energy-Efficient Ethernet (EEE) */
854 priv
->dma_cap
.eee
= (hw_cap
& DMA_HW_FEAT_EEESEL
) >> 14;
855 priv
->dma_cap
.av
= (hw_cap
& DMA_HW_FEAT_AVSEL
) >> 15;
857 priv
->dma_cap
.tx_coe
= (hw_cap
& DMA_HW_FEAT_TXCOESEL
) >> 16;
858 priv
->dma_cap
.rx_coe_type1
=
859 (hw_cap
& DMA_HW_FEAT_RXTYP1COE
) >> 17;
860 priv
->dma_cap
.rx_coe_type2
=
861 (hw_cap
& DMA_HW_FEAT_RXTYP2COE
) >> 18;
862 priv
->dma_cap
.rxfifo_over_2048
=
863 (hw_cap
& DMA_HW_FEAT_RXFIFOSIZE
) >> 19;
864 /* TX and RX number of channels */
865 priv
->dma_cap
.number_rx_channel
=
866 (hw_cap
& DMA_HW_FEAT_RXCHCNT
) >> 20;
867 priv
->dma_cap
.number_tx_channel
=
868 (hw_cap
& DMA_HW_FEAT_TXCHCNT
) >> 22;
869 /* Alternate (enhanced) DESC mode*/
870 priv
->dma_cap
.enh_desc
=
871 (hw_cap
& DMA_HW_FEAT_ENHDESSEL
) >> 24;
878 static void stmmac_check_ether_addr(struct stmmac_priv
*priv
)
880 /* verify if the MAC address is valid, in case of failures it
881 * generates a random MAC address */
882 if (!is_valid_ether_addr(priv
->dev
->dev_addr
)) {
883 priv
->hw
->mac
->get_umac_addr((void __iomem
*)
884 priv
->dev
->base_addr
,
885 priv
->dev
->dev_addr
, 0);
886 if (!is_valid_ether_addr(priv
->dev
->dev_addr
))
887 eth_hw_addr_random(priv
->dev
);
889 pr_warning("%s: device MAC address %pM\n", priv
->dev
->name
,
890 priv
->dev
->dev_addr
);
894 * stmmac_open - open entry point of the driver
895 * @dev : pointer to the device structure.
897 * This function is the open entry point of the driver.
899 * 0 on success and an appropriate (-)ve integer as defined in errno.h
902 static int stmmac_open(struct net_device
*dev
)
904 struct stmmac_priv
*priv
= netdev_priv(dev
);
907 stmmac_check_ether_addr(priv
);
909 /* MDIO bus Registration */
910 ret
= stmmac_mdio_register(dev
);
912 pr_debug("%s: MDIO bus (id: %d) registration failed",
913 __func__
, priv
->plat
->bus_id
);
917 #ifdef CONFIG_STMMAC_TIMER
918 priv
->tm
= kzalloc(sizeof(struct stmmac_timer
*), GFP_KERNEL
);
919 if (unlikely(priv
->tm
== NULL
))
922 priv
->tm
->freq
= tmrate
;
924 /* Test if the external timer can be actually used.
925 * In case of failure continue without timer. */
926 if (unlikely((stmmac_open_ext_timer(dev
, priv
->tm
)) < 0)) {
927 pr_warning("stmmaceth: cannot attach the external timer.\n");
929 priv
->tm
->timer_start
= stmmac_no_timer_started
;
930 priv
->tm
->timer_stop
= stmmac_no_timer_stopped
;
932 priv
->tm
->enable
= 1;
934 ret
= stmmac_init_phy(dev
);
936 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__
, ret
);
940 /* Create and initialize the TX/RX descriptors chains. */
941 priv
->dma_tx_size
= STMMAC_ALIGN(dma_txsize
);
942 priv
->dma_rx_size
= STMMAC_ALIGN(dma_rxsize
);
943 priv
->dma_buf_sz
= STMMAC_ALIGN(buf_sz
);
944 init_dma_desc_rings(dev
);
946 /* DMA initialization and SW reset */
947 ret
= priv
->hw
->dma
->init(priv
->ioaddr
, priv
->plat
->dma_cfg
->pbl
,
948 priv
->plat
->dma_cfg
->fixed_burst
,
949 priv
->plat
->dma_cfg
->burst_len
,
950 priv
->dma_tx_phy
, priv
->dma_rx_phy
);
952 pr_err("%s: DMA initialization failed\n", __func__
);
956 /* Copy the MAC addr into the HW */
957 priv
->hw
->mac
->set_umac_addr(priv
->ioaddr
, dev
->dev_addr
, 0);
959 /* If required, perform hw setup of the bus. */
960 if (priv
->plat
->bus_setup
)
961 priv
->plat
->bus_setup(priv
->ioaddr
);
963 /* Initialize the MAC Core */
964 priv
->hw
->mac
->core_init(priv
->ioaddr
);
966 /* Request the IRQ lines */
967 ret
= request_irq(dev
->irq
, stmmac_interrupt
,
968 IRQF_SHARED
, dev
->name
, dev
);
969 if (unlikely(ret
< 0)) {
970 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
971 __func__
, dev
->irq
, ret
);
975 /* Request the Wake IRQ in case of another line is used for WoL */
976 if (priv
->wol_irq
!= dev
->irq
) {
977 ret
= request_irq(priv
->wol_irq
, stmmac_interrupt
,
978 IRQF_SHARED
, dev
->name
, dev
);
979 if (unlikely(ret
< 0)) {
980 pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
981 "(error: %d)\n", __func__
, priv
->wol_irq
, ret
);
982 goto open_error_wolirq
;
986 /* Enable the MAC Rx/Tx */
987 stmmac_set_mac(priv
->ioaddr
, true);
989 /* Set the HW DMA mode and the COE */
990 stmmac_dma_operation_mode(priv
);
992 /* Extra statistics */
993 memset(&priv
->xstats
, 0, sizeof(struct stmmac_extra_stats
));
994 priv
->xstats
.threshold
= tc
;
996 stmmac_mmc_setup(priv
);
998 #ifdef CONFIG_STMMAC_DEBUG_FS
999 ret
= stmmac_init_fs(dev
);
1001 pr_warning("%s: failed debugFS registration\n", __func__
);
1003 /* Start the ball rolling... */
1004 DBG(probe
, DEBUG
, "%s: DMA RX/TX processes started...\n", dev
->name
);
1005 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1006 priv
->hw
->dma
->start_rx(priv
->ioaddr
);
1008 #ifdef CONFIG_STMMAC_TIMER
1009 priv
->tm
->timer_start(tmrate
);
1012 /* Dump DMA/MAC registers */
1013 if (netif_msg_hw(priv
)) {
1014 priv
->hw
->mac
->dump_regs(priv
->ioaddr
);
1015 priv
->hw
->dma
->dump_regs(priv
->ioaddr
);
1019 phy_start(priv
->phydev
);
1021 napi_enable(&priv
->napi
);
1022 skb_queue_head_init(&priv
->rx_recycle
);
1023 netif_start_queue(dev
);
1028 free_irq(dev
->irq
, dev
);
1031 #ifdef CONFIG_STMMAC_TIMER
1035 phy_disconnect(priv
->phydev
);
1041 * stmmac_release - close entry point of the driver
1042 * @dev : device pointer.
1044 * This is the stop entry point of the driver.
1046 static int stmmac_release(struct net_device
*dev
)
1048 struct stmmac_priv
*priv
= netdev_priv(dev
);
1050 /* Stop and disconnect the PHY */
1052 phy_stop(priv
->phydev
);
1053 phy_disconnect(priv
->phydev
);
1054 priv
->phydev
= NULL
;
1057 netif_stop_queue(dev
);
1059 #ifdef CONFIG_STMMAC_TIMER
1060 /* Stop and release the timer */
1061 stmmac_close_ext_timer();
1062 if (priv
->tm
!= NULL
)
1065 napi_disable(&priv
->napi
);
1066 skb_queue_purge(&priv
->rx_recycle
);
1068 /* Free the IRQ lines */
1069 free_irq(dev
->irq
, dev
);
1070 if (priv
->wol_irq
!= dev
->irq
)
1071 free_irq(priv
->wol_irq
, dev
);
1073 /* Stop TX/RX DMA and clear the descriptors */
1074 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1075 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
1077 /* Release and free the Rx/Tx resources */
1078 free_dma_desc_resources(priv
);
1080 /* Disable the MAC Rx/Tx */
1081 stmmac_set_mac(priv
->ioaddr
, false);
1083 netif_carrier_off(dev
);
1085 #ifdef CONFIG_STMMAC_DEBUG_FS
1088 stmmac_mdio_unregister(dev
);
1095 * @skb : the socket buffer
1096 * @dev : device pointer
1097 * Description : Tx entry point of the driver.
1099 static netdev_tx_t
stmmac_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1101 struct stmmac_priv
*priv
= netdev_priv(dev
);
1102 unsigned int txsize
= priv
->dma_tx_size
;
1104 int i
, csum_insertion
= 0;
1105 int nfrags
= skb_shinfo(skb
)->nr_frags
;
1106 struct dma_desc
*desc
, *first
;
1107 unsigned int nopaged_len
= skb_headlen(skb
);
1109 if (unlikely(stmmac_tx_avail(priv
) < nfrags
+ 1)) {
1110 if (!netif_queue_stopped(dev
)) {
1111 netif_stop_queue(dev
);
1112 /* This is a hard error, log it. */
1113 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1116 return NETDEV_TX_BUSY
;
1119 spin_lock(&priv
->tx_lock
);
1121 entry
= priv
->cur_tx
% txsize
;
1123 #ifdef STMMAC_XMIT_DEBUG
1124 if ((skb
->len
> ETH_FRAME_LEN
) || nfrags
)
1125 pr_info("stmmac xmit:\n"
1126 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1127 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1128 skb
, skb
->len
, nopaged_len
, nfrags
, skb
->ip_summed
,
1129 !skb_is_gso(skb
) ? "isn't" : "is");
1132 csum_insertion
= (skb
->ip_summed
== CHECKSUM_PARTIAL
);
1134 desc
= priv
->dma_tx
+ entry
;
1137 #ifdef STMMAC_XMIT_DEBUG
1138 if ((nfrags
> 0) || (skb
->len
> ETH_FRAME_LEN
))
1139 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1140 "\t\tn_frags: %d, ip_summed: %d\n",
1141 skb
->len
, nopaged_len
, nfrags
, skb
->ip_summed
);
1143 priv
->tx_skbuff
[entry
] = skb
;
1145 if (priv
->hw
->ring
->is_jumbo_frm(skb
->len
, priv
->plat
->enh_desc
)) {
1146 entry
= priv
->hw
->ring
->jumbo_frm(priv
, skb
, csum_insertion
);
1147 desc
= priv
->dma_tx
+ entry
;
1149 desc
->des2
= dma_map_single(priv
->device
, skb
->data
,
1150 nopaged_len
, DMA_TO_DEVICE
);
1151 priv
->hw
->desc
->prepare_tx_desc(desc
, 1, nopaged_len
,
1155 for (i
= 0; i
< nfrags
; i
++) {
1156 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1157 int len
= skb_frag_size(frag
);
1159 entry
= (++priv
->cur_tx
) % txsize
;
1160 desc
= priv
->dma_tx
+ entry
;
1162 TX_DBG("\t[entry %d] segment len: %d\n", entry
, len
);
1163 desc
->des2
= skb_frag_dma_map(priv
->device
, frag
, 0, len
,
1165 priv
->tx_skbuff
[entry
] = NULL
;
1166 priv
->hw
->desc
->prepare_tx_desc(desc
, 0, len
, csum_insertion
);
1168 priv
->hw
->desc
->set_tx_owner(desc
);
1171 /* Interrupt on completition only for the latest segment */
1172 priv
->hw
->desc
->close_tx_desc(desc
);
1174 #ifdef CONFIG_STMMAC_TIMER
1175 /* Clean IC while using timer */
1176 if (likely(priv
->tm
->enable
))
1177 priv
->hw
->desc
->clear_tx_ic(desc
);
1182 /* To avoid raise condition */
1183 priv
->hw
->desc
->set_tx_owner(first
);
1187 #ifdef STMMAC_XMIT_DEBUG
1188 if (netif_msg_pktdata(priv
)) {
1189 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1190 "first=%p, nfrags=%d\n",
1191 (priv
->cur_tx
% txsize
), (priv
->dirty_tx
% txsize
),
1192 entry
, first
, nfrags
);
1193 display_ring(priv
->dma_tx
, txsize
);
1194 pr_info(">>> frame to be transmitted: ");
1195 print_pkt(skb
->data
, skb
->len
);
1198 if (unlikely(stmmac_tx_avail(priv
) <= (MAX_SKB_FRAGS
+ 1))) {
1199 TX_DBG("%s: stop transmitted packets\n", __func__
);
1200 netif_stop_queue(dev
);
1203 dev
->stats
.tx_bytes
+= skb
->len
;
1205 skb_tx_timestamp(skb
);
1207 priv
->hw
->dma
->enable_dma_transmission(priv
->ioaddr
);
1209 spin_unlock(&priv
->tx_lock
);
1211 return NETDEV_TX_OK
;
1214 static inline void stmmac_rx_refill(struct stmmac_priv
*priv
)
1216 unsigned int rxsize
= priv
->dma_rx_size
;
1217 int bfsize
= priv
->dma_buf_sz
;
1218 struct dma_desc
*p
= priv
->dma_rx
;
1220 for (; priv
->cur_rx
- priv
->dirty_rx
> 0; priv
->dirty_rx
++) {
1221 unsigned int entry
= priv
->dirty_rx
% rxsize
;
1222 if (likely(priv
->rx_skbuff
[entry
] == NULL
)) {
1223 struct sk_buff
*skb
;
1225 skb
= __skb_dequeue(&priv
->rx_recycle
);
1227 skb
= netdev_alloc_skb_ip_align(priv
->dev
,
1230 if (unlikely(skb
== NULL
))
1233 priv
->rx_skbuff
[entry
] = skb
;
1234 priv
->rx_skbuff_dma
[entry
] =
1235 dma_map_single(priv
->device
, skb
->data
, bfsize
,
1238 (p
+ entry
)->des2
= priv
->rx_skbuff_dma
[entry
];
1240 if (unlikely(priv
->plat
->has_gmac
))
1241 priv
->hw
->ring
->refill_desc3(bfsize
, p
+ entry
);
1243 RX_DBG(KERN_INFO
"\trefill entry #%d\n", entry
);
1246 priv
->hw
->desc
->set_rx_owner(p
+ entry
);
1250 static int stmmac_rx(struct stmmac_priv
*priv
, int limit
)
1252 unsigned int rxsize
= priv
->dma_rx_size
;
1253 unsigned int entry
= priv
->cur_rx
% rxsize
;
1254 unsigned int next_entry
;
1255 unsigned int count
= 0;
1256 struct dma_desc
*p
= priv
->dma_rx
+ entry
;
1257 struct dma_desc
*p_next
;
1259 #ifdef STMMAC_RX_DEBUG
1260 if (netif_msg_hw(priv
)) {
1261 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1262 display_ring(priv
->dma_rx
, rxsize
);
1266 while (!priv
->hw
->desc
->get_rx_owner(p
)) {
1274 next_entry
= (++priv
->cur_rx
) % rxsize
;
1275 p_next
= priv
->dma_rx
+ next_entry
;
1278 /* read the status of the incoming frame */
1279 status
= (priv
->hw
->desc
->rx_status(&priv
->dev
->stats
,
1281 if (unlikely(status
== discard_frame
))
1282 priv
->dev
->stats
.rx_errors
++;
1284 struct sk_buff
*skb
;
1287 frame_len
= priv
->hw
->desc
->get_rx_frame_len(p
,
1288 priv
->plat
->rx_coe
);
1289 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1290 * Type frames (LLC/LLC-SNAP) */
1291 if (unlikely(status
!= llc_snap
))
1292 frame_len
-= ETH_FCS_LEN
;
1293 #ifdef STMMAC_RX_DEBUG
1294 if (frame_len
> ETH_FRAME_LEN
)
1295 pr_debug("\tRX frame size %d, COE status: %d\n",
1298 if (netif_msg_hw(priv
))
1299 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1302 skb
= priv
->rx_skbuff
[entry
];
1303 if (unlikely(!skb
)) {
1304 pr_err("%s: Inconsistent Rx descriptor chain\n",
1306 priv
->dev
->stats
.rx_dropped
++;
1309 prefetch(skb
->data
- NET_IP_ALIGN
);
1310 priv
->rx_skbuff
[entry
] = NULL
;
1312 skb_put(skb
, frame_len
);
1313 dma_unmap_single(priv
->device
,
1314 priv
->rx_skbuff_dma
[entry
],
1315 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
1316 #ifdef STMMAC_RX_DEBUG
1317 if (netif_msg_pktdata(priv
)) {
1318 pr_info(" frame received (%dbytes)", frame_len
);
1319 print_pkt(skb
->data
, frame_len
);
1322 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
1324 if (unlikely(!priv
->plat
->rx_coe
)) {
1325 /* No RX COE for old mac10/100 devices */
1326 skb_checksum_none_assert(skb
);
1327 netif_receive_skb(skb
);
1329 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1330 napi_gro_receive(&priv
->napi
, skb
);
1333 priv
->dev
->stats
.rx_packets
++;
1334 priv
->dev
->stats
.rx_bytes
+= frame_len
;
1337 p
= p_next
; /* use prefetched values */
1340 stmmac_rx_refill(priv
);
1342 priv
->xstats
.rx_pkt_n
+= count
;
1348 * stmmac_poll - stmmac poll method (NAPI)
1349 * @napi : pointer to the napi structure.
1350 * @budget : maximum number of packets that the current CPU can receive from
1353 * This function implements the the reception process.
1354 * Also it runs the TX completion thread
1356 static int stmmac_poll(struct napi_struct
*napi
, int budget
)
1358 struct stmmac_priv
*priv
= container_of(napi
, struct stmmac_priv
, napi
);
1361 priv
->xstats
.poll_n
++;
1363 work_done
= stmmac_rx(priv
, budget
);
1365 if (work_done
< budget
) {
1366 napi_complete(napi
);
1367 stmmac_enable_irq(priv
);
1374 * @dev : Pointer to net device structure
1375 * Description: this function is called when a packet transmission fails to
1376 * complete within a reasonable tmrate. The driver will mark the error in the
1377 * netdev structure and arrange for the device to be reset to a sane state
1378 * in order to transmit a new packet.
1380 static void stmmac_tx_timeout(struct net_device
*dev
)
1382 struct stmmac_priv
*priv
= netdev_priv(dev
);
1384 /* Clear Tx resources and restart transmitting again */
1385 stmmac_tx_err(priv
);
1388 /* Configuration changes (passed on by ifconfig) */
1389 static int stmmac_config(struct net_device
*dev
, struct ifmap
*map
)
1391 if (dev
->flags
& IFF_UP
) /* can't act on a running interface */
1394 /* Don't allow changing the I/O address */
1395 if (map
->base_addr
!= dev
->base_addr
) {
1396 pr_warning("%s: can't change I/O address\n", dev
->name
);
1400 /* Don't allow changing the IRQ */
1401 if (map
->irq
!= dev
->irq
) {
1402 pr_warning("%s: can't change IRQ number %d\n",
1403 dev
->name
, dev
->irq
);
1407 /* ignore other fields */
1412 * stmmac_set_rx_mode - entry point for multicast addressing
1413 * @dev : pointer to the device structure
1415 * This function is a driver entry point which gets called by the kernel
1416 * whenever multicast addresses must be enabled/disabled.
1420 static void stmmac_set_rx_mode(struct net_device
*dev
)
1422 struct stmmac_priv
*priv
= netdev_priv(dev
);
1424 spin_lock(&priv
->lock
);
1425 priv
->hw
->mac
->set_filter(dev
);
1426 spin_unlock(&priv
->lock
);
1430 * stmmac_change_mtu - entry point to change MTU size for the device.
1431 * @dev : device pointer.
1432 * @new_mtu : the new MTU size for the device.
1433 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1434 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1435 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1437 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1440 static int stmmac_change_mtu(struct net_device
*dev
, int new_mtu
)
1442 struct stmmac_priv
*priv
= netdev_priv(dev
);
1445 if (netif_running(dev
)) {
1446 pr_err("%s: must be stopped to change its MTU\n", dev
->name
);
1450 if (priv
->plat
->enh_desc
)
1451 max_mtu
= JUMBO_LEN
;
1453 max_mtu
= SKB_MAX_HEAD(NET_SKB_PAD
+ NET_IP_ALIGN
);
1455 if ((new_mtu
< 46) || (new_mtu
> max_mtu
)) {
1456 pr_err("%s: invalid MTU, max MTU is: %d\n", dev
->name
, max_mtu
);
1461 netdev_update_features(dev
);
1466 static netdev_features_t
stmmac_fix_features(struct net_device
*dev
,
1467 netdev_features_t features
)
1469 struct stmmac_priv
*priv
= netdev_priv(dev
);
1471 if (priv
->plat
->rx_coe
== STMMAC_RX_COE_NONE
)
1472 features
&= ~NETIF_F_RXCSUM
;
1473 else if (priv
->plat
->rx_coe
== STMMAC_RX_COE_TYPE1
)
1474 features
&= ~NETIF_F_IPV6_CSUM
;
1475 if (!priv
->plat
->tx_coe
)
1476 features
&= ~NETIF_F_ALL_CSUM
;
1478 /* Some GMAC devices have a bugged Jumbo frame support that
1479 * needs to have the Tx COE disabled for oversized frames
1480 * (due to limited buffer sizes). In this case we disable
1481 * the TX csum insertionin the TDES and not use SF. */
1482 if (priv
->plat
->bugged_jumbo
&& (dev
->mtu
> ETH_DATA_LEN
))
1483 features
&= ~NETIF_F_ALL_CSUM
;
1488 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
)
1490 struct net_device
*dev
= (struct net_device
*)dev_id
;
1491 struct stmmac_priv
*priv
= netdev_priv(dev
);
1493 if (unlikely(!dev
)) {
1494 pr_err("%s: invalid dev pointer\n", __func__
);
1498 if (priv
->plat
->has_gmac
)
1499 /* To handle GMAC own interrupts */
1500 priv
->hw
->mac
->host_irq_status((void __iomem
*) dev
->base_addr
);
1502 stmmac_dma_interrupt(priv
);
1507 #ifdef CONFIG_NET_POLL_CONTROLLER
1508 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1509 * to allow network I/O with interrupts disabled. */
1510 static void stmmac_poll_controller(struct net_device
*dev
)
1512 disable_irq(dev
->irq
);
1513 stmmac_interrupt(dev
->irq
, dev
);
1514 enable_irq(dev
->irq
);
1519 * stmmac_ioctl - Entry point for the Ioctl
1520 * @dev: Device pointer.
1521 * @rq: An IOCTL specefic structure, that can contain a pointer to
1522 * a proprietary structure used to pass information to the driver.
1523 * @cmd: IOCTL command
1525 * Currently there are no special functionality supported in IOCTL, just the
1526 * phy_mii_ioctl(...) can be invoked.
1528 static int stmmac_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
1530 struct stmmac_priv
*priv
= netdev_priv(dev
);
1533 if (!netif_running(dev
))
1539 ret
= phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
1544 #ifdef CONFIG_STMMAC_DEBUG_FS
1545 static struct dentry
*stmmac_fs_dir
;
1546 static struct dentry
*stmmac_rings_status
;
1547 static struct dentry
*stmmac_dma_cap
;
1549 static int stmmac_sysfs_ring_read(struct seq_file
*seq
, void *v
)
1557 struct net_device
*dev
= seq
->private;
1558 struct stmmac_priv
*priv
= netdev_priv(dev
);
1560 seq_printf(seq
, "=======================\n");
1561 seq_printf(seq
, " RX descriptor ring\n");
1562 seq_printf(seq
, "=======================\n");
1564 for (i
= 0; i
< priv
->dma_rx_size
; i
++) {
1565 struct tmp_s
*x
= (struct tmp_s
*)(priv
->dma_rx
+ i
);
1566 seq_printf(seq
, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1567 i
, (unsigned int)(x
->a
),
1568 (unsigned int)((x
->a
) >> 32), x
->b
, x
->c
);
1569 seq_printf(seq
, "\n");
1572 seq_printf(seq
, "\n");
1573 seq_printf(seq
, "=======================\n");
1574 seq_printf(seq
, " TX descriptor ring\n");
1575 seq_printf(seq
, "=======================\n");
1577 for (i
= 0; i
< priv
->dma_tx_size
; i
++) {
1578 struct tmp_s
*x
= (struct tmp_s
*)(priv
->dma_tx
+ i
);
1579 seq_printf(seq
, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1580 i
, (unsigned int)(x
->a
),
1581 (unsigned int)((x
->a
) >> 32), x
->b
, x
->c
);
1582 seq_printf(seq
, "\n");
1588 static int stmmac_sysfs_ring_open(struct inode
*inode
, struct file
*file
)
1590 return single_open(file
, stmmac_sysfs_ring_read
, inode
->i_private
);
1593 static const struct file_operations stmmac_rings_status_fops
= {
1594 .owner
= THIS_MODULE
,
1595 .open
= stmmac_sysfs_ring_open
,
1597 .llseek
= seq_lseek
,
1598 .release
= seq_release
,
1601 static int stmmac_sysfs_dma_cap_read(struct seq_file
*seq
, void *v
)
1603 struct net_device
*dev
= seq
->private;
1604 struct stmmac_priv
*priv
= netdev_priv(dev
);
1606 if (!priv
->hw_cap_support
) {
1607 seq_printf(seq
, "DMA HW features not supported\n");
1611 seq_printf(seq
, "==============================\n");
1612 seq_printf(seq
, "\tDMA HW features\n");
1613 seq_printf(seq
, "==============================\n");
1615 seq_printf(seq
, "\t10/100 Mbps %s\n",
1616 (priv
->dma_cap
.mbps_10_100
) ? "Y" : "N");
1617 seq_printf(seq
, "\t1000 Mbps %s\n",
1618 (priv
->dma_cap
.mbps_1000
) ? "Y" : "N");
1619 seq_printf(seq
, "\tHalf duple %s\n",
1620 (priv
->dma_cap
.half_duplex
) ? "Y" : "N");
1621 seq_printf(seq
, "\tHash Filter: %s\n",
1622 (priv
->dma_cap
.hash_filter
) ? "Y" : "N");
1623 seq_printf(seq
, "\tMultiple MAC address registers: %s\n",
1624 (priv
->dma_cap
.multi_addr
) ? "Y" : "N");
1625 seq_printf(seq
, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1626 (priv
->dma_cap
.pcs
) ? "Y" : "N");
1627 seq_printf(seq
, "\tSMA (MDIO) Interface: %s\n",
1628 (priv
->dma_cap
.sma_mdio
) ? "Y" : "N");
1629 seq_printf(seq
, "\tPMT Remote wake up: %s\n",
1630 (priv
->dma_cap
.pmt_remote_wake_up
) ? "Y" : "N");
1631 seq_printf(seq
, "\tPMT Magic Frame: %s\n",
1632 (priv
->dma_cap
.pmt_magic_frame
) ? "Y" : "N");
1633 seq_printf(seq
, "\tRMON module: %s\n",
1634 (priv
->dma_cap
.rmon
) ? "Y" : "N");
1635 seq_printf(seq
, "\tIEEE 1588-2002 Time Stamp: %s\n",
1636 (priv
->dma_cap
.time_stamp
) ? "Y" : "N");
1637 seq_printf(seq
, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1638 (priv
->dma_cap
.atime_stamp
) ? "Y" : "N");
1639 seq_printf(seq
, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1640 (priv
->dma_cap
.eee
) ? "Y" : "N");
1641 seq_printf(seq
, "\tAV features: %s\n", (priv
->dma_cap
.av
) ? "Y" : "N");
1642 seq_printf(seq
, "\tChecksum Offload in TX: %s\n",
1643 (priv
->dma_cap
.tx_coe
) ? "Y" : "N");
1644 seq_printf(seq
, "\tIP Checksum Offload (type1) in RX: %s\n",
1645 (priv
->dma_cap
.rx_coe_type1
) ? "Y" : "N");
1646 seq_printf(seq
, "\tIP Checksum Offload (type2) in RX: %s\n",
1647 (priv
->dma_cap
.rx_coe_type2
) ? "Y" : "N");
1648 seq_printf(seq
, "\tRXFIFO > 2048bytes: %s\n",
1649 (priv
->dma_cap
.rxfifo_over_2048
) ? "Y" : "N");
1650 seq_printf(seq
, "\tNumber of Additional RX channel: %d\n",
1651 priv
->dma_cap
.number_rx_channel
);
1652 seq_printf(seq
, "\tNumber of Additional TX channel: %d\n",
1653 priv
->dma_cap
.number_tx_channel
);
1654 seq_printf(seq
, "\tEnhanced descriptors: %s\n",
1655 (priv
->dma_cap
.enh_desc
) ? "Y" : "N");
1660 static int stmmac_sysfs_dma_cap_open(struct inode
*inode
, struct file
*file
)
1662 return single_open(file
, stmmac_sysfs_dma_cap_read
, inode
->i_private
);
1665 static const struct file_operations stmmac_dma_cap_fops
= {
1666 .owner
= THIS_MODULE
,
1667 .open
= stmmac_sysfs_dma_cap_open
,
1669 .llseek
= seq_lseek
,
1670 .release
= seq_release
,
1673 static int stmmac_init_fs(struct net_device
*dev
)
1675 /* Create debugfs entries */
1676 stmmac_fs_dir
= debugfs_create_dir(STMMAC_RESOURCE_NAME
, NULL
);
1678 if (!stmmac_fs_dir
|| IS_ERR(stmmac_fs_dir
)) {
1679 pr_err("ERROR %s, debugfs create directory failed\n",
1680 STMMAC_RESOURCE_NAME
);
1685 /* Entry to report DMA RX/TX rings */
1686 stmmac_rings_status
= debugfs_create_file("descriptors_status",
1687 S_IRUGO
, stmmac_fs_dir
, dev
,
1688 &stmmac_rings_status_fops
);
1690 if (!stmmac_rings_status
|| IS_ERR(stmmac_rings_status
)) {
1691 pr_info("ERROR creating stmmac ring debugfs file\n");
1692 debugfs_remove(stmmac_fs_dir
);
1697 /* Entry to report the DMA HW features */
1698 stmmac_dma_cap
= debugfs_create_file("dma_cap", S_IRUGO
, stmmac_fs_dir
,
1699 dev
, &stmmac_dma_cap_fops
);
1701 if (!stmmac_dma_cap
|| IS_ERR(stmmac_dma_cap
)) {
1702 pr_info("ERROR creating stmmac MMC debugfs file\n");
1703 debugfs_remove(stmmac_rings_status
);
1704 debugfs_remove(stmmac_fs_dir
);
1712 static void stmmac_exit_fs(void)
1714 debugfs_remove(stmmac_rings_status
);
1715 debugfs_remove(stmmac_dma_cap
);
1716 debugfs_remove(stmmac_fs_dir
);
1718 #endif /* CONFIG_STMMAC_DEBUG_FS */
1720 static const struct net_device_ops stmmac_netdev_ops
= {
1721 .ndo_open
= stmmac_open
,
1722 .ndo_start_xmit
= stmmac_xmit
,
1723 .ndo_stop
= stmmac_release
,
1724 .ndo_change_mtu
= stmmac_change_mtu
,
1725 .ndo_fix_features
= stmmac_fix_features
,
1726 .ndo_set_rx_mode
= stmmac_set_rx_mode
,
1727 .ndo_tx_timeout
= stmmac_tx_timeout
,
1728 .ndo_do_ioctl
= stmmac_ioctl
,
1729 .ndo_set_config
= stmmac_config
,
1730 #ifdef CONFIG_NET_POLL_CONTROLLER
1731 .ndo_poll_controller
= stmmac_poll_controller
,
1733 .ndo_set_mac_address
= eth_mac_addr
,
1737 * stmmac_hw_init - Init the MAC device
1738 * @priv : pointer to the private device structure.
1739 * Description: this function detects which MAC device
1740 * (GMAC/MAC10-100) has to attached, checks the HW capability
1741 * (if supported) and sets the driver's features (for example
1742 * to use the ring or chaine mode or support the normal/enh
1743 * descriptor structure).
1745 static int stmmac_hw_init(struct stmmac_priv
*priv
)
1748 struct mac_device_info
*mac
;
1750 /* Identify the MAC HW device */
1751 if (priv
->plat
->has_gmac
)
1752 mac
= dwmac1000_setup(priv
->ioaddr
);
1754 mac
= dwmac100_setup(priv
->ioaddr
);
1760 /* To use the chained or ring mode */
1761 priv
->hw
->ring
= &ring_mode_ops
;
1763 /* Get and dump the chip ID */
1764 stmmac_get_synopsys_id(priv
);
1766 /* Get the HW capability (new GMAC newer than 3.50a) */
1767 priv
->hw_cap_support
= stmmac_get_hw_features(priv
);
1768 if (priv
->hw_cap_support
) {
1769 pr_info(" DMA HW capability register supported");
1771 /* We can override some gmac/dma configuration fields: e.g.
1772 * enh_desc, tx_coe (e.g. that are passed through the
1773 * platform) with the values from the HW capability
1774 * register (if supported).
1776 priv
->plat
->enh_desc
= priv
->dma_cap
.enh_desc
;
1777 priv
->plat
->pmt
= priv
->dma_cap
.pmt_remote_wake_up
;
1779 priv
->plat
->tx_coe
= priv
->dma_cap
.tx_coe
;
1781 if (priv
->dma_cap
.rx_coe_type2
)
1782 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE2
;
1783 else if (priv
->dma_cap
.rx_coe_type1
)
1784 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE1
;
1787 pr_info(" No HW DMA feature register supported");
1789 /* Select the enhnaced/normal descriptor structures */
1790 stmmac_selec_desc_mode(priv
);
1792 /* Enable the IPC (Checksum Offload) and check if the feature has been
1793 * enabled during the core configuration. */
1794 ret
= priv
->hw
->mac
->rx_ipc(priv
->ioaddr
);
1796 pr_warning(" RX IPC Checksum Offload not configured.\n");
1797 priv
->plat
->rx_coe
= STMMAC_RX_COE_NONE
;
1800 if (priv
->plat
->rx_coe
)
1801 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
1802 priv
->plat
->rx_coe
);
1803 if (priv
->plat
->tx_coe
)
1804 pr_info(" TX Checksum insertion supported\n");
1806 if (priv
->plat
->pmt
) {
1807 pr_info(" Wake-Up On Lan supported\n");
1808 device_set_wakeup_capable(priv
->device
, 1);
1816 * @device: device pointer
1817 * Description: this is the main probe function used to
1818 * call the alloc_etherdev, allocate the priv structure.
1820 struct stmmac_priv
*stmmac_dvr_probe(struct device
*device
,
1821 struct plat_stmmacenet_data
*plat_dat
,
1825 struct net_device
*ndev
= NULL
;
1826 struct stmmac_priv
*priv
;
1828 ndev
= alloc_etherdev(sizeof(struct stmmac_priv
));
1832 SET_NETDEV_DEV(ndev
, device
);
1834 priv
= netdev_priv(ndev
);
1835 priv
->device
= device
;
1840 stmmac_set_ethtool_ops(ndev
);
1841 priv
->pause
= pause
;
1842 priv
->plat
= plat_dat
;
1843 priv
->ioaddr
= addr
;
1844 priv
->dev
->base_addr
= (unsigned long)addr
;
1846 /* Verify driver arguments */
1847 stmmac_verify_args();
1849 /* Override with kernel parameters if supplied XXX CRS XXX
1850 * this needs to have multiple instances */
1851 if ((phyaddr
>= 0) && (phyaddr
<= 31))
1852 priv
->plat
->phy_addr
= phyaddr
;
1854 /* Init MAC and get the capabilities */
1855 stmmac_hw_init(priv
);
1857 ndev
->netdev_ops
= &stmmac_netdev_ops
;
1859 ndev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
1861 ndev
->features
|= ndev
->hw_features
| NETIF_F_HIGHDMA
;
1862 ndev
->watchdog_timeo
= msecs_to_jiffies(watchdog
);
1863 #ifdef STMMAC_VLAN_TAG_USED
1864 /* Both mac100 and gmac support receive VLAN tag detection */
1865 ndev
->features
|= NETIF_F_HW_VLAN_RX
;
1867 priv
->msg_enable
= netif_msg_init(debug
, default_msg_level
);
1870 priv
->flow_ctrl
= FLOW_AUTO
; /* RX/TX pause on */
1872 netif_napi_add(ndev
, &priv
->napi
, stmmac_poll
, 64);
1874 spin_lock_init(&priv
->lock
);
1875 spin_lock_init(&priv
->tx_lock
);
1877 ret
= register_netdev(ndev
);
1879 pr_err("%s: ERROR %i registering the device\n", __func__
, ret
);
1886 netif_napi_del(&priv
->napi
);
1888 unregister_netdev(ndev
);
1896 * @ndev: net device pointer
1897 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1898 * changes the link status, releases the DMA descriptor rings.
1900 int stmmac_dvr_remove(struct net_device
*ndev
)
1902 struct stmmac_priv
*priv
= netdev_priv(ndev
);
1904 pr_info("%s:\n\tremoving driver", __func__
);
1906 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
1907 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1909 stmmac_set_mac(priv
->ioaddr
, false);
1910 netif_carrier_off(ndev
);
1911 unregister_netdev(ndev
);
1918 int stmmac_suspend(struct net_device
*ndev
)
1920 struct stmmac_priv
*priv
= netdev_priv(ndev
);
1923 if (!ndev
|| !netif_running(ndev
))
1927 phy_stop(priv
->phydev
);
1929 spin_lock(&priv
->lock
);
1931 netif_device_detach(ndev
);
1932 netif_stop_queue(ndev
);
1934 #ifdef CONFIG_STMMAC_TIMER
1935 priv
->tm
->timer_stop();
1936 if (likely(priv
->tm
->enable
))
1939 napi_disable(&priv
->napi
);
1941 /* Stop TX/RX DMA */
1942 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1943 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
1944 /* Clear the Rx/Tx descriptors */
1945 priv
->hw
->desc
->init_rx_desc(priv
->dma_rx
, priv
->dma_rx_size
,
1947 priv
->hw
->desc
->init_tx_desc(priv
->dma_tx
, priv
->dma_tx_size
);
1949 /* Enable Power down mode by programming the PMT regs */
1950 if (device_may_wakeup(priv
->device
))
1951 priv
->hw
->mac
->pmt(priv
->ioaddr
, priv
->wolopts
);
1953 stmmac_set_mac(priv
->ioaddr
, false);
1955 spin_unlock(&priv
->lock
);
1959 int stmmac_resume(struct net_device
*ndev
)
1961 struct stmmac_priv
*priv
= netdev_priv(ndev
);
1963 if (!netif_running(ndev
))
1966 spin_lock(&priv
->lock
);
1968 /* Power Down bit, into the PM register, is cleared
1969 * automatically as soon as a magic packet or a Wake-up frame
1970 * is received. Anyway, it's better to manually clear
1971 * this bit because it can generate problems while resuming
1972 * from another devices (e.g. serial console). */
1973 if (device_may_wakeup(priv
->device
))
1974 priv
->hw
->mac
->pmt(priv
->ioaddr
, 0);
1976 netif_device_attach(ndev
);
1978 /* Enable the MAC and DMA */
1979 stmmac_set_mac(priv
->ioaddr
, true);
1980 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1981 priv
->hw
->dma
->start_rx(priv
->ioaddr
);
1983 #ifdef CONFIG_STMMAC_TIMER
1984 if (likely(priv
->tm
->enable
))
1985 priv
->tm
->timer_start(tmrate
);
1987 napi_enable(&priv
->napi
);
1989 netif_start_queue(ndev
);
1991 spin_unlock(&priv
->lock
);
1994 phy_start(priv
->phydev
);
1999 int stmmac_freeze(struct net_device
*ndev
)
2001 if (!ndev
|| !netif_running(ndev
))
2004 return stmmac_release(ndev
);
2007 int stmmac_restore(struct net_device
*ndev
)
2009 if (!ndev
|| !netif_running(ndev
))
2012 return stmmac_open(ndev
);
2014 #endif /* CONFIG_PM */
2017 static int __init
stmmac_cmdline_opt(char *str
)
2023 while ((opt
= strsep(&str
, ",")) != NULL
) {
2024 if (!strncmp(opt
, "debug:", 6)) {
2025 if (strict_strtoul(opt
+ 6, 0, (unsigned long *)&debug
))
2027 } else if (!strncmp(opt
, "phyaddr:", 8)) {
2028 if (strict_strtoul(opt
+ 8, 0,
2029 (unsigned long *)&phyaddr
))
2031 } else if (!strncmp(opt
, "dma_txsize:", 11)) {
2032 if (strict_strtoul(opt
+ 11, 0,
2033 (unsigned long *)&dma_txsize
))
2035 } else if (!strncmp(opt
, "dma_rxsize:", 11)) {
2036 if (strict_strtoul(opt
+ 11, 0,
2037 (unsigned long *)&dma_rxsize
))
2039 } else if (!strncmp(opt
, "buf_sz:", 7)) {
2040 if (strict_strtoul(opt
+ 7, 0,
2041 (unsigned long *)&buf_sz
))
2043 } else if (!strncmp(opt
, "tc:", 3)) {
2044 if (strict_strtoul(opt
+ 3, 0, (unsigned long *)&tc
))
2046 } else if (!strncmp(opt
, "watchdog:", 9)) {
2047 if (strict_strtoul(opt
+ 9, 0,
2048 (unsigned long *)&watchdog
))
2050 } else if (!strncmp(opt
, "flow_ctrl:", 10)) {
2051 if (strict_strtoul(opt
+ 10, 0,
2052 (unsigned long *)&flow_ctrl
))
2054 } else if (!strncmp(opt
, "pause:", 6)) {
2055 if (strict_strtoul(opt
+ 6, 0, (unsigned long *)&pause
))
2057 #ifdef CONFIG_STMMAC_TIMER
2058 } else if (!strncmp(opt
, "tmrate:", 7)) {
2059 if (strict_strtoul(opt
+ 7, 0,
2060 (unsigned long *)&tmrate
))
2068 pr_err("%s: ERROR broken module parameter conversion", __func__
);
2072 __setup("stmmaceth=", stmmac_cmdline_opt
);
2075 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2076 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2077 MODULE_LICENSE("GPL");