1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
54 #include <linux/reset.h>
55 #include <linux/of_mdio.h>
56 #include "dwmac1000.h"
58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
59 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
61 /* Module parameters */
63 static int watchdog
= TX_TIMEO
;
64 module_param(watchdog
, int, S_IRUGO
| S_IWUSR
);
65 MODULE_PARM_DESC(watchdog
, "Transmit timeout in milliseconds (default 5s)");
67 static int debug
= -1;
68 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
69 MODULE_PARM_DESC(debug
, "Message Level (-1: default, 0: no output, 16: all)");
71 static int phyaddr
= -1;
72 module_param(phyaddr
, int, S_IRUGO
);
73 MODULE_PARM_DESC(phyaddr
, "Physical device address");
75 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
76 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
78 static int flow_ctrl
= FLOW_OFF
;
79 module_param(flow_ctrl
, int, S_IRUGO
| S_IWUSR
);
80 MODULE_PARM_DESC(flow_ctrl
, "Flow control ability [on/off]");
82 static int pause
= PAUSE_TIME
;
83 module_param(pause
, int, S_IRUGO
| S_IWUSR
);
84 MODULE_PARM_DESC(pause
, "Flow Control Pause Time");
87 static int tc
= TC_DEFAULT
;
88 module_param(tc
, int, S_IRUGO
| S_IWUSR
);
89 MODULE_PARM_DESC(tc
, "DMA threshold control value");
91 #define DEFAULT_BUFSIZE 1536
92 static int buf_sz
= DEFAULT_BUFSIZE
;
93 module_param(buf_sz
, int, S_IRUGO
| S_IWUSR
);
94 MODULE_PARM_DESC(buf_sz
, "DMA buffer size");
96 #define STMMAC_RX_COPYBREAK 256
98 static const u32 default_msg_level
= (NETIF_MSG_DRV
| NETIF_MSG_PROBE
|
99 NETIF_MSG_LINK
| NETIF_MSG_IFUP
|
100 NETIF_MSG_IFDOWN
| NETIF_MSG_TIMER
);
102 #define STMMAC_DEFAULT_LPI_TIMER 1000
103 static int eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
104 module_param(eee_timer
, int, S_IRUGO
| S_IWUSR
);
105 MODULE_PARM_DESC(eee_timer
, "LPI tx expiration time in msec");
106 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
108 /* By default the driver will use the ring mode to manage tx and rx descriptors
109 * but passing this value so user can force to use the chain instead of the ring
111 static unsigned int chain_mode
;
112 module_param(chain_mode
, int, S_IRUGO
);
113 MODULE_PARM_DESC(chain_mode
, "To use chain instead of ring mode");
115 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
);
117 #ifdef CONFIG_DEBUG_FS
118 static int stmmac_init_fs(struct net_device
*dev
);
119 static void stmmac_exit_fs(struct net_device
*dev
);
122 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
125 * stmmac_verify_args - verify the driver parameters.
126 * Description: it checks the driver parameters and set a default in case of
129 static void stmmac_verify_args(void)
131 if (unlikely(watchdog
< 0))
133 if (unlikely((buf_sz
< DEFAULT_BUFSIZE
) || (buf_sz
> BUF_SIZE_16KiB
)))
134 buf_sz
= DEFAULT_BUFSIZE
;
135 if (unlikely(flow_ctrl
> 1))
136 flow_ctrl
= FLOW_AUTO
;
137 else if (likely(flow_ctrl
< 0))
138 flow_ctrl
= FLOW_OFF
;
139 if (unlikely((pause
< 0) || (pause
> 0xffff)))
142 eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
146 * stmmac_clk_csr_set - dynamically set the MDC clock
147 * @priv: driver private structure
148 * Description: this is to dynamically set the MDC clock according to the csr
151 * If a specific clk_csr value is passed from the platform
152 * this means that the CSR Clock Range selection cannot be
153 * changed at run-time and it is fixed (as reported in the driver
154 * documentation). Viceversa the driver will try to set the MDC
155 * clock dynamically according to the actual clock input.
157 static void stmmac_clk_csr_set(struct stmmac_priv
*priv
)
161 clk_rate
= clk_get_rate(priv
->stmmac_clk
);
163 /* Platform provided default clk_csr would be assumed valid
164 * for all other cases except for the below mentioned ones.
165 * For values higher than the IEEE 802.3 specified frequency
166 * we can not estimate the proper divider as it is not known
167 * the frequency of clk_csr_i. So we do not change the default
170 if (!(priv
->clk_csr
& MAC_CSR_H_FRQ_MASK
)) {
171 if (clk_rate
< CSR_F_35M
)
172 priv
->clk_csr
= STMMAC_CSR_20_35M
;
173 else if ((clk_rate
>= CSR_F_35M
) && (clk_rate
< CSR_F_60M
))
174 priv
->clk_csr
= STMMAC_CSR_35_60M
;
175 else if ((clk_rate
>= CSR_F_60M
) && (clk_rate
< CSR_F_100M
))
176 priv
->clk_csr
= STMMAC_CSR_60_100M
;
177 else if ((clk_rate
>= CSR_F_100M
) && (clk_rate
< CSR_F_150M
))
178 priv
->clk_csr
= STMMAC_CSR_100_150M
;
179 else if ((clk_rate
>= CSR_F_150M
) && (clk_rate
< CSR_F_250M
))
180 priv
->clk_csr
= STMMAC_CSR_150_250M
;
181 else if ((clk_rate
>= CSR_F_250M
) && (clk_rate
< CSR_F_300M
))
182 priv
->clk_csr
= STMMAC_CSR_250_300M
;
186 static void print_pkt(unsigned char *buf
, int len
)
188 pr_debug("len = %d byte, buf addr: 0x%p\n", len
, buf
);
189 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
, buf
, len
);
192 static inline u32
stmmac_tx_avail(struct stmmac_priv
*priv
)
196 if (priv
->dirty_tx
> priv
->cur_tx
)
197 avail
= priv
->dirty_tx
- priv
->cur_tx
- 1;
199 avail
= DMA_TX_SIZE
- priv
->cur_tx
+ priv
->dirty_tx
- 1;
204 static inline u32
stmmac_rx_dirty(struct stmmac_priv
*priv
)
208 if (priv
->dirty_rx
<= priv
->cur_rx
)
209 dirty
= priv
->cur_rx
- priv
->dirty_rx
;
211 dirty
= DMA_RX_SIZE
- priv
->dirty_rx
+ priv
->cur_rx
;
217 * stmmac_hw_fix_mac_speed - callback for speed selection
218 * @priv: driver private structure
219 * Description: on some platforms (e.g. ST), some HW system configuraton
220 * registers have to be set according to the link speed negotiated.
222 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv
*priv
)
224 struct phy_device
*phydev
= priv
->phydev
;
226 if (likely(priv
->plat
->fix_mac_speed
))
227 priv
->plat
->fix_mac_speed(priv
->plat
->bsp_priv
, phydev
->speed
);
231 * stmmac_enable_eee_mode - check and enter in LPI mode
232 * @priv: driver private structure
233 * Description: this function is to verify and enter in LPI mode in case of
236 static void stmmac_enable_eee_mode(struct stmmac_priv
*priv
)
238 /* Check and enter in LPI mode */
239 if ((priv
->dirty_tx
== priv
->cur_tx
) &&
240 (priv
->tx_path_in_lpi_mode
== false))
241 priv
->hw
->mac
->set_eee_mode(priv
->hw
);
245 * stmmac_disable_eee_mode - disable and exit from LPI mode
246 * @priv: driver private structure
247 * Description: this function is to exit and disable EEE in case of
248 * LPI state is true. This is called by the xmit.
250 void stmmac_disable_eee_mode(struct stmmac_priv
*priv
)
252 priv
->hw
->mac
->reset_eee_mode(priv
->hw
);
253 del_timer_sync(&priv
->eee_ctrl_timer
);
254 priv
->tx_path_in_lpi_mode
= false;
258 * stmmac_eee_ctrl_timer - EEE TX SW timer.
261 * if there is no data transfer and if we are not in LPI state,
262 * then MAC Transmitter can be moved to LPI state.
264 static void stmmac_eee_ctrl_timer(unsigned long arg
)
266 struct stmmac_priv
*priv
= (struct stmmac_priv
*)arg
;
268 stmmac_enable_eee_mode(priv
);
269 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
273 * stmmac_eee_init - init EEE
274 * @priv: driver private structure
276 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
277 * can also manage EEE, this function enable the LPI state and start related
280 bool stmmac_eee_init(struct stmmac_priv
*priv
)
285 /* Using PCS we cannot dial with the phy registers at this stage
286 * so we do not support extra feature like EEE.
288 if ((priv
->hw
->pcs
== STMMAC_PCS_RGMII
) ||
289 (priv
->hw
->pcs
== STMMAC_PCS_TBI
) ||
290 (priv
->hw
->pcs
== STMMAC_PCS_RTBI
))
293 /* MAC core supports the EEE feature. */
294 if (priv
->dma_cap
.eee
) {
295 int tx_lpi_timer
= priv
->tx_lpi_timer
;
297 /* Check if the PHY supports EEE */
298 if (phy_init_eee(priv
->phydev
, 1)) {
299 /* To manage at run-time if the EEE cannot be supported
300 * anymore (for example because the lp caps have been
302 * In that case the driver disable own timers.
304 spin_lock_irqsave(&priv
->lock
, flags
);
305 if (priv
->eee_active
) {
306 pr_debug("stmmac: disable EEE\n");
307 del_timer_sync(&priv
->eee_ctrl_timer
);
308 priv
->hw
->mac
->set_eee_timer(priv
->hw
, 0,
311 priv
->eee_active
= 0;
312 spin_unlock_irqrestore(&priv
->lock
, flags
);
315 /* Activate the EEE and start timers */
316 spin_lock_irqsave(&priv
->lock
, flags
);
317 if (!priv
->eee_active
) {
318 priv
->eee_active
= 1;
319 setup_timer(&priv
->eee_ctrl_timer
,
320 stmmac_eee_ctrl_timer
,
321 (unsigned long)priv
);
322 mod_timer(&priv
->eee_ctrl_timer
,
323 STMMAC_LPI_T(eee_timer
));
325 priv
->hw
->mac
->set_eee_timer(priv
->hw
,
326 STMMAC_DEFAULT_LIT_LS
,
329 /* Set HW EEE according to the speed */
330 priv
->hw
->mac
->set_eee_pls(priv
->hw
, priv
->phydev
->link
);
333 spin_unlock_irqrestore(&priv
->lock
, flags
);
335 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
341 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
342 * @priv: driver private structure
343 * @p : descriptor pointer
344 * @skb : the socket buffer
346 * This function will read timestamp from the descriptor & pass it to stack.
347 * and also perform some sanity checks.
349 static void stmmac_get_tx_hwtstamp(struct stmmac_priv
*priv
,
350 struct dma_desc
*p
, struct sk_buff
*skb
)
352 struct skb_shared_hwtstamps shhwtstamp
;
355 if (!priv
->hwts_tx_en
)
358 /* exit if skb doesn't support hw tstamp */
359 if (likely(!skb
|| !(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)))
362 /* check tx tstamp status */
363 if (!priv
->hw
->desc
->get_tx_timestamp_status(p
)) {
364 /* get the valid tstamp */
365 ns
= priv
->hw
->desc
->get_timestamp(p
, priv
->adv_ts
);
367 memset(&shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
368 shhwtstamp
.hwtstamp
= ns_to_ktime(ns
);
370 netdev_info(priv
->dev
, "get valid TX hw timestamp %llu\n", ns
);
371 /* pass tstamp to stack */
372 skb_tstamp_tx(skb
, &shhwtstamp
);
378 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
379 * @priv: driver private structure
380 * @p : descriptor pointer
381 * @np : next descriptor pointer
382 * @skb : the socket buffer
384 * This function will read received packet's timestamp from the descriptor
385 * and pass it to stack. It also perform some sanity checks.
387 static void stmmac_get_rx_hwtstamp(struct stmmac_priv
*priv
, struct dma_desc
*p
,
388 struct dma_desc
*np
, struct sk_buff
*skb
)
390 struct skb_shared_hwtstamps
*shhwtstamp
= NULL
;
393 if (!priv
->hwts_rx_en
)
396 /* Check if timestamp is available */
397 if (!priv
->hw
->desc
->get_rx_timestamp_status(p
, priv
->adv_ts
)) {
398 /* For GMAC4, the valid timestamp is from CTX next desc. */
399 if (priv
->plat
->has_gmac4
)
400 ns
= priv
->hw
->desc
->get_timestamp(np
, priv
->adv_ts
);
402 ns
= priv
->hw
->desc
->get_timestamp(p
, priv
->adv_ts
);
404 netdev_info(priv
->dev
, "get valid RX hw timestamp %llu\n", ns
);
405 shhwtstamp
= skb_hwtstamps(skb
);
406 memset(shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
407 shhwtstamp
->hwtstamp
= ns_to_ktime(ns
);
409 netdev_err(priv
->dev
, "cannot get RX hw timestamp\n");
414 * stmmac_hwtstamp_ioctl - control hardware timestamping.
415 * @dev: device pointer.
416 * @ifr: An IOCTL specefic structure, that can contain a pointer to
417 * a proprietary structure used to pass information to the driver.
419 * This function configures the MAC to enable/disable both outgoing(TX)
420 * and incoming(RX) packets time stamping based on user input.
422 * 0 on success and an appropriate -ve integer on failure.
424 static int stmmac_hwtstamp_ioctl(struct net_device
*dev
, struct ifreq
*ifr
)
426 struct stmmac_priv
*priv
= netdev_priv(dev
);
427 struct hwtstamp_config config
;
428 struct timespec64 now
;
432 u32 ptp_over_ipv4_udp
= 0;
433 u32 ptp_over_ipv6_udp
= 0;
434 u32 ptp_over_ethernet
= 0;
435 u32 snap_type_sel
= 0;
436 u32 ts_master_en
= 0;
441 if (!(priv
->dma_cap
.time_stamp
|| priv
->adv_ts
)) {
442 netdev_alert(priv
->dev
, "No support for HW time stamping\n");
443 priv
->hwts_tx_en
= 0;
444 priv
->hwts_rx_en
= 0;
449 if (copy_from_user(&config
, ifr
->ifr_data
,
450 sizeof(struct hwtstamp_config
)))
453 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
454 __func__
, config
.flags
, config
.tx_type
, config
.rx_filter
);
456 /* reserved for future extensions */
460 if (config
.tx_type
!= HWTSTAMP_TX_OFF
&&
461 config
.tx_type
!= HWTSTAMP_TX_ON
)
465 switch (config
.rx_filter
) {
466 case HWTSTAMP_FILTER_NONE
:
467 /* time stamp no incoming packet at all */
468 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
471 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
472 /* PTP v1, UDP, any kind of event packet */
473 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
474 /* take time stamp for all event messages */
475 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
477 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
478 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
481 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
482 /* PTP v1, UDP, Sync packet */
483 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_SYNC
;
484 /* take time stamp for SYNC messages only */
485 ts_event_en
= PTP_TCR_TSEVNTENA
;
487 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
488 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
491 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
492 /* PTP v1, UDP, Delay_req packet */
493 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
;
494 /* take time stamp for Delay_Req messages only */
495 ts_master_en
= PTP_TCR_TSMSTRENA
;
496 ts_event_en
= PTP_TCR_TSEVNTENA
;
498 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
499 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
502 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
503 /* PTP v2, UDP, any kind of event packet */
504 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_EVENT
;
505 ptp_v2
= PTP_TCR_TSVER2ENA
;
506 /* take time stamp for all event messages */
507 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
509 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
510 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
513 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
514 /* PTP v2, UDP, Sync packet */
515 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_SYNC
;
516 ptp_v2
= PTP_TCR_TSVER2ENA
;
517 /* take time stamp for SYNC messages only */
518 ts_event_en
= PTP_TCR_TSEVNTENA
;
520 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
521 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
524 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
525 /* PTP v2, UDP, Delay_req packet */
526 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
;
527 ptp_v2
= PTP_TCR_TSVER2ENA
;
528 /* take time stamp for Delay_Req messages only */
529 ts_master_en
= PTP_TCR_TSMSTRENA
;
530 ts_event_en
= PTP_TCR_TSEVNTENA
;
532 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
533 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
536 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
537 /* PTP v2/802.AS1 any layer, any kind of event packet */
538 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
539 ptp_v2
= PTP_TCR_TSVER2ENA
;
540 /* take time stamp for all event messages */
541 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
543 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
544 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
545 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
548 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
549 /* PTP v2/802.AS1, any layer, Sync packet */
550 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_SYNC
;
551 ptp_v2
= PTP_TCR_TSVER2ENA
;
552 /* take time stamp for SYNC messages only */
553 ts_event_en
= PTP_TCR_TSEVNTENA
;
555 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
556 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
557 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
560 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
561 /* PTP v2/802.AS1, any layer, Delay_req packet */
562 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
;
563 ptp_v2
= PTP_TCR_TSVER2ENA
;
564 /* take time stamp for Delay_Req messages only */
565 ts_master_en
= PTP_TCR_TSMSTRENA
;
566 ts_event_en
= PTP_TCR_TSEVNTENA
;
568 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
569 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
570 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
573 case HWTSTAMP_FILTER_ALL
:
574 /* time stamp any incoming packet */
575 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
576 tstamp_all
= PTP_TCR_TSENALL
;
583 switch (config
.rx_filter
) {
584 case HWTSTAMP_FILTER_NONE
:
585 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
588 /* PTP v1, UDP, any kind of event packet */
589 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
593 priv
->hwts_rx_en
= ((config
.rx_filter
== HWTSTAMP_FILTER_NONE
) ? 0 : 1);
594 priv
->hwts_tx_en
= config
.tx_type
== HWTSTAMP_TX_ON
;
596 if (!priv
->hwts_tx_en
&& !priv
->hwts_rx_en
)
597 priv
->hw
->ptp
->config_hw_tstamping(priv
->ptpaddr
, 0);
599 value
= (PTP_TCR_TSENA
| PTP_TCR_TSCFUPDT
| PTP_TCR_TSCTRLSSR
|
600 tstamp_all
| ptp_v2
| ptp_over_ethernet
|
601 ptp_over_ipv6_udp
| ptp_over_ipv4_udp
| ts_event_en
|
602 ts_master_en
| snap_type_sel
);
603 priv
->hw
->ptp
->config_hw_tstamping(priv
->ptpaddr
, value
);
605 /* program Sub Second Increment reg */
606 sec_inc
= priv
->hw
->ptp
->config_sub_second_increment(
607 priv
->ptpaddr
, priv
->clk_ptp_rate
,
608 priv
->plat
->has_gmac4
);
609 temp
= div_u64(1000000000ULL, sec_inc
);
611 /* calculate default added value:
613 * addend = (2^32)/freq_div_ratio;
614 * where, freq_div_ratio = 1e9ns/sec_inc
616 temp
= (u64
)(temp
<< 32);
617 priv
->default_addend
= div_u64(temp
, priv
->clk_ptp_rate
);
618 priv
->hw
->ptp
->config_addend(priv
->ptpaddr
,
619 priv
->default_addend
);
621 /* initialize system time */
622 ktime_get_real_ts64(&now
);
624 /* lower 32 bits of tv_sec are safe until y2106 */
625 priv
->hw
->ptp
->init_systime(priv
->ptpaddr
, (u32
)now
.tv_sec
,
629 return copy_to_user(ifr
->ifr_data
, &config
,
630 sizeof(struct hwtstamp_config
)) ? -EFAULT
: 0;
634 * stmmac_init_ptp - init PTP
635 * @priv: driver private structure
636 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
637 * This is done by looking at the HW cap. register.
638 * This function also registers the ptp driver.
640 static int stmmac_init_ptp(struct stmmac_priv
*priv
)
642 if (!(priv
->dma_cap
.time_stamp
|| priv
->dma_cap
.atime_stamp
))
645 /* Fall-back to main clock in case of no PTP ref is passed */
646 priv
->clk_ptp_ref
= devm_clk_get(priv
->device
, "clk_ptp_ref");
647 if (IS_ERR(priv
->clk_ptp_ref
)) {
648 priv
->clk_ptp_rate
= clk_get_rate(priv
->stmmac_clk
);
649 priv
->clk_ptp_ref
= NULL
;
650 netdev_dbg(priv
->dev
, "PTP uses main clock\n");
652 clk_prepare_enable(priv
->clk_ptp_ref
);
653 priv
->clk_ptp_rate
= clk_get_rate(priv
->clk_ptp_ref
);
654 netdev_dbg(priv
->dev
, "PTP rate %d\n", priv
->clk_ptp_rate
);
658 /* Check if adv_ts can be enabled for dwmac 4.x core */
659 if (priv
->plat
->has_gmac4
&& priv
->dma_cap
.atime_stamp
)
661 /* Dwmac 3.x core with extend_desc can support adv_ts */
662 else if (priv
->extend_desc
&& priv
->dma_cap
.atime_stamp
)
665 if (priv
->dma_cap
.time_stamp
)
666 netdev_info(priv
->dev
, "IEEE 1588-2002 Timestamp supported\n");
669 netdev_info(priv
->dev
,
670 "IEEE 1588-2008 Advanced Timestamp supported\n");
672 priv
->hw
->ptp
= &stmmac_ptp
;
673 priv
->hwts_tx_en
= 0;
674 priv
->hwts_rx_en
= 0;
676 stmmac_ptp_register(priv
);
681 static void stmmac_release_ptp(struct stmmac_priv
*priv
)
683 if (priv
->clk_ptp_ref
)
684 clk_disable_unprepare(priv
->clk_ptp_ref
);
685 stmmac_ptp_unregister(priv
);
689 * stmmac_adjust_link - adjusts the link parameters
690 * @dev: net device structure
691 * Description: this is the helper called by the physical abstraction layer
692 * drivers to communicate the phy link status. According the speed and duplex
693 * this driver can invoke registered glue-logic as well.
694 * It also invoke the eee initialization because it could happen when switch
695 * on different networks (that are eee capable).
697 static void stmmac_adjust_link(struct net_device
*dev
)
699 struct stmmac_priv
*priv
= netdev_priv(dev
);
700 struct phy_device
*phydev
= priv
->phydev
;
703 unsigned int fc
= priv
->flow_ctrl
, pause_time
= priv
->pause
;
708 spin_lock_irqsave(&priv
->lock
, flags
);
711 u32 ctrl
= readl(priv
->ioaddr
+ MAC_CTRL_REG
);
713 /* Now we make sure that we can be in full duplex mode.
714 * If not, we operate in half-duplex mode. */
715 if (phydev
->duplex
!= priv
->oldduplex
) {
717 if (!(phydev
->duplex
))
718 ctrl
&= ~priv
->hw
->link
.duplex
;
720 ctrl
|= priv
->hw
->link
.duplex
;
721 priv
->oldduplex
= phydev
->duplex
;
723 /* Flow Control operation */
725 priv
->hw
->mac
->flow_ctrl(priv
->hw
, phydev
->duplex
,
728 if (phydev
->speed
!= priv
->speed
) {
730 switch (phydev
->speed
) {
732 if (likely((priv
->plat
->has_gmac
) ||
733 (priv
->plat
->has_gmac4
)))
734 ctrl
&= ~priv
->hw
->link
.port
;
735 stmmac_hw_fix_mac_speed(priv
);
739 if (likely((priv
->plat
->has_gmac
) ||
740 (priv
->plat
->has_gmac4
))) {
741 ctrl
|= priv
->hw
->link
.port
;
742 if (phydev
->speed
== SPEED_100
) {
743 ctrl
|= priv
->hw
->link
.speed
;
745 ctrl
&= ~(priv
->hw
->link
.speed
);
748 ctrl
&= ~priv
->hw
->link
.port
;
750 stmmac_hw_fix_mac_speed(priv
);
753 if (netif_msg_link(priv
))
754 pr_warn("%s: Speed (%d) not 10/100\n",
755 dev
->name
, phydev
->speed
);
759 priv
->speed
= phydev
->speed
;
762 writel(ctrl
, priv
->ioaddr
+ MAC_CTRL_REG
);
764 if (!priv
->oldlink
) {
768 } else if (priv
->oldlink
) {
772 priv
->oldduplex
= -1;
775 if (new_state
&& netif_msg_link(priv
))
776 phy_print_status(phydev
);
778 spin_unlock_irqrestore(&priv
->lock
, flags
);
780 if (phydev
->is_pseudo_fixed_link
)
781 /* Stop PHY layer to call the hook to adjust the link in case
782 * of a switch is attached to the stmmac driver.
784 phydev
->irq
= PHY_IGNORE_INTERRUPT
;
786 /* At this stage, init the EEE if supported.
787 * Never called in case of fixed_link.
789 priv
->eee_enabled
= stmmac_eee_init(priv
);
793 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
794 * @priv: driver private structure
795 * Description: this is to verify if the HW supports the PCS.
796 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
797 * configured for the TBI, RTBI, or SGMII PHY interface.
799 static void stmmac_check_pcs_mode(struct stmmac_priv
*priv
)
801 int interface
= priv
->plat
->interface
;
803 if (priv
->dma_cap
.pcs
) {
804 if ((interface
== PHY_INTERFACE_MODE_RGMII
) ||
805 (interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
806 (interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
807 (interface
== PHY_INTERFACE_MODE_RGMII_TXID
)) {
808 pr_debug("STMMAC: PCS RGMII support enable\n");
809 priv
->hw
->pcs
= STMMAC_PCS_RGMII
;
810 } else if (interface
== PHY_INTERFACE_MODE_SGMII
) {
811 pr_debug("STMMAC: PCS SGMII support enable\n");
812 priv
->hw
->pcs
= STMMAC_PCS_SGMII
;
818 * stmmac_init_phy - PHY initialization
819 * @dev: net device structure
820 * Description: it initializes the driver's PHY state, and attaches the PHY
825 static int stmmac_init_phy(struct net_device
*dev
)
827 struct stmmac_priv
*priv
= netdev_priv(dev
);
828 struct phy_device
*phydev
;
829 char phy_id_fmt
[MII_BUS_ID_SIZE
+ 3];
830 char bus_id
[MII_BUS_ID_SIZE
];
831 int interface
= priv
->plat
->interface
;
832 int max_speed
= priv
->plat
->max_speed
;
835 priv
->oldduplex
= -1;
837 if (priv
->plat
->phy_node
) {
838 phydev
= of_phy_connect(dev
, priv
->plat
->phy_node
,
839 &stmmac_adjust_link
, 0, interface
);
841 snprintf(bus_id
, MII_BUS_ID_SIZE
, "stmmac-%x",
844 snprintf(phy_id_fmt
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, bus_id
,
845 priv
->plat
->phy_addr
);
846 pr_debug("stmmac_init_phy: trying to attach to %s\n",
849 phydev
= phy_connect(dev
, phy_id_fmt
, &stmmac_adjust_link
,
853 if (IS_ERR_OR_NULL(phydev
)) {
854 pr_err("%s: Could not attach to PHY\n", dev
->name
);
858 return PTR_ERR(phydev
);
861 /* Stop Advertising 1000BASE Capability if interface is not GMII */
862 if ((interface
== PHY_INTERFACE_MODE_MII
) ||
863 (interface
== PHY_INTERFACE_MODE_RMII
) ||
864 (max_speed
< 1000 && max_speed
> 0))
865 phydev
->advertising
&= ~(SUPPORTED_1000baseT_Half
|
866 SUPPORTED_1000baseT_Full
);
869 * Broken HW is sometimes missing the pull-up resistor on the
870 * MDIO line, which results in reads to non-existent devices returning
871 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
873 * Note: phydev->phy_id is the result of reading the UID PHY registers.
875 if (!priv
->plat
->phy_node
&& phydev
->phy_id
== 0) {
876 phy_disconnect(phydev
);
880 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
881 * subsequent PHY polling, make sure we force a link transition if
882 * we have a UP/DOWN/UP transition
884 if (phydev
->is_pseudo_fixed_link
)
885 phydev
->irq
= PHY_POLL
;
887 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
888 " Link = %d\n", dev
->name
, phydev
->phy_id
, phydev
->link
);
890 priv
->phydev
= phydev
;
895 static void stmmac_display_rings(struct stmmac_priv
*priv
)
897 void *head_rx
, *head_tx
;
899 if (priv
->extend_desc
) {
900 head_rx
= (void *)priv
->dma_erx
;
901 head_tx
= (void *)priv
->dma_etx
;
903 head_rx
= (void *)priv
->dma_rx
;
904 head_tx
= (void *)priv
->dma_tx
;
907 /* Display Rx ring */
908 priv
->hw
->desc
->display_ring(head_rx
, DMA_RX_SIZE
, true);
909 /* Display Tx ring */
910 priv
->hw
->desc
->display_ring(head_tx
, DMA_TX_SIZE
, false);
913 static int stmmac_set_bfsize(int mtu
, int bufsize
)
917 if (mtu
>= BUF_SIZE_4KiB
)
919 else if (mtu
>= BUF_SIZE_2KiB
)
921 else if (mtu
> DEFAULT_BUFSIZE
)
924 ret
= DEFAULT_BUFSIZE
;
930 * stmmac_clear_descriptors - clear descriptors
931 * @priv: driver private structure
932 * Description: this function is called to clear the tx and rx descriptors
933 * in case of both basic and extended descriptors are used.
935 static void stmmac_clear_descriptors(struct stmmac_priv
*priv
)
939 /* Clear the Rx/Tx descriptors */
940 for (i
= 0; i
< DMA_RX_SIZE
; i
++)
941 if (priv
->extend_desc
)
942 priv
->hw
->desc
->init_rx_desc(&priv
->dma_erx
[i
].basic
,
943 priv
->use_riwt
, priv
->mode
,
944 (i
== DMA_RX_SIZE
- 1));
946 priv
->hw
->desc
->init_rx_desc(&priv
->dma_rx
[i
],
947 priv
->use_riwt
, priv
->mode
,
948 (i
== DMA_RX_SIZE
- 1));
949 for (i
= 0; i
< DMA_TX_SIZE
; i
++)
950 if (priv
->extend_desc
)
951 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
953 (i
== DMA_TX_SIZE
- 1));
955 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
957 (i
== DMA_TX_SIZE
- 1));
961 * stmmac_init_rx_buffers - init the RX descriptor buffer.
962 * @priv: driver private structure
963 * @p: descriptor pointer
964 * @i: descriptor index
966 * Description: this function is called to allocate a receive buffer, perform
967 * the DMA mapping and init the descriptor.
969 static int stmmac_init_rx_buffers(struct stmmac_priv
*priv
, struct dma_desc
*p
,
974 skb
= __netdev_alloc_skb_ip_align(priv
->dev
, priv
->dma_buf_sz
, flags
);
976 pr_err("%s: Rx init fails; skb is NULL\n", __func__
);
979 priv
->rx_skbuff
[i
] = skb
;
980 priv
->rx_skbuff_dma
[i
] = dma_map_single(priv
->device
, skb
->data
,
983 if (dma_mapping_error(priv
->device
, priv
->rx_skbuff_dma
[i
])) {
984 pr_err("%s: DMA mapping error\n", __func__
);
985 dev_kfree_skb_any(skb
);
989 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
)
990 p
->des0
= priv
->rx_skbuff_dma
[i
];
992 p
->des2
= priv
->rx_skbuff_dma
[i
];
994 if ((priv
->hw
->mode
->init_desc3
) &&
995 (priv
->dma_buf_sz
== BUF_SIZE_16KiB
))
996 priv
->hw
->mode
->init_desc3(p
);
1001 static void stmmac_free_rx_buffers(struct stmmac_priv
*priv
, int i
)
1003 if (priv
->rx_skbuff
[i
]) {
1004 dma_unmap_single(priv
->device
, priv
->rx_skbuff_dma
[i
],
1005 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
1006 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
1008 priv
->rx_skbuff
[i
] = NULL
;
1012 * init_dma_desc_rings - init the RX/TX descriptor rings
1013 * @dev: net device structure
1015 * Description: this function initializes the DMA RX/TX descriptors
1016 * and allocates the socket buffers. It suppors the chained and ring
1019 static int init_dma_desc_rings(struct net_device
*dev
, gfp_t flags
)
1022 struct stmmac_priv
*priv
= netdev_priv(dev
);
1023 unsigned int bfsize
= 0;
1026 if (priv
->hw
->mode
->set_16kib_bfsize
)
1027 bfsize
= priv
->hw
->mode
->set_16kib_bfsize(dev
->mtu
);
1029 if (bfsize
< BUF_SIZE_16KiB
)
1030 bfsize
= stmmac_set_bfsize(dev
->mtu
, priv
->dma_buf_sz
);
1032 priv
->dma_buf_sz
= bfsize
;
1034 if (netif_msg_probe(priv
)) {
1035 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__
,
1036 (u32
) priv
->dma_rx_phy
, (u32
) priv
->dma_tx_phy
);
1038 /* RX INITIALIZATION */
1039 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1041 for (i
= 0; i
< DMA_RX_SIZE
; i
++) {
1043 if (priv
->extend_desc
)
1044 p
= &((priv
->dma_erx
+ i
)->basic
);
1046 p
= priv
->dma_rx
+ i
;
1048 ret
= stmmac_init_rx_buffers(priv
, p
, i
, flags
);
1050 goto err_init_rx_buffers
;
1052 if (netif_msg_probe(priv
))
1053 pr_debug("[%p]\t[%p]\t[%x]\n", priv
->rx_skbuff
[i
],
1054 priv
->rx_skbuff
[i
]->data
,
1055 (unsigned int)priv
->rx_skbuff_dma
[i
]);
1058 priv
->dirty_rx
= (unsigned int)(i
- DMA_RX_SIZE
);
1061 /* Setup the chained descriptor addresses */
1062 if (priv
->mode
== STMMAC_CHAIN_MODE
) {
1063 if (priv
->extend_desc
) {
1064 priv
->hw
->mode
->init(priv
->dma_erx
, priv
->dma_rx_phy
,
1066 priv
->hw
->mode
->init(priv
->dma_etx
, priv
->dma_tx_phy
,
1069 priv
->hw
->mode
->init(priv
->dma_rx
, priv
->dma_rx_phy
,
1071 priv
->hw
->mode
->init(priv
->dma_tx
, priv
->dma_tx_phy
,
1076 /* TX INITIALIZATION */
1077 for (i
= 0; i
< DMA_TX_SIZE
; i
++) {
1079 if (priv
->extend_desc
)
1080 p
= &((priv
->dma_etx
+ i
)->basic
);
1082 p
= priv
->dma_tx
+ i
;
1084 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
1093 priv
->tx_skbuff_dma
[i
].buf
= 0;
1094 priv
->tx_skbuff_dma
[i
].map_as_page
= false;
1095 priv
->tx_skbuff_dma
[i
].len
= 0;
1096 priv
->tx_skbuff_dma
[i
].last_segment
= false;
1097 priv
->tx_skbuff
[i
] = NULL
;
1102 netdev_reset_queue(priv
->dev
);
1104 stmmac_clear_descriptors(priv
);
1106 if (netif_msg_hw(priv
))
1107 stmmac_display_rings(priv
);
1110 err_init_rx_buffers
:
1112 stmmac_free_rx_buffers(priv
, i
);
1116 static void dma_free_rx_skbufs(struct stmmac_priv
*priv
)
1120 for (i
= 0; i
< DMA_RX_SIZE
; i
++)
1121 stmmac_free_rx_buffers(priv
, i
);
1124 static void dma_free_tx_skbufs(struct stmmac_priv
*priv
)
1128 for (i
= 0; i
< DMA_TX_SIZE
; i
++) {
1131 if (priv
->extend_desc
)
1132 p
= &((priv
->dma_etx
+ i
)->basic
);
1134 p
= priv
->dma_tx
+ i
;
1136 if (priv
->tx_skbuff_dma
[i
].buf
) {
1137 if (priv
->tx_skbuff_dma
[i
].map_as_page
)
1138 dma_unmap_page(priv
->device
,
1139 priv
->tx_skbuff_dma
[i
].buf
,
1140 priv
->tx_skbuff_dma
[i
].len
,
1143 dma_unmap_single(priv
->device
,
1144 priv
->tx_skbuff_dma
[i
].buf
,
1145 priv
->tx_skbuff_dma
[i
].len
,
1149 if (priv
->tx_skbuff
[i
] != NULL
) {
1150 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
1151 priv
->tx_skbuff
[i
] = NULL
;
1152 priv
->tx_skbuff_dma
[i
].buf
= 0;
1153 priv
->tx_skbuff_dma
[i
].map_as_page
= false;
1159 * alloc_dma_desc_resources - alloc TX/RX resources.
1160 * @priv: private structure
1161 * Description: according to which descriptor can be used (extend or basic)
1162 * this function allocates the resources for TX and RX paths. In case of
1163 * reception, for example, it pre-allocated the RX socket buffer in order to
1164 * allow zero-copy mechanism.
1166 static int alloc_dma_desc_resources(struct stmmac_priv
*priv
)
1170 priv
->rx_skbuff_dma
= kmalloc_array(DMA_RX_SIZE
, sizeof(dma_addr_t
),
1172 if (!priv
->rx_skbuff_dma
)
1175 priv
->rx_skbuff
= kmalloc_array(DMA_RX_SIZE
, sizeof(struct sk_buff
*),
1177 if (!priv
->rx_skbuff
)
1180 priv
->tx_skbuff_dma
= kmalloc_array(DMA_TX_SIZE
,
1181 sizeof(*priv
->tx_skbuff_dma
),
1183 if (!priv
->tx_skbuff_dma
)
1184 goto err_tx_skbuff_dma
;
1186 priv
->tx_skbuff
= kmalloc_array(DMA_TX_SIZE
, sizeof(struct sk_buff
*),
1188 if (!priv
->tx_skbuff
)
1191 if (priv
->extend_desc
) {
1192 priv
->dma_erx
= dma_zalloc_coherent(priv
->device
, DMA_RX_SIZE
*
1200 priv
->dma_etx
= dma_zalloc_coherent(priv
->device
, DMA_TX_SIZE
*
1205 if (!priv
->dma_etx
) {
1206 dma_free_coherent(priv
->device
, DMA_RX_SIZE
*
1207 sizeof(struct dma_extended_desc
),
1208 priv
->dma_erx
, priv
->dma_rx_phy
);
1212 priv
->dma_rx
= dma_zalloc_coherent(priv
->device
, DMA_RX_SIZE
*
1213 sizeof(struct dma_desc
),
1219 priv
->dma_tx
= dma_zalloc_coherent(priv
->device
, DMA_TX_SIZE
*
1220 sizeof(struct dma_desc
),
1223 if (!priv
->dma_tx
) {
1224 dma_free_coherent(priv
->device
, DMA_RX_SIZE
*
1225 sizeof(struct dma_desc
),
1226 priv
->dma_rx
, priv
->dma_rx_phy
);
1234 kfree(priv
->tx_skbuff
);
1236 kfree(priv
->tx_skbuff_dma
);
1238 kfree(priv
->rx_skbuff
);
1240 kfree(priv
->rx_skbuff_dma
);
1244 static void free_dma_desc_resources(struct stmmac_priv
*priv
)
1246 /* Release the DMA TX/RX socket buffers */
1247 dma_free_rx_skbufs(priv
);
1248 dma_free_tx_skbufs(priv
);
1250 /* Free DMA regions of consistent memory previously allocated */
1251 if (!priv
->extend_desc
) {
1252 dma_free_coherent(priv
->device
,
1253 DMA_TX_SIZE
* sizeof(struct dma_desc
),
1254 priv
->dma_tx
, priv
->dma_tx_phy
);
1255 dma_free_coherent(priv
->device
,
1256 DMA_RX_SIZE
* sizeof(struct dma_desc
),
1257 priv
->dma_rx
, priv
->dma_rx_phy
);
1259 dma_free_coherent(priv
->device
, DMA_TX_SIZE
*
1260 sizeof(struct dma_extended_desc
),
1261 priv
->dma_etx
, priv
->dma_tx_phy
);
1262 dma_free_coherent(priv
->device
, DMA_RX_SIZE
*
1263 sizeof(struct dma_extended_desc
),
1264 priv
->dma_erx
, priv
->dma_rx_phy
);
1266 kfree(priv
->rx_skbuff_dma
);
1267 kfree(priv
->rx_skbuff
);
1268 kfree(priv
->tx_skbuff_dma
);
1269 kfree(priv
->tx_skbuff
);
1273 * stmmac_dma_operation_mode - HW DMA operation mode
1274 * @priv: driver private structure
1275 * Description: it is used for configuring the DMA operation mode register in
1276 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1278 static void stmmac_dma_operation_mode(struct stmmac_priv
*priv
)
1280 int rxfifosz
= priv
->plat
->rx_fifo_size
;
1282 if (priv
->plat
->force_thresh_dma_mode
)
1283 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, tc
, rxfifosz
);
1284 else if (priv
->plat
->force_sf_dma_mode
|| priv
->plat
->tx_coe
) {
1286 * In case of GMAC, SF mode can be enabled
1287 * to perform the TX COE in HW. This depends on:
1288 * 1) TX COE if actually supported
1289 * 2) There is no bugged Jumbo frame support
1290 * that needs to not insert csum in the TDES.
1292 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, SF_DMA_MODE
, SF_DMA_MODE
,
1294 priv
->xstats
.threshold
= SF_DMA_MODE
;
1296 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, SF_DMA_MODE
,
1301 * stmmac_tx_clean - to manage the transmission completion
1302 * @priv: driver private structure
1303 * Description: it reclaims the transmit resources after transmission completes.
1305 static void stmmac_tx_clean(struct stmmac_priv
*priv
)
1307 unsigned int bytes_compl
= 0, pkts_compl
= 0;
1308 unsigned int entry
= priv
->dirty_tx
;
1310 spin_lock(&priv
->tx_lock
);
1312 priv
->xstats
.tx_clean
++;
1314 while (entry
!= priv
->cur_tx
) {
1315 struct sk_buff
*skb
= priv
->tx_skbuff
[entry
];
1319 if (priv
->extend_desc
)
1320 p
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1322 p
= priv
->dma_tx
+ entry
;
1324 status
= priv
->hw
->desc
->tx_status(&priv
->dev
->stats
,
1327 /* Check if the descriptor is owned by the DMA */
1328 if (unlikely(status
& tx_dma_own
))
1331 /* Just consider the last segment and ...*/
1332 if (likely(!(status
& tx_not_ls
))) {
1333 /* ... verify the status error condition */
1334 if (unlikely(status
& tx_err
)) {
1335 priv
->dev
->stats
.tx_errors
++;
1337 priv
->dev
->stats
.tx_packets
++;
1338 priv
->xstats
.tx_pkt_n
++;
1340 stmmac_get_tx_hwtstamp(priv
, p
, skb
);
1343 if (likely(priv
->tx_skbuff_dma
[entry
].buf
)) {
1344 if (priv
->tx_skbuff_dma
[entry
].map_as_page
)
1345 dma_unmap_page(priv
->device
,
1346 priv
->tx_skbuff_dma
[entry
].buf
,
1347 priv
->tx_skbuff_dma
[entry
].len
,
1350 dma_unmap_single(priv
->device
,
1351 priv
->tx_skbuff_dma
[entry
].buf
,
1352 priv
->tx_skbuff_dma
[entry
].len
,
1354 priv
->tx_skbuff_dma
[entry
].buf
= 0;
1355 priv
->tx_skbuff_dma
[entry
].len
= 0;
1356 priv
->tx_skbuff_dma
[entry
].map_as_page
= false;
1359 if (priv
->hw
->mode
->clean_desc3
)
1360 priv
->hw
->mode
->clean_desc3(priv
, p
);
1362 priv
->tx_skbuff_dma
[entry
].last_segment
= false;
1363 priv
->tx_skbuff_dma
[entry
].is_jumbo
= false;
1365 if (likely(skb
!= NULL
)) {
1367 bytes_compl
+= skb
->len
;
1368 dev_consume_skb_any(skb
);
1369 priv
->tx_skbuff
[entry
] = NULL
;
1372 priv
->hw
->desc
->release_tx_desc(p
, priv
->mode
);
1374 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
1376 priv
->dirty_tx
= entry
;
1378 netdev_completed_queue(priv
->dev
, pkts_compl
, bytes_compl
);
1380 if (unlikely(netif_queue_stopped(priv
->dev
) &&
1381 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH
)) {
1382 netif_tx_lock(priv
->dev
);
1383 if (netif_queue_stopped(priv
->dev
) &&
1384 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH
) {
1385 if (netif_msg_tx_done(priv
))
1386 pr_debug("%s: restart transmit\n", __func__
);
1387 netif_wake_queue(priv
->dev
);
1389 netif_tx_unlock(priv
->dev
);
1392 if ((priv
->eee_enabled
) && (!priv
->tx_path_in_lpi_mode
)) {
1393 stmmac_enable_eee_mode(priv
);
1394 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
1396 spin_unlock(&priv
->tx_lock
);
1399 static inline void stmmac_enable_dma_irq(struct stmmac_priv
*priv
)
1401 priv
->hw
->dma
->enable_dma_irq(priv
->ioaddr
);
1404 static inline void stmmac_disable_dma_irq(struct stmmac_priv
*priv
)
1406 priv
->hw
->dma
->disable_dma_irq(priv
->ioaddr
);
1410 * stmmac_tx_err - to manage the tx error
1411 * @priv: driver private structure
1412 * Description: it cleans the descriptors and restarts the transmission
1413 * in case of transmission errors.
1415 static void stmmac_tx_err(struct stmmac_priv
*priv
)
1418 netif_stop_queue(priv
->dev
);
1420 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1421 dma_free_tx_skbufs(priv
);
1422 for (i
= 0; i
< DMA_TX_SIZE
; i
++)
1423 if (priv
->extend_desc
)
1424 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
1426 (i
== DMA_TX_SIZE
- 1));
1428 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
1430 (i
== DMA_TX_SIZE
- 1));
1433 netdev_reset_queue(priv
->dev
);
1434 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1436 priv
->dev
->stats
.tx_errors
++;
1437 netif_wake_queue(priv
->dev
);
1441 * stmmac_dma_interrupt - DMA ISR
1442 * @priv: driver private structure
1443 * Description: this is the DMA ISR. It is called by the main ISR.
1444 * It calls the dwmac dma routine and schedule poll method in case of some
1447 static void stmmac_dma_interrupt(struct stmmac_priv
*priv
)
1450 int rxfifosz
= priv
->plat
->rx_fifo_size
;
1452 status
= priv
->hw
->dma
->dma_interrupt(priv
->ioaddr
, &priv
->xstats
);
1453 if (likely((status
& handle_rx
)) || (status
& handle_tx
)) {
1454 if (likely(napi_schedule_prep(&priv
->napi
))) {
1455 stmmac_disable_dma_irq(priv
);
1456 __napi_schedule(&priv
->napi
);
1459 if (unlikely(status
& tx_hard_error_bump_tc
)) {
1460 /* Try to bump up the dma threshold on this failure */
1461 if (unlikely(priv
->xstats
.threshold
!= SF_DMA_MODE
) &&
1464 if (priv
->plat
->force_thresh_dma_mode
)
1465 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, tc
,
1468 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
,
1469 SF_DMA_MODE
, rxfifosz
);
1470 priv
->xstats
.threshold
= tc
;
1472 } else if (unlikely(status
== tx_hard_error
))
1473 stmmac_tx_err(priv
);
1477 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1478 * @priv: driver private structure
1479 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1481 static void stmmac_mmc_setup(struct stmmac_priv
*priv
)
1483 unsigned int mode
= MMC_CNTRL_RESET_ON_READ
| MMC_CNTRL_COUNTER_RESET
|
1484 MMC_CNTRL_PRESET
| MMC_CNTRL_FULL_HALF_PRESET
;
1486 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
1487 priv
->ptpaddr
= priv
->ioaddr
+ PTP_GMAC4_OFFSET
;
1488 priv
->mmcaddr
= priv
->ioaddr
+ MMC_GMAC4_OFFSET
;
1490 priv
->ptpaddr
= priv
->ioaddr
+ PTP_GMAC3_X_OFFSET
;
1491 priv
->mmcaddr
= priv
->ioaddr
+ MMC_GMAC3_X_OFFSET
;
1494 dwmac_mmc_intr_all_mask(priv
->mmcaddr
);
1496 if (priv
->dma_cap
.rmon
) {
1497 dwmac_mmc_ctrl(priv
->mmcaddr
, mode
);
1498 memset(&priv
->mmc
, 0, sizeof(struct stmmac_counters
));
1500 pr_info(" No MAC Management Counters available\n");
1504 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1505 * @priv: driver private structure
1506 * Description: select the Enhanced/Alternate or Normal descriptors.
1507 * In case of Enhanced/Alternate, it checks if the extended descriptors are
1508 * supported by the HW capability register.
1510 static void stmmac_selec_desc_mode(struct stmmac_priv
*priv
)
1512 if (priv
->plat
->enh_desc
) {
1513 pr_info(" Enhanced/Alternate descriptors\n");
1515 /* GMAC older than 3.50 has no extended descriptors */
1516 if (priv
->synopsys_id
>= DWMAC_CORE_3_50
) {
1517 pr_info("\tEnabled extended descriptors\n");
1518 priv
->extend_desc
= 1;
1520 pr_warn("Extended descriptors not supported\n");
1522 priv
->hw
->desc
= &enh_desc_ops
;
1524 pr_info(" Normal descriptors\n");
1525 priv
->hw
->desc
= &ndesc_ops
;
1530 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1531 * @priv: driver private structure
1533 * new GMAC chip generations have a new register to indicate the
1534 * presence of the optional feature/functions.
1535 * This can be also used to override the value passed through the
1536 * platform and necessary for old MAC10/100 and GMAC chips.
1538 static int stmmac_get_hw_features(struct stmmac_priv
*priv
)
1542 if (priv
->hw
->dma
->get_hw_feature
) {
1543 priv
->hw
->dma
->get_hw_feature(priv
->ioaddr
,
1552 * stmmac_check_ether_addr - check if the MAC addr is valid
1553 * @priv: driver private structure
1555 * it is to verify if the MAC address is valid, in case of failures it
1556 * generates a random MAC address
1558 static void stmmac_check_ether_addr(struct stmmac_priv
*priv
)
1560 if (!is_valid_ether_addr(priv
->dev
->dev_addr
)) {
1561 priv
->hw
->mac
->get_umac_addr(priv
->hw
,
1562 priv
->dev
->dev_addr
, 0);
1563 if (!is_valid_ether_addr(priv
->dev
->dev_addr
))
1564 eth_hw_addr_random(priv
->dev
);
1565 pr_info("%s: device MAC address %pM\n", priv
->dev
->name
,
1566 priv
->dev
->dev_addr
);
1571 * stmmac_init_dma_engine - DMA init.
1572 * @priv: driver private structure
1574 * It inits the DMA invoking the specific MAC/GMAC callback.
1575 * Some DMA parameters can be passed from the platform;
1576 * in case of these are not passed a default is kept for the MAC or GMAC.
1578 static int stmmac_init_dma_engine(struct stmmac_priv
*priv
)
1580 int pbl
= DEFAULT_DMA_PBL
, fixed_burst
= 0, aal
= 0;
1581 int mixed_burst
= 0;
1585 if (priv
->plat
->dma_cfg
) {
1586 pbl
= priv
->plat
->dma_cfg
->pbl
;
1587 fixed_burst
= priv
->plat
->dma_cfg
->fixed_burst
;
1588 mixed_burst
= priv
->plat
->dma_cfg
->mixed_burst
;
1589 aal
= priv
->plat
->dma_cfg
->aal
;
1592 if (priv
->extend_desc
&& (priv
->mode
== STMMAC_RING_MODE
))
1595 ret
= priv
->hw
->dma
->reset(priv
->ioaddr
);
1597 dev_err(priv
->device
, "Failed to reset the dma\n");
1601 priv
->hw
->dma
->init(priv
->ioaddr
, pbl
, fixed_burst
, mixed_burst
,
1602 aal
, priv
->dma_tx_phy
, priv
->dma_rx_phy
, atds
);
1604 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
1605 priv
->rx_tail_addr
= priv
->dma_rx_phy
+
1606 (DMA_RX_SIZE
* sizeof(struct dma_desc
));
1607 priv
->hw
->dma
->set_rx_tail_ptr(priv
->ioaddr
, priv
->rx_tail_addr
,
1610 priv
->tx_tail_addr
= priv
->dma_tx_phy
+
1611 (DMA_TX_SIZE
* sizeof(struct dma_desc
));
1612 priv
->hw
->dma
->set_tx_tail_ptr(priv
->ioaddr
, priv
->tx_tail_addr
,
1616 if (priv
->plat
->axi
&& priv
->hw
->dma
->axi
)
1617 priv
->hw
->dma
->axi(priv
->ioaddr
, priv
->plat
->axi
);
1623 * stmmac_tx_timer - mitigation sw timer for tx.
1624 * @data: data pointer
1626 * This is the timer handler to directly invoke the stmmac_tx_clean.
1628 static void stmmac_tx_timer(unsigned long data
)
1630 struct stmmac_priv
*priv
= (struct stmmac_priv
*)data
;
1632 stmmac_tx_clean(priv
);
1636 * stmmac_init_tx_coalesce - init tx mitigation options.
1637 * @priv: driver private structure
1639 * This inits the transmit coalesce parameters: i.e. timer rate,
1640 * timer handler and default threshold used for enabling the
1641 * interrupt on completion bit.
1643 static void stmmac_init_tx_coalesce(struct stmmac_priv
*priv
)
1645 priv
->tx_coal_frames
= STMMAC_TX_FRAMES
;
1646 priv
->tx_coal_timer
= STMMAC_COAL_TX_TIMER
;
1647 init_timer(&priv
->txtimer
);
1648 priv
->txtimer
.expires
= STMMAC_COAL_TIMER(priv
->tx_coal_timer
);
1649 priv
->txtimer
.data
= (unsigned long)priv
;
1650 priv
->txtimer
.function
= stmmac_tx_timer
;
1651 add_timer(&priv
->txtimer
);
1655 * stmmac_hw_setup - setup mac in a usable state.
1656 * @dev : pointer to the device structure.
1658 * this is the main function to setup the HW in a usable state because the
1659 * dma engine is reset, the core registers are configured (e.g. AXI,
1660 * Checksum features, timers). The DMA is ready to start receiving and
1663 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1666 static int stmmac_hw_setup(struct net_device
*dev
, bool init_ptp
)
1668 struct stmmac_priv
*priv
= netdev_priv(dev
);
1671 /* DMA initialization and SW reset */
1672 ret
= stmmac_init_dma_engine(priv
);
1674 pr_err("%s: DMA engine initialization failed\n", __func__
);
1678 /* Copy the MAC addr into the HW */
1679 priv
->hw
->mac
->set_umac_addr(priv
->hw
, dev
->dev_addr
, 0);
1681 /* If required, perform hw setup of the bus. */
1682 if (priv
->plat
->bus_setup
)
1683 priv
->plat
->bus_setup(priv
->ioaddr
);
1685 /* PS and related bits will be programmed according to the speed */
1686 if (priv
->hw
->pcs
) {
1687 int speed
= priv
->plat
->mac_port_sel_speed
;
1689 if ((speed
== SPEED_10
) || (speed
== SPEED_100
) ||
1690 (speed
== SPEED_1000
)) {
1691 priv
->hw
->ps
= speed
;
1693 dev_warn(priv
->device
, "invalid port speed\n");
1698 /* Initialize the MAC Core */
1699 priv
->hw
->mac
->core_init(priv
->hw
, dev
->mtu
);
1701 ret
= priv
->hw
->mac
->rx_ipc(priv
->hw
);
1703 pr_warn(" RX IPC Checksum Offload disabled\n");
1704 priv
->plat
->rx_coe
= STMMAC_RX_COE_NONE
;
1705 priv
->hw
->rx_csum
= 0;
1708 /* Enable the MAC Rx/Tx */
1709 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
)
1710 stmmac_dwmac4_set_mac(priv
->ioaddr
, true);
1712 stmmac_set_mac(priv
->ioaddr
, true);
1714 /* Set the HW DMA mode and the COE */
1715 stmmac_dma_operation_mode(priv
);
1717 stmmac_mmc_setup(priv
);
1720 ret
= stmmac_init_ptp(priv
);
1722 netdev_warn(priv
->dev
, "fail to init PTP.\n");
1725 #ifdef CONFIG_DEBUG_FS
1726 ret
= stmmac_init_fs(dev
);
1728 pr_warn("%s: failed debugFS registration\n", __func__
);
1730 /* Start the ball rolling... */
1731 pr_debug("%s: DMA RX/TX processes started...\n", dev
->name
);
1732 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1733 priv
->hw
->dma
->start_rx(priv
->ioaddr
);
1735 /* Dump DMA/MAC registers */
1736 if (netif_msg_hw(priv
)) {
1737 priv
->hw
->mac
->dump_regs(priv
->hw
);
1738 priv
->hw
->dma
->dump_regs(priv
->ioaddr
);
1740 priv
->tx_lpi_timer
= STMMAC_DEFAULT_TWT_LS
;
1742 if ((priv
->use_riwt
) && (priv
->hw
->dma
->rx_watchdog
)) {
1743 priv
->rx_riwt
= MAX_DMA_RIWT
;
1744 priv
->hw
->dma
->rx_watchdog(priv
->ioaddr
, MAX_DMA_RIWT
);
1747 if (priv
->hw
->pcs
&& priv
->hw
->mac
->pcs_ctrl_ane
)
1748 priv
->hw
->mac
->pcs_ctrl_ane(priv
->hw
, 1, priv
->hw
->ps
, 0);
1750 /* set TX ring length */
1751 if (priv
->hw
->dma
->set_tx_ring_len
)
1752 priv
->hw
->dma
->set_tx_ring_len(priv
->ioaddr
,
1754 /* set RX ring length */
1755 if (priv
->hw
->dma
->set_rx_ring_len
)
1756 priv
->hw
->dma
->set_rx_ring_len(priv
->ioaddr
,
1760 priv
->hw
->dma
->enable_tso(priv
->ioaddr
, 1, STMMAC_CHAN0
);
1766 * stmmac_open - open entry point of the driver
1767 * @dev : pointer to the device structure.
1769 * This function is the open entry point of the driver.
1771 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1774 static int stmmac_open(struct net_device
*dev
)
1776 struct stmmac_priv
*priv
= netdev_priv(dev
);
1779 stmmac_check_ether_addr(priv
);
1781 if (priv
->hw
->pcs
!= STMMAC_PCS_RGMII
&&
1782 priv
->hw
->pcs
!= STMMAC_PCS_TBI
&&
1783 priv
->hw
->pcs
!= STMMAC_PCS_RTBI
) {
1784 ret
= stmmac_init_phy(dev
);
1786 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1792 /* Extra statistics */
1793 memset(&priv
->xstats
, 0, sizeof(struct stmmac_extra_stats
));
1794 priv
->xstats
.threshold
= tc
;
1796 priv
->dma_buf_sz
= STMMAC_ALIGN(buf_sz
);
1797 priv
->rx_copybreak
= STMMAC_RX_COPYBREAK
;
1799 ret
= alloc_dma_desc_resources(priv
);
1801 pr_err("%s: DMA descriptors allocation failed\n", __func__
);
1802 goto dma_desc_error
;
1805 ret
= init_dma_desc_rings(dev
, GFP_KERNEL
);
1807 pr_err("%s: DMA descriptors initialization failed\n", __func__
);
1811 ret
= stmmac_hw_setup(dev
, true);
1813 pr_err("%s: Hw setup failed\n", __func__
);
1817 stmmac_init_tx_coalesce(priv
);
1820 phy_start(priv
->phydev
);
1822 /* Request the IRQ lines */
1823 ret
= request_irq(dev
->irq
, stmmac_interrupt
,
1824 IRQF_SHARED
, dev
->name
, dev
);
1825 if (unlikely(ret
< 0)) {
1826 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1827 __func__
, dev
->irq
, ret
);
1831 /* Request the Wake IRQ in case of another line is used for WoL */
1832 if (priv
->wol_irq
!= dev
->irq
) {
1833 ret
= request_irq(priv
->wol_irq
, stmmac_interrupt
,
1834 IRQF_SHARED
, dev
->name
, dev
);
1835 if (unlikely(ret
< 0)) {
1836 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1837 __func__
, priv
->wol_irq
, ret
);
1842 /* Request the IRQ lines */
1843 if (priv
->lpi_irq
> 0) {
1844 ret
= request_irq(priv
->lpi_irq
, stmmac_interrupt
, IRQF_SHARED
,
1846 if (unlikely(ret
< 0)) {
1847 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1848 __func__
, priv
->lpi_irq
, ret
);
1853 napi_enable(&priv
->napi
);
1854 netif_start_queue(dev
);
1859 if (priv
->wol_irq
!= dev
->irq
)
1860 free_irq(priv
->wol_irq
, dev
);
1862 free_irq(dev
->irq
, dev
);
1865 free_dma_desc_resources(priv
);
1868 phy_disconnect(priv
->phydev
);
1874 * stmmac_release - close entry point of the driver
1875 * @dev : device pointer.
1877 * This is the stop entry point of the driver.
1879 static int stmmac_release(struct net_device
*dev
)
1881 struct stmmac_priv
*priv
= netdev_priv(dev
);
1883 if (priv
->eee_enabled
)
1884 del_timer_sync(&priv
->eee_ctrl_timer
);
1886 /* Stop and disconnect the PHY */
1888 phy_stop(priv
->phydev
);
1889 phy_disconnect(priv
->phydev
);
1890 priv
->phydev
= NULL
;
1893 netif_stop_queue(dev
);
1895 napi_disable(&priv
->napi
);
1897 del_timer_sync(&priv
->txtimer
);
1899 /* Free the IRQ lines */
1900 free_irq(dev
->irq
, dev
);
1901 if (priv
->wol_irq
!= dev
->irq
)
1902 free_irq(priv
->wol_irq
, dev
);
1903 if (priv
->lpi_irq
> 0)
1904 free_irq(priv
->lpi_irq
, dev
);
1906 /* Stop TX/RX DMA and clear the descriptors */
1907 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1908 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
1910 /* Release and free the Rx/Tx resources */
1911 free_dma_desc_resources(priv
);
1913 /* Disable the MAC Rx/Tx */
1914 stmmac_set_mac(priv
->ioaddr
, false);
1916 netif_carrier_off(dev
);
1918 #ifdef CONFIG_DEBUG_FS
1919 stmmac_exit_fs(dev
);
1922 stmmac_release_ptp(priv
);
1928 * stmmac_tso_allocator - close entry point of the driver
1929 * @priv: driver private structure
1930 * @des: buffer start address
1931 * @total_len: total length to fill in descriptors
1932 * @last_segmant: condition for the last descriptor
1934 * This function fills descriptor and request new descriptors according to
1935 * buffer length to fill
1937 static void stmmac_tso_allocator(struct stmmac_priv
*priv
, unsigned int des
,
1938 int total_len
, bool last_segment
)
1940 struct dma_desc
*desc
;
1944 tmp_len
= total_len
;
1946 while (tmp_len
> 0) {
1947 priv
->cur_tx
= STMMAC_GET_ENTRY(priv
->cur_tx
, DMA_TX_SIZE
);
1948 desc
= priv
->dma_tx
+ priv
->cur_tx
;
1950 desc
->des0
= des
+ (total_len
- tmp_len
);
1951 buff_size
= tmp_len
>= TSO_MAX_BUFF_SIZE
?
1952 TSO_MAX_BUFF_SIZE
: tmp_len
;
1954 priv
->hw
->desc
->prepare_tso_tx_desc(desc
, 0, buff_size
,
1956 (last_segment
) && (buff_size
< TSO_MAX_BUFF_SIZE
),
1959 tmp_len
-= TSO_MAX_BUFF_SIZE
;
1964 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
1965 * @skb : the socket buffer
1966 * @dev : device pointer
1967 * Description: this is the transmit function that is called on TSO frames
1968 * (support available on GMAC4 and newer chips).
1969 * Diagram below show the ring programming in case of TSO frames:
1973 * | DES0 |---> buffer1 = L2/L3/L4 header
1974 * | DES1 |---> TCP Payload (can continue on next descr...)
1975 * | DES2 |---> buffer 1 and 2 len
1976 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
1982 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
1984 * | DES2 | --> buffer 1 and 2 len
1988 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
1990 static netdev_tx_t
stmmac_tso_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1993 int tmp_pay_len
= 0;
1994 struct stmmac_priv
*priv
= netdev_priv(dev
);
1995 int nfrags
= skb_shinfo(skb
)->nr_frags
;
1996 unsigned int first_entry
, des
;
1997 struct dma_desc
*desc
, *first
, *mss_desc
= NULL
;
2001 spin_lock(&priv
->tx_lock
);
2003 /* Compute header lengths */
2004 proto_hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
2006 /* Desc availability based on threshold should be enough safe */
2007 if (unlikely(stmmac_tx_avail(priv
) <
2008 (((skb
->len
- proto_hdr_len
) / TSO_MAX_BUFF_SIZE
+ 1)))) {
2009 if (!netif_queue_stopped(dev
)) {
2010 netif_stop_queue(dev
);
2011 /* This is a hard error, log it. */
2012 pr_err("%s: Tx Ring full when queue awake\n", __func__
);
2014 spin_unlock(&priv
->tx_lock
);
2015 return NETDEV_TX_BUSY
;
2018 pay_len
= skb_headlen(skb
) - proto_hdr_len
; /* no frags */
2020 mss
= skb_shinfo(skb
)->gso_size
;
2022 /* set new MSS value if needed */
2023 if (mss
!= priv
->mss
) {
2024 mss_desc
= priv
->dma_tx
+ priv
->cur_tx
;
2025 priv
->hw
->desc
->set_mss(mss_desc
, mss
);
2027 priv
->cur_tx
= STMMAC_GET_ENTRY(priv
->cur_tx
, DMA_TX_SIZE
);
2030 if (netif_msg_tx_queued(priv
)) {
2031 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2032 __func__
, tcp_hdrlen(skb
), proto_hdr_len
, pay_len
, mss
);
2033 pr_info("\tskb->len %d, skb->data_len %d\n", skb
->len
,
2037 first_entry
= priv
->cur_tx
;
2039 desc
= priv
->dma_tx
+ first_entry
;
2042 /* first descriptor: fill Headers on Buf1 */
2043 des
= dma_map_single(priv
->device
, skb
->data
, skb_headlen(skb
),
2045 if (dma_mapping_error(priv
->device
, des
))
2048 priv
->tx_skbuff_dma
[first_entry
].buf
= des
;
2049 priv
->tx_skbuff_dma
[first_entry
].len
= skb_headlen(skb
);
2050 priv
->tx_skbuff
[first_entry
] = skb
;
2054 /* Fill start of payload in buff2 of first descriptor */
2056 first
->des1
= des
+ proto_hdr_len
;
2058 /* If needed take extra descriptors to fill the remaining payload */
2059 tmp_pay_len
= pay_len
- TSO_MAX_BUFF_SIZE
;
2061 stmmac_tso_allocator(priv
, des
, tmp_pay_len
, (nfrags
== 0));
2063 /* Prepare fragments */
2064 for (i
= 0; i
< nfrags
; i
++) {
2065 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2067 des
= skb_frag_dma_map(priv
->device
, frag
, 0,
2068 skb_frag_size(frag
),
2071 stmmac_tso_allocator(priv
, des
, skb_frag_size(frag
),
2074 priv
->tx_skbuff_dma
[priv
->cur_tx
].buf
= des
;
2075 priv
->tx_skbuff_dma
[priv
->cur_tx
].len
= skb_frag_size(frag
);
2076 priv
->tx_skbuff
[priv
->cur_tx
] = NULL
;
2077 priv
->tx_skbuff_dma
[priv
->cur_tx
].map_as_page
= true;
2080 priv
->tx_skbuff_dma
[priv
->cur_tx
].last_segment
= true;
2082 priv
->cur_tx
= STMMAC_GET_ENTRY(priv
->cur_tx
, DMA_TX_SIZE
);
2084 if (unlikely(stmmac_tx_avail(priv
) <= (MAX_SKB_FRAGS
+ 1))) {
2085 if (netif_msg_hw(priv
))
2086 pr_debug("%s: stop transmitted packets\n", __func__
);
2087 netif_stop_queue(dev
);
2090 dev
->stats
.tx_bytes
+= skb
->len
;
2091 priv
->xstats
.tx_tso_frames
++;
2092 priv
->xstats
.tx_tso_nfrags
+= nfrags
;
2094 /* Manage tx mitigation */
2095 priv
->tx_count_frames
+= nfrags
+ 1;
2096 if (likely(priv
->tx_coal_frames
> priv
->tx_count_frames
)) {
2097 mod_timer(&priv
->txtimer
,
2098 STMMAC_COAL_TIMER(priv
->tx_coal_timer
));
2100 priv
->tx_count_frames
= 0;
2101 priv
->hw
->desc
->set_tx_ic(desc
);
2102 priv
->xstats
.tx_set_ic_bit
++;
2105 if (!priv
->hwts_tx_en
)
2106 skb_tx_timestamp(skb
);
2108 if (unlikely((skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) &&
2109 priv
->hwts_tx_en
)) {
2110 /* declare that device is doing timestamping */
2111 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
2112 priv
->hw
->desc
->enable_tx_timestamp(first
);
2115 /* Complete the first descriptor before granting the DMA */
2116 priv
->hw
->desc
->prepare_tso_tx_desc(first
, 1,
2119 1, priv
->tx_skbuff_dma
[first_entry
].last_segment
,
2120 tcp_hdrlen(skb
) / 4, (skb
->len
- proto_hdr_len
));
2122 /* If context desc is used to change MSS */
2124 priv
->hw
->desc
->set_tx_owner(mss_desc
);
2126 /* The own bit must be the latest setting done when prepare the
2127 * descriptor and then barrier is needed to make sure that
2128 * all is coherent before granting the DMA engine.
2132 if (netif_msg_pktdata(priv
)) {
2133 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2134 __func__
, priv
->cur_tx
, priv
->dirty_tx
, first_entry
,
2135 priv
->cur_tx
, first
, nfrags
);
2137 priv
->hw
->desc
->display_ring((void *)priv
->dma_tx
, DMA_TX_SIZE
,
2140 pr_info(">>> frame to be transmitted: ");
2141 print_pkt(skb
->data
, skb_headlen(skb
));
2144 netdev_sent_queue(dev
, skb
->len
);
2146 priv
->hw
->dma
->set_tx_tail_ptr(priv
->ioaddr
, priv
->tx_tail_addr
,
2149 spin_unlock(&priv
->tx_lock
);
2150 return NETDEV_TX_OK
;
2153 spin_unlock(&priv
->tx_lock
);
2154 dev_err(priv
->device
, "Tx dma map failed\n");
2156 priv
->dev
->stats
.tx_dropped
++;
2157 return NETDEV_TX_OK
;
2161 * stmmac_xmit - Tx entry point of the driver
2162 * @skb : the socket buffer
2163 * @dev : device pointer
2164 * Description : this is the tx entry point of the driver.
2165 * It programs the chain or the ring and supports oversized frames
2168 static netdev_tx_t
stmmac_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2170 struct stmmac_priv
*priv
= netdev_priv(dev
);
2171 unsigned int nopaged_len
= skb_headlen(skb
);
2172 int i
, csum_insertion
= 0, is_jumbo
= 0;
2173 int nfrags
= skb_shinfo(skb
)->nr_frags
;
2174 unsigned int entry
, first_entry
;
2175 struct dma_desc
*desc
, *first
;
2176 unsigned int enh_desc
;
2179 /* Manage oversized TCP frames for GMAC4 device */
2180 if (skb_is_gso(skb
) && priv
->tso
) {
2181 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
2182 return stmmac_tso_xmit(skb
, dev
);
2185 spin_lock(&priv
->tx_lock
);
2187 if (unlikely(stmmac_tx_avail(priv
) < nfrags
+ 1)) {
2188 spin_unlock(&priv
->tx_lock
);
2189 if (!netif_queue_stopped(dev
)) {
2190 netif_stop_queue(dev
);
2191 /* This is a hard error, log it. */
2192 pr_err("%s: Tx Ring full when queue awake\n", __func__
);
2194 return NETDEV_TX_BUSY
;
2197 if (priv
->tx_path_in_lpi_mode
)
2198 stmmac_disable_eee_mode(priv
);
2200 entry
= priv
->cur_tx
;
2201 first_entry
= entry
;
2203 csum_insertion
= (skb
->ip_summed
== CHECKSUM_PARTIAL
);
2205 if (likely(priv
->extend_desc
))
2206 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
2208 desc
= priv
->dma_tx
+ entry
;
2212 priv
->tx_skbuff
[first_entry
] = skb
;
2214 enh_desc
= priv
->plat
->enh_desc
;
2215 /* To program the descriptors according to the size of the frame */
2217 is_jumbo
= priv
->hw
->mode
->is_jumbo_frm(skb
->len
, enh_desc
);
2219 if (unlikely(is_jumbo
) && likely(priv
->synopsys_id
<
2221 entry
= priv
->hw
->mode
->jumbo_frm(priv
, skb
, csum_insertion
);
2222 if (unlikely(entry
< 0))
2226 for (i
= 0; i
< nfrags
; i
++) {
2227 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2228 int len
= skb_frag_size(frag
);
2229 bool last_segment
= (i
== (nfrags
- 1));
2231 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
2233 if (likely(priv
->extend_desc
))
2234 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
2236 desc
= priv
->dma_tx
+ entry
;
2238 des
= skb_frag_dma_map(priv
->device
, frag
, 0, len
,
2240 if (dma_mapping_error(priv
->device
, des
))
2241 goto dma_map_err
; /* should reuse desc w/o issues */
2243 priv
->tx_skbuff
[entry
] = NULL
;
2245 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
)) {
2247 priv
->tx_skbuff_dma
[entry
].buf
= desc
->des0
;
2250 priv
->tx_skbuff_dma
[entry
].buf
= desc
->des2
;
2253 priv
->tx_skbuff_dma
[entry
].map_as_page
= true;
2254 priv
->tx_skbuff_dma
[entry
].len
= len
;
2255 priv
->tx_skbuff_dma
[entry
].last_segment
= last_segment
;
2257 /* Prepare the descriptor and set the own bit too */
2258 priv
->hw
->desc
->prepare_tx_desc(desc
, 0, len
, csum_insertion
,
2259 priv
->mode
, 1, last_segment
);
2262 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
2264 priv
->cur_tx
= entry
;
2266 if (netif_msg_pktdata(priv
)) {
2269 pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2270 __func__
, priv
->cur_tx
, priv
->dirty_tx
, first_entry
,
2271 entry
, first
, nfrags
);
2273 if (priv
->extend_desc
)
2274 tx_head
= (void *)priv
->dma_etx
;
2276 tx_head
= (void *)priv
->dma_tx
;
2278 priv
->hw
->desc
->display_ring(tx_head
, DMA_TX_SIZE
, false);
2280 pr_debug(">>> frame to be transmitted: ");
2281 print_pkt(skb
->data
, skb
->len
);
2284 if (unlikely(stmmac_tx_avail(priv
) <= (MAX_SKB_FRAGS
+ 1))) {
2285 if (netif_msg_hw(priv
))
2286 pr_debug("%s: stop transmitted packets\n", __func__
);
2287 netif_stop_queue(dev
);
2290 dev
->stats
.tx_bytes
+= skb
->len
;
2292 /* According to the coalesce parameter the IC bit for the latest
2293 * segment is reset and the timer re-started to clean the tx status.
2294 * This approach takes care about the fragments: desc is the first
2295 * element in case of no SG.
2297 priv
->tx_count_frames
+= nfrags
+ 1;
2298 if (likely(priv
->tx_coal_frames
> priv
->tx_count_frames
)) {
2299 mod_timer(&priv
->txtimer
,
2300 STMMAC_COAL_TIMER(priv
->tx_coal_timer
));
2302 priv
->tx_count_frames
= 0;
2303 priv
->hw
->desc
->set_tx_ic(desc
);
2304 priv
->xstats
.tx_set_ic_bit
++;
2307 if (!priv
->hwts_tx_en
)
2308 skb_tx_timestamp(skb
);
2310 /* Ready to fill the first descriptor and set the OWN bit w/o any
2311 * problems because all the descriptors are actually ready to be
2312 * passed to the DMA engine.
2314 if (likely(!is_jumbo
)) {
2315 bool last_segment
= (nfrags
== 0);
2317 des
= dma_map_single(priv
->device
, skb
->data
,
2318 nopaged_len
, DMA_TO_DEVICE
);
2319 if (dma_mapping_error(priv
->device
, des
))
2322 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
)) {
2324 priv
->tx_skbuff_dma
[first_entry
].buf
= first
->des0
;
2327 priv
->tx_skbuff_dma
[first_entry
].buf
= first
->des2
;
2330 priv
->tx_skbuff_dma
[first_entry
].len
= nopaged_len
;
2331 priv
->tx_skbuff_dma
[first_entry
].last_segment
= last_segment
;
2333 if (unlikely((skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) &&
2334 priv
->hwts_tx_en
)) {
2335 /* declare that device is doing timestamping */
2336 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
2337 priv
->hw
->desc
->enable_tx_timestamp(first
);
2340 /* Prepare the first descriptor setting the OWN bit too */
2341 priv
->hw
->desc
->prepare_tx_desc(first
, 1, nopaged_len
,
2342 csum_insertion
, priv
->mode
, 1,
2345 /* The own bit must be the latest setting done when prepare the
2346 * descriptor and then barrier is needed to make sure that
2347 * all is coherent before granting the DMA engine.
2352 netdev_sent_queue(dev
, skb
->len
);
2354 if (priv
->synopsys_id
< DWMAC_CORE_4_00
)
2355 priv
->hw
->dma
->enable_dma_transmission(priv
->ioaddr
);
2357 priv
->hw
->dma
->set_tx_tail_ptr(priv
->ioaddr
, priv
->tx_tail_addr
,
2360 spin_unlock(&priv
->tx_lock
);
2361 return NETDEV_TX_OK
;
2364 spin_unlock(&priv
->tx_lock
);
2365 dev_err(priv
->device
, "Tx dma map failed\n");
2367 priv
->dev
->stats
.tx_dropped
++;
2368 return NETDEV_TX_OK
;
2371 static void stmmac_rx_vlan(struct net_device
*dev
, struct sk_buff
*skb
)
2373 struct ethhdr
*ehdr
;
2376 if ((dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) ==
2377 NETIF_F_HW_VLAN_CTAG_RX
&&
2378 !__vlan_get_tag(skb
, &vlanid
)) {
2379 /* pop the vlan tag */
2380 ehdr
= (struct ethhdr
*)skb
->data
;
2381 memmove(skb
->data
+ VLAN_HLEN
, ehdr
, ETH_ALEN
* 2);
2382 skb_pull(skb
, VLAN_HLEN
);
2383 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vlanid
);
2388 static inline int stmmac_rx_threshold_count(struct stmmac_priv
*priv
)
2390 if (priv
->rx_zeroc_thresh
< STMMAC_RX_THRESH
)
2397 * stmmac_rx_refill - refill used skb preallocated buffers
2398 * @priv: driver private structure
2399 * Description : this is to reallocate the skb for the reception process
2400 * that is based on zero-copy.
2402 static inline void stmmac_rx_refill(struct stmmac_priv
*priv
)
2404 int bfsize
= priv
->dma_buf_sz
;
2405 unsigned int entry
= priv
->dirty_rx
;
2406 int dirty
= stmmac_rx_dirty(priv
);
2408 while (dirty
-- > 0) {
2411 if (priv
->extend_desc
)
2412 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2414 p
= priv
->dma_rx
+ entry
;
2416 if (likely(priv
->rx_skbuff
[entry
] == NULL
)) {
2417 struct sk_buff
*skb
;
2419 skb
= netdev_alloc_skb_ip_align(priv
->dev
, bfsize
);
2420 if (unlikely(!skb
)) {
2421 /* so for a while no zero-copy! */
2422 priv
->rx_zeroc_thresh
= STMMAC_RX_THRESH
;
2423 if (unlikely(net_ratelimit()))
2424 dev_err(priv
->device
,
2425 "fail to alloc skb entry %d\n",
2430 priv
->rx_skbuff
[entry
] = skb
;
2431 priv
->rx_skbuff_dma
[entry
] =
2432 dma_map_single(priv
->device
, skb
->data
, bfsize
,
2434 if (dma_mapping_error(priv
->device
,
2435 priv
->rx_skbuff_dma
[entry
])) {
2436 dev_err(priv
->device
, "Rx dma map failed\n");
2441 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
)) {
2442 p
->des0
= priv
->rx_skbuff_dma
[entry
];
2445 p
->des2
= priv
->rx_skbuff_dma
[entry
];
2447 if (priv
->hw
->mode
->refill_desc3
)
2448 priv
->hw
->mode
->refill_desc3(priv
, p
);
2450 if (priv
->rx_zeroc_thresh
> 0)
2451 priv
->rx_zeroc_thresh
--;
2453 if (netif_msg_rx_status(priv
))
2454 pr_debug("\trefill entry #%d\n", entry
);
2458 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
))
2459 priv
->hw
->desc
->init_rx_desc(p
, priv
->use_riwt
, 0, 0);
2461 priv
->hw
->desc
->set_rx_owner(p
);
2465 entry
= STMMAC_GET_ENTRY(entry
, DMA_RX_SIZE
);
2467 priv
->dirty_rx
= entry
;
2471 * stmmac_rx - manage the receive process
2472 * @priv: driver private structure
2473 * @limit: napi bugget.
2474 * Description : this the function called by the napi poll method.
2475 * It gets all the frames inside the ring.
2477 static int stmmac_rx(struct stmmac_priv
*priv
, int limit
)
2479 unsigned int entry
= priv
->cur_rx
;
2480 unsigned int next_entry
;
2481 unsigned int count
= 0;
2482 int coe
= priv
->hw
->rx_csum
;
2484 if (netif_msg_rx_status(priv
)) {
2487 pr_info(">>>>>> %s: descriptor ring:\n", __func__
);
2488 if (priv
->extend_desc
)
2489 rx_head
= (void *)priv
->dma_erx
;
2491 rx_head
= (void *)priv
->dma_rx
;
2493 priv
->hw
->desc
->display_ring(rx_head
, DMA_RX_SIZE
, true);
2495 while (count
< limit
) {
2498 struct dma_desc
*np
;
2500 if (priv
->extend_desc
)
2501 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2503 p
= priv
->dma_rx
+ entry
;
2505 /* read the status of the incoming frame */
2506 status
= priv
->hw
->desc
->rx_status(&priv
->dev
->stats
,
2508 /* check if managed by the DMA otherwise go ahead */
2509 if (unlikely(status
& dma_own
))
2514 priv
->cur_rx
= STMMAC_GET_ENTRY(priv
->cur_rx
, DMA_RX_SIZE
);
2515 next_entry
= priv
->cur_rx
;
2517 if (priv
->extend_desc
)
2518 np
= (struct dma_desc
*)(priv
->dma_erx
+ next_entry
);
2520 np
= priv
->dma_rx
+ next_entry
;
2524 if ((priv
->extend_desc
) && (priv
->hw
->desc
->rx_extended_status
))
2525 priv
->hw
->desc
->rx_extended_status(&priv
->dev
->stats
,
2529 if (unlikely(status
== discard_frame
)) {
2530 priv
->dev
->stats
.rx_errors
++;
2531 if (priv
->hwts_rx_en
&& !priv
->extend_desc
) {
2532 /* DESC2 & DESC3 will be overwitten by device
2533 * with timestamp value, hence reinitialize
2534 * them in stmmac_rx_refill() function so that
2535 * device can reuse it.
2537 priv
->rx_skbuff
[entry
] = NULL
;
2538 dma_unmap_single(priv
->device
,
2539 priv
->rx_skbuff_dma
[entry
],
2544 struct sk_buff
*skb
;
2548 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
))
2553 frame_len
= priv
->hw
->desc
->get_rx_frame_len(p
, coe
);
2555 /* If frame length is greather than skb buffer size
2556 * (preallocated during init) then the packet is
2559 if (frame_len
> priv
->dma_buf_sz
) {
2560 pr_err("%s: len %d larger than size (%d)\n",
2561 priv
->dev
->name
, frame_len
,
2563 priv
->dev
->stats
.rx_length_errors
++;
2567 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2568 * Type frames (LLC/LLC-SNAP)
2570 if (unlikely(status
!= llc_snap
))
2571 frame_len
-= ETH_FCS_LEN
;
2573 if (netif_msg_rx_status(priv
)) {
2574 pr_info("\tdesc: %p [entry %d] buff=0x%x\n",
2576 if (frame_len
> ETH_FRAME_LEN
)
2577 pr_debug("\tframe size %d, COE: %d\n",
2581 /* The zero-copy is always used for all the sizes
2582 * in case of GMAC4 because it needs
2583 * to refill the used descriptors, always.
2585 if (unlikely(!priv
->plat
->has_gmac4
&&
2586 ((frame_len
< priv
->rx_copybreak
) ||
2587 stmmac_rx_threshold_count(priv
)))) {
2588 skb
= netdev_alloc_skb_ip_align(priv
->dev
,
2590 if (unlikely(!skb
)) {
2591 if (net_ratelimit())
2592 dev_warn(priv
->device
,
2593 "packet dropped\n");
2594 priv
->dev
->stats
.rx_dropped
++;
2598 dma_sync_single_for_cpu(priv
->device
,
2602 skb_copy_to_linear_data(skb
,
2604 rx_skbuff
[entry
]->data
,
2607 skb_put(skb
, frame_len
);
2608 dma_sync_single_for_device(priv
->device
,
2613 skb
= priv
->rx_skbuff
[entry
];
2614 if (unlikely(!skb
)) {
2615 pr_err("%s: Inconsistent Rx chain\n",
2617 priv
->dev
->stats
.rx_dropped
++;
2620 prefetch(skb
->data
- NET_IP_ALIGN
);
2621 priv
->rx_skbuff
[entry
] = NULL
;
2622 priv
->rx_zeroc_thresh
++;
2624 skb_put(skb
, frame_len
);
2625 dma_unmap_single(priv
->device
,
2626 priv
->rx_skbuff_dma
[entry
],
2631 if (netif_msg_pktdata(priv
)) {
2632 pr_debug("frame received (%dbytes)", frame_len
);
2633 print_pkt(skb
->data
, frame_len
);
2636 stmmac_get_rx_hwtstamp(priv
, p
, np
, skb
);
2638 stmmac_rx_vlan(priv
->dev
, skb
);
2640 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
2643 skb_checksum_none_assert(skb
);
2645 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2647 napi_gro_receive(&priv
->napi
, skb
);
2649 priv
->dev
->stats
.rx_packets
++;
2650 priv
->dev
->stats
.rx_bytes
+= frame_len
;
2655 stmmac_rx_refill(priv
);
2657 priv
->xstats
.rx_pkt_n
+= count
;
2663 * stmmac_poll - stmmac poll method (NAPI)
2664 * @napi : pointer to the napi structure.
2665 * @budget : maximum number of packets that the current CPU can receive from
2668 * To look at the incoming frames and clear the tx resources.
2670 static int stmmac_poll(struct napi_struct
*napi
, int budget
)
2672 struct stmmac_priv
*priv
= container_of(napi
, struct stmmac_priv
, napi
);
2675 priv
->xstats
.napi_poll
++;
2676 stmmac_tx_clean(priv
);
2678 work_done
= stmmac_rx(priv
, budget
);
2679 if (work_done
< budget
) {
2680 napi_complete(napi
);
2681 stmmac_enable_dma_irq(priv
);
2688 * @dev : Pointer to net device structure
2689 * Description: this function is called when a packet transmission fails to
2690 * complete within a reasonable time. The driver will mark the error in the
2691 * netdev structure and arrange for the device to be reset to a sane state
2692 * in order to transmit a new packet.
2694 static void stmmac_tx_timeout(struct net_device
*dev
)
2696 struct stmmac_priv
*priv
= netdev_priv(dev
);
2698 /* Clear Tx resources and restart transmitting again */
2699 stmmac_tx_err(priv
);
2703 * stmmac_set_rx_mode - entry point for multicast addressing
2704 * @dev : pointer to the device structure
2706 * This function is a driver entry point which gets called by the kernel
2707 * whenever multicast addresses must be enabled/disabled.
2711 static void stmmac_set_rx_mode(struct net_device
*dev
)
2713 struct stmmac_priv
*priv
= netdev_priv(dev
);
2715 priv
->hw
->mac
->set_filter(priv
->hw
, dev
);
2719 * stmmac_change_mtu - entry point to change MTU size for the device.
2720 * @dev : device pointer.
2721 * @new_mtu : the new MTU size for the device.
2722 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2723 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2724 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2726 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2729 static int stmmac_change_mtu(struct net_device
*dev
, int new_mtu
)
2731 struct stmmac_priv
*priv
= netdev_priv(dev
);
2734 if (netif_running(dev
)) {
2735 pr_err("%s: must be stopped to change its MTU\n", dev
->name
);
2739 if ((priv
->plat
->enh_desc
) || (priv
->synopsys_id
>= DWMAC_CORE_4_00
))
2740 max_mtu
= JUMBO_LEN
;
2742 max_mtu
= SKB_MAX_HEAD(NET_SKB_PAD
+ NET_IP_ALIGN
);
2744 if (priv
->plat
->maxmtu
< max_mtu
)
2745 max_mtu
= priv
->plat
->maxmtu
;
2747 if ((new_mtu
< 46) || (new_mtu
> max_mtu
)) {
2748 pr_err("%s: invalid MTU, max MTU is: %d\n", dev
->name
, max_mtu
);
2754 netdev_update_features(dev
);
2759 static netdev_features_t
stmmac_fix_features(struct net_device
*dev
,
2760 netdev_features_t features
)
2762 struct stmmac_priv
*priv
= netdev_priv(dev
);
2764 if (priv
->plat
->rx_coe
== STMMAC_RX_COE_NONE
)
2765 features
&= ~NETIF_F_RXCSUM
;
2767 if (!priv
->plat
->tx_coe
)
2768 features
&= ~NETIF_F_CSUM_MASK
;
2770 /* Some GMAC devices have a bugged Jumbo frame support that
2771 * needs to have the Tx COE disabled for oversized frames
2772 * (due to limited buffer sizes). In this case we disable
2773 * the TX csum insertionin the TDES and not use SF.
2775 if (priv
->plat
->bugged_jumbo
&& (dev
->mtu
> ETH_DATA_LEN
))
2776 features
&= ~NETIF_F_CSUM_MASK
;
2778 /* Disable tso if asked by ethtool */
2779 if ((priv
->plat
->tso_en
) && (priv
->dma_cap
.tsoen
)) {
2780 if (features
& NETIF_F_TSO
)
2789 static int stmmac_set_features(struct net_device
*netdev
,
2790 netdev_features_t features
)
2792 struct stmmac_priv
*priv
= netdev_priv(netdev
);
2794 /* Keep the COE Type in case of csum is supporting */
2795 if (features
& NETIF_F_RXCSUM
)
2796 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
2798 priv
->hw
->rx_csum
= 0;
2799 /* No check needed because rx_coe has been set before and it will be
2800 * fixed in case of issue.
2802 priv
->hw
->mac
->rx_ipc(priv
->hw
);
2808 * stmmac_interrupt - main ISR
2809 * @irq: interrupt number.
2810 * @dev_id: to pass the net device pointer.
2811 * Description: this is the main driver interrupt service routine.
2813 * o DMA service routine (to manage incoming frame reception and transmission
2815 * o Core interrupts to manage: remote wake-up, management counter, LPI
2818 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
)
2820 struct net_device
*dev
= (struct net_device
*)dev_id
;
2821 struct stmmac_priv
*priv
= netdev_priv(dev
);
2824 pm_wakeup_event(priv
->device
, 0);
2826 if (unlikely(!dev
)) {
2827 pr_err("%s: invalid dev pointer\n", __func__
);
2831 /* To handle GMAC own interrupts */
2832 if ((priv
->plat
->has_gmac
) || (priv
->plat
->has_gmac4
)) {
2833 int status
= priv
->hw
->mac
->host_irq_status(priv
->hw
,
2835 if (unlikely(status
)) {
2836 /* For LPI we need to save the tx status */
2837 if (status
& CORE_IRQ_TX_PATH_IN_LPI_MODE
)
2838 priv
->tx_path_in_lpi_mode
= true;
2839 if (status
& CORE_IRQ_TX_PATH_EXIT_LPI_MODE
)
2840 priv
->tx_path_in_lpi_mode
= false;
2841 if (status
& CORE_IRQ_MTL_RX_OVERFLOW
&& priv
->hw
->dma
->set_rx_tail_ptr
)
2842 priv
->hw
->dma
->set_rx_tail_ptr(priv
->ioaddr
,
2847 /* PCS link status */
2848 if (priv
->hw
->pcs
) {
2849 if (priv
->xstats
.pcs_link
)
2850 netif_carrier_on(dev
);
2852 netif_carrier_off(dev
);
2856 /* To handle DMA interrupts */
2857 stmmac_dma_interrupt(priv
);
2862 #ifdef CONFIG_NET_POLL_CONTROLLER
2863 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2864 * to allow network I/O with interrupts disabled.
2866 static void stmmac_poll_controller(struct net_device
*dev
)
2868 disable_irq(dev
->irq
);
2869 stmmac_interrupt(dev
->irq
, dev
);
2870 enable_irq(dev
->irq
);
2875 * stmmac_ioctl - Entry point for the Ioctl
2876 * @dev: Device pointer.
2877 * @rq: An IOCTL specefic structure, that can contain a pointer to
2878 * a proprietary structure used to pass information to the driver.
2879 * @cmd: IOCTL command
2881 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2883 static int stmmac_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2885 struct stmmac_priv
*priv
= netdev_priv(dev
);
2886 int ret
= -EOPNOTSUPP
;
2888 if (!netif_running(dev
))
2897 ret
= phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
2900 ret
= stmmac_hwtstamp_ioctl(dev
, rq
);
2909 #ifdef CONFIG_DEBUG_FS
2910 static struct dentry
*stmmac_fs_dir
;
2912 static void sysfs_display_ring(void *head
, int size
, int extend_desc
,
2913 struct seq_file
*seq
)
2916 struct dma_extended_desc
*ep
= (struct dma_extended_desc
*)head
;
2917 struct dma_desc
*p
= (struct dma_desc
*)head
;
2919 for (i
= 0; i
< size
; i
++) {
2923 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2924 i
, (unsigned int)virt_to_phys(ep
),
2925 ep
->basic
.des0
, ep
->basic
.des1
,
2926 ep
->basic
.des2
, ep
->basic
.des3
);
2930 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2931 i
, (unsigned int)virt_to_phys(ep
),
2932 p
->des0
, p
->des1
, p
->des2
, p
->des3
);
2935 seq_printf(seq
, "\n");
2939 static int stmmac_sysfs_ring_read(struct seq_file
*seq
, void *v
)
2941 struct net_device
*dev
= seq
->private;
2942 struct stmmac_priv
*priv
= netdev_priv(dev
);
2944 if (priv
->extend_desc
) {
2945 seq_printf(seq
, "Extended RX descriptor ring:\n");
2946 sysfs_display_ring((void *)priv
->dma_erx
, DMA_RX_SIZE
, 1, seq
);
2947 seq_printf(seq
, "Extended TX descriptor ring:\n");
2948 sysfs_display_ring((void *)priv
->dma_etx
, DMA_TX_SIZE
, 1, seq
);
2950 seq_printf(seq
, "RX descriptor ring:\n");
2951 sysfs_display_ring((void *)priv
->dma_rx
, DMA_RX_SIZE
, 0, seq
);
2952 seq_printf(seq
, "TX descriptor ring:\n");
2953 sysfs_display_ring((void *)priv
->dma_tx
, DMA_TX_SIZE
, 0, seq
);
2959 static int stmmac_sysfs_ring_open(struct inode
*inode
, struct file
*file
)
2961 return single_open(file
, stmmac_sysfs_ring_read
, inode
->i_private
);
2964 static const struct file_operations stmmac_rings_status_fops
= {
2965 .owner
= THIS_MODULE
,
2966 .open
= stmmac_sysfs_ring_open
,
2968 .llseek
= seq_lseek
,
2969 .release
= single_release
,
2972 static int stmmac_sysfs_dma_cap_read(struct seq_file
*seq
, void *v
)
2974 struct net_device
*dev
= seq
->private;
2975 struct stmmac_priv
*priv
= netdev_priv(dev
);
2977 if (!priv
->hw_cap_support
) {
2978 seq_printf(seq
, "DMA HW features not supported\n");
2982 seq_printf(seq
, "==============================\n");
2983 seq_printf(seq
, "\tDMA HW features\n");
2984 seq_printf(seq
, "==============================\n");
2986 seq_printf(seq
, "\t10/100 Mbps %s\n",
2987 (priv
->dma_cap
.mbps_10_100
) ? "Y" : "N");
2988 seq_printf(seq
, "\t1000 Mbps %s\n",
2989 (priv
->dma_cap
.mbps_1000
) ? "Y" : "N");
2990 seq_printf(seq
, "\tHalf duple %s\n",
2991 (priv
->dma_cap
.half_duplex
) ? "Y" : "N");
2992 seq_printf(seq
, "\tHash Filter: %s\n",
2993 (priv
->dma_cap
.hash_filter
) ? "Y" : "N");
2994 seq_printf(seq
, "\tMultiple MAC address registers: %s\n",
2995 (priv
->dma_cap
.multi_addr
) ? "Y" : "N");
2996 seq_printf(seq
, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2997 (priv
->dma_cap
.pcs
) ? "Y" : "N");
2998 seq_printf(seq
, "\tSMA (MDIO) Interface: %s\n",
2999 (priv
->dma_cap
.sma_mdio
) ? "Y" : "N");
3000 seq_printf(seq
, "\tPMT Remote wake up: %s\n",
3001 (priv
->dma_cap
.pmt_remote_wake_up
) ? "Y" : "N");
3002 seq_printf(seq
, "\tPMT Magic Frame: %s\n",
3003 (priv
->dma_cap
.pmt_magic_frame
) ? "Y" : "N");
3004 seq_printf(seq
, "\tRMON module: %s\n",
3005 (priv
->dma_cap
.rmon
) ? "Y" : "N");
3006 seq_printf(seq
, "\tIEEE 1588-2002 Time Stamp: %s\n",
3007 (priv
->dma_cap
.time_stamp
) ? "Y" : "N");
3008 seq_printf(seq
, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
3009 (priv
->dma_cap
.atime_stamp
) ? "Y" : "N");
3010 seq_printf(seq
, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
3011 (priv
->dma_cap
.eee
) ? "Y" : "N");
3012 seq_printf(seq
, "\tAV features: %s\n", (priv
->dma_cap
.av
) ? "Y" : "N");
3013 seq_printf(seq
, "\tChecksum Offload in TX: %s\n",
3014 (priv
->dma_cap
.tx_coe
) ? "Y" : "N");
3015 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
3016 seq_printf(seq
, "\tIP Checksum Offload in RX: %s\n",
3017 (priv
->dma_cap
.rx_coe
) ? "Y" : "N");
3019 seq_printf(seq
, "\tIP Checksum Offload (type1) in RX: %s\n",
3020 (priv
->dma_cap
.rx_coe_type1
) ? "Y" : "N");
3021 seq_printf(seq
, "\tIP Checksum Offload (type2) in RX: %s\n",
3022 (priv
->dma_cap
.rx_coe_type2
) ? "Y" : "N");
3024 seq_printf(seq
, "\tRXFIFO > 2048bytes: %s\n",
3025 (priv
->dma_cap
.rxfifo_over_2048
) ? "Y" : "N");
3026 seq_printf(seq
, "\tNumber of Additional RX channel: %d\n",
3027 priv
->dma_cap
.number_rx_channel
);
3028 seq_printf(seq
, "\tNumber of Additional TX channel: %d\n",
3029 priv
->dma_cap
.number_tx_channel
);
3030 seq_printf(seq
, "\tEnhanced descriptors: %s\n",
3031 (priv
->dma_cap
.enh_desc
) ? "Y" : "N");
3036 static int stmmac_sysfs_dma_cap_open(struct inode
*inode
, struct file
*file
)
3038 return single_open(file
, stmmac_sysfs_dma_cap_read
, inode
->i_private
);
3041 static const struct file_operations stmmac_dma_cap_fops
= {
3042 .owner
= THIS_MODULE
,
3043 .open
= stmmac_sysfs_dma_cap_open
,
3045 .llseek
= seq_lseek
,
3046 .release
= single_release
,
3049 static int stmmac_init_fs(struct net_device
*dev
)
3051 struct stmmac_priv
*priv
= netdev_priv(dev
);
3053 /* Create per netdev entries */
3054 priv
->dbgfs_dir
= debugfs_create_dir(dev
->name
, stmmac_fs_dir
);
3056 if (!priv
->dbgfs_dir
|| IS_ERR(priv
->dbgfs_dir
)) {
3057 pr_err("ERROR %s/%s, debugfs create directory failed\n",
3058 STMMAC_RESOURCE_NAME
, dev
->name
);
3063 /* Entry to report DMA RX/TX rings */
3064 priv
->dbgfs_rings_status
=
3065 debugfs_create_file("descriptors_status", S_IRUGO
,
3066 priv
->dbgfs_dir
, dev
,
3067 &stmmac_rings_status_fops
);
3069 if (!priv
->dbgfs_rings_status
|| IS_ERR(priv
->dbgfs_rings_status
)) {
3070 pr_info("ERROR creating stmmac ring debugfs file\n");
3071 debugfs_remove_recursive(priv
->dbgfs_dir
);
3076 /* Entry to report the DMA HW features */
3077 priv
->dbgfs_dma_cap
= debugfs_create_file("dma_cap", S_IRUGO
,
3079 dev
, &stmmac_dma_cap_fops
);
3081 if (!priv
->dbgfs_dma_cap
|| IS_ERR(priv
->dbgfs_dma_cap
)) {
3082 pr_info("ERROR creating stmmac MMC debugfs file\n");
3083 debugfs_remove_recursive(priv
->dbgfs_dir
);
3091 static void stmmac_exit_fs(struct net_device
*dev
)
3093 struct stmmac_priv
*priv
= netdev_priv(dev
);
3095 debugfs_remove_recursive(priv
->dbgfs_dir
);
3097 #endif /* CONFIG_DEBUG_FS */
3099 static const struct net_device_ops stmmac_netdev_ops
= {
3100 .ndo_open
= stmmac_open
,
3101 .ndo_start_xmit
= stmmac_xmit
,
3102 .ndo_stop
= stmmac_release
,
3103 .ndo_change_mtu
= stmmac_change_mtu
,
3104 .ndo_fix_features
= stmmac_fix_features
,
3105 .ndo_set_features
= stmmac_set_features
,
3106 .ndo_set_rx_mode
= stmmac_set_rx_mode
,
3107 .ndo_tx_timeout
= stmmac_tx_timeout
,
3108 .ndo_do_ioctl
= stmmac_ioctl
,
3109 #ifdef CONFIG_NET_POLL_CONTROLLER
3110 .ndo_poll_controller
= stmmac_poll_controller
,
3112 .ndo_set_mac_address
= eth_mac_addr
,
3116 * stmmac_hw_init - Init the MAC device
3117 * @priv: driver private structure
3118 * Description: this function is to configure the MAC device according to
3119 * some platform parameters or the HW capability register. It prepares the
3120 * driver to use either ring or chain modes and to setup either enhanced or
3121 * normal descriptors.
3123 static int stmmac_hw_init(struct stmmac_priv
*priv
)
3125 struct mac_device_info
*mac
;
3127 /* Identify the MAC HW device */
3128 if (priv
->plat
->has_gmac
) {
3129 priv
->dev
->priv_flags
|= IFF_UNICAST_FLT
;
3130 mac
= dwmac1000_setup(priv
->ioaddr
,
3131 priv
->plat
->multicast_filter_bins
,
3132 priv
->plat
->unicast_filter_entries
,
3133 &priv
->synopsys_id
);
3134 } else if (priv
->plat
->has_gmac4
) {
3135 priv
->dev
->priv_flags
|= IFF_UNICAST_FLT
;
3136 mac
= dwmac4_setup(priv
->ioaddr
,
3137 priv
->plat
->multicast_filter_bins
,
3138 priv
->plat
->unicast_filter_entries
,
3139 &priv
->synopsys_id
);
3141 mac
= dwmac100_setup(priv
->ioaddr
, &priv
->synopsys_id
);
3148 /* To use the chained or ring mode */
3149 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
3150 priv
->hw
->mode
= &dwmac4_ring_mode_ops
;
3153 priv
->hw
->mode
= &chain_mode_ops
;
3154 pr_info(" Chain mode enabled\n");
3155 priv
->mode
= STMMAC_CHAIN_MODE
;
3157 priv
->hw
->mode
= &ring_mode_ops
;
3158 pr_info(" Ring mode enabled\n");
3159 priv
->mode
= STMMAC_RING_MODE
;
3163 /* Get the HW capability (new GMAC newer than 3.50a) */
3164 priv
->hw_cap_support
= stmmac_get_hw_features(priv
);
3165 if (priv
->hw_cap_support
) {
3166 pr_info(" DMA HW capability register supported");
3168 /* We can override some gmac/dma configuration fields: e.g.
3169 * enh_desc, tx_coe (e.g. that are passed through the
3170 * platform) with the values from the HW capability
3171 * register (if supported).
3173 priv
->plat
->enh_desc
= priv
->dma_cap
.enh_desc
;
3174 priv
->plat
->pmt
= priv
->dma_cap
.pmt_remote_wake_up
;
3175 priv
->hw
->pmt
= priv
->plat
->pmt
;
3177 /* TXCOE doesn't work in thresh DMA mode */
3178 if (priv
->plat
->force_thresh_dma_mode
)
3179 priv
->plat
->tx_coe
= 0;
3181 priv
->plat
->tx_coe
= priv
->dma_cap
.tx_coe
;
3183 /* In case of GMAC4 rx_coe is from HW cap register. */
3184 priv
->plat
->rx_coe
= priv
->dma_cap
.rx_coe
;
3186 if (priv
->dma_cap
.rx_coe_type2
)
3187 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE2
;
3188 else if (priv
->dma_cap
.rx_coe_type1
)
3189 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE1
;
3192 pr_info(" No HW DMA feature register supported");
3194 /* To use alternate (extended), normal or GMAC4 descriptor structures */
3195 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
)
3196 priv
->hw
->desc
= &dwmac4_desc_ops
;
3198 stmmac_selec_desc_mode(priv
);
3200 if (priv
->plat
->rx_coe
) {
3201 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
3202 pr_info(" RX Checksum Offload Engine supported\n");
3203 if (priv
->synopsys_id
< DWMAC_CORE_4_00
)
3204 pr_info("\tCOE Type %d\n", priv
->hw
->rx_csum
);
3206 if (priv
->plat
->tx_coe
)
3207 pr_info(" TX Checksum insertion supported\n");
3209 if (priv
->plat
->pmt
) {
3210 pr_info(" Wake-Up On Lan supported\n");
3211 device_set_wakeup_capable(priv
->device
, 1);
3214 if (priv
->dma_cap
.tsoen
)
3215 pr_info(" TSO supported\n");
3222 * @device: device pointer
3223 * @plat_dat: platform data pointer
3224 * @res: stmmac resource pointer
3225 * Description: this is the main probe function used to
3226 * call the alloc_etherdev, allocate the priv structure.
3228 * returns 0 on success, otherwise errno.
3230 int stmmac_dvr_probe(struct device
*device
,
3231 struct plat_stmmacenet_data
*plat_dat
,
3232 struct stmmac_resources
*res
)
3235 struct net_device
*ndev
= NULL
;
3236 struct stmmac_priv
*priv
;
3238 ndev
= alloc_etherdev(sizeof(struct stmmac_priv
));
3242 SET_NETDEV_DEV(ndev
, device
);
3244 priv
= netdev_priv(ndev
);
3245 priv
->device
= device
;
3248 stmmac_set_ethtool_ops(ndev
);
3249 priv
->pause
= pause
;
3250 priv
->plat
= plat_dat
;
3251 priv
->ioaddr
= res
->addr
;
3252 priv
->dev
->base_addr
= (unsigned long)res
->addr
;
3254 priv
->dev
->irq
= res
->irq
;
3255 priv
->wol_irq
= res
->wol_irq
;
3256 priv
->lpi_irq
= res
->lpi_irq
;
3259 memcpy(priv
->dev
->dev_addr
, res
->mac
, ETH_ALEN
);
3261 dev_set_drvdata(device
, priv
->dev
);
3263 /* Verify driver arguments */
3264 stmmac_verify_args();
3266 /* Override with kernel parameters if supplied XXX CRS XXX
3267 * this needs to have multiple instances
3269 if ((phyaddr
>= 0) && (phyaddr
<= 31))
3270 priv
->plat
->phy_addr
= phyaddr
;
3272 priv
->stmmac_clk
= devm_clk_get(priv
->device
, STMMAC_RESOURCE_NAME
);
3273 if (IS_ERR(priv
->stmmac_clk
)) {
3274 dev_warn(priv
->device
, "%s: warning: cannot get CSR clock\n",
3276 /* If failed to obtain stmmac_clk and specific clk_csr value
3277 * is NOT passed from the platform, probe fail.
3279 if (!priv
->plat
->clk_csr
) {
3280 ret
= PTR_ERR(priv
->stmmac_clk
);
3283 priv
->stmmac_clk
= NULL
;
3286 clk_prepare_enable(priv
->stmmac_clk
);
3288 priv
->pclk
= devm_clk_get(priv
->device
, "pclk");
3289 if (IS_ERR(priv
->pclk
)) {
3290 if (PTR_ERR(priv
->pclk
) == -EPROBE_DEFER
) {
3291 ret
= -EPROBE_DEFER
;
3292 goto error_pclk_get
;
3296 clk_prepare_enable(priv
->pclk
);
3298 priv
->stmmac_rst
= devm_reset_control_get(priv
->device
,
3299 STMMAC_RESOURCE_NAME
);
3300 if (IS_ERR(priv
->stmmac_rst
)) {
3301 if (PTR_ERR(priv
->stmmac_rst
) == -EPROBE_DEFER
) {
3302 ret
= -EPROBE_DEFER
;
3305 dev_info(priv
->device
, "no reset control found\n");
3306 priv
->stmmac_rst
= NULL
;
3308 if (priv
->stmmac_rst
)
3309 reset_control_deassert(priv
->stmmac_rst
);
3311 /* Init MAC and get the capabilities */
3312 ret
= stmmac_hw_init(priv
);
3316 ndev
->netdev_ops
= &stmmac_netdev_ops
;
3318 ndev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
3321 if ((priv
->plat
->tso_en
) && (priv
->dma_cap
.tsoen
)) {
3322 ndev
->hw_features
|= NETIF_F_TSO
;
3324 pr_info(" TSO feature enabled\n");
3326 ndev
->features
|= ndev
->hw_features
| NETIF_F_HIGHDMA
;
3327 ndev
->watchdog_timeo
= msecs_to_jiffies(watchdog
);
3328 #ifdef STMMAC_VLAN_TAG_USED
3329 /* Both mac100 and gmac support receive VLAN tag detection */
3330 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_RX
;
3332 priv
->msg_enable
= netif_msg_init(debug
, default_msg_level
);
3335 priv
->flow_ctrl
= FLOW_AUTO
; /* RX/TX pause on */
3337 /* Rx Watchdog is available in the COREs newer than the 3.40.
3338 * In some case, for example on bugged HW this feature
3339 * has to be disable and this can be done by passing the
3340 * riwt_off field from the platform.
3342 if ((priv
->synopsys_id
>= DWMAC_CORE_3_50
) && (!priv
->plat
->riwt_off
)) {
3344 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
3347 netif_napi_add(ndev
, &priv
->napi
, stmmac_poll
, 64);
3349 spin_lock_init(&priv
->lock
);
3350 spin_lock_init(&priv
->tx_lock
);
3352 ret
= register_netdev(ndev
);
3354 pr_err("%s: ERROR %i registering the device\n", __func__
, ret
);
3355 goto error_netdev_register
;
3358 /* If a specific clk_csr value is passed from the platform
3359 * this means that the CSR Clock Range selection cannot be
3360 * changed at run-time and it is fixed. Viceversa the driver'll try to
3361 * set the MDC clock dynamically according to the csr actual
3364 if (!priv
->plat
->clk_csr
)
3365 stmmac_clk_csr_set(priv
);
3367 priv
->clk_csr
= priv
->plat
->clk_csr
;
3369 stmmac_check_pcs_mode(priv
);
3371 if (priv
->hw
->pcs
!= STMMAC_PCS_RGMII
&&
3372 priv
->hw
->pcs
!= STMMAC_PCS_TBI
&&
3373 priv
->hw
->pcs
!= STMMAC_PCS_RTBI
) {
3374 /* MDIO bus Registration */
3375 ret
= stmmac_mdio_register(ndev
);
3377 pr_debug("%s: MDIO bus (id: %d) registration failed",
3378 __func__
, priv
->plat
->bus_id
);
3379 goto error_mdio_register
;
3385 error_mdio_register
:
3386 unregister_netdev(ndev
);
3387 error_netdev_register
:
3388 netif_napi_del(&priv
->napi
);
3390 clk_disable_unprepare(priv
->pclk
);
3392 clk_disable_unprepare(priv
->stmmac_clk
);
3398 EXPORT_SYMBOL_GPL(stmmac_dvr_probe
);
3402 * @dev: device pointer
3403 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3404 * changes the link status, releases the DMA descriptor rings.
3406 int stmmac_dvr_remove(struct device
*dev
)
3408 struct net_device
*ndev
= dev_get_drvdata(dev
);
3409 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3411 pr_info("%s:\n\tremoving driver", __func__
);
3413 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
3414 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
3416 stmmac_set_mac(priv
->ioaddr
, false);
3417 netif_carrier_off(ndev
);
3418 unregister_netdev(ndev
);
3419 of_node_put(priv
->plat
->phy_node
);
3420 if (priv
->stmmac_rst
)
3421 reset_control_assert(priv
->stmmac_rst
);
3422 clk_disable_unprepare(priv
->pclk
);
3423 clk_disable_unprepare(priv
->stmmac_clk
);
3424 if (priv
->hw
->pcs
!= STMMAC_PCS_RGMII
&&
3425 priv
->hw
->pcs
!= STMMAC_PCS_TBI
&&
3426 priv
->hw
->pcs
!= STMMAC_PCS_RTBI
)
3427 stmmac_mdio_unregister(ndev
);
3432 EXPORT_SYMBOL_GPL(stmmac_dvr_remove
);
3435 * stmmac_suspend - suspend callback
3436 * @dev: device pointer
3437 * Description: this is the function to suspend the device and it is called
3438 * by the platform driver to stop the network queue, release the resources,
3439 * program the PMT register (for WoL), clean and release driver resources.
3441 int stmmac_suspend(struct device
*dev
)
3443 struct net_device
*ndev
= dev_get_drvdata(dev
);
3444 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3445 unsigned long flags
;
3447 if (!ndev
|| !netif_running(ndev
))
3451 phy_stop(priv
->phydev
);
3453 spin_lock_irqsave(&priv
->lock
, flags
);
3455 netif_device_detach(ndev
);
3456 netif_stop_queue(ndev
);
3458 napi_disable(&priv
->napi
);
3460 /* Stop TX/RX DMA */
3461 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
3462 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
3464 /* Enable Power down mode by programming the PMT regs */
3465 if (device_may_wakeup(priv
->device
)) {
3466 priv
->hw
->mac
->pmt(priv
->hw
, priv
->wolopts
);
3469 stmmac_set_mac(priv
->ioaddr
, false);
3470 pinctrl_pm_select_sleep_state(priv
->device
);
3471 /* Disable clock in case of PWM is off */
3472 clk_disable(priv
->pclk
);
3473 clk_disable(priv
->stmmac_clk
);
3475 spin_unlock_irqrestore(&priv
->lock
, flags
);
3479 priv
->oldduplex
= -1;
3482 EXPORT_SYMBOL_GPL(stmmac_suspend
);
3485 * stmmac_resume - resume callback
3486 * @dev: device pointer
3487 * Description: when resume this function is invoked to setup the DMA and CORE
3488 * in a usable state.
3490 int stmmac_resume(struct device
*dev
)
3492 struct net_device
*ndev
= dev_get_drvdata(dev
);
3493 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3494 unsigned long flags
;
3496 if (!netif_running(ndev
))
3499 /* Power Down bit, into the PM register, is cleared
3500 * automatically as soon as a magic packet or a Wake-up frame
3501 * is received. Anyway, it's better to manually clear
3502 * this bit because it can generate problems while resuming
3503 * from another devices (e.g. serial console).
3505 if (device_may_wakeup(priv
->device
)) {
3506 spin_lock_irqsave(&priv
->lock
, flags
);
3507 priv
->hw
->mac
->pmt(priv
->hw
, 0);
3508 spin_unlock_irqrestore(&priv
->lock
, flags
);
3511 pinctrl_pm_select_default_state(priv
->device
);
3512 /* enable the clk prevously disabled */
3513 clk_enable(priv
->stmmac_clk
);
3514 clk_enable(priv
->pclk
);
3515 /* reset the phy so that it's ready */
3517 stmmac_mdio_reset(priv
->mii
);
3520 netif_device_attach(ndev
);
3522 spin_lock_irqsave(&priv
->lock
, flags
);
3528 /* reset private mss value to force mss context settings at
3529 * next tso xmit (only used for gmac4).
3533 stmmac_clear_descriptors(priv
);
3535 stmmac_hw_setup(ndev
, false);
3536 stmmac_init_tx_coalesce(priv
);
3537 stmmac_set_rx_mode(ndev
);
3539 napi_enable(&priv
->napi
);
3541 netif_start_queue(ndev
);
3543 spin_unlock_irqrestore(&priv
->lock
, flags
);
3546 phy_start(priv
->phydev
);
3550 EXPORT_SYMBOL_GPL(stmmac_resume
);
3553 static int __init
stmmac_cmdline_opt(char *str
)
3559 while ((opt
= strsep(&str
, ",")) != NULL
) {
3560 if (!strncmp(opt
, "debug:", 6)) {
3561 if (kstrtoint(opt
+ 6, 0, &debug
))
3563 } else if (!strncmp(opt
, "phyaddr:", 8)) {
3564 if (kstrtoint(opt
+ 8, 0, &phyaddr
))
3566 } else if (!strncmp(opt
, "buf_sz:", 7)) {
3567 if (kstrtoint(opt
+ 7, 0, &buf_sz
))
3569 } else if (!strncmp(opt
, "tc:", 3)) {
3570 if (kstrtoint(opt
+ 3, 0, &tc
))
3572 } else if (!strncmp(opt
, "watchdog:", 9)) {
3573 if (kstrtoint(opt
+ 9, 0, &watchdog
))
3575 } else if (!strncmp(opt
, "flow_ctrl:", 10)) {
3576 if (kstrtoint(opt
+ 10, 0, &flow_ctrl
))
3578 } else if (!strncmp(opt
, "pause:", 6)) {
3579 if (kstrtoint(opt
+ 6, 0, &pause
))
3581 } else if (!strncmp(opt
, "eee_timer:", 10)) {
3582 if (kstrtoint(opt
+ 10, 0, &eee_timer
))
3584 } else if (!strncmp(opt
, "chain_mode:", 11)) {
3585 if (kstrtoint(opt
+ 11, 0, &chain_mode
))
3592 pr_err("%s: ERROR broken module parameter conversion", __func__
);
3596 __setup("stmmaceth=", stmmac_cmdline_opt
);
3599 static int __init
stmmac_init(void)
3601 #ifdef CONFIG_DEBUG_FS
3602 /* Create debugfs main directory if it doesn't exist yet */
3603 if (!stmmac_fs_dir
) {
3604 stmmac_fs_dir
= debugfs_create_dir(STMMAC_RESOURCE_NAME
, NULL
);
3606 if (!stmmac_fs_dir
|| IS_ERR(stmmac_fs_dir
)) {
3607 pr_err("ERROR %s, debugfs create directory failed\n",
3608 STMMAC_RESOURCE_NAME
);
3618 static void __exit
stmmac_exit(void)
3620 #ifdef CONFIG_DEBUG_FS
3621 debugfs_remove_recursive(stmmac_fs_dir
);
3625 module_init(stmmac_init
)
3626 module_exit(stmmac_exit
)
3628 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3629 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3630 MODULE_LICENSE("GPL");