1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
54 #include <linux/reset.h>
55 #include <linux/of_mdio.h>
56 #include "dwmac1000.h"
58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
60 /* Module parameters */
62 static int watchdog
= TX_TIMEO
;
63 module_param(watchdog
, int, S_IRUGO
| S_IWUSR
);
64 MODULE_PARM_DESC(watchdog
, "Transmit timeout in milliseconds (default 5s)");
66 static int debug
= -1;
67 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
68 MODULE_PARM_DESC(debug
, "Message Level (-1: default, 0: no output, 16: all)");
70 static int phyaddr
= -1;
71 module_param(phyaddr
, int, S_IRUGO
);
72 MODULE_PARM_DESC(phyaddr
, "Physical device address");
74 #define DMA_TX_SIZE 256
75 static int dma_txsize
= DMA_TX_SIZE
;
76 module_param(dma_txsize
, int, S_IRUGO
| S_IWUSR
);
77 MODULE_PARM_DESC(dma_txsize
, "Number of descriptors in the TX list");
79 #define DMA_RX_SIZE 256
80 static int dma_rxsize
= DMA_RX_SIZE
;
81 module_param(dma_rxsize
, int, S_IRUGO
| S_IWUSR
);
82 MODULE_PARM_DESC(dma_rxsize
, "Number of descriptors in the RX list");
84 static int flow_ctrl
= FLOW_OFF
;
85 module_param(flow_ctrl
, int, S_IRUGO
| S_IWUSR
);
86 MODULE_PARM_DESC(flow_ctrl
, "Flow control ability [on/off]");
88 static int pause
= PAUSE_TIME
;
89 module_param(pause
, int, S_IRUGO
| S_IWUSR
);
90 MODULE_PARM_DESC(pause
, "Flow Control Pause Time");
93 static int tc
= TC_DEFAULT
;
94 module_param(tc
, int, S_IRUGO
| S_IWUSR
);
95 MODULE_PARM_DESC(tc
, "DMA threshold control value");
97 #define DEFAULT_BUFSIZE 1536
98 static int buf_sz
= DEFAULT_BUFSIZE
;
99 module_param(buf_sz
, int, S_IRUGO
| S_IWUSR
);
100 MODULE_PARM_DESC(buf_sz
, "DMA buffer size");
102 static const u32 default_msg_level
= (NETIF_MSG_DRV
| NETIF_MSG_PROBE
|
103 NETIF_MSG_LINK
| NETIF_MSG_IFUP
|
104 NETIF_MSG_IFDOWN
| NETIF_MSG_TIMER
);
106 #define STMMAC_DEFAULT_LPI_TIMER 1000
107 static int eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
108 module_param(eee_timer
, int, S_IRUGO
| S_IWUSR
);
109 MODULE_PARM_DESC(eee_timer
, "LPI tx expiration time in msec");
110 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
112 /* By default the driver will use the ring mode to manage tx and rx descriptors
113 * but passing this value so user can force to use the chain instead of the ring
115 static unsigned int chain_mode
;
116 module_param(chain_mode
, int, S_IRUGO
);
117 MODULE_PARM_DESC(chain_mode
, "To use chain instead of ring mode");
119 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
);
121 #ifdef CONFIG_DEBUG_FS
122 static int stmmac_init_fs(struct net_device
*dev
);
123 static void stmmac_exit_fs(struct net_device
*dev
);
126 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
129 * stmmac_verify_args - verify the driver parameters.
130 * Description: it checks the driver parameters and set a default in case of
133 static void stmmac_verify_args(void)
135 if (unlikely(watchdog
< 0))
137 if (unlikely(dma_rxsize
< 0))
138 dma_rxsize
= DMA_RX_SIZE
;
139 if (unlikely(dma_txsize
< 0))
140 dma_txsize
= DMA_TX_SIZE
;
141 if (unlikely((buf_sz
< DEFAULT_BUFSIZE
) || (buf_sz
> BUF_SIZE_16KiB
)))
142 buf_sz
= DEFAULT_BUFSIZE
;
143 if (unlikely(flow_ctrl
> 1))
144 flow_ctrl
= FLOW_AUTO
;
145 else if (likely(flow_ctrl
< 0))
146 flow_ctrl
= FLOW_OFF
;
147 if (unlikely((pause
< 0) || (pause
> 0xffff)))
150 eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
154 * stmmac_clk_csr_set - dynamically set the MDC clock
155 * @priv: driver private structure
156 * Description: this is to dynamically set the MDC clock according to the csr
159 * If a specific clk_csr value is passed from the platform
160 * this means that the CSR Clock Range selection cannot be
161 * changed at run-time and it is fixed (as reported in the driver
162 * documentation). Viceversa the driver will try to set the MDC
163 * clock dynamically according to the actual clock input.
165 static void stmmac_clk_csr_set(struct stmmac_priv
*priv
)
169 clk_rate
= clk_get_rate(priv
->stmmac_clk
);
171 /* Platform provided default clk_csr would be assumed valid
172 * for all other cases except for the below mentioned ones.
173 * For values higher than the IEEE 802.3 specified frequency
174 * we can not estimate the proper divider as it is not known
175 * the frequency of clk_csr_i. So we do not change the default
178 if (!(priv
->clk_csr
& MAC_CSR_H_FRQ_MASK
)) {
179 if (clk_rate
< CSR_F_35M
)
180 priv
->clk_csr
= STMMAC_CSR_20_35M
;
181 else if ((clk_rate
>= CSR_F_35M
) && (clk_rate
< CSR_F_60M
))
182 priv
->clk_csr
= STMMAC_CSR_35_60M
;
183 else if ((clk_rate
>= CSR_F_60M
) && (clk_rate
< CSR_F_100M
))
184 priv
->clk_csr
= STMMAC_CSR_60_100M
;
185 else if ((clk_rate
>= CSR_F_100M
) && (clk_rate
< CSR_F_150M
))
186 priv
->clk_csr
= STMMAC_CSR_100_150M
;
187 else if ((clk_rate
>= CSR_F_150M
) && (clk_rate
< CSR_F_250M
))
188 priv
->clk_csr
= STMMAC_CSR_150_250M
;
189 else if ((clk_rate
>= CSR_F_250M
) && (clk_rate
< CSR_F_300M
))
190 priv
->clk_csr
= STMMAC_CSR_250_300M
;
194 static void print_pkt(unsigned char *buf
, int len
)
196 pr_debug("len = %d byte, buf addr: 0x%p\n", len
, buf
);
197 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
, buf
, len
);
200 /* minimum number of free TX descriptors required to wake up TX process */
201 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
203 static inline u32
stmmac_tx_avail(struct stmmac_priv
*priv
)
205 return priv
->dirty_tx
+ priv
->dma_tx_size
- priv
->cur_tx
- 1;
209 * stmmac_hw_fix_mac_speed - callback for speed selection
210 * @priv: driver private structure
211 * Description: on some platforms (e.g. ST), some HW system configuraton
212 * registers have to be set according to the link speed negotiated.
214 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv
*priv
)
216 struct phy_device
*phydev
= priv
->phydev
;
218 if (likely(priv
->plat
->fix_mac_speed
))
219 priv
->plat
->fix_mac_speed(priv
->plat
->bsp_priv
, phydev
->speed
);
223 * stmmac_enable_eee_mode - check and enter in LPI mode
224 * @priv: driver private structure
225 * Description: this function is to verify and enter in LPI mode in case of
228 static void stmmac_enable_eee_mode(struct stmmac_priv
*priv
)
230 /* Check and enter in LPI mode */
231 if ((priv
->dirty_tx
== priv
->cur_tx
) &&
232 (priv
->tx_path_in_lpi_mode
== false))
233 priv
->hw
->mac
->set_eee_mode(priv
->hw
);
237 * stmmac_disable_eee_mode - disable and exit from LPI mode
238 * @priv: driver private structure
239 * Description: this function is to exit and disable EEE in case of
240 * LPI state is true. This is called by the xmit.
242 void stmmac_disable_eee_mode(struct stmmac_priv
*priv
)
244 priv
->hw
->mac
->reset_eee_mode(priv
->hw
);
245 del_timer_sync(&priv
->eee_ctrl_timer
);
246 priv
->tx_path_in_lpi_mode
= false;
250 * stmmac_eee_ctrl_timer - EEE TX SW timer.
253 * if there is no data transfer and if we are not in LPI state,
254 * then MAC Transmitter can be moved to LPI state.
256 static void stmmac_eee_ctrl_timer(unsigned long arg
)
258 struct stmmac_priv
*priv
= (struct stmmac_priv
*)arg
;
260 stmmac_enable_eee_mode(priv
);
261 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
265 * stmmac_eee_init - init EEE
266 * @priv: driver private structure
268 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
269 * can also manage EEE, this function enable the LPI state and start related
272 bool stmmac_eee_init(struct stmmac_priv
*priv
)
274 char *phy_bus_name
= priv
->plat
->phy_bus_name
;
278 /* Using PCS we cannot dial with the phy registers at this stage
279 * so we do not support extra feature like EEE.
281 if ((priv
->pcs
== STMMAC_PCS_RGMII
) || (priv
->pcs
== STMMAC_PCS_TBI
) ||
282 (priv
->pcs
== STMMAC_PCS_RTBI
))
285 /* Never init EEE in case of a switch is attached */
286 if (phy_bus_name
&& (!strcmp(phy_bus_name
, "fixed")))
289 /* MAC core supports the EEE feature. */
290 if (priv
->dma_cap
.eee
) {
291 int tx_lpi_timer
= priv
->tx_lpi_timer
;
293 /* Check if the PHY supports EEE */
294 if (phy_init_eee(priv
->phydev
, 1)) {
295 /* To manage at run-time if the EEE cannot be supported
296 * anymore (for example because the lp caps have been
298 * In that case the driver disable own timers.
300 spin_lock_irqsave(&priv
->lock
, flags
);
301 if (priv
->eee_active
) {
302 pr_debug("stmmac: disable EEE\n");
303 del_timer_sync(&priv
->eee_ctrl_timer
);
304 priv
->hw
->mac
->set_eee_timer(priv
->hw
, 0,
307 priv
->eee_active
= 0;
308 spin_unlock_irqrestore(&priv
->lock
, flags
);
311 /* Activate the EEE and start timers */
312 spin_lock_irqsave(&priv
->lock
, flags
);
313 if (!priv
->eee_active
) {
314 priv
->eee_active
= 1;
315 setup_timer(&priv
->eee_ctrl_timer
,
316 stmmac_eee_ctrl_timer
,
317 (unsigned long)priv
);
318 mod_timer(&priv
->eee_ctrl_timer
,
319 STMMAC_LPI_T(eee_timer
));
321 priv
->hw
->mac
->set_eee_timer(priv
->hw
,
322 STMMAC_DEFAULT_LIT_LS
,
325 /* Set HW EEE according to the speed */
326 priv
->hw
->mac
->set_eee_pls(priv
->hw
, priv
->phydev
->link
);
329 spin_unlock_irqrestore(&priv
->lock
, flags
);
331 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
337 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
338 * @priv: driver private structure
339 * @entry : descriptor index to be used.
340 * @skb : the socket buffer
342 * This function will read timestamp from the descriptor & pass it to stack.
343 * and also perform some sanity checks.
345 static void stmmac_get_tx_hwtstamp(struct stmmac_priv
*priv
,
346 unsigned int entry
, struct sk_buff
*skb
)
348 struct skb_shared_hwtstamps shhwtstamp
;
352 if (!priv
->hwts_tx_en
)
355 /* exit if skb doesn't support hw tstamp */
356 if (likely(!skb
|| !(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)))
360 desc
= (priv
->dma_etx
+ entry
);
362 desc
= (priv
->dma_tx
+ entry
);
364 /* check tx tstamp status */
365 if (!priv
->hw
->desc
->get_tx_timestamp_status((struct dma_desc
*)desc
))
368 /* get the valid tstamp */
369 ns
= priv
->hw
->desc
->get_timestamp(desc
, priv
->adv_ts
);
371 memset(&shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
372 shhwtstamp
.hwtstamp
= ns_to_ktime(ns
);
373 /* pass tstamp to stack */
374 skb_tstamp_tx(skb
, &shhwtstamp
);
379 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
380 * @priv: driver private structure
381 * @entry : descriptor index to be used.
382 * @skb : the socket buffer
384 * This function will read received packet's timestamp from the descriptor
385 * and pass it to stack. It also perform some sanity checks.
387 static void stmmac_get_rx_hwtstamp(struct stmmac_priv
*priv
,
388 unsigned int entry
, struct sk_buff
*skb
)
390 struct skb_shared_hwtstamps
*shhwtstamp
= NULL
;
394 if (!priv
->hwts_rx_en
)
398 desc
= (priv
->dma_erx
+ entry
);
400 desc
= (priv
->dma_rx
+ entry
);
402 /* exit if rx tstamp is not valid */
403 if (!priv
->hw
->desc
->get_rx_timestamp_status(desc
, priv
->adv_ts
))
406 /* get valid tstamp */
407 ns
= priv
->hw
->desc
->get_timestamp(desc
, priv
->adv_ts
);
408 shhwtstamp
= skb_hwtstamps(skb
);
409 memset(shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
410 shhwtstamp
->hwtstamp
= ns_to_ktime(ns
);
414 * stmmac_hwtstamp_ioctl - control hardware timestamping.
415 * @dev: device pointer.
416 * @ifr: An IOCTL specefic structure, that can contain a pointer to
417 * a proprietary structure used to pass information to the driver.
419 * This function configures the MAC to enable/disable both outgoing(TX)
420 * and incoming(RX) packets time stamping based on user input.
422 * 0 on success and an appropriate -ve integer on failure.
424 static int stmmac_hwtstamp_ioctl(struct net_device
*dev
, struct ifreq
*ifr
)
426 struct stmmac_priv
*priv
= netdev_priv(dev
);
427 struct hwtstamp_config config
;
428 struct timespec64 now
;
432 u32 ptp_over_ipv4_udp
= 0;
433 u32 ptp_over_ipv6_udp
= 0;
434 u32 ptp_over_ethernet
= 0;
435 u32 snap_type_sel
= 0;
436 u32 ts_master_en
= 0;
441 if (!(priv
->dma_cap
.time_stamp
|| priv
->adv_ts
)) {
442 netdev_alert(priv
->dev
, "No support for HW time stamping\n");
443 priv
->hwts_tx_en
= 0;
444 priv
->hwts_rx_en
= 0;
449 if (copy_from_user(&config
, ifr
->ifr_data
,
450 sizeof(struct hwtstamp_config
)))
453 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
454 __func__
, config
.flags
, config
.tx_type
, config
.rx_filter
);
456 /* reserved for future extensions */
460 if (config
.tx_type
!= HWTSTAMP_TX_OFF
&&
461 config
.tx_type
!= HWTSTAMP_TX_ON
)
465 switch (config
.rx_filter
) {
466 case HWTSTAMP_FILTER_NONE
:
467 /* time stamp no incoming packet at all */
468 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
471 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
472 /* PTP v1, UDP, any kind of event packet */
473 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
474 /* take time stamp for all event messages */
475 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
477 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
478 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
481 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
482 /* PTP v1, UDP, Sync packet */
483 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_SYNC
;
484 /* take time stamp for SYNC messages only */
485 ts_event_en
= PTP_TCR_TSEVNTENA
;
487 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
488 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
491 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
492 /* PTP v1, UDP, Delay_req packet */
493 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
;
494 /* take time stamp for Delay_Req messages only */
495 ts_master_en
= PTP_TCR_TSMSTRENA
;
496 ts_event_en
= PTP_TCR_TSEVNTENA
;
498 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
499 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
502 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
503 /* PTP v2, UDP, any kind of event packet */
504 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_EVENT
;
505 ptp_v2
= PTP_TCR_TSVER2ENA
;
506 /* take time stamp for all event messages */
507 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
509 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
510 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
513 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
514 /* PTP v2, UDP, Sync packet */
515 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_SYNC
;
516 ptp_v2
= PTP_TCR_TSVER2ENA
;
517 /* take time stamp for SYNC messages only */
518 ts_event_en
= PTP_TCR_TSEVNTENA
;
520 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
521 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
524 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
525 /* PTP v2, UDP, Delay_req packet */
526 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
;
527 ptp_v2
= PTP_TCR_TSVER2ENA
;
528 /* take time stamp for Delay_Req messages only */
529 ts_master_en
= PTP_TCR_TSMSTRENA
;
530 ts_event_en
= PTP_TCR_TSEVNTENA
;
532 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
533 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
536 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
537 /* PTP v2/802.AS1 any layer, any kind of event packet */
538 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
539 ptp_v2
= PTP_TCR_TSVER2ENA
;
540 /* take time stamp for all event messages */
541 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
543 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
544 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
545 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
548 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
549 /* PTP v2/802.AS1, any layer, Sync packet */
550 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_SYNC
;
551 ptp_v2
= PTP_TCR_TSVER2ENA
;
552 /* take time stamp for SYNC messages only */
553 ts_event_en
= PTP_TCR_TSEVNTENA
;
555 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
556 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
557 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
560 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
561 /* PTP v2/802.AS1, any layer, Delay_req packet */
562 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
;
563 ptp_v2
= PTP_TCR_TSVER2ENA
;
564 /* take time stamp for Delay_Req messages only */
565 ts_master_en
= PTP_TCR_TSMSTRENA
;
566 ts_event_en
= PTP_TCR_TSEVNTENA
;
568 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
569 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
570 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
573 case HWTSTAMP_FILTER_ALL
:
574 /* time stamp any incoming packet */
575 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
576 tstamp_all
= PTP_TCR_TSENALL
;
583 switch (config
.rx_filter
) {
584 case HWTSTAMP_FILTER_NONE
:
585 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
588 /* PTP v1, UDP, any kind of event packet */
589 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
593 priv
->hwts_rx_en
= ((config
.rx_filter
== HWTSTAMP_FILTER_NONE
) ? 0 : 1);
594 priv
->hwts_tx_en
= config
.tx_type
== HWTSTAMP_TX_ON
;
596 if (!priv
->hwts_tx_en
&& !priv
->hwts_rx_en
)
597 priv
->hw
->ptp
->config_hw_tstamping(priv
->ioaddr
, 0);
599 value
= (PTP_TCR_TSENA
| PTP_TCR_TSCFUPDT
| PTP_TCR_TSCTRLSSR
|
600 tstamp_all
| ptp_v2
| ptp_over_ethernet
|
601 ptp_over_ipv6_udp
| ptp_over_ipv4_udp
| ts_event_en
|
602 ts_master_en
| snap_type_sel
);
603 priv
->hw
->ptp
->config_hw_tstamping(priv
->ioaddr
, value
);
605 /* program Sub Second Increment reg */
606 sec_inc
= priv
->hw
->ptp
->config_sub_second_increment(
607 priv
->ioaddr
, priv
->clk_ptp_rate
);
608 temp
= div_u64(1000000000ULL, sec_inc
);
610 /* calculate default added value:
612 * addend = (2^32)/freq_div_ratio;
613 * where, freq_div_ratio = 1e9ns/sec_inc
615 temp
= (u64
)(temp
<< 32);
616 priv
->default_addend
= div_u64(temp
, priv
->clk_ptp_rate
);
617 priv
->hw
->ptp
->config_addend(priv
->ioaddr
,
618 priv
->default_addend
);
620 /* initialize system time */
621 ktime_get_real_ts64(&now
);
623 /* lower 32 bits of tv_sec are safe until y2106 */
624 priv
->hw
->ptp
->init_systime(priv
->ioaddr
, (u32
)now
.tv_sec
,
628 return copy_to_user(ifr
->ifr_data
, &config
,
629 sizeof(struct hwtstamp_config
)) ? -EFAULT
: 0;
633 * stmmac_init_ptp - init PTP
634 * @priv: driver private structure
635 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
636 * This is done by looking at the HW cap. register.
637 * This function also registers the ptp driver.
639 static int stmmac_init_ptp(struct stmmac_priv
*priv
)
641 if (!(priv
->dma_cap
.time_stamp
|| priv
->dma_cap
.atime_stamp
))
644 /* Fall-back to main clock in case of no PTP ref is passed */
645 priv
->clk_ptp_ref
= devm_clk_get(priv
->device
, "clk_ptp_ref");
646 if (IS_ERR(priv
->clk_ptp_ref
)) {
647 priv
->clk_ptp_rate
= clk_get_rate(priv
->stmmac_clk
);
648 priv
->clk_ptp_ref
= NULL
;
650 clk_prepare_enable(priv
->clk_ptp_ref
);
651 priv
->clk_ptp_rate
= clk_get_rate(priv
->clk_ptp_ref
);
655 if (priv
->dma_cap
.atime_stamp
&& priv
->extend_desc
)
658 if (netif_msg_hw(priv
) && priv
->dma_cap
.time_stamp
)
659 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
661 if (netif_msg_hw(priv
) && priv
->adv_ts
)
662 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
664 priv
->hw
->ptp
= &stmmac_ptp
;
665 priv
->hwts_tx_en
= 0;
666 priv
->hwts_rx_en
= 0;
668 return stmmac_ptp_register(priv
);
671 static void stmmac_release_ptp(struct stmmac_priv
*priv
)
673 if (priv
->clk_ptp_ref
)
674 clk_disable_unprepare(priv
->clk_ptp_ref
);
675 stmmac_ptp_unregister(priv
);
679 * stmmac_adjust_link - adjusts the link parameters
680 * @dev: net device structure
681 * Description: this is the helper called by the physical abstraction layer
682 * drivers to communicate the phy link status. According the speed and duplex
683 * this driver can invoke registered glue-logic as well.
684 * It also invoke the eee initialization because it could happen when switch
685 * on different networks (that are eee capable).
687 static void stmmac_adjust_link(struct net_device
*dev
)
689 struct stmmac_priv
*priv
= netdev_priv(dev
);
690 struct phy_device
*phydev
= priv
->phydev
;
693 unsigned int fc
= priv
->flow_ctrl
, pause_time
= priv
->pause
;
698 spin_lock_irqsave(&priv
->lock
, flags
);
701 u32 ctrl
= readl(priv
->ioaddr
+ MAC_CTRL_REG
);
703 /* Now we make sure that we can be in full duplex mode.
704 * If not, we operate in half-duplex mode. */
705 if (phydev
->duplex
!= priv
->oldduplex
) {
707 if (!(phydev
->duplex
))
708 ctrl
&= ~priv
->hw
->link
.duplex
;
710 ctrl
|= priv
->hw
->link
.duplex
;
711 priv
->oldduplex
= phydev
->duplex
;
713 /* Flow Control operation */
715 priv
->hw
->mac
->flow_ctrl(priv
->hw
, phydev
->duplex
,
718 if (phydev
->speed
!= priv
->speed
) {
720 switch (phydev
->speed
) {
722 if (likely(priv
->plat
->has_gmac
))
723 ctrl
&= ~priv
->hw
->link
.port
;
724 stmmac_hw_fix_mac_speed(priv
);
728 if (priv
->plat
->has_gmac
) {
729 ctrl
|= priv
->hw
->link
.port
;
730 if (phydev
->speed
== SPEED_100
) {
731 ctrl
|= priv
->hw
->link
.speed
;
733 ctrl
&= ~(priv
->hw
->link
.speed
);
736 ctrl
&= ~priv
->hw
->link
.port
;
738 stmmac_hw_fix_mac_speed(priv
);
741 if (netif_msg_link(priv
))
742 pr_warn("%s: Speed (%d) not 10/100\n",
743 dev
->name
, phydev
->speed
);
747 priv
->speed
= phydev
->speed
;
750 writel(ctrl
, priv
->ioaddr
+ MAC_CTRL_REG
);
752 if (!priv
->oldlink
) {
756 } else if (priv
->oldlink
) {
760 priv
->oldduplex
= -1;
763 if (new_state
&& netif_msg_link(priv
))
764 phy_print_status(phydev
);
766 spin_unlock_irqrestore(&priv
->lock
, flags
);
768 /* At this stage, it could be needed to setup the EEE or adjust some
769 * MAC related HW registers.
771 priv
->eee_enabled
= stmmac_eee_init(priv
);
775 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
776 * @priv: driver private structure
777 * Description: this is to verify if the HW supports the PCS.
778 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
779 * configured for the TBI, RTBI, or SGMII PHY interface.
781 static void stmmac_check_pcs_mode(struct stmmac_priv
*priv
)
783 int interface
= priv
->plat
->interface
;
785 if (priv
->dma_cap
.pcs
) {
786 if ((interface
== PHY_INTERFACE_MODE_RGMII
) ||
787 (interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
788 (interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
789 (interface
== PHY_INTERFACE_MODE_RGMII_TXID
)) {
790 pr_debug("STMMAC: PCS RGMII support enable\n");
791 priv
->pcs
= STMMAC_PCS_RGMII
;
792 } else if (interface
== PHY_INTERFACE_MODE_SGMII
) {
793 pr_debug("STMMAC: PCS SGMII support enable\n");
794 priv
->pcs
= STMMAC_PCS_SGMII
;
800 * stmmac_init_phy - PHY initialization
801 * @dev: net device structure
802 * Description: it initializes the driver's PHY state, and attaches the PHY
807 static int stmmac_init_phy(struct net_device
*dev
)
809 struct stmmac_priv
*priv
= netdev_priv(dev
);
810 struct phy_device
*phydev
;
811 char phy_id_fmt
[MII_BUS_ID_SIZE
+ 3];
812 char bus_id
[MII_BUS_ID_SIZE
];
813 int interface
= priv
->plat
->interface
;
814 int max_speed
= priv
->plat
->max_speed
;
817 priv
->oldduplex
= -1;
819 if (priv
->plat
->phy_node
) {
820 phydev
= of_phy_connect(dev
, priv
->plat
->phy_node
,
821 &stmmac_adjust_link
, 0, interface
);
823 if (priv
->plat
->phy_bus_name
)
824 snprintf(bus_id
, MII_BUS_ID_SIZE
, "%s-%x",
825 priv
->plat
->phy_bus_name
, priv
->plat
->bus_id
);
827 snprintf(bus_id
, MII_BUS_ID_SIZE
, "stmmac-%x",
830 snprintf(phy_id_fmt
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, bus_id
,
831 priv
->plat
->phy_addr
);
832 pr_debug("stmmac_init_phy: trying to attach to %s\n",
835 phydev
= phy_connect(dev
, phy_id_fmt
, &stmmac_adjust_link
,
839 if (IS_ERR_OR_NULL(phydev
)) {
840 pr_err("%s: Could not attach to PHY\n", dev
->name
);
844 return PTR_ERR(phydev
);
847 /* Stop Advertising 1000BASE Capability if interface is not GMII */
848 if ((interface
== PHY_INTERFACE_MODE_MII
) ||
849 (interface
== PHY_INTERFACE_MODE_RMII
) ||
850 (max_speed
< 1000 && max_speed
> 0))
851 phydev
->advertising
&= ~(SUPPORTED_1000baseT_Half
|
852 SUPPORTED_1000baseT_Full
);
855 * Broken HW is sometimes missing the pull-up resistor on the
856 * MDIO line, which results in reads to non-existent devices returning
857 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
859 * Note: phydev->phy_id is the result of reading the UID PHY registers.
861 if (!priv
->plat
->phy_node
&& phydev
->phy_id
== 0) {
862 phy_disconnect(phydev
);
865 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
866 " Link = %d\n", dev
->name
, phydev
->phy_id
, phydev
->link
);
868 priv
->phydev
= phydev
;
874 * stmmac_display_ring - display ring
875 * @head: pointer to the head of the ring passed.
876 * @size: size of the ring.
877 * @extend_desc: to verify if extended descriptors are used.
878 * Description: display the control/status and buffer descriptors.
880 static void stmmac_display_ring(void *head
, int size
, int extend_desc
)
883 struct dma_extended_desc
*ep
= (struct dma_extended_desc
*)head
;
884 struct dma_desc
*p
= (struct dma_desc
*)head
;
886 for (i
= 0; i
< size
; i
++) {
890 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
891 i
, (unsigned int)virt_to_phys(ep
),
892 (unsigned int)x
, (unsigned int)(x
>> 32),
893 ep
->basic
.des2
, ep
->basic
.des3
);
897 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
898 i
, (unsigned int)virt_to_phys(p
),
899 (unsigned int)x
, (unsigned int)(x
>> 32),
907 static void stmmac_display_rings(struct stmmac_priv
*priv
)
909 unsigned int txsize
= priv
->dma_tx_size
;
910 unsigned int rxsize
= priv
->dma_rx_size
;
912 if (priv
->extend_desc
) {
913 pr_info("Extended RX descriptor ring:\n");
914 stmmac_display_ring((void *)priv
->dma_erx
, rxsize
, 1);
915 pr_info("Extended TX descriptor ring:\n");
916 stmmac_display_ring((void *)priv
->dma_etx
, txsize
, 1);
918 pr_info("RX descriptor ring:\n");
919 stmmac_display_ring((void *)priv
->dma_rx
, rxsize
, 0);
920 pr_info("TX descriptor ring:\n");
921 stmmac_display_ring((void *)priv
->dma_tx
, txsize
, 0);
925 static int stmmac_set_bfsize(int mtu
, int bufsize
)
929 if (mtu
>= BUF_SIZE_4KiB
)
931 else if (mtu
>= BUF_SIZE_2KiB
)
933 else if (mtu
> DEFAULT_BUFSIZE
)
936 ret
= DEFAULT_BUFSIZE
;
942 * stmmac_clear_descriptors - clear descriptors
943 * @priv: driver private structure
944 * Description: this function is called to clear the tx and rx descriptors
945 * in case of both basic and extended descriptors are used.
947 static void stmmac_clear_descriptors(struct stmmac_priv
*priv
)
950 unsigned int txsize
= priv
->dma_tx_size
;
951 unsigned int rxsize
= priv
->dma_rx_size
;
953 /* Clear the Rx/Tx descriptors */
954 for (i
= 0; i
< rxsize
; i
++)
955 if (priv
->extend_desc
)
956 priv
->hw
->desc
->init_rx_desc(&priv
->dma_erx
[i
].basic
,
957 priv
->use_riwt
, priv
->mode
,
960 priv
->hw
->desc
->init_rx_desc(&priv
->dma_rx
[i
],
961 priv
->use_riwt
, priv
->mode
,
963 for (i
= 0; i
< txsize
; i
++)
964 if (priv
->extend_desc
)
965 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
969 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
975 * stmmac_init_rx_buffers - init the RX descriptor buffer.
976 * @priv: driver private structure
977 * @p: descriptor pointer
978 * @i: descriptor index
980 * Description: this function is called to allocate a receive buffer, perform
981 * the DMA mapping and init the descriptor.
983 static int stmmac_init_rx_buffers(struct stmmac_priv
*priv
, struct dma_desc
*p
,
988 skb
= __netdev_alloc_skb_ip_align(priv
->dev
, priv
->dma_buf_sz
, flags
);
990 pr_err("%s: Rx init fails; skb is NULL\n", __func__
);
993 priv
->rx_skbuff
[i
] = skb
;
994 priv
->rx_skbuff_dma
[i
] = dma_map_single(priv
->device
, skb
->data
,
997 if (dma_mapping_error(priv
->device
, priv
->rx_skbuff_dma
[i
])) {
998 pr_err("%s: DMA mapping error\n", __func__
);
999 dev_kfree_skb_any(skb
);
1003 p
->des2
= priv
->rx_skbuff_dma
[i
];
1005 if ((priv
->hw
->mode
->init_desc3
) &&
1006 (priv
->dma_buf_sz
== BUF_SIZE_16KiB
))
1007 priv
->hw
->mode
->init_desc3(p
);
1012 static void stmmac_free_rx_buffers(struct stmmac_priv
*priv
, int i
)
1014 if (priv
->rx_skbuff
[i
]) {
1015 dma_unmap_single(priv
->device
, priv
->rx_skbuff_dma
[i
],
1016 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
1017 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
1019 priv
->rx_skbuff
[i
] = NULL
;
1023 * init_dma_desc_rings - init the RX/TX descriptor rings
1024 * @dev: net device structure
1026 * Description: this function initializes the DMA RX/TX descriptors
1027 * and allocates the socket buffers. It suppors the chained and ring
1030 static int init_dma_desc_rings(struct net_device
*dev
, gfp_t flags
)
1033 struct stmmac_priv
*priv
= netdev_priv(dev
);
1034 unsigned int txsize
= priv
->dma_tx_size
;
1035 unsigned int rxsize
= priv
->dma_rx_size
;
1036 unsigned int bfsize
= 0;
1039 if (priv
->hw
->mode
->set_16kib_bfsize
)
1040 bfsize
= priv
->hw
->mode
->set_16kib_bfsize(dev
->mtu
);
1042 if (bfsize
< BUF_SIZE_16KiB
)
1043 bfsize
= stmmac_set_bfsize(dev
->mtu
, priv
->dma_buf_sz
);
1045 priv
->dma_buf_sz
= bfsize
;
1047 if (netif_msg_probe(priv
))
1048 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__
,
1049 txsize
, rxsize
, bfsize
);
1051 if (netif_msg_probe(priv
)) {
1052 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__
,
1053 (u32
) priv
->dma_rx_phy
, (u32
) priv
->dma_tx_phy
);
1055 /* RX INITIALIZATION */
1056 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1058 for (i
= 0; i
< rxsize
; i
++) {
1060 if (priv
->extend_desc
)
1061 p
= &((priv
->dma_erx
+ i
)->basic
);
1063 p
= priv
->dma_rx
+ i
;
1065 ret
= stmmac_init_rx_buffers(priv
, p
, i
, flags
);
1067 goto err_init_rx_buffers
;
1069 if (netif_msg_probe(priv
))
1070 pr_debug("[%p]\t[%p]\t[%x]\n", priv
->rx_skbuff
[i
],
1071 priv
->rx_skbuff
[i
]->data
,
1072 (unsigned int)priv
->rx_skbuff_dma
[i
]);
1075 priv
->dirty_rx
= (unsigned int)(i
- rxsize
);
1078 /* Setup the chained descriptor addresses */
1079 if (priv
->mode
== STMMAC_CHAIN_MODE
) {
1080 if (priv
->extend_desc
) {
1081 priv
->hw
->mode
->init(priv
->dma_erx
, priv
->dma_rx_phy
,
1083 priv
->hw
->mode
->init(priv
->dma_etx
, priv
->dma_tx_phy
,
1086 priv
->hw
->mode
->init(priv
->dma_rx
, priv
->dma_rx_phy
,
1088 priv
->hw
->mode
->init(priv
->dma_tx
, priv
->dma_tx_phy
,
1093 /* TX INITIALIZATION */
1094 for (i
= 0; i
< txsize
; i
++) {
1096 if (priv
->extend_desc
)
1097 p
= &((priv
->dma_etx
+ i
)->basic
);
1099 p
= priv
->dma_tx
+ i
;
1101 priv
->tx_skbuff_dma
[i
].buf
= 0;
1102 priv
->tx_skbuff_dma
[i
].map_as_page
= false;
1103 priv
->tx_skbuff
[i
] = NULL
;
1108 netdev_reset_queue(priv
->dev
);
1110 stmmac_clear_descriptors(priv
);
1112 if (netif_msg_hw(priv
))
1113 stmmac_display_rings(priv
);
1116 err_init_rx_buffers
:
1118 stmmac_free_rx_buffers(priv
, i
);
1122 static void dma_free_rx_skbufs(struct stmmac_priv
*priv
)
1126 for (i
= 0; i
< priv
->dma_rx_size
; i
++)
1127 stmmac_free_rx_buffers(priv
, i
);
1130 static void dma_free_tx_skbufs(struct stmmac_priv
*priv
)
1134 for (i
= 0; i
< priv
->dma_tx_size
; i
++) {
1137 if (priv
->extend_desc
)
1138 p
= &((priv
->dma_etx
+ i
)->basic
);
1140 p
= priv
->dma_tx
+ i
;
1142 if (priv
->tx_skbuff_dma
[i
].buf
) {
1143 if (priv
->tx_skbuff_dma
[i
].map_as_page
)
1144 dma_unmap_page(priv
->device
,
1145 priv
->tx_skbuff_dma
[i
].buf
,
1146 priv
->hw
->desc
->get_tx_len(p
),
1149 dma_unmap_single(priv
->device
,
1150 priv
->tx_skbuff_dma
[i
].buf
,
1151 priv
->hw
->desc
->get_tx_len(p
),
1155 if (priv
->tx_skbuff
[i
] != NULL
) {
1156 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
1157 priv
->tx_skbuff
[i
] = NULL
;
1158 priv
->tx_skbuff_dma
[i
].buf
= 0;
1159 priv
->tx_skbuff_dma
[i
].map_as_page
= false;
1165 * alloc_dma_desc_resources - alloc TX/RX resources.
1166 * @priv: private structure
1167 * Description: according to which descriptor can be used (extend or basic)
1168 * this function allocates the resources for TX and RX paths. In case of
1169 * reception, for example, it pre-allocated the RX socket buffer in order to
1170 * allow zero-copy mechanism.
1172 static int alloc_dma_desc_resources(struct stmmac_priv
*priv
)
1174 unsigned int txsize
= priv
->dma_tx_size
;
1175 unsigned int rxsize
= priv
->dma_rx_size
;
1178 priv
->rx_skbuff_dma
= kmalloc_array(rxsize
, sizeof(dma_addr_t
),
1180 if (!priv
->rx_skbuff_dma
)
1183 priv
->rx_skbuff
= kmalloc_array(rxsize
, sizeof(struct sk_buff
*),
1185 if (!priv
->rx_skbuff
)
1188 priv
->tx_skbuff_dma
= kmalloc_array(txsize
,
1189 sizeof(*priv
->tx_skbuff_dma
),
1191 if (!priv
->tx_skbuff_dma
)
1192 goto err_tx_skbuff_dma
;
1194 priv
->tx_skbuff
= kmalloc_array(txsize
, sizeof(struct sk_buff
*),
1196 if (!priv
->tx_skbuff
)
1199 if (priv
->extend_desc
) {
1200 priv
->dma_erx
= dma_zalloc_coherent(priv
->device
, rxsize
*
1208 priv
->dma_etx
= dma_zalloc_coherent(priv
->device
, txsize
*
1213 if (!priv
->dma_etx
) {
1214 dma_free_coherent(priv
->device
, priv
->dma_rx_size
*
1215 sizeof(struct dma_extended_desc
),
1216 priv
->dma_erx
, priv
->dma_rx_phy
);
1220 priv
->dma_rx
= dma_zalloc_coherent(priv
->device
, rxsize
*
1221 sizeof(struct dma_desc
),
1227 priv
->dma_tx
= dma_zalloc_coherent(priv
->device
, txsize
*
1228 sizeof(struct dma_desc
),
1231 if (!priv
->dma_tx
) {
1232 dma_free_coherent(priv
->device
, priv
->dma_rx_size
*
1233 sizeof(struct dma_desc
),
1234 priv
->dma_rx
, priv
->dma_rx_phy
);
1242 kfree(priv
->tx_skbuff
);
1244 kfree(priv
->tx_skbuff_dma
);
1246 kfree(priv
->rx_skbuff
);
1248 kfree(priv
->rx_skbuff_dma
);
1252 static void free_dma_desc_resources(struct stmmac_priv
*priv
)
1254 /* Release the DMA TX/RX socket buffers */
1255 dma_free_rx_skbufs(priv
);
1256 dma_free_tx_skbufs(priv
);
1258 /* Free DMA regions of consistent memory previously allocated */
1259 if (!priv
->extend_desc
) {
1260 dma_free_coherent(priv
->device
,
1261 priv
->dma_tx_size
* sizeof(struct dma_desc
),
1262 priv
->dma_tx
, priv
->dma_tx_phy
);
1263 dma_free_coherent(priv
->device
,
1264 priv
->dma_rx_size
* sizeof(struct dma_desc
),
1265 priv
->dma_rx
, priv
->dma_rx_phy
);
1267 dma_free_coherent(priv
->device
, priv
->dma_tx_size
*
1268 sizeof(struct dma_extended_desc
),
1269 priv
->dma_etx
, priv
->dma_tx_phy
);
1270 dma_free_coherent(priv
->device
, priv
->dma_rx_size
*
1271 sizeof(struct dma_extended_desc
),
1272 priv
->dma_erx
, priv
->dma_rx_phy
);
1274 kfree(priv
->rx_skbuff_dma
);
1275 kfree(priv
->rx_skbuff
);
1276 kfree(priv
->tx_skbuff_dma
);
1277 kfree(priv
->tx_skbuff
);
1281 * stmmac_dma_operation_mode - HW DMA operation mode
1282 * @priv: driver private structure
1283 * Description: it is used for configuring the DMA operation mode register in
1284 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1286 static void stmmac_dma_operation_mode(struct stmmac_priv
*priv
)
1288 int rxfifosz
= priv
->plat
->rx_fifo_size
;
1290 if (priv
->plat
->force_thresh_dma_mode
)
1291 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, tc
, rxfifosz
);
1292 else if (priv
->plat
->force_sf_dma_mode
|| priv
->plat
->tx_coe
) {
1294 * In case of GMAC, SF mode can be enabled
1295 * to perform the TX COE in HW. This depends on:
1296 * 1) TX COE if actually supported
1297 * 2) There is no bugged Jumbo frame support
1298 * that needs to not insert csum in the TDES.
1300 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, SF_DMA_MODE
, SF_DMA_MODE
,
1302 priv
->xstats
.threshold
= SF_DMA_MODE
;
1304 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, SF_DMA_MODE
,
1309 * stmmac_tx_clean - to manage the transmission completion
1310 * @priv: driver private structure
1311 * Description: it reclaims the transmit resources after transmission completes.
1313 static void stmmac_tx_clean(struct stmmac_priv
*priv
)
1315 unsigned int txsize
= priv
->dma_tx_size
;
1316 unsigned int bytes_compl
= 0, pkts_compl
= 0;
1318 spin_lock(&priv
->tx_lock
);
1320 priv
->xstats
.tx_clean
++;
1322 while (priv
->dirty_tx
!= priv
->cur_tx
) {
1324 unsigned int entry
= priv
->dirty_tx
% txsize
;
1325 struct sk_buff
*skb
= priv
->tx_skbuff
[entry
];
1328 if (priv
->extend_desc
)
1329 p
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1331 p
= priv
->dma_tx
+ entry
;
1333 /* Check if the descriptor is owned by the DMA. */
1334 if (priv
->hw
->desc
->get_tx_owner(p
))
1337 /* Verify tx error by looking at the last segment. */
1338 last
= priv
->hw
->desc
->get_tx_ls(p
);
1341 priv
->hw
->desc
->tx_status(&priv
->dev
->stats
,
1344 if (likely(tx_error
== 0)) {
1345 priv
->dev
->stats
.tx_packets
++;
1346 priv
->xstats
.tx_pkt_n
++;
1348 priv
->dev
->stats
.tx_errors
++;
1350 stmmac_get_tx_hwtstamp(priv
, entry
, skb
);
1352 if (netif_msg_tx_done(priv
))
1353 pr_debug("%s: curr %d, dirty %d\n", __func__
,
1354 priv
->cur_tx
, priv
->dirty_tx
);
1356 if (likely(priv
->tx_skbuff_dma
[entry
].buf
)) {
1357 if (priv
->tx_skbuff_dma
[entry
].map_as_page
)
1358 dma_unmap_page(priv
->device
,
1359 priv
->tx_skbuff_dma
[entry
].buf
,
1360 priv
->hw
->desc
->get_tx_len(p
),
1363 dma_unmap_single(priv
->device
,
1364 priv
->tx_skbuff_dma
[entry
].buf
,
1365 priv
->hw
->desc
->get_tx_len(p
),
1367 priv
->tx_skbuff_dma
[entry
].buf
= 0;
1368 priv
->tx_skbuff_dma
[entry
].map_as_page
= false;
1370 priv
->hw
->mode
->clean_desc3(priv
, p
);
1372 if (likely(skb
!= NULL
)) {
1374 bytes_compl
+= skb
->len
;
1375 dev_consume_skb_any(skb
);
1376 priv
->tx_skbuff
[entry
] = NULL
;
1379 priv
->hw
->desc
->release_tx_desc(p
, priv
->mode
);
1384 netdev_completed_queue(priv
->dev
, pkts_compl
, bytes_compl
);
1386 if (unlikely(netif_queue_stopped(priv
->dev
) &&
1387 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH(priv
))) {
1388 netif_tx_lock(priv
->dev
);
1389 if (netif_queue_stopped(priv
->dev
) &&
1390 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH(priv
)) {
1391 if (netif_msg_tx_done(priv
))
1392 pr_debug("%s: restart transmit\n", __func__
);
1393 netif_wake_queue(priv
->dev
);
1395 netif_tx_unlock(priv
->dev
);
1398 if ((priv
->eee_enabled
) && (!priv
->tx_path_in_lpi_mode
)) {
1399 stmmac_enable_eee_mode(priv
);
1400 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
1402 spin_unlock(&priv
->tx_lock
);
1405 static inline void stmmac_enable_dma_irq(struct stmmac_priv
*priv
)
1407 priv
->hw
->dma
->enable_dma_irq(priv
->ioaddr
);
1410 static inline void stmmac_disable_dma_irq(struct stmmac_priv
*priv
)
1412 priv
->hw
->dma
->disable_dma_irq(priv
->ioaddr
);
1416 * stmmac_tx_err - to manage the tx error
1417 * @priv: driver private structure
1418 * Description: it cleans the descriptors and restarts the transmission
1419 * in case of transmission errors.
1421 static void stmmac_tx_err(struct stmmac_priv
*priv
)
1424 int txsize
= priv
->dma_tx_size
;
1425 netif_stop_queue(priv
->dev
);
1427 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1428 dma_free_tx_skbufs(priv
);
1429 for (i
= 0; i
< txsize
; i
++)
1430 if (priv
->extend_desc
)
1431 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
1435 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
1440 netdev_reset_queue(priv
->dev
);
1441 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1443 priv
->dev
->stats
.tx_errors
++;
1444 netif_wake_queue(priv
->dev
);
1448 * stmmac_dma_interrupt - DMA ISR
1449 * @priv: driver private structure
1450 * Description: this is the DMA ISR. It is called by the main ISR.
1451 * It calls the dwmac dma routine and schedule poll method in case of some
1454 static void stmmac_dma_interrupt(struct stmmac_priv
*priv
)
1457 int rxfifosz
= priv
->plat
->rx_fifo_size
;
1459 status
= priv
->hw
->dma
->dma_interrupt(priv
->ioaddr
, &priv
->xstats
);
1460 if (likely((status
& handle_rx
)) || (status
& handle_tx
)) {
1461 if (likely(napi_schedule_prep(&priv
->napi
))) {
1462 stmmac_disable_dma_irq(priv
);
1463 __napi_schedule(&priv
->napi
);
1466 if (unlikely(status
& tx_hard_error_bump_tc
)) {
1467 /* Try to bump up the dma threshold on this failure */
1468 if (unlikely(priv
->xstats
.threshold
!= SF_DMA_MODE
) &&
1471 if (priv
->plat
->force_thresh_dma_mode
)
1472 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, tc
,
1475 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
,
1476 SF_DMA_MODE
, rxfifosz
);
1477 priv
->xstats
.threshold
= tc
;
1479 } else if (unlikely(status
== tx_hard_error
))
1480 stmmac_tx_err(priv
);
1484 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1485 * @priv: driver private structure
1486 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1488 static void stmmac_mmc_setup(struct stmmac_priv
*priv
)
1490 unsigned int mode
= MMC_CNTRL_RESET_ON_READ
| MMC_CNTRL_COUNTER_RESET
|
1491 MMC_CNTRL_PRESET
| MMC_CNTRL_FULL_HALF_PRESET
;
1493 dwmac_mmc_intr_all_mask(priv
->ioaddr
);
1495 if (priv
->dma_cap
.rmon
) {
1496 dwmac_mmc_ctrl(priv
->ioaddr
, mode
);
1497 memset(&priv
->mmc
, 0, sizeof(struct stmmac_counters
));
1499 pr_info(" No MAC Management Counters available\n");
1503 * stmmac_get_synopsys_id - return the SYINID.
1504 * @priv: driver private structure
1505 * Description: this simple function is to decode and return the SYINID
1506 * starting from the HW core register.
1508 static u32
stmmac_get_synopsys_id(struct stmmac_priv
*priv
)
1510 u32 hwid
= priv
->hw
->synopsys_uid
;
1512 /* Check Synopsys Id (not available on old chips) */
1514 u32 uid
= ((hwid
& 0x0000ff00) >> 8);
1515 u32 synid
= (hwid
& 0x000000ff);
1517 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1526 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1527 * @priv: driver private structure
1528 * Description: select the Enhanced/Alternate or Normal descriptors.
1529 * In case of Enhanced/Alternate, it checks if the extended descriptors are
1530 * supported by the HW capability register.
1532 static void stmmac_selec_desc_mode(struct stmmac_priv
*priv
)
1534 if (priv
->plat
->enh_desc
) {
1535 pr_info(" Enhanced/Alternate descriptors\n");
1537 /* GMAC older than 3.50 has no extended descriptors */
1538 if (priv
->synopsys_id
>= DWMAC_CORE_3_50
) {
1539 pr_info("\tEnabled extended descriptors\n");
1540 priv
->extend_desc
= 1;
1542 pr_warn("Extended descriptors not supported\n");
1544 priv
->hw
->desc
= &enh_desc_ops
;
1546 pr_info(" Normal descriptors\n");
1547 priv
->hw
->desc
= &ndesc_ops
;
1552 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1553 * @priv: driver private structure
1555 * new GMAC chip generations have a new register to indicate the
1556 * presence of the optional feature/functions.
1557 * This can be also used to override the value passed through the
1558 * platform and necessary for old MAC10/100 and GMAC chips.
1560 static int stmmac_get_hw_features(struct stmmac_priv
*priv
)
1564 if (priv
->hw
->dma
->get_hw_feature
) {
1565 hw_cap
= priv
->hw
->dma
->get_hw_feature(priv
->ioaddr
);
1567 priv
->dma_cap
.mbps_10_100
= (hw_cap
& DMA_HW_FEAT_MIISEL
);
1568 priv
->dma_cap
.mbps_1000
= (hw_cap
& DMA_HW_FEAT_GMIISEL
) >> 1;
1569 priv
->dma_cap
.half_duplex
= (hw_cap
& DMA_HW_FEAT_HDSEL
) >> 2;
1570 priv
->dma_cap
.hash_filter
= (hw_cap
& DMA_HW_FEAT_HASHSEL
) >> 4;
1571 priv
->dma_cap
.multi_addr
= (hw_cap
& DMA_HW_FEAT_ADDMAC
) >> 5;
1572 priv
->dma_cap
.pcs
= (hw_cap
& DMA_HW_FEAT_PCSSEL
) >> 6;
1573 priv
->dma_cap
.sma_mdio
= (hw_cap
& DMA_HW_FEAT_SMASEL
) >> 8;
1574 priv
->dma_cap
.pmt_remote_wake_up
=
1575 (hw_cap
& DMA_HW_FEAT_RWKSEL
) >> 9;
1576 priv
->dma_cap
.pmt_magic_frame
=
1577 (hw_cap
& DMA_HW_FEAT_MGKSEL
) >> 10;
1579 priv
->dma_cap
.rmon
= (hw_cap
& DMA_HW_FEAT_MMCSEL
) >> 11;
1580 /* IEEE 1588-2002 */
1581 priv
->dma_cap
.time_stamp
=
1582 (hw_cap
& DMA_HW_FEAT_TSVER1SEL
) >> 12;
1583 /* IEEE 1588-2008 */
1584 priv
->dma_cap
.atime_stamp
=
1585 (hw_cap
& DMA_HW_FEAT_TSVER2SEL
) >> 13;
1586 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1587 priv
->dma_cap
.eee
= (hw_cap
& DMA_HW_FEAT_EEESEL
) >> 14;
1588 priv
->dma_cap
.av
= (hw_cap
& DMA_HW_FEAT_AVSEL
) >> 15;
1589 /* TX and RX csum */
1590 priv
->dma_cap
.tx_coe
= (hw_cap
& DMA_HW_FEAT_TXCOESEL
) >> 16;
1591 priv
->dma_cap
.rx_coe_type1
=
1592 (hw_cap
& DMA_HW_FEAT_RXTYP1COE
) >> 17;
1593 priv
->dma_cap
.rx_coe_type2
=
1594 (hw_cap
& DMA_HW_FEAT_RXTYP2COE
) >> 18;
1595 priv
->dma_cap
.rxfifo_over_2048
=
1596 (hw_cap
& DMA_HW_FEAT_RXFIFOSIZE
) >> 19;
1597 /* TX and RX number of channels */
1598 priv
->dma_cap
.number_rx_channel
=
1599 (hw_cap
& DMA_HW_FEAT_RXCHCNT
) >> 20;
1600 priv
->dma_cap
.number_tx_channel
=
1601 (hw_cap
& DMA_HW_FEAT_TXCHCNT
) >> 22;
1602 /* Alternate (enhanced) DESC mode */
1603 priv
->dma_cap
.enh_desc
= (hw_cap
& DMA_HW_FEAT_ENHDESSEL
) >> 24;
1610 * stmmac_check_ether_addr - check if the MAC addr is valid
1611 * @priv: driver private structure
1613 * it is to verify if the MAC address is valid, in case of failures it
1614 * generates a random MAC address
1616 static void stmmac_check_ether_addr(struct stmmac_priv
*priv
)
1618 if (!is_valid_ether_addr(priv
->dev
->dev_addr
)) {
1619 priv
->hw
->mac
->get_umac_addr(priv
->hw
,
1620 priv
->dev
->dev_addr
, 0);
1621 if (!is_valid_ether_addr(priv
->dev
->dev_addr
))
1622 eth_hw_addr_random(priv
->dev
);
1623 pr_info("%s: device MAC address %pM\n", priv
->dev
->name
,
1624 priv
->dev
->dev_addr
);
1629 * stmmac_init_dma_engine - DMA init.
1630 * @priv: driver private structure
1632 * It inits the DMA invoking the specific MAC/GMAC callback.
1633 * Some DMA parameters can be passed from the platform;
1634 * in case of these are not passed a default is kept for the MAC or GMAC.
1636 static int stmmac_init_dma_engine(struct stmmac_priv
*priv
)
1638 int pbl
= DEFAULT_DMA_PBL
, fixed_burst
= 0, burst_len
= 0;
1639 int mixed_burst
= 0;
1642 if (priv
->plat
->dma_cfg
) {
1643 pbl
= priv
->plat
->dma_cfg
->pbl
;
1644 fixed_burst
= priv
->plat
->dma_cfg
->fixed_burst
;
1645 mixed_burst
= priv
->plat
->dma_cfg
->mixed_burst
;
1646 burst_len
= priv
->plat
->dma_cfg
->burst_len
;
1649 if (priv
->extend_desc
&& (priv
->mode
== STMMAC_RING_MODE
))
1652 return priv
->hw
->dma
->init(priv
->ioaddr
, pbl
, fixed_burst
, mixed_burst
,
1653 burst_len
, priv
->dma_tx_phy
,
1654 priv
->dma_rx_phy
, atds
);
1658 * stmmac_tx_timer - mitigation sw timer for tx.
1659 * @data: data pointer
1661 * This is the timer handler to directly invoke the stmmac_tx_clean.
1663 static void stmmac_tx_timer(unsigned long data
)
1665 struct stmmac_priv
*priv
= (struct stmmac_priv
*)data
;
1667 stmmac_tx_clean(priv
);
1671 * stmmac_init_tx_coalesce - init tx mitigation options.
1672 * @priv: driver private structure
1674 * This inits the transmit coalesce parameters: i.e. timer rate,
1675 * timer handler and default threshold used for enabling the
1676 * interrupt on completion bit.
1678 static void stmmac_init_tx_coalesce(struct stmmac_priv
*priv
)
1680 priv
->tx_coal_frames
= STMMAC_TX_FRAMES
;
1681 priv
->tx_coal_timer
= STMMAC_COAL_TX_TIMER
;
1682 init_timer(&priv
->txtimer
);
1683 priv
->txtimer
.expires
= STMMAC_COAL_TIMER(priv
->tx_coal_timer
);
1684 priv
->txtimer
.data
= (unsigned long)priv
;
1685 priv
->txtimer
.function
= stmmac_tx_timer
;
1686 add_timer(&priv
->txtimer
);
1690 * stmmac_hw_setup - setup mac in a usable state.
1691 * @dev : pointer to the device structure.
1693 * this is the main function to setup the HW in a usable state because the
1694 * dma engine is reset, the core registers are configured (e.g. AXI,
1695 * Checksum features, timers). The DMA is ready to start receiving and
1698 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1701 static int stmmac_hw_setup(struct net_device
*dev
, bool init_ptp
)
1703 struct stmmac_priv
*priv
= netdev_priv(dev
);
1706 /* DMA initialization and SW reset */
1707 ret
= stmmac_init_dma_engine(priv
);
1709 pr_err("%s: DMA engine initialization failed\n", __func__
);
1713 /* Copy the MAC addr into the HW */
1714 priv
->hw
->mac
->set_umac_addr(priv
->hw
, dev
->dev_addr
, 0);
1716 /* If required, perform hw setup of the bus. */
1717 if (priv
->plat
->bus_setup
)
1718 priv
->plat
->bus_setup(priv
->ioaddr
);
1720 /* Initialize the MAC Core */
1721 priv
->hw
->mac
->core_init(priv
->hw
, dev
->mtu
);
1723 ret
= priv
->hw
->mac
->rx_ipc(priv
->hw
);
1725 pr_warn(" RX IPC Checksum Offload disabled\n");
1726 priv
->plat
->rx_coe
= STMMAC_RX_COE_NONE
;
1727 priv
->hw
->rx_csum
= 0;
1730 /* Enable the MAC Rx/Tx */
1731 stmmac_set_mac(priv
->ioaddr
, true);
1733 /* Set the HW DMA mode and the COE */
1734 stmmac_dma_operation_mode(priv
);
1736 stmmac_mmc_setup(priv
);
1739 ret
= stmmac_init_ptp(priv
);
1740 if (ret
&& ret
!= -EOPNOTSUPP
)
1741 pr_warn("%s: failed PTP initialisation\n", __func__
);
1744 #ifdef CONFIG_DEBUG_FS
1745 ret
= stmmac_init_fs(dev
);
1747 pr_warn("%s: failed debugFS registration\n", __func__
);
1749 /* Start the ball rolling... */
1750 pr_debug("%s: DMA RX/TX processes started...\n", dev
->name
);
1751 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1752 priv
->hw
->dma
->start_rx(priv
->ioaddr
);
1754 /* Dump DMA/MAC registers */
1755 if (netif_msg_hw(priv
)) {
1756 priv
->hw
->mac
->dump_regs(priv
->hw
);
1757 priv
->hw
->dma
->dump_regs(priv
->ioaddr
);
1759 priv
->tx_lpi_timer
= STMMAC_DEFAULT_TWT_LS
;
1761 if ((priv
->use_riwt
) && (priv
->hw
->dma
->rx_watchdog
)) {
1762 priv
->rx_riwt
= MAX_DMA_RIWT
;
1763 priv
->hw
->dma
->rx_watchdog(priv
->ioaddr
, MAX_DMA_RIWT
);
1766 if (priv
->pcs
&& priv
->hw
->mac
->ctrl_ane
)
1767 priv
->hw
->mac
->ctrl_ane(priv
->hw
, 0);
1773 * stmmac_open - open entry point of the driver
1774 * @dev : pointer to the device structure.
1776 * This function is the open entry point of the driver.
1778 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1781 static int stmmac_open(struct net_device
*dev
)
1783 struct stmmac_priv
*priv
= netdev_priv(dev
);
1786 stmmac_check_ether_addr(priv
);
1788 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
1789 priv
->pcs
!= STMMAC_PCS_RTBI
) {
1790 ret
= stmmac_init_phy(dev
);
1792 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1798 /* Extra statistics */
1799 memset(&priv
->xstats
, 0, sizeof(struct stmmac_extra_stats
));
1800 priv
->xstats
.threshold
= tc
;
1802 /* Create and initialize the TX/RX descriptors chains. */
1803 priv
->dma_tx_size
= STMMAC_ALIGN(dma_txsize
);
1804 priv
->dma_rx_size
= STMMAC_ALIGN(dma_rxsize
);
1805 priv
->dma_buf_sz
= STMMAC_ALIGN(buf_sz
);
1807 ret
= alloc_dma_desc_resources(priv
);
1809 pr_err("%s: DMA descriptors allocation failed\n", __func__
);
1810 goto dma_desc_error
;
1813 ret
= init_dma_desc_rings(dev
, GFP_KERNEL
);
1815 pr_err("%s: DMA descriptors initialization failed\n", __func__
);
1819 ret
= stmmac_hw_setup(dev
, true);
1821 pr_err("%s: Hw setup failed\n", __func__
);
1825 stmmac_init_tx_coalesce(priv
);
1828 phy_start(priv
->phydev
);
1830 /* Request the IRQ lines */
1831 ret
= request_irq(dev
->irq
, stmmac_interrupt
,
1832 IRQF_SHARED
, dev
->name
, dev
);
1833 if (unlikely(ret
< 0)) {
1834 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1835 __func__
, dev
->irq
, ret
);
1839 /* Request the Wake IRQ in case of another line is used for WoL */
1840 if (priv
->wol_irq
!= dev
->irq
) {
1841 ret
= request_irq(priv
->wol_irq
, stmmac_interrupt
,
1842 IRQF_SHARED
, dev
->name
, dev
);
1843 if (unlikely(ret
< 0)) {
1844 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1845 __func__
, priv
->wol_irq
, ret
);
1850 /* Request the IRQ lines */
1851 if (priv
->lpi_irq
> 0) {
1852 ret
= request_irq(priv
->lpi_irq
, stmmac_interrupt
, IRQF_SHARED
,
1854 if (unlikely(ret
< 0)) {
1855 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1856 __func__
, priv
->lpi_irq
, ret
);
1861 napi_enable(&priv
->napi
);
1862 netif_start_queue(dev
);
1867 if (priv
->wol_irq
!= dev
->irq
)
1868 free_irq(priv
->wol_irq
, dev
);
1870 free_irq(dev
->irq
, dev
);
1873 free_dma_desc_resources(priv
);
1876 phy_disconnect(priv
->phydev
);
1882 * stmmac_release - close entry point of the driver
1883 * @dev : device pointer.
1885 * This is the stop entry point of the driver.
1887 static int stmmac_release(struct net_device
*dev
)
1889 struct stmmac_priv
*priv
= netdev_priv(dev
);
1891 if (priv
->eee_enabled
)
1892 del_timer_sync(&priv
->eee_ctrl_timer
);
1894 /* Stop and disconnect the PHY */
1896 phy_stop(priv
->phydev
);
1897 phy_disconnect(priv
->phydev
);
1898 priv
->phydev
= NULL
;
1901 netif_stop_queue(dev
);
1903 napi_disable(&priv
->napi
);
1905 del_timer_sync(&priv
->txtimer
);
1907 /* Free the IRQ lines */
1908 free_irq(dev
->irq
, dev
);
1909 if (priv
->wol_irq
!= dev
->irq
)
1910 free_irq(priv
->wol_irq
, dev
);
1911 if (priv
->lpi_irq
> 0)
1912 free_irq(priv
->lpi_irq
, dev
);
1914 /* Stop TX/RX DMA and clear the descriptors */
1915 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1916 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
1918 /* Release and free the Rx/Tx resources */
1919 free_dma_desc_resources(priv
);
1921 /* Disable the MAC Rx/Tx */
1922 stmmac_set_mac(priv
->ioaddr
, false);
1924 netif_carrier_off(dev
);
1926 #ifdef CONFIG_DEBUG_FS
1927 stmmac_exit_fs(dev
);
1930 stmmac_release_ptp(priv
);
1936 * stmmac_xmit - Tx entry point of the driver
1937 * @skb : the socket buffer
1938 * @dev : device pointer
1939 * Description : this is the tx entry point of the driver.
1940 * It programs the chain or the ring and supports oversized frames
1943 static netdev_tx_t
stmmac_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1945 struct stmmac_priv
*priv
= netdev_priv(dev
);
1946 unsigned int txsize
= priv
->dma_tx_size
;
1948 int i
, csum_insertion
= 0, is_jumbo
= 0;
1949 int nfrags
= skb_shinfo(skb
)->nr_frags
;
1950 struct dma_desc
*desc
, *first
;
1951 unsigned int nopaged_len
= skb_headlen(skb
);
1952 unsigned int enh_desc
= priv
->plat
->enh_desc
;
1954 spin_lock(&priv
->tx_lock
);
1956 if (unlikely(stmmac_tx_avail(priv
) < nfrags
+ 1)) {
1957 spin_unlock(&priv
->tx_lock
);
1958 if (!netif_queue_stopped(dev
)) {
1959 netif_stop_queue(dev
);
1960 /* This is a hard error, log it. */
1961 pr_err("%s: Tx Ring full when queue awake\n", __func__
);
1963 return NETDEV_TX_BUSY
;
1966 if (priv
->tx_path_in_lpi_mode
)
1967 stmmac_disable_eee_mode(priv
);
1969 entry
= priv
->cur_tx
% txsize
;
1971 csum_insertion
= (skb
->ip_summed
== CHECKSUM_PARTIAL
);
1973 if (priv
->extend_desc
)
1974 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1976 desc
= priv
->dma_tx
+ entry
;
1980 /* To program the descriptors according to the size of the frame */
1982 is_jumbo
= priv
->hw
->mode
->is_jumbo_frm(skb
->len
, enh_desc
);
1984 if (likely(!is_jumbo
)) {
1985 desc
->des2
= dma_map_single(priv
->device
, skb
->data
,
1986 nopaged_len
, DMA_TO_DEVICE
);
1987 if (dma_mapping_error(priv
->device
, desc
->des2
))
1989 priv
->tx_skbuff_dma
[entry
].buf
= desc
->des2
;
1990 priv
->hw
->desc
->prepare_tx_desc(desc
, 1, nopaged_len
,
1991 csum_insertion
, priv
->mode
);
1994 entry
= priv
->hw
->mode
->jumbo_frm(priv
, skb
, csum_insertion
);
1995 if (unlikely(entry
< 0))
1999 for (i
= 0; i
< nfrags
; i
++) {
2000 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2001 int len
= skb_frag_size(frag
);
2003 priv
->tx_skbuff
[entry
] = NULL
;
2004 entry
= (++priv
->cur_tx
) % txsize
;
2005 if (priv
->extend_desc
)
2006 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
2008 desc
= priv
->dma_tx
+ entry
;
2010 desc
->des2
= skb_frag_dma_map(priv
->device
, frag
, 0, len
,
2012 if (dma_mapping_error(priv
->device
, desc
->des2
))
2013 goto dma_map_err
; /* should reuse desc w/o issues */
2015 priv
->tx_skbuff_dma
[entry
].buf
= desc
->des2
;
2016 priv
->tx_skbuff_dma
[entry
].map_as_page
= true;
2017 priv
->hw
->desc
->prepare_tx_desc(desc
, 0, len
, csum_insertion
,
2020 priv
->hw
->desc
->set_tx_owner(desc
);
2024 priv
->tx_skbuff
[entry
] = skb
;
2026 /* Finalize the latest segment. */
2027 priv
->hw
->desc
->close_tx_desc(desc
);
2030 /* According to the coalesce parameter the IC bit for the latest
2031 * segment could be reset and the timer re-started to invoke the
2032 * stmmac_tx function. This approach takes care about the fragments.
2034 priv
->tx_count_frames
+= nfrags
+ 1;
2035 if (priv
->tx_coal_frames
> priv
->tx_count_frames
) {
2036 priv
->hw
->desc
->clear_tx_ic(desc
);
2037 priv
->xstats
.tx_reset_ic_bit
++;
2038 mod_timer(&priv
->txtimer
,
2039 STMMAC_COAL_TIMER(priv
->tx_coal_timer
));
2041 priv
->tx_count_frames
= 0;
2043 /* To avoid raise condition */
2044 priv
->hw
->desc
->set_tx_owner(first
);
2049 if (netif_msg_pktdata(priv
)) {
2050 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2051 __func__
, (priv
->cur_tx
% txsize
),
2052 (priv
->dirty_tx
% txsize
), entry
, first
, nfrags
);
2054 if (priv
->extend_desc
)
2055 stmmac_display_ring((void *)priv
->dma_etx
, txsize
, 1);
2057 stmmac_display_ring((void *)priv
->dma_tx
, txsize
, 0);
2059 pr_debug(">>> frame to be transmitted: ");
2060 print_pkt(skb
->data
, skb
->len
);
2062 if (unlikely(stmmac_tx_avail(priv
) <= (MAX_SKB_FRAGS
+ 1))) {
2063 if (netif_msg_hw(priv
))
2064 pr_debug("%s: stop transmitted packets\n", __func__
);
2065 netif_stop_queue(dev
);
2068 dev
->stats
.tx_bytes
+= skb
->len
;
2070 if (unlikely((skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) &&
2071 priv
->hwts_tx_en
)) {
2072 /* declare that device is doing timestamping */
2073 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
2074 priv
->hw
->desc
->enable_tx_timestamp(first
);
2077 if (!priv
->hwts_tx_en
)
2078 skb_tx_timestamp(skb
);
2080 netdev_sent_queue(dev
, skb
->len
);
2081 priv
->hw
->dma
->enable_dma_transmission(priv
->ioaddr
);
2083 spin_unlock(&priv
->tx_lock
);
2084 return NETDEV_TX_OK
;
2087 spin_unlock(&priv
->tx_lock
);
2088 dev_err(priv
->device
, "Tx dma map failed\n");
2090 priv
->dev
->stats
.tx_dropped
++;
2091 return NETDEV_TX_OK
;
2094 static void stmmac_rx_vlan(struct net_device
*dev
, struct sk_buff
*skb
)
2096 struct ethhdr
*ehdr
;
2099 if ((dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) ==
2100 NETIF_F_HW_VLAN_CTAG_RX
&&
2101 !__vlan_get_tag(skb
, &vlanid
)) {
2102 /* pop the vlan tag */
2103 ehdr
= (struct ethhdr
*)skb
->data
;
2104 memmove(skb
->data
+ VLAN_HLEN
, ehdr
, ETH_ALEN
* 2);
2105 skb_pull(skb
, VLAN_HLEN
);
2106 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vlanid
);
2112 * stmmac_rx_refill - refill used skb preallocated buffers
2113 * @priv: driver private structure
2114 * Description : this is to reallocate the skb for the reception process
2115 * that is based on zero-copy.
2117 static inline void stmmac_rx_refill(struct stmmac_priv
*priv
)
2119 unsigned int rxsize
= priv
->dma_rx_size
;
2120 int bfsize
= priv
->dma_buf_sz
;
2122 for (; priv
->cur_rx
- priv
->dirty_rx
> 0; priv
->dirty_rx
++) {
2123 unsigned int entry
= priv
->dirty_rx
% rxsize
;
2126 if (priv
->extend_desc
)
2127 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2129 p
= priv
->dma_rx
+ entry
;
2131 if (likely(priv
->rx_skbuff
[entry
] == NULL
)) {
2132 struct sk_buff
*skb
;
2134 skb
= netdev_alloc_skb_ip_align(priv
->dev
, bfsize
);
2136 if (unlikely(skb
== NULL
))
2139 priv
->rx_skbuff
[entry
] = skb
;
2140 priv
->rx_skbuff_dma
[entry
] =
2141 dma_map_single(priv
->device
, skb
->data
, bfsize
,
2143 if (dma_mapping_error(priv
->device
,
2144 priv
->rx_skbuff_dma
[entry
])) {
2145 dev_err(priv
->device
, "Rx dma map failed\n");
2149 p
->des2
= priv
->rx_skbuff_dma
[entry
];
2151 priv
->hw
->mode
->refill_desc3(priv
, p
);
2153 if (netif_msg_rx_status(priv
))
2154 pr_debug("\trefill entry #%d\n", entry
);
2157 priv
->hw
->desc
->set_rx_owner(p
);
2163 * stmmac_rx - manage the receive process
2164 * @priv: driver private structure
2165 * @limit: napi bugget.
2166 * Description : this the function called by the napi poll method.
2167 * It gets all the frames inside the ring.
2169 static int stmmac_rx(struct stmmac_priv
*priv
, int limit
)
2171 unsigned int rxsize
= priv
->dma_rx_size
;
2172 unsigned int entry
= priv
->cur_rx
% rxsize
;
2173 unsigned int next_entry
;
2174 unsigned int count
= 0;
2175 int coe
= priv
->hw
->rx_csum
;
2177 if (netif_msg_rx_status(priv
)) {
2178 pr_debug("%s: descriptor ring:\n", __func__
);
2179 if (priv
->extend_desc
)
2180 stmmac_display_ring((void *)priv
->dma_erx
, rxsize
, 1);
2182 stmmac_display_ring((void *)priv
->dma_rx
, rxsize
, 0);
2184 while (count
< limit
) {
2188 if (priv
->extend_desc
)
2189 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2191 p
= priv
->dma_rx
+ entry
;
2193 if (priv
->hw
->desc
->get_rx_owner(p
))
2198 next_entry
= (++priv
->cur_rx
) % rxsize
;
2199 if (priv
->extend_desc
)
2200 prefetch(priv
->dma_erx
+ next_entry
);
2202 prefetch(priv
->dma_rx
+ next_entry
);
2204 /* read the status of the incoming frame */
2205 status
= priv
->hw
->desc
->rx_status(&priv
->dev
->stats
,
2207 if ((priv
->extend_desc
) && (priv
->hw
->desc
->rx_extended_status
))
2208 priv
->hw
->desc
->rx_extended_status(&priv
->dev
->stats
,
2212 if (unlikely(status
== discard_frame
)) {
2213 priv
->dev
->stats
.rx_errors
++;
2214 if (priv
->hwts_rx_en
&& !priv
->extend_desc
) {
2215 /* DESC2 & DESC3 will be overwitten by device
2216 * with timestamp value, hence reinitialize
2217 * them in stmmac_rx_refill() function so that
2218 * device can reuse it.
2220 priv
->rx_skbuff
[entry
] = NULL
;
2221 dma_unmap_single(priv
->device
,
2222 priv
->rx_skbuff_dma
[entry
],
2227 struct sk_buff
*skb
;
2230 frame_len
= priv
->hw
->desc
->get_rx_frame_len(p
, coe
);
2232 /* check if frame_len fits the preallocated memory */
2233 if (frame_len
> priv
->dma_buf_sz
) {
2234 priv
->dev
->stats
.rx_length_errors
++;
2238 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2239 * Type frames (LLC/LLC-SNAP)
2241 if (unlikely(status
!= llc_snap
))
2242 frame_len
-= ETH_FCS_LEN
;
2244 if (netif_msg_rx_status(priv
)) {
2245 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2247 if (frame_len
> ETH_FRAME_LEN
)
2248 pr_debug("\tframe size %d, COE: %d\n",
2251 skb
= priv
->rx_skbuff
[entry
];
2252 if (unlikely(!skb
)) {
2253 pr_err("%s: Inconsistent Rx descriptor chain\n",
2255 priv
->dev
->stats
.rx_dropped
++;
2258 prefetch(skb
->data
- NET_IP_ALIGN
);
2259 priv
->rx_skbuff
[entry
] = NULL
;
2261 stmmac_get_rx_hwtstamp(priv
, entry
, skb
);
2263 skb_put(skb
, frame_len
);
2264 dma_unmap_single(priv
->device
,
2265 priv
->rx_skbuff_dma
[entry
],
2266 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
2268 if (netif_msg_pktdata(priv
)) {
2269 pr_debug("frame received (%dbytes)", frame_len
);
2270 print_pkt(skb
->data
, frame_len
);
2273 stmmac_rx_vlan(priv
->dev
, skb
);
2275 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
2278 skb_checksum_none_assert(skb
);
2280 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2282 napi_gro_receive(&priv
->napi
, skb
);
2284 priv
->dev
->stats
.rx_packets
++;
2285 priv
->dev
->stats
.rx_bytes
+= frame_len
;
2290 stmmac_rx_refill(priv
);
2292 priv
->xstats
.rx_pkt_n
+= count
;
2298 * stmmac_poll - stmmac poll method (NAPI)
2299 * @napi : pointer to the napi structure.
2300 * @budget : maximum number of packets that the current CPU can receive from
2303 * To look at the incoming frames and clear the tx resources.
2305 static int stmmac_poll(struct napi_struct
*napi
, int budget
)
2307 struct stmmac_priv
*priv
= container_of(napi
, struct stmmac_priv
, napi
);
2310 priv
->xstats
.napi_poll
++;
2311 stmmac_tx_clean(priv
);
2313 work_done
= stmmac_rx(priv
, budget
);
2314 if (work_done
< budget
) {
2315 napi_complete(napi
);
2316 stmmac_enable_dma_irq(priv
);
2323 * @dev : Pointer to net device structure
2324 * Description: this function is called when a packet transmission fails to
2325 * complete within a reasonable time. The driver will mark the error in the
2326 * netdev structure and arrange for the device to be reset to a sane state
2327 * in order to transmit a new packet.
2329 static void stmmac_tx_timeout(struct net_device
*dev
)
2331 struct stmmac_priv
*priv
= netdev_priv(dev
);
2333 /* Clear Tx resources and restart transmitting again */
2334 stmmac_tx_err(priv
);
2338 * stmmac_set_rx_mode - entry point for multicast addressing
2339 * @dev : pointer to the device structure
2341 * This function is a driver entry point which gets called by the kernel
2342 * whenever multicast addresses must be enabled/disabled.
2346 static void stmmac_set_rx_mode(struct net_device
*dev
)
2348 struct stmmac_priv
*priv
= netdev_priv(dev
);
2350 priv
->hw
->mac
->set_filter(priv
->hw
, dev
);
2354 * stmmac_change_mtu - entry point to change MTU size for the device.
2355 * @dev : device pointer.
2356 * @new_mtu : the new MTU size for the device.
2357 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2358 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2359 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2361 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2364 static int stmmac_change_mtu(struct net_device
*dev
, int new_mtu
)
2366 struct stmmac_priv
*priv
= netdev_priv(dev
);
2369 if (netif_running(dev
)) {
2370 pr_err("%s: must be stopped to change its MTU\n", dev
->name
);
2374 if (priv
->plat
->enh_desc
)
2375 max_mtu
= JUMBO_LEN
;
2377 max_mtu
= SKB_MAX_HEAD(NET_SKB_PAD
+ NET_IP_ALIGN
);
2379 if (priv
->plat
->maxmtu
< max_mtu
)
2380 max_mtu
= priv
->plat
->maxmtu
;
2382 if ((new_mtu
< 46) || (new_mtu
> max_mtu
)) {
2383 pr_err("%s: invalid MTU, max MTU is: %d\n", dev
->name
, max_mtu
);
2388 netdev_update_features(dev
);
2393 static netdev_features_t
stmmac_fix_features(struct net_device
*dev
,
2394 netdev_features_t features
)
2396 struct stmmac_priv
*priv
= netdev_priv(dev
);
2398 if (priv
->plat
->rx_coe
== STMMAC_RX_COE_NONE
)
2399 features
&= ~NETIF_F_RXCSUM
;
2401 if (!priv
->plat
->tx_coe
)
2402 features
&= ~NETIF_F_CSUM_MASK
;
2404 /* Some GMAC devices have a bugged Jumbo frame support that
2405 * needs to have the Tx COE disabled for oversized frames
2406 * (due to limited buffer sizes). In this case we disable
2407 * the TX csum insertionin the TDES and not use SF.
2409 if (priv
->plat
->bugged_jumbo
&& (dev
->mtu
> ETH_DATA_LEN
))
2410 features
&= ~NETIF_F_CSUM_MASK
;
2415 static int stmmac_set_features(struct net_device
*netdev
,
2416 netdev_features_t features
)
2418 struct stmmac_priv
*priv
= netdev_priv(netdev
);
2420 /* Keep the COE Type in case of csum is supporting */
2421 if (features
& NETIF_F_RXCSUM
)
2422 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
2424 priv
->hw
->rx_csum
= 0;
2425 /* No check needed because rx_coe has been set before and it will be
2426 * fixed in case of issue.
2428 priv
->hw
->mac
->rx_ipc(priv
->hw
);
2434 * stmmac_interrupt - main ISR
2435 * @irq: interrupt number.
2436 * @dev_id: to pass the net device pointer.
2437 * Description: this is the main driver interrupt service routine.
2439 * o DMA service routine (to manage incoming frame reception and transmission
2441 * o Core interrupts to manage: remote wake-up, management counter, LPI
2444 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
)
2446 struct net_device
*dev
= (struct net_device
*)dev_id
;
2447 struct stmmac_priv
*priv
= netdev_priv(dev
);
2450 pm_wakeup_event(priv
->device
, 0);
2452 if (unlikely(!dev
)) {
2453 pr_err("%s: invalid dev pointer\n", __func__
);
2457 /* To handle GMAC own interrupts */
2458 if (priv
->plat
->has_gmac
) {
2459 int status
= priv
->hw
->mac
->host_irq_status(priv
->hw
,
2461 if (unlikely(status
)) {
2462 /* For LPI we need to save the tx status */
2463 if (status
& CORE_IRQ_TX_PATH_IN_LPI_MODE
)
2464 priv
->tx_path_in_lpi_mode
= true;
2465 if (status
& CORE_IRQ_TX_PATH_EXIT_LPI_MODE
)
2466 priv
->tx_path_in_lpi_mode
= false;
2470 /* To handle DMA interrupts */
2471 stmmac_dma_interrupt(priv
);
2476 #ifdef CONFIG_NET_POLL_CONTROLLER
2477 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2478 * to allow network I/O with interrupts disabled.
2480 static void stmmac_poll_controller(struct net_device
*dev
)
2482 disable_irq(dev
->irq
);
2483 stmmac_interrupt(dev
->irq
, dev
);
2484 enable_irq(dev
->irq
);
2489 * stmmac_ioctl - Entry point for the Ioctl
2490 * @dev: Device pointer.
2491 * @rq: An IOCTL specefic structure, that can contain a pointer to
2492 * a proprietary structure used to pass information to the driver.
2493 * @cmd: IOCTL command
2495 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2497 static int stmmac_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2499 struct stmmac_priv
*priv
= netdev_priv(dev
);
2500 int ret
= -EOPNOTSUPP
;
2502 if (!netif_running(dev
))
2511 ret
= phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
2514 ret
= stmmac_hwtstamp_ioctl(dev
, rq
);
2523 #ifdef CONFIG_DEBUG_FS
2524 static struct dentry
*stmmac_fs_dir
;
2526 static void sysfs_display_ring(void *head
, int size
, int extend_desc
,
2527 struct seq_file
*seq
)
2530 struct dma_extended_desc
*ep
= (struct dma_extended_desc
*)head
;
2531 struct dma_desc
*p
= (struct dma_desc
*)head
;
2533 for (i
= 0; i
< size
; i
++) {
2537 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2538 i
, (unsigned int)virt_to_phys(ep
),
2539 (unsigned int)x
, (unsigned int)(x
>> 32),
2540 ep
->basic
.des2
, ep
->basic
.des3
);
2544 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2545 i
, (unsigned int)virt_to_phys(ep
),
2546 (unsigned int)x
, (unsigned int)(x
>> 32),
2550 seq_printf(seq
, "\n");
2554 static int stmmac_sysfs_ring_read(struct seq_file
*seq
, void *v
)
2556 struct net_device
*dev
= seq
->private;
2557 struct stmmac_priv
*priv
= netdev_priv(dev
);
2558 unsigned int txsize
= priv
->dma_tx_size
;
2559 unsigned int rxsize
= priv
->dma_rx_size
;
2561 if (priv
->extend_desc
) {
2562 seq_printf(seq
, "Extended RX descriptor ring:\n");
2563 sysfs_display_ring((void *)priv
->dma_erx
, rxsize
, 1, seq
);
2564 seq_printf(seq
, "Extended TX descriptor ring:\n");
2565 sysfs_display_ring((void *)priv
->dma_etx
, txsize
, 1, seq
);
2567 seq_printf(seq
, "RX descriptor ring:\n");
2568 sysfs_display_ring((void *)priv
->dma_rx
, rxsize
, 0, seq
);
2569 seq_printf(seq
, "TX descriptor ring:\n");
2570 sysfs_display_ring((void *)priv
->dma_tx
, txsize
, 0, seq
);
2576 static int stmmac_sysfs_ring_open(struct inode
*inode
, struct file
*file
)
2578 return single_open(file
, stmmac_sysfs_ring_read
, inode
->i_private
);
2581 static const struct file_operations stmmac_rings_status_fops
= {
2582 .owner
= THIS_MODULE
,
2583 .open
= stmmac_sysfs_ring_open
,
2585 .llseek
= seq_lseek
,
2586 .release
= single_release
,
2589 static int stmmac_sysfs_dma_cap_read(struct seq_file
*seq
, void *v
)
2591 struct net_device
*dev
= seq
->private;
2592 struct stmmac_priv
*priv
= netdev_priv(dev
);
2594 if (!priv
->hw_cap_support
) {
2595 seq_printf(seq
, "DMA HW features not supported\n");
2599 seq_printf(seq
, "==============================\n");
2600 seq_printf(seq
, "\tDMA HW features\n");
2601 seq_printf(seq
, "==============================\n");
2603 seq_printf(seq
, "\t10/100 Mbps %s\n",
2604 (priv
->dma_cap
.mbps_10_100
) ? "Y" : "N");
2605 seq_printf(seq
, "\t1000 Mbps %s\n",
2606 (priv
->dma_cap
.mbps_1000
) ? "Y" : "N");
2607 seq_printf(seq
, "\tHalf duple %s\n",
2608 (priv
->dma_cap
.half_duplex
) ? "Y" : "N");
2609 seq_printf(seq
, "\tHash Filter: %s\n",
2610 (priv
->dma_cap
.hash_filter
) ? "Y" : "N");
2611 seq_printf(seq
, "\tMultiple MAC address registers: %s\n",
2612 (priv
->dma_cap
.multi_addr
) ? "Y" : "N");
2613 seq_printf(seq
, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2614 (priv
->dma_cap
.pcs
) ? "Y" : "N");
2615 seq_printf(seq
, "\tSMA (MDIO) Interface: %s\n",
2616 (priv
->dma_cap
.sma_mdio
) ? "Y" : "N");
2617 seq_printf(seq
, "\tPMT Remote wake up: %s\n",
2618 (priv
->dma_cap
.pmt_remote_wake_up
) ? "Y" : "N");
2619 seq_printf(seq
, "\tPMT Magic Frame: %s\n",
2620 (priv
->dma_cap
.pmt_magic_frame
) ? "Y" : "N");
2621 seq_printf(seq
, "\tRMON module: %s\n",
2622 (priv
->dma_cap
.rmon
) ? "Y" : "N");
2623 seq_printf(seq
, "\tIEEE 1588-2002 Time Stamp: %s\n",
2624 (priv
->dma_cap
.time_stamp
) ? "Y" : "N");
2625 seq_printf(seq
, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2626 (priv
->dma_cap
.atime_stamp
) ? "Y" : "N");
2627 seq_printf(seq
, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2628 (priv
->dma_cap
.eee
) ? "Y" : "N");
2629 seq_printf(seq
, "\tAV features: %s\n", (priv
->dma_cap
.av
) ? "Y" : "N");
2630 seq_printf(seq
, "\tChecksum Offload in TX: %s\n",
2631 (priv
->dma_cap
.tx_coe
) ? "Y" : "N");
2632 seq_printf(seq
, "\tIP Checksum Offload (type1) in RX: %s\n",
2633 (priv
->dma_cap
.rx_coe_type1
) ? "Y" : "N");
2634 seq_printf(seq
, "\tIP Checksum Offload (type2) in RX: %s\n",
2635 (priv
->dma_cap
.rx_coe_type2
) ? "Y" : "N");
2636 seq_printf(seq
, "\tRXFIFO > 2048bytes: %s\n",
2637 (priv
->dma_cap
.rxfifo_over_2048
) ? "Y" : "N");
2638 seq_printf(seq
, "\tNumber of Additional RX channel: %d\n",
2639 priv
->dma_cap
.number_rx_channel
);
2640 seq_printf(seq
, "\tNumber of Additional TX channel: %d\n",
2641 priv
->dma_cap
.number_tx_channel
);
2642 seq_printf(seq
, "\tEnhanced descriptors: %s\n",
2643 (priv
->dma_cap
.enh_desc
) ? "Y" : "N");
2648 static int stmmac_sysfs_dma_cap_open(struct inode
*inode
, struct file
*file
)
2650 return single_open(file
, stmmac_sysfs_dma_cap_read
, inode
->i_private
);
2653 static const struct file_operations stmmac_dma_cap_fops
= {
2654 .owner
= THIS_MODULE
,
2655 .open
= stmmac_sysfs_dma_cap_open
,
2657 .llseek
= seq_lseek
,
2658 .release
= single_release
,
2661 static int stmmac_init_fs(struct net_device
*dev
)
2663 struct stmmac_priv
*priv
= netdev_priv(dev
);
2665 /* Create per netdev entries */
2666 priv
->dbgfs_dir
= debugfs_create_dir(dev
->name
, stmmac_fs_dir
);
2668 if (!priv
->dbgfs_dir
|| IS_ERR(priv
->dbgfs_dir
)) {
2669 pr_err("ERROR %s/%s, debugfs create directory failed\n",
2670 STMMAC_RESOURCE_NAME
, dev
->name
);
2675 /* Entry to report DMA RX/TX rings */
2676 priv
->dbgfs_rings_status
=
2677 debugfs_create_file("descriptors_status", S_IRUGO
,
2678 priv
->dbgfs_dir
, dev
,
2679 &stmmac_rings_status_fops
);
2681 if (!priv
->dbgfs_rings_status
|| IS_ERR(priv
->dbgfs_rings_status
)) {
2682 pr_info("ERROR creating stmmac ring debugfs file\n");
2683 debugfs_remove_recursive(priv
->dbgfs_dir
);
2688 /* Entry to report the DMA HW features */
2689 priv
->dbgfs_dma_cap
= debugfs_create_file("dma_cap", S_IRUGO
,
2691 dev
, &stmmac_dma_cap_fops
);
2693 if (!priv
->dbgfs_dma_cap
|| IS_ERR(priv
->dbgfs_dma_cap
)) {
2694 pr_info("ERROR creating stmmac MMC debugfs file\n");
2695 debugfs_remove_recursive(priv
->dbgfs_dir
);
2703 static void stmmac_exit_fs(struct net_device
*dev
)
2705 struct stmmac_priv
*priv
= netdev_priv(dev
);
2707 debugfs_remove_recursive(priv
->dbgfs_dir
);
2709 #endif /* CONFIG_DEBUG_FS */
2711 static const struct net_device_ops stmmac_netdev_ops
= {
2712 .ndo_open
= stmmac_open
,
2713 .ndo_start_xmit
= stmmac_xmit
,
2714 .ndo_stop
= stmmac_release
,
2715 .ndo_change_mtu
= stmmac_change_mtu
,
2716 .ndo_fix_features
= stmmac_fix_features
,
2717 .ndo_set_features
= stmmac_set_features
,
2718 .ndo_set_rx_mode
= stmmac_set_rx_mode
,
2719 .ndo_tx_timeout
= stmmac_tx_timeout
,
2720 .ndo_do_ioctl
= stmmac_ioctl
,
2721 #ifdef CONFIG_NET_POLL_CONTROLLER
2722 .ndo_poll_controller
= stmmac_poll_controller
,
2724 .ndo_set_mac_address
= eth_mac_addr
,
2728 * stmmac_hw_init - Init the MAC device
2729 * @priv: driver private structure
2730 * Description: this function is to configure the MAC device according to
2731 * some platform parameters or the HW capability register. It prepares the
2732 * driver to use either ring or chain modes and to setup either enhanced or
2733 * normal descriptors.
2735 static int stmmac_hw_init(struct stmmac_priv
*priv
)
2737 struct mac_device_info
*mac
;
2739 /* Identify the MAC HW device */
2740 if (priv
->plat
->has_gmac
) {
2741 priv
->dev
->priv_flags
|= IFF_UNICAST_FLT
;
2742 mac
= dwmac1000_setup(priv
->ioaddr
,
2743 priv
->plat
->multicast_filter_bins
,
2744 priv
->plat
->unicast_filter_entries
);
2746 mac
= dwmac100_setup(priv
->ioaddr
);
2753 /* Get and dump the chip ID */
2754 priv
->synopsys_id
= stmmac_get_synopsys_id(priv
);
2756 /* To use the chained or ring mode */
2758 priv
->hw
->mode
= &chain_mode_ops
;
2759 pr_info(" Chain mode enabled\n");
2760 priv
->mode
= STMMAC_CHAIN_MODE
;
2762 priv
->hw
->mode
= &ring_mode_ops
;
2763 pr_info(" Ring mode enabled\n");
2764 priv
->mode
= STMMAC_RING_MODE
;
2767 /* Get the HW capability (new GMAC newer than 3.50a) */
2768 priv
->hw_cap_support
= stmmac_get_hw_features(priv
);
2769 if (priv
->hw_cap_support
) {
2770 pr_info(" DMA HW capability register supported");
2772 /* We can override some gmac/dma configuration fields: e.g.
2773 * enh_desc, tx_coe (e.g. that are passed through the
2774 * platform) with the values from the HW capability
2775 * register (if supported).
2777 priv
->plat
->enh_desc
= priv
->dma_cap
.enh_desc
;
2778 priv
->plat
->pmt
= priv
->dma_cap
.pmt_remote_wake_up
;
2780 /* TXCOE doesn't work in thresh DMA mode */
2781 if (priv
->plat
->force_thresh_dma_mode
)
2782 priv
->plat
->tx_coe
= 0;
2784 priv
->plat
->tx_coe
= priv
->dma_cap
.tx_coe
;
2786 if (priv
->dma_cap
.rx_coe_type2
)
2787 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE2
;
2788 else if (priv
->dma_cap
.rx_coe_type1
)
2789 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE1
;
2792 pr_info(" No HW DMA feature register supported");
2794 /* To use alternate (extended) or normal descriptor structures */
2795 stmmac_selec_desc_mode(priv
);
2797 if (priv
->plat
->rx_coe
) {
2798 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
2799 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2800 priv
->plat
->rx_coe
);
2802 if (priv
->plat
->tx_coe
)
2803 pr_info(" TX Checksum insertion supported\n");
2805 if (priv
->plat
->pmt
) {
2806 pr_info(" Wake-Up On Lan supported\n");
2807 device_set_wakeup_capable(priv
->device
, 1);
2815 * @device: device pointer
2816 * @plat_dat: platform data pointer
2817 * @res: stmmac resource pointer
2818 * Description: this is the main probe function used to
2819 * call the alloc_etherdev, allocate the priv structure.
2821 * returns 0 on success, otherwise errno.
2823 int stmmac_dvr_probe(struct device
*device
,
2824 struct plat_stmmacenet_data
*plat_dat
,
2825 struct stmmac_resources
*res
)
2828 struct net_device
*ndev
= NULL
;
2829 struct stmmac_priv
*priv
;
2831 ndev
= alloc_etherdev(sizeof(struct stmmac_priv
));
2835 SET_NETDEV_DEV(ndev
, device
);
2837 priv
= netdev_priv(ndev
);
2838 priv
->device
= device
;
2841 stmmac_set_ethtool_ops(ndev
);
2842 priv
->pause
= pause
;
2843 priv
->plat
= plat_dat
;
2844 priv
->ioaddr
= res
->addr
;
2845 priv
->dev
->base_addr
= (unsigned long)res
->addr
;
2847 priv
->dev
->irq
= res
->irq
;
2848 priv
->wol_irq
= res
->wol_irq
;
2849 priv
->lpi_irq
= res
->lpi_irq
;
2852 memcpy(priv
->dev
->dev_addr
, res
->mac
, ETH_ALEN
);
2854 dev_set_drvdata(device
, priv
->dev
);
2856 /* Verify driver arguments */
2857 stmmac_verify_args();
2859 /* Override with kernel parameters if supplied XXX CRS XXX
2860 * this needs to have multiple instances
2862 if ((phyaddr
>= 0) && (phyaddr
<= 31))
2863 priv
->plat
->phy_addr
= phyaddr
;
2865 priv
->stmmac_clk
= devm_clk_get(priv
->device
, STMMAC_RESOURCE_NAME
);
2866 if (IS_ERR(priv
->stmmac_clk
)) {
2867 dev_warn(priv
->device
, "%s: warning: cannot get CSR clock\n",
2869 /* If failed to obtain stmmac_clk and specific clk_csr value
2870 * is NOT passed from the platform, probe fail.
2872 if (!priv
->plat
->clk_csr
) {
2873 ret
= PTR_ERR(priv
->stmmac_clk
);
2876 priv
->stmmac_clk
= NULL
;
2879 clk_prepare_enable(priv
->stmmac_clk
);
2881 priv
->pclk
= devm_clk_get(priv
->device
, "pclk");
2882 if (IS_ERR(priv
->pclk
)) {
2883 if (PTR_ERR(priv
->pclk
) == -EPROBE_DEFER
) {
2884 ret
= -EPROBE_DEFER
;
2885 goto error_pclk_get
;
2889 clk_prepare_enable(priv
->pclk
);
2891 priv
->stmmac_rst
= devm_reset_control_get(priv
->device
,
2892 STMMAC_RESOURCE_NAME
);
2893 if (IS_ERR(priv
->stmmac_rst
)) {
2894 if (PTR_ERR(priv
->stmmac_rst
) == -EPROBE_DEFER
) {
2895 ret
= -EPROBE_DEFER
;
2898 dev_info(priv
->device
, "no reset control found\n");
2899 priv
->stmmac_rst
= NULL
;
2901 if (priv
->stmmac_rst
)
2902 reset_control_deassert(priv
->stmmac_rst
);
2904 /* Init MAC and get the capabilities */
2905 ret
= stmmac_hw_init(priv
);
2909 ndev
->netdev_ops
= &stmmac_netdev_ops
;
2911 ndev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
2913 ndev
->features
|= ndev
->hw_features
| NETIF_F_HIGHDMA
;
2914 ndev
->watchdog_timeo
= msecs_to_jiffies(watchdog
);
2915 #ifdef STMMAC_VLAN_TAG_USED
2916 /* Both mac100 and gmac support receive VLAN tag detection */
2917 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_RX
;
2919 priv
->msg_enable
= netif_msg_init(debug
, default_msg_level
);
2922 priv
->flow_ctrl
= FLOW_AUTO
; /* RX/TX pause on */
2924 /* Rx Watchdog is available in the COREs newer than the 3.40.
2925 * In some case, for example on bugged HW this feature
2926 * has to be disable and this can be done by passing the
2927 * riwt_off field from the platform.
2929 if ((priv
->synopsys_id
>= DWMAC_CORE_3_50
) && (!priv
->plat
->riwt_off
)) {
2931 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2934 netif_napi_add(ndev
, &priv
->napi
, stmmac_poll
, 64);
2936 spin_lock_init(&priv
->lock
);
2937 spin_lock_init(&priv
->tx_lock
);
2939 ret
= register_netdev(ndev
);
2941 pr_err("%s: ERROR %i registering the device\n", __func__
, ret
);
2942 goto error_netdev_register
;
2945 /* If a specific clk_csr value is passed from the platform
2946 * this means that the CSR Clock Range selection cannot be
2947 * changed at run-time and it is fixed. Viceversa the driver'll try to
2948 * set the MDC clock dynamically according to the csr actual
2951 if (!priv
->plat
->clk_csr
)
2952 stmmac_clk_csr_set(priv
);
2954 priv
->clk_csr
= priv
->plat
->clk_csr
;
2956 stmmac_check_pcs_mode(priv
);
2958 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
2959 priv
->pcs
!= STMMAC_PCS_RTBI
) {
2960 /* MDIO bus Registration */
2961 ret
= stmmac_mdio_register(ndev
);
2963 pr_debug("%s: MDIO bus (id: %d) registration failed",
2964 __func__
, priv
->plat
->bus_id
);
2965 goto error_mdio_register
;
2971 error_mdio_register
:
2972 unregister_netdev(ndev
);
2973 error_netdev_register
:
2974 netif_napi_del(&priv
->napi
);
2976 clk_disable_unprepare(priv
->pclk
);
2978 clk_disable_unprepare(priv
->stmmac_clk
);
2984 EXPORT_SYMBOL_GPL(stmmac_dvr_probe
);
2988 * @ndev: net device pointer
2989 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2990 * changes the link status, releases the DMA descriptor rings.
2992 int stmmac_dvr_remove(struct net_device
*ndev
)
2994 struct stmmac_priv
*priv
= netdev_priv(ndev
);
2996 pr_info("%s:\n\tremoving driver", __func__
);
2998 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
2999 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
3001 stmmac_set_mac(priv
->ioaddr
, false);
3002 netif_carrier_off(ndev
);
3003 unregister_netdev(ndev
);
3004 if (priv
->stmmac_rst
)
3005 reset_control_assert(priv
->stmmac_rst
);
3006 clk_disable_unprepare(priv
->pclk
);
3007 clk_disable_unprepare(priv
->stmmac_clk
);
3008 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
3009 priv
->pcs
!= STMMAC_PCS_RTBI
)
3010 stmmac_mdio_unregister(ndev
);
3015 EXPORT_SYMBOL_GPL(stmmac_dvr_remove
);
3018 * stmmac_suspend - suspend callback
3019 * @ndev: net device pointer
3020 * Description: this is the function to suspend the device and it is called
3021 * by the platform driver to stop the network queue, release the resources,
3022 * program the PMT register (for WoL), clean and release driver resources.
3024 int stmmac_suspend(struct net_device
*ndev
)
3026 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3027 unsigned long flags
;
3029 if (!ndev
|| !netif_running(ndev
))
3033 phy_stop(priv
->phydev
);
3035 spin_lock_irqsave(&priv
->lock
, flags
);
3037 netif_device_detach(ndev
);
3038 netif_stop_queue(ndev
);
3040 napi_disable(&priv
->napi
);
3042 /* Stop TX/RX DMA */
3043 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
3044 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
3046 /* Enable Power down mode by programming the PMT regs */
3047 if (device_may_wakeup(priv
->device
)) {
3048 priv
->hw
->mac
->pmt(priv
->hw
, priv
->wolopts
);
3051 stmmac_set_mac(priv
->ioaddr
, false);
3052 pinctrl_pm_select_sleep_state(priv
->device
);
3053 /* Disable clock in case of PWM is off */
3054 clk_disable(priv
->pclk
);
3055 clk_disable(priv
->stmmac_clk
);
3057 spin_unlock_irqrestore(&priv
->lock
, flags
);
3061 priv
->oldduplex
= -1;
3064 EXPORT_SYMBOL_GPL(stmmac_suspend
);
3067 * stmmac_resume - resume callback
3068 * @ndev: net device pointer
3069 * Description: when resume this function is invoked to setup the DMA and CORE
3070 * in a usable state.
3072 int stmmac_resume(struct net_device
*ndev
)
3074 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3075 unsigned long flags
;
3077 if (!netif_running(ndev
))
3080 spin_lock_irqsave(&priv
->lock
, flags
);
3082 /* Power Down bit, into the PM register, is cleared
3083 * automatically as soon as a magic packet or a Wake-up frame
3084 * is received. Anyway, it's better to manually clear
3085 * this bit because it can generate problems while resuming
3086 * from another devices (e.g. serial console).
3088 if (device_may_wakeup(priv
->device
)) {
3089 priv
->hw
->mac
->pmt(priv
->hw
, 0);
3092 pinctrl_pm_select_default_state(priv
->device
);
3093 /* enable the clk prevously disabled */
3094 clk_enable(priv
->stmmac_clk
);
3095 clk_enable(priv
->pclk
);
3096 /* reset the phy so that it's ready */
3098 stmmac_mdio_reset(priv
->mii
);
3101 netif_device_attach(ndev
);
3107 stmmac_clear_descriptors(priv
);
3109 stmmac_hw_setup(ndev
, false);
3110 stmmac_init_tx_coalesce(priv
);
3111 stmmac_set_rx_mode(ndev
);
3113 napi_enable(&priv
->napi
);
3115 netif_start_queue(ndev
);
3117 spin_unlock_irqrestore(&priv
->lock
, flags
);
3120 phy_start(priv
->phydev
);
3124 EXPORT_SYMBOL_GPL(stmmac_resume
);
3127 static int __init
stmmac_cmdline_opt(char *str
)
3133 while ((opt
= strsep(&str
, ",")) != NULL
) {
3134 if (!strncmp(opt
, "debug:", 6)) {
3135 if (kstrtoint(opt
+ 6, 0, &debug
))
3137 } else if (!strncmp(opt
, "phyaddr:", 8)) {
3138 if (kstrtoint(opt
+ 8, 0, &phyaddr
))
3140 } else if (!strncmp(opt
, "dma_txsize:", 11)) {
3141 if (kstrtoint(opt
+ 11, 0, &dma_txsize
))
3143 } else if (!strncmp(opt
, "dma_rxsize:", 11)) {
3144 if (kstrtoint(opt
+ 11, 0, &dma_rxsize
))
3146 } else if (!strncmp(opt
, "buf_sz:", 7)) {
3147 if (kstrtoint(opt
+ 7, 0, &buf_sz
))
3149 } else if (!strncmp(opt
, "tc:", 3)) {
3150 if (kstrtoint(opt
+ 3, 0, &tc
))
3152 } else if (!strncmp(opt
, "watchdog:", 9)) {
3153 if (kstrtoint(opt
+ 9, 0, &watchdog
))
3155 } else if (!strncmp(opt
, "flow_ctrl:", 10)) {
3156 if (kstrtoint(opt
+ 10, 0, &flow_ctrl
))
3158 } else if (!strncmp(opt
, "pause:", 6)) {
3159 if (kstrtoint(opt
+ 6, 0, &pause
))
3161 } else if (!strncmp(opt
, "eee_timer:", 10)) {
3162 if (kstrtoint(opt
+ 10, 0, &eee_timer
))
3164 } else if (!strncmp(opt
, "chain_mode:", 11)) {
3165 if (kstrtoint(opt
+ 11, 0, &chain_mode
))
3172 pr_err("%s: ERROR broken module parameter conversion", __func__
);
3176 __setup("stmmaceth=", stmmac_cmdline_opt
);
3179 static int __init
stmmac_init(void)
3181 #ifdef CONFIG_DEBUG_FS
3182 /* Create debugfs main directory if it doesn't exist yet */
3183 if (!stmmac_fs_dir
) {
3184 stmmac_fs_dir
= debugfs_create_dir(STMMAC_RESOURCE_NAME
, NULL
);
3186 if (!stmmac_fs_dir
|| IS_ERR(stmmac_fs_dir
)) {
3187 pr_err("ERROR %s, debugfs create directory failed\n",
3188 STMMAC_RESOURCE_NAME
);
3198 static void __exit
stmmac_exit(void)
3200 #ifdef CONFIG_DEBUG_FS
3201 debugfs_remove_recursive(stmmac_fs_dir
);
3205 module_init(stmmac_init
)
3206 module_exit(stmmac_exit
)
3208 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3209 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3210 MODULE_LICENSE("GPL");