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git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
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1 /*******************************************************************************
2 STMMAC Ethernet Driver -- MDIO bus implementation
3 Provides Bus interface for MII registers
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Carl Shaw <carl.shaw@st.com>
24 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 *******************************************************************************/
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/slab.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_mdio.h>
37 #define MII_BUSY 0x00000001
38 #define MII_WRITE 0x00000002
40 static int stmmac_mdio_busy_wait(void __iomem
*ioaddr
, unsigned int mii_addr
)
43 unsigned long finish
= jiffies
+ 3 * HZ
;
47 if (readl(ioaddr
+ mii_addr
) & MII_BUSY
)
51 } while (!time_after_eq(curr
, finish
));
58 * @bus: points to the mii_bus structure
59 * @phyaddr: MII addr reg bits 15-11
60 * @phyreg: MII addr reg bits 10-6
61 * Description: it reads data from the MII register from within the phy device.
62 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
63 * accessing the PHY registers.
64 * Fortunately, it seems this has no drawback for the 7109 MAC.
66 static int stmmac_mdio_read(struct mii_bus
*bus
, int phyaddr
, int phyreg
)
68 struct net_device
*ndev
= bus
->priv
;
69 struct stmmac_priv
*priv
= netdev_priv(ndev
);
70 unsigned int mii_address
= priv
->hw
->mii
.addr
;
71 unsigned int mii_data
= priv
->hw
->mii
.data
;
74 u16 regValue
= (((phyaddr
<< 11) & (0x0000F800)) |
75 ((phyreg
<< 6) & (0x000007C0)));
76 regValue
|= MII_BUSY
| ((priv
->clk_csr
& 0xF) << 2);
78 if (stmmac_mdio_busy_wait(priv
->ioaddr
, mii_address
))
81 writel(regValue
, priv
->ioaddr
+ mii_address
);
83 if (stmmac_mdio_busy_wait(priv
->ioaddr
, mii_address
))
86 /* Read the data from the MII data register */
87 data
= (int)readl(priv
->ioaddr
+ mii_data
);
94 * @bus: points to the mii_bus structure
95 * @phyaddr: MII addr reg bits 15-11
96 * @phyreg: MII addr reg bits 10-6
98 * Description: it writes the data into the MII register from within the device.
100 static int stmmac_mdio_write(struct mii_bus
*bus
, int phyaddr
, int phyreg
,
103 struct net_device
*ndev
= bus
->priv
;
104 struct stmmac_priv
*priv
= netdev_priv(ndev
);
105 unsigned int mii_address
= priv
->hw
->mii
.addr
;
106 unsigned int mii_data
= priv
->hw
->mii
.data
;
109 (((phyaddr
<< 11) & (0x0000F800)) | ((phyreg
<< 6) & (0x000007C0)))
112 value
|= MII_BUSY
| ((priv
->clk_csr
& 0xF) << 2);
114 /* Wait until any existing MII operation is complete */
115 if (stmmac_mdio_busy_wait(priv
->ioaddr
, mii_address
))
118 /* Set the MII address register to write */
119 writel(phydata
, priv
->ioaddr
+ mii_data
);
120 writel(value
, priv
->ioaddr
+ mii_address
);
122 /* Wait until any existing MII operation is complete */
123 return stmmac_mdio_busy_wait(priv
->ioaddr
, mii_address
);
128 * @bus: points to the mii_bus structure
129 * Description: reset the MII bus
131 int stmmac_mdio_reset(struct mii_bus
*bus
)
133 #if defined(CONFIG_STMMAC_PLATFORM)
134 struct net_device
*ndev
= bus
->priv
;
135 struct stmmac_priv
*priv
= netdev_priv(ndev
);
136 unsigned int mii_address
= priv
->hw
->mii
.addr
;
137 struct stmmac_mdio_bus_data
*data
= priv
->plat
->mdio_bus_data
;
140 if (priv
->device
->of_node
) {
142 if (data
->reset_gpio
< 0) {
143 struct device_node
*np
= priv
->device
->of_node
;
147 data
->reset_gpio
= of_get_named_gpio(np
,
148 "snps,reset-gpio", 0);
149 if (data
->reset_gpio
< 0)
152 data
->active_low
= of_property_read_bool(np
,
153 "snps,reset-active-low");
154 of_property_read_u32_array(np
,
155 "snps,reset-delays-us", data
->delays
, 3);
157 if (gpio_request(data
->reset_gpio
, "mdio-reset"))
161 gpio_direction_output(data
->reset_gpio
,
162 data
->active_low
? 1 : 0);
164 msleep(DIV_ROUND_UP(data
->delays
[0], 1000));
166 gpio_set_value(data
->reset_gpio
, data
->active_low
? 0 : 1);
168 msleep(DIV_ROUND_UP(data
->delays
[1], 1000));
170 gpio_set_value(data
->reset_gpio
, data
->active_low
? 1 : 0);
172 msleep(DIV_ROUND_UP(data
->delays
[2], 1000));
176 if (data
->phy_reset
) {
177 pr_debug("stmmac_mdio_reset: calling phy_reset\n");
178 data
->phy_reset(priv
->plat
->bsp_priv
);
181 /* This is a workaround for problems with the STE101P PHY.
182 * It doesn't complete its reset until at least one clock cycle
183 * on MDC, so perform a dummy mdio read.
185 writel(0, priv
->ioaddr
+ mii_address
);
191 * stmmac_mdio_register
192 * @ndev: net device structure
193 * Description: it registers the MII bus
195 int stmmac_mdio_register(struct net_device
*ndev
)
198 struct mii_bus
*new_bus
;
199 struct stmmac_priv
*priv
= netdev_priv(ndev
);
200 struct stmmac_mdio_bus_data
*mdio_bus_data
= priv
->plat
->mdio_bus_data
;
202 struct device_node
*mdio_node
= NULL
;
203 struct device_node
*child_node
= NULL
;
208 if (IS_ENABLED(CONFIG_OF
)) {
209 for_each_child_of_node(priv
->device
->of_node
, child_node
) {
210 if (of_device_is_compatible(child_node
,
211 "snps,dwmac-mdio")) {
212 mdio_node
= child_node
;
218 netdev_dbg(ndev
, "FOUND MDIO subnode\n");
220 netdev_err(ndev
, "NO MDIO subnode\n");
225 new_bus
= mdiobus_alloc();
229 if (mdio_bus_data
->irqs
)
230 memcpy(new_bus
->irq
, mdio_bus_data
, sizeof(new_bus
->irq
));
233 if (priv
->device
->of_node
)
234 mdio_bus_data
->reset_gpio
= -1;
237 new_bus
->name
= "stmmac";
238 new_bus
->read
= &stmmac_mdio_read
;
239 new_bus
->write
= &stmmac_mdio_write
;
240 new_bus
->reset
= &stmmac_mdio_reset
;
241 snprintf(new_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
242 new_bus
->name
, priv
->plat
->bus_id
);
243 new_bus
->priv
= ndev
;
244 new_bus
->phy_mask
= mdio_bus_data
->phy_mask
;
245 new_bus
->parent
= priv
->device
;
247 err
= of_mdiobus_register(new_bus
, mdio_node
);
249 pr_err("%s: Cannot register as MDIO bus\n", new_bus
->name
);
250 goto bus_register_fail
;
254 for (addr
= 0; addr
< PHY_MAX_ADDR
; addr
++) {
255 struct phy_device
*phydev
= new_bus
->phy_map
[addr
];
262 * If an IRQ was provided to be assigned after
263 * the bus probe, do it here.
265 if ((mdio_bus_data
->irqs
== NULL
) &&
266 (mdio_bus_data
->probed_phy_irq
> 0)) {
268 mdio_bus_data
->probed_phy_irq
;
269 phydev
->irq
= mdio_bus_data
->probed_phy_irq
;
273 * If we're going to bind the MAC to this PHY bus,
274 * and no PHY number was provided to the MAC,
275 * use the one probed here.
277 if (priv
->plat
->phy_addr
== -1)
278 priv
->plat
->phy_addr
= addr
;
280 act
= (priv
->plat
->phy_addr
== addr
);
281 switch (phydev
->irq
) {
285 case PHY_IGNORE_INTERRUPT
:
289 sprintf(irq_num
, "%d", phydev
->irq
);
293 pr_info("%s: PHY ID %08x at %d IRQ %s (%s)%s\n",
294 ndev
->name
, phydev
->phy_id
, addr
,
295 irq_str
, phydev_name(phydev
),
296 act
? " active" : "");
301 if (!found
&& !mdio_node
) {
302 pr_warn("%s: No PHY found\n", ndev
->name
);
303 mdiobus_unregister(new_bus
);
304 mdiobus_free(new_bus
);
313 mdiobus_free(new_bus
);
318 * stmmac_mdio_unregister
319 * @ndev: net device structure
320 * Description: it unregisters the MII bus
322 int stmmac_mdio_unregister(struct net_device
*ndev
)
324 struct stmmac_priv
*priv
= netdev_priv(ndev
);
329 mdiobus_unregister(priv
->mii
);
330 priv
->mii
->priv
= NULL
;
331 mdiobus_free(priv
->mii
);