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1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
5 *
6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
12 *
13 */
14
15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/fcntl.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/in.h>
24 #include <linux/sched.h>
25 #include <linux/string.h>
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <linux/pci.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/mii.h>
34 #include <linux/ethtool.h>
35 #include <linux/crc32.h>
36 #include <linux/random.h>
37 #include <linux/workqueue.h>
38 #include <linux/if_vlan.h>
39 #include <linux/bitops.h>
40 #include <linux/mm.h>
41 #include <linux/gfp.h>
42
43 #include <asm/io.h>
44 #include <asm/byteorder.h>
45 #include <linux/uaccess.h>
46 #include <asm/irq.h>
47
48 #ifdef CONFIG_SPARC
49 #include <asm/idprom.h>
50 #include <asm/prom.h>
51 #endif
52
53 #ifdef CONFIG_PPC_PMAC
54 #include <asm/prom.h>
55 #include <asm/machdep.h>
56 #include <asm/pmac_feature.h>
57 #endif
58
59 #include <linux/sungem_phy.h>
60 #include "sungem.h"
61
62 /* Stripping FCS is causing problems, disabled for now */
63 #undef STRIP_FCS
64
65 #define DEFAULT_MSG (NETIF_MSG_DRV | \
66 NETIF_MSG_PROBE | \
67 NETIF_MSG_LINK)
68
69 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
70 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
71 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
72 SUPPORTED_Pause | SUPPORTED_Autoneg)
73
74 #define DRV_NAME "sungem"
75 #define DRV_VERSION "1.0"
76 #define DRV_AUTHOR "David S. Miller <davem@redhat.com>"
77
78 static char version[] =
79 DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n";
80
81 MODULE_AUTHOR(DRV_AUTHOR);
82 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
83 MODULE_LICENSE("GPL");
84
85 #define GEM_MODULE_NAME "gem"
86
87 static const struct pci_device_id gem_pci_tbl[] = {
88 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
89 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
90
91 /* These models only differ from the original GEM in
92 * that their tx/rx fifos are of a different size and
93 * they only support 10/100 speeds. -DaveM
94 *
95 * Apple's GMAC does support gigabit on machines with
96 * the BCM54xx PHYs. -BenH
97 */
98 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
99 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
100 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
102 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
104 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
106 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
108 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
110 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
112 {0, }
113 };
114
115 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
116
117 static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg)
118 {
119 u32 cmd;
120 int limit = 10000;
121
122 cmd = (1 << 30);
123 cmd |= (2 << 28);
124 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
125 cmd |= (reg << 18) & MIF_FRAME_REGAD;
126 cmd |= (MIF_FRAME_TAMSB);
127 writel(cmd, gp->regs + MIF_FRAME);
128
129 while (--limit) {
130 cmd = readl(gp->regs + MIF_FRAME);
131 if (cmd & MIF_FRAME_TALSB)
132 break;
133
134 udelay(10);
135 }
136
137 if (!limit)
138 cmd = 0xffff;
139
140 return cmd & MIF_FRAME_DATA;
141 }
142
143 static inline int _sungem_phy_read(struct net_device *dev, int mii_id, int reg)
144 {
145 struct gem *gp = netdev_priv(dev);
146 return __sungem_phy_read(gp, mii_id, reg);
147 }
148
149 static inline u16 sungem_phy_read(struct gem *gp, int reg)
150 {
151 return __sungem_phy_read(gp, gp->mii_phy_addr, reg);
152 }
153
154 static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
155 {
156 u32 cmd;
157 int limit = 10000;
158
159 cmd = (1 << 30);
160 cmd |= (1 << 28);
161 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
162 cmd |= (reg << 18) & MIF_FRAME_REGAD;
163 cmd |= (MIF_FRAME_TAMSB);
164 cmd |= (val & MIF_FRAME_DATA);
165 writel(cmd, gp->regs + MIF_FRAME);
166
167 while (limit--) {
168 cmd = readl(gp->regs + MIF_FRAME);
169 if (cmd & MIF_FRAME_TALSB)
170 break;
171
172 udelay(10);
173 }
174 }
175
176 static inline void _sungem_phy_write(struct net_device *dev, int mii_id, int reg, int val)
177 {
178 struct gem *gp = netdev_priv(dev);
179 __sungem_phy_write(gp, mii_id, reg, val & 0xffff);
180 }
181
182 static inline void sungem_phy_write(struct gem *gp, int reg, u16 val)
183 {
184 __sungem_phy_write(gp, gp->mii_phy_addr, reg, val);
185 }
186
187 static inline void gem_enable_ints(struct gem *gp)
188 {
189 /* Enable all interrupts but TXDONE */
190 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
191 }
192
193 static inline void gem_disable_ints(struct gem *gp)
194 {
195 /* Disable all interrupts, including TXDONE */
196 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
197 (void)readl(gp->regs + GREG_IMASK); /* write posting */
198 }
199
200 static void gem_get_cell(struct gem *gp)
201 {
202 BUG_ON(gp->cell_enabled < 0);
203 gp->cell_enabled++;
204 #ifdef CONFIG_PPC_PMAC
205 if (gp->cell_enabled == 1) {
206 mb();
207 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
208 udelay(10);
209 }
210 #endif /* CONFIG_PPC_PMAC */
211 }
212
213 /* Turn off the chip's clock */
214 static void gem_put_cell(struct gem *gp)
215 {
216 BUG_ON(gp->cell_enabled <= 0);
217 gp->cell_enabled--;
218 #ifdef CONFIG_PPC_PMAC
219 if (gp->cell_enabled == 0) {
220 mb();
221 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
222 udelay(10);
223 }
224 #endif /* CONFIG_PPC_PMAC */
225 }
226
227 static inline void gem_netif_stop(struct gem *gp)
228 {
229 netif_trans_update(gp->dev); /* prevent tx timeout */
230 napi_disable(&gp->napi);
231 netif_tx_disable(gp->dev);
232 }
233
234 static inline void gem_netif_start(struct gem *gp)
235 {
236 /* NOTE: unconditional netif_wake_queue is only
237 * appropriate so long as all callers are assured to
238 * have free tx slots.
239 */
240 netif_wake_queue(gp->dev);
241 napi_enable(&gp->napi);
242 }
243
244 static void gem_schedule_reset(struct gem *gp)
245 {
246 gp->reset_task_pending = 1;
247 schedule_work(&gp->reset_task);
248 }
249
250 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
251 {
252 if (netif_msg_intr(gp))
253 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
254 }
255
256 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
257 {
258 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
259 u32 pcs_miistat;
260
261 if (netif_msg_intr(gp))
262 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
263 gp->dev->name, pcs_istat);
264
265 if (!(pcs_istat & PCS_ISTAT_LSC)) {
266 netdev_err(dev, "PCS irq but no link status change???\n");
267 return 0;
268 }
269
270 /* The link status bit latches on zero, so you must
271 * read it twice in such a case to see a transition
272 * to the link being up.
273 */
274 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
275 if (!(pcs_miistat & PCS_MIISTAT_LS))
276 pcs_miistat |=
277 (readl(gp->regs + PCS_MIISTAT) &
278 PCS_MIISTAT_LS);
279
280 if (pcs_miistat & PCS_MIISTAT_ANC) {
281 /* The remote-fault indication is only valid
282 * when autoneg has completed.
283 */
284 if (pcs_miistat & PCS_MIISTAT_RF)
285 netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");
286 else
287 netdev_info(dev, "PCS AutoNEG complete\n");
288 }
289
290 if (pcs_miistat & PCS_MIISTAT_LS) {
291 netdev_info(dev, "PCS link is now up\n");
292 netif_carrier_on(gp->dev);
293 } else {
294 netdev_info(dev, "PCS link is now down\n");
295 netif_carrier_off(gp->dev);
296 /* If this happens and the link timer is not running,
297 * reset so we re-negotiate.
298 */
299 if (!timer_pending(&gp->link_timer))
300 return 1;
301 }
302
303 return 0;
304 }
305
306 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
307 {
308 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
309
310 if (netif_msg_intr(gp))
311 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
312 gp->dev->name, txmac_stat);
313
314 /* Defer timer expiration is quite normal,
315 * don't even log the event.
316 */
317 if ((txmac_stat & MAC_TXSTAT_DTE) &&
318 !(txmac_stat & ~MAC_TXSTAT_DTE))
319 return 0;
320
321 if (txmac_stat & MAC_TXSTAT_URUN) {
322 netdev_err(dev, "TX MAC xmit underrun\n");
323 dev->stats.tx_fifo_errors++;
324 }
325
326 if (txmac_stat & MAC_TXSTAT_MPE) {
327 netdev_err(dev, "TX MAC max packet size error\n");
328 dev->stats.tx_errors++;
329 }
330
331 /* The rest are all cases of one of the 16-bit TX
332 * counters expiring.
333 */
334 if (txmac_stat & MAC_TXSTAT_NCE)
335 dev->stats.collisions += 0x10000;
336
337 if (txmac_stat & MAC_TXSTAT_ECE) {
338 dev->stats.tx_aborted_errors += 0x10000;
339 dev->stats.collisions += 0x10000;
340 }
341
342 if (txmac_stat & MAC_TXSTAT_LCE) {
343 dev->stats.tx_aborted_errors += 0x10000;
344 dev->stats.collisions += 0x10000;
345 }
346
347 /* We do not keep track of MAC_TXSTAT_FCE and
348 * MAC_TXSTAT_PCE events.
349 */
350 return 0;
351 }
352
353 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
354 * so we do the following.
355 *
356 * If any part of the reset goes wrong, we return 1 and that causes the
357 * whole chip to be reset.
358 */
359 static int gem_rxmac_reset(struct gem *gp)
360 {
361 struct net_device *dev = gp->dev;
362 int limit, i;
363 u64 desc_dma;
364 u32 val;
365
366 /* First, reset & disable MAC RX. */
367 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
368 for (limit = 0; limit < 5000; limit++) {
369 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
370 break;
371 udelay(10);
372 }
373 if (limit == 5000) {
374 netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");
375 return 1;
376 }
377
378 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
379 gp->regs + MAC_RXCFG);
380 for (limit = 0; limit < 5000; limit++) {
381 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
382 break;
383 udelay(10);
384 }
385 if (limit == 5000) {
386 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
387 return 1;
388 }
389
390 /* Second, disable RX DMA. */
391 writel(0, gp->regs + RXDMA_CFG);
392 for (limit = 0; limit < 5000; limit++) {
393 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
394 break;
395 udelay(10);
396 }
397 if (limit == 5000) {
398 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
399 return 1;
400 }
401
402 mdelay(5);
403
404 /* Execute RX reset command. */
405 writel(gp->swrst_base | GREG_SWRST_RXRST,
406 gp->regs + GREG_SWRST);
407 for (limit = 0; limit < 5000; limit++) {
408 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
409 break;
410 udelay(10);
411 }
412 if (limit == 5000) {
413 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
414 return 1;
415 }
416
417 /* Refresh the RX ring. */
418 for (i = 0; i < RX_RING_SIZE; i++) {
419 struct gem_rxd *rxd = &gp->init_block->rxd[i];
420
421 if (gp->rx_skbs[i] == NULL) {
422 netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");
423 return 1;
424 }
425
426 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
427 }
428 gp->rx_new = gp->rx_old = 0;
429
430 /* Now we must reprogram the rest of RX unit. */
431 desc_dma = (u64) gp->gblock_dvma;
432 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
433 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
434 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
435 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
436 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
437 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
438 writel(val, gp->regs + RXDMA_CFG);
439 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
440 writel(((5 & RXDMA_BLANK_IPKTS) |
441 ((8 << 12) & RXDMA_BLANK_ITIME)),
442 gp->regs + RXDMA_BLANK);
443 else
444 writel(((5 & RXDMA_BLANK_IPKTS) |
445 ((4 << 12) & RXDMA_BLANK_ITIME)),
446 gp->regs + RXDMA_BLANK);
447 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
448 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
449 writel(val, gp->regs + RXDMA_PTHRESH);
450 val = readl(gp->regs + RXDMA_CFG);
451 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
452 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
453 val = readl(gp->regs + MAC_RXCFG);
454 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
455
456 return 0;
457 }
458
459 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
460 {
461 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
462 int ret = 0;
463
464 if (netif_msg_intr(gp))
465 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
466 gp->dev->name, rxmac_stat);
467
468 if (rxmac_stat & MAC_RXSTAT_OFLW) {
469 u32 smac = readl(gp->regs + MAC_SMACHINE);
470
471 netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);
472 dev->stats.rx_over_errors++;
473 dev->stats.rx_fifo_errors++;
474
475 ret = gem_rxmac_reset(gp);
476 }
477
478 if (rxmac_stat & MAC_RXSTAT_ACE)
479 dev->stats.rx_frame_errors += 0x10000;
480
481 if (rxmac_stat & MAC_RXSTAT_CCE)
482 dev->stats.rx_crc_errors += 0x10000;
483
484 if (rxmac_stat & MAC_RXSTAT_LCE)
485 dev->stats.rx_length_errors += 0x10000;
486
487 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
488 * events.
489 */
490 return ret;
491 }
492
493 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
494 {
495 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
496
497 if (netif_msg_intr(gp))
498 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
499 gp->dev->name, mac_cstat);
500
501 /* This interrupt is just for pause frame and pause
502 * tracking. It is useful for diagnostics and debug
503 * but probably by default we will mask these events.
504 */
505 if (mac_cstat & MAC_CSTAT_PS)
506 gp->pause_entered++;
507
508 if (mac_cstat & MAC_CSTAT_PRCV)
509 gp->pause_last_time_recvd = (mac_cstat >> 16);
510
511 return 0;
512 }
513
514 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
515 {
516 u32 mif_status = readl(gp->regs + MIF_STATUS);
517 u32 reg_val, changed_bits;
518
519 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
520 changed_bits = (mif_status & MIF_STATUS_STAT);
521
522 gem_handle_mif_event(gp, reg_val, changed_bits);
523
524 return 0;
525 }
526
527 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
528 {
529 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
530
531 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
532 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
533 netdev_err(dev, "PCI error [%04x]", pci_estat);
534
535 if (pci_estat & GREG_PCIESTAT_BADACK)
536 pr_cont(" <No ACK64# during ABS64 cycle>");
537 if (pci_estat & GREG_PCIESTAT_DTRTO)
538 pr_cont(" <Delayed transaction timeout>");
539 if (pci_estat & GREG_PCIESTAT_OTHER)
540 pr_cont(" <other>");
541 pr_cont("\n");
542 } else {
543 pci_estat |= GREG_PCIESTAT_OTHER;
544 netdev_err(dev, "PCI error\n");
545 }
546
547 if (pci_estat & GREG_PCIESTAT_OTHER) {
548 u16 pci_cfg_stat;
549
550 /* Interrogate PCI config space for the
551 * true cause.
552 */
553 pci_read_config_word(gp->pdev, PCI_STATUS,
554 &pci_cfg_stat);
555 netdev_err(dev, "Read PCI cfg space status [%04x]\n",
556 pci_cfg_stat);
557 if (pci_cfg_stat & PCI_STATUS_PARITY)
558 netdev_err(dev, "PCI parity error detected\n");
559 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
560 netdev_err(dev, "PCI target abort\n");
561 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
562 netdev_err(dev, "PCI master acks target abort\n");
563 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
564 netdev_err(dev, "PCI master abort\n");
565 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
566 netdev_err(dev, "PCI system error SERR#\n");
567 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
568 netdev_err(dev, "PCI parity error\n");
569
570 /* Write the error bits back to clear them. */
571 pci_cfg_stat &= (PCI_STATUS_PARITY |
572 PCI_STATUS_SIG_TARGET_ABORT |
573 PCI_STATUS_REC_TARGET_ABORT |
574 PCI_STATUS_REC_MASTER_ABORT |
575 PCI_STATUS_SIG_SYSTEM_ERROR |
576 PCI_STATUS_DETECTED_PARITY);
577 pci_write_config_word(gp->pdev,
578 PCI_STATUS, pci_cfg_stat);
579 }
580
581 /* For all PCI errors, we should reset the chip. */
582 return 1;
583 }
584
585 /* All non-normal interrupt conditions get serviced here.
586 * Returns non-zero if we should just exit the interrupt
587 * handler right now (ie. if we reset the card which invalidates
588 * all of the other original irq status bits).
589 */
590 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
591 {
592 if (gem_status & GREG_STAT_RXNOBUF) {
593 /* Frame arrived, no free RX buffers available. */
594 if (netif_msg_rx_err(gp))
595 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
596 gp->dev->name);
597 dev->stats.rx_dropped++;
598 }
599
600 if (gem_status & GREG_STAT_RXTAGERR) {
601 /* corrupt RX tag framing */
602 if (netif_msg_rx_err(gp))
603 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
604 gp->dev->name);
605 dev->stats.rx_errors++;
606
607 return 1;
608 }
609
610 if (gem_status & GREG_STAT_PCS) {
611 if (gem_pcs_interrupt(dev, gp, gem_status))
612 return 1;
613 }
614
615 if (gem_status & GREG_STAT_TXMAC) {
616 if (gem_txmac_interrupt(dev, gp, gem_status))
617 return 1;
618 }
619
620 if (gem_status & GREG_STAT_RXMAC) {
621 if (gem_rxmac_interrupt(dev, gp, gem_status))
622 return 1;
623 }
624
625 if (gem_status & GREG_STAT_MAC) {
626 if (gem_mac_interrupt(dev, gp, gem_status))
627 return 1;
628 }
629
630 if (gem_status & GREG_STAT_MIF) {
631 if (gem_mif_interrupt(dev, gp, gem_status))
632 return 1;
633 }
634
635 if (gem_status & GREG_STAT_PCIERR) {
636 if (gem_pci_interrupt(dev, gp, gem_status))
637 return 1;
638 }
639
640 return 0;
641 }
642
643 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
644 {
645 int entry, limit;
646
647 entry = gp->tx_old;
648 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
649 while (entry != limit) {
650 struct sk_buff *skb;
651 struct gem_txd *txd;
652 dma_addr_t dma_addr;
653 u32 dma_len;
654 int frag;
655
656 if (netif_msg_tx_done(gp))
657 printk(KERN_DEBUG "%s: tx done, slot %d\n",
658 gp->dev->name, entry);
659 skb = gp->tx_skbs[entry];
660 if (skb_shinfo(skb)->nr_frags) {
661 int last = entry + skb_shinfo(skb)->nr_frags;
662 int walk = entry;
663 int incomplete = 0;
664
665 last &= (TX_RING_SIZE - 1);
666 for (;;) {
667 walk = NEXT_TX(walk);
668 if (walk == limit)
669 incomplete = 1;
670 if (walk == last)
671 break;
672 }
673 if (incomplete)
674 break;
675 }
676 gp->tx_skbs[entry] = NULL;
677 dev->stats.tx_bytes += skb->len;
678
679 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
680 txd = &gp->init_block->txd[entry];
681
682 dma_addr = le64_to_cpu(txd->buffer);
683 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
684
685 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
686 entry = NEXT_TX(entry);
687 }
688
689 dev->stats.tx_packets++;
690 dev_consume_skb_any(skb);
691 }
692 gp->tx_old = entry;
693
694 /* Need to make the tx_old update visible to gem_start_xmit()
695 * before checking for netif_queue_stopped(). Without the
696 * memory barrier, there is a small possibility that gem_start_xmit()
697 * will miss it and cause the queue to be stopped forever.
698 */
699 smp_mb();
700
701 if (unlikely(netif_queue_stopped(dev) &&
702 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) {
703 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
704
705 __netif_tx_lock(txq, smp_processor_id());
706 if (netif_queue_stopped(dev) &&
707 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
708 netif_wake_queue(dev);
709 __netif_tx_unlock(txq);
710 }
711 }
712
713 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
714 {
715 int cluster_start, curr, count, kick;
716
717 cluster_start = curr = (gp->rx_new & ~(4 - 1));
718 count = 0;
719 kick = -1;
720 dma_wmb();
721 while (curr != limit) {
722 curr = NEXT_RX(curr);
723 if (++count == 4) {
724 struct gem_rxd *rxd =
725 &gp->init_block->rxd[cluster_start];
726 for (;;) {
727 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
728 rxd++;
729 cluster_start = NEXT_RX(cluster_start);
730 if (cluster_start == curr)
731 break;
732 }
733 kick = curr;
734 count = 0;
735 }
736 }
737 if (kick >= 0) {
738 mb();
739 writel(kick, gp->regs + RXDMA_KICK);
740 }
741 }
742
743 #define ALIGNED_RX_SKB_ADDR(addr) \
744 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
745 static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size,
746 gfp_t gfp_flags)
747 {
748 struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);
749
750 if (likely(skb)) {
751 unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data);
752 skb_reserve(skb, offset);
753 }
754 return skb;
755 }
756
757 static int gem_rx(struct gem *gp, int work_to_do)
758 {
759 struct net_device *dev = gp->dev;
760 int entry, drops, work_done = 0;
761 u32 done;
762 __sum16 csum;
763
764 if (netif_msg_rx_status(gp))
765 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
766 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
767
768 entry = gp->rx_new;
769 drops = 0;
770 done = readl(gp->regs + RXDMA_DONE);
771 for (;;) {
772 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
773 struct sk_buff *skb;
774 u64 status = le64_to_cpu(rxd->status_word);
775 dma_addr_t dma_addr;
776 int len;
777
778 if ((status & RXDCTRL_OWN) != 0)
779 break;
780
781 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
782 break;
783
784 /* When writing back RX descriptor, GEM writes status
785 * then buffer address, possibly in separate transactions.
786 * If we don't wait for the chip to write both, we could
787 * post a new buffer to this descriptor then have GEM spam
788 * on the buffer address. We sync on the RX completion
789 * register to prevent this from happening.
790 */
791 if (entry == done) {
792 done = readl(gp->regs + RXDMA_DONE);
793 if (entry == done)
794 break;
795 }
796
797 /* We can now account for the work we're about to do */
798 work_done++;
799
800 skb = gp->rx_skbs[entry];
801
802 len = (status & RXDCTRL_BUFSZ) >> 16;
803 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
804 dev->stats.rx_errors++;
805 if (len < ETH_ZLEN)
806 dev->stats.rx_length_errors++;
807 if (len & RXDCTRL_BAD)
808 dev->stats.rx_crc_errors++;
809
810 /* We'll just return it to GEM. */
811 drop_it:
812 dev->stats.rx_dropped++;
813 goto next;
814 }
815
816 dma_addr = le64_to_cpu(rxd->buffer);
817 if (len > RX_COPY_THRESHOLD) {
818 struct sk_buff *new_skb;
819
820 new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
821 if (new_skb == NULL) {
822 drops++;
823 goto drop_it;
824 }
825 pci_unmap_page(gp->pdev, dma_addr,
826 RX_BUF_ALLOC_SIZE(gp),
827 PCI_DMA_FROMDEVICE);
828 gp->rx_skbs[entry] = new_skb;
829 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
830 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
831 virt_to_page(new_skb->data),
832 offset_in_page(new_skb->data),
833 RX_BUF_ALLOC_SIZE(gp),
834 PCI_DMA_FROMDEVICE));
835 skb_reserve(new_skb, RX_OFFSET);
836
837 /* Trim the original skb for the netif. */
838 skb_trim(skb, len);
839 } else {
840 struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);
841
842 if (copy_skb == NULL) {
843 drops++;
844 goto drop_it;
845 }
846
847 skb_reserve(copy_skb, 2);
848 skb_put(copy_skb, len);
849 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
850 skb_copy_from_linear_data(skb, copy_skb->data, len);
851 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
852
853 /* We'll reuse the original ring buffer. */
854 skb = copy_skb;
855 }
856
857 csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
858 skb->csum = csum_unfold(csum);
859 skb->ip_summed = CHECKSUM_COMPLETE;
860 skb->protocol = eth_type_trans(skb, gp->dev);
861
862 napi_gro_receive(&gp->napi, skb);
863
864 dev->stats.rx_packets++;
865 dev->stats.rx_bytes += len;
866
867 next:
868 entry = NEXT_RX(entry);
869 }
870
871 gem_post_rxds(gp, entry);
872
873 gp->rx_new = entry;
874
875 if (drops)
876 netdev_info(gp->dev, "Memory squeeze, deferring packet\n");
877
878 return work_done;
879 }
880
881 static int gem_poll(struct napi_struct *napi, int budget)
882 {
883 struct gem *gp = container_of(napi, struct gem, napi);
884 struct net_device *dev = gp->dev;
885 int work_done;
886
887 work_done = 0;
888 do {
889 /* Handle anomalies */
890 if (unlikely(gp->status & GREG_STAT_ABNORMAL)) {
891 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
892 int reset;
893
894 /* We run the abnormal interrupt handling code with
895 * the Tx lock. It only resets the Rx portion of the
896 * chip, but we need to guard it against DMA being
897 * restarted by the link poll timer
898 */
899 __netif_tx_lock(txq, smp_processor_id());
900 reset = gem_abnormal_irq(dev, gp, gp->status);
901 __netif_tx_unlock(txq);
902 if (reset) {
903 gem_schedule_reset(gp);
904 napi_complete(napi);
905 return work_done;
906 }
907 }
908
909 /* Run TX completion thread */
910 gem_tx(dev, gp, gp->status);
911
912 /* Run RX thread. We don't use any locking here,
913 * code willing to do bad things - like cleaning the
914 * rx ring - must call napi_disable(), which
915 * schedule_timeout()'s if polling is already disabled.
916 */
917 work_done += gem_rx(gp, budget - work_done);
918
919 if (work_done >= budget)
920 return work_done;
921
922 gp->status = readl(gp->regs + GREG_STAT);
923 } while (gp->status & GREG_STAT_NAPI);
924
925 napi_complete_done(napi, work_done);
926 gem_enable_ints(gp);
927
928 return work_done;
929 }
930
931 static irqreturn_t gem_interrupt(int irq, void *dev_id)
932 {
933 struct net_device *dev = dev_id;
934 struct gem *gp = netdev_priv(dev);
935
936 if (napi_schedule_prep(&gp->napi)) {
937 u32 gem_status = readl(gp->regs + GREG_STAT);
938
939 if (unlikely(gem_status == 0)) {
940 napi_enable(&gp->napi);
941 return IRQ_NONE;
942 }
943 if (netif_msg_intr(gp))
944 printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n",
945 gp->dev->name, gem_status);
946
947 gp->status = gem_status;
948 gem_disable_ints(gp);
949 __napi_schedule(&gp->napi);
950 }
951
952 /* If polling was disabled at the time we received that
953 * interrupt, we may return IRQ_HANDLED here while we
954 * should return IRQ_NONE. No big deal...
955 */
956 return IRQ_HANDLED;
957 }
958
959 #ifdef CONFIG_NET_POLL_CONTROLLER
960 static void gem_poll_controller(struct net_device *dev)
961 {
962 struct gem *gp = netdev_priv(dev);
963
964 disable_irq(gp->pdev->irq);
965 gem_interrupt(gp->pdev->irq, dev);
966 enable_irq(gp->pdev->irq);
967 }
968 #endif
969
970 static void gem_tx_timeout(struct net_device *dev)
971 {
972 struct gem *gp = netdev_priv(dev);
973
974 netdev_err(dev, "transmit timed out, resetting\n");
975
976 netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",
977 readl(gp->regs + TXDMA_CFG),
978 readl(gp->regs + MAC_TXSTAT),
979 readl(gp->regs + MAC_TXCFG));
980 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
981 readl(gp->regs + RXDMA_CFG),
982 readl(gp->regs + MAC_RXSTAT),
983 readl(gp->regs + MAC_RXCFG));
984
985 gem_schedule_reset(gp);
986 }
987
988 static __inline__ int gem_intme(int entry)
989 {
990 /* Algorithm: IRQ every 1/2 of descriptors. */
991 if (!(entry & ((TX_RING_SIZE>>1)-1)))
992 return 1;
993
994 return 0;
995 }
996
997 static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
998 struct net_device *dev)
999 {
1000 struct gem *gp = netdev_priv(dev);
1001 int entry;
1002 u64 ctrl;
1003
1004 ctrl = 0;
1005 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1006 const u64 csum_start_off = skb_checksum_start_offset(skb);
1007 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1008
1009 ctrl = (TXDCTRL_CENAB |
1010 (csum_start_off << 15) |
1011 (csum_stuff_off << 21));
1012 }
1013
1014 if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1015 /* This is a hard error, log it. */
1016 if (!netif_queue_stopped(dev)) {
1017 netif_stop_queue(dev);
1018 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
1019 }
1020 return NETDEV_TX_BUSY;
1021 }
1022
1023 entry = gp->tx_new;
1024 gp->tx_skbs[entry] = skb;
1025
1026 if (skb_shinfo(skb)->nr_frags == 0) {
1027 struct gem_txd *txd = &gp->init_block->txd[entry];
1028 dma_addr_t mapping;
1029 u32 len;
1030
1031 len = skb->len;
1032 mapping = pci_map_page(gp->pdev,
1033 virt_to_page(skb->data),
1034 offset_in_page(skb->data),
1035 len, PCI_DMA_TODEVICE);
1036 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1037 if (gem_intme(entry))
1038 ctrl |= TXDCTRL_INTME;
1039 txd->buffer = cpu_to_le64(mapping);
1040 dma_wmb();
1041 txd->control_word = cpu_to_le64(ctrl);
1042 entry = NEXT_TX(entry);
1043 } else {
1044 struct gem_txd *txd;
1045 u32 first_len;
1046 u64 intme;
1047 dma_addr_t first_mapping;
1048 int frag, first_entry = entry;
1049
1050 intme = 0;
1051 if (gem_intme(entry))
1052 intme |= TXDCTRL_INTME;
1053
1054 /* We must give this initial chunk to the device last.
1055 * Otherwise we could race with the device.
1056 */
1057 first_len = skb_headlen(skb);
1058 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1059 offset_in_page(skb->data),
1060 first_len, PCI_DMA_TODEVICE);
1061 entry = NEXT_TX(entry);
1062
1063 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1064 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1065 u32 len;
1066 dma_addr_t mapping;
1067 u64 this_ctrl;
1068
1069 len = skb_frag_size(this_frag);
1070 mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag,
1071 0, len, DMA_TO_DEVICE);
1072 this_ctrl = ctrl;
1073 if (frag == skb_shinfo(skb)->nr_frags - 1)
1074 this_ctrl |= TXDCTRL_EOF;
1075
1076 txd = &gp->init_block->txd[entry];
1077 txd->buffer = cpu_to_le64(mapping);
1078 dma_wmb();
1079 txd->control_word = cpu_to_le64(this_ctrl | len);
1080
1081 if (gem_intme(entry))
1082 intme |= TXDCTRL_INTME;
1083
1084 entry = NEXT_TX(entry);
1085 }
1086 txd = &gp->init_block->txd[first_entry];
1087 txd->buffer = cpu_to_le64(first_mapping);
1088 dma_wmb();
1089 txd->control_word =
1090 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1091 }
1092
1093 gp->tx_new = entry;
1094 if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) {
1095 netif_stop_queue(dev);
1096
1097 /* netif_stop_queue() must be done before checking
1098 * checking tx index in TX_BUFFS_AVAIL() below, because
1099 * in gem_tx(), we update tx_old before checking for
1100 * netif_queue_stopped().
1101 */
1102 smp_mb();
1103 if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
1104 netif_wake_queue(dev);
1105 }
1106 if (netif_msg_tx_queued(gp))
1107 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1108 dev->name, entry, skb->len);
1109 mb();
1110 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1111
1112 return NETDEV_TX_OK;
1113 }
1114
1115 static void gem_pcs_reset(struct gem *gp)
1116 {
1117 int limit;
1118 u32 val;
1119
1120 /* Reset PCS unit. */
1121 val = readl(gp->regs + PCS_MIICTRL);
1122 val |= PCS_MIICTRL_RST;
1123 writel(val, gp->regs + PCS_MIICTRL);
1124
1125 limit = 32;
1126 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1127 udelay(100);
1128 if (limit-- <= 0)
1129 break;
1130 }
1131 if (limit < 0)
1132 netdev_warn(gp->dev, "PCS reset bit would not clear\n");
1133 }
1134
1135 static void gem_pcs_reinit_adv(struct gem *gp)
1136 {
1137 u32 val;
1138
1139 /* Make sure PCS is disabled while changing advertisement
1140 * configuration.
1141 */
1142 val = readl(gp->regs + PCS_CFG);
1143 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1144 writel(val, gp->regs + PCS_CFG);
1145
1146 /* Advertise all capabilities except asymmetric
1147 * pause.
1148 */
1149 val = readl(gp->regs + PCS_MIIADV);
1150 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1151 PCS_MIIADV_SP | PCS_MIIADV_AP);
1152 writel(val, gp->regs + PCS_MIIADV);
1153
1154 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1155 * and re-enable PCS.
1156 */
1157 val = readl(gp->regs + PCS_MIICTRL);
1158 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1159 val &= ~PCS_MIICTRL_WB;
1160 writel(val, gp->regs + PCS_MIICTRL);
1161
1162 val = readl(gp->regs + PCS_CFG);
1163 val |= PCS_CFG_ENABLE;
1164 writel(val, gp->regs + PCS_CFG);
1165
1166 /* Make sure serialink loopback is off. The meaning
1167 * of this bit is logically inverted based upon whether
1168 * you are in Serialink or SERDES mode.
1169 */
1170 val = readl(gp->regs + PCS_SCTRL);
1171 if (gp->phy_type == phy_serialink)
1172 val &= ~PCS_SCTRL_LOOP;
1173 else
1174 val |= PCS_SCTRL_LOOP;
1175 writel(val, gp->regs + PCS_SCTRL);
1176 }
1177
1178 #define STOP_TRIES 32
1179
1180 static void gem_reset(struct gem *gp)
1181 {
1182 int limit;
1183 u32 val;
1184
1185 /* Make sure we won't get any more interrupts */
1186 writel(0xffffffff, gp->regs + GREG_IMASK);
1187
1188 /* Reset the chip */
1189 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1190 gp->regs + GREG_SWRST);
1191
1192 limit = STOP_TRIES;
1193
1194 do {
1195 udelay(20);
1196 val = readl(gp->regs + GREG_SWRST);
1197 if (limit-- <= 0)
1198 break;
1199 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1200
1201 if (limit < 0)
1202 netdev_err(gp->dev, "SW reset is ghetto\n");
1203
1204 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1205 gem_pcs_reinit_adv(gp);
1206 }
1207
1208 static void gem_start_dma(struct gem *gp)
1209 {
1210 u32 val;
1211
1212 /* We are ready to rock, turn everything on. */
1213 val = readl(gp->regs + TXDMA_CFG);
1214 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1215 val = readl(gp->regs + RXDMA_CFG);
1216 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1217 val = readl(gp->regs + MAC_TXCFG);
1218 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1219 val = readl(gp->regs + MAC_RXCFG);
1220 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1221
1222 (void) readl(gp->regs + MAC_RXCFG);
1223 udelay(100);
1224
1225 gem_enable_ints(gp);
1226
1227 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1228 }
1229
1230 /* DMA won't be actually stopped before about 4ms tho ...
1231 */
1232 static void gem_stop_dma(struct gem *gp)
1233 {
1234 u32 val;
1235
1236 /* We are done rocking, turn everything off. */
1237 val = readl(gp->regs + TXDMA_CFG);
1238 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1239 val = readl(gp->regs + RXDMA_CFG);
1240 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1241 val = readl(gp->regs + MAC_TXCFG);
1242 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1243 val = readl(gp->regs + MAC_RXCFG);
1244 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1245
1246 (void) readl(gp->regs + MAC_RXCFG);
1247
1248 /* Need to wait a bit ... done by the caller */
1249 }
1250
1251
1252 // XXX dbl check what that function should do when called on PCS PHY
1253 static void gem_begin_auto_negotiation(struct gem *gp,
1254 const struct ethtool_link_ksettings *ep)
1255 {
1256 u32 advertise, features;
1257 int autoneg;
1258 int speed;
1259 int duplex;
1260 u32 advertising;
1261
1262 if (ep)
1263 ethtool_convert_link_mode_to_legacy_u32(
1264 &advertising, ep->link_modes.advertising);
1265
1266 if (gp->phy_type != phy_mii_mdio0 &&
1267 gp->phy_type != phy_mii_mdio1)
1268 goto non_mii;
1269
1270 /* Setup advertise */
1271 if (found_mii_phy(gp))
1272 features = gp->phy_mii.def->features;
1273 else
1274 features = 0;
1275
1276 advertise = features & ADVERTISE_MASK;
1277 if (gp->phy_mii.advertising != 0)
1278 advertise &= gp->phy_mii.advertising;
1279
1280 autoneg = gp->want_autoneg;
1281 speed = gp->phy_mii.speed;
1282 duplex = gp->phy_mii.duplex;
1283
1284 /* Setup link parameters */
1285 if (!ep)
1286 goto start_aneg;
1287 if (ep->base.autoneg == AUTONEG_ENABLE) {
1288 advertise = advertising;
1289 autoneg = 1;
1290 } else {
1291 autoneg = 0;
1292 speed = ep->base.speed;
1293 duplex = ep->base.duplex;
1294 }
1295
1296 start_aneg:
1297 /* Sanitize settings based on PHY capabilities */
1298 if ((features & SUPPORTED_Autoneg) == 0)
1299 autoneg = 0;
1300 if (speed == SPEED_1000 &&
1301 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1302 speed = SPEED_100;
1303 if (speed == SPEED_100 &&
1304 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1305 speed = SPEED_10;
1306 if (duplex == DUPLEX_FULL &&
1307 !(features & (SUPPORTED_1000baseT_Full |
1308 SUPPORTED_100baseT_Full |
1309 SUPPORTED_10baseT_Full)))
1310 duplex = DUPLEX_HALF;
1311 if (speed == 0)
1312 speed = SPEED_10;
1313
1314 /* If we are asleep, we don't try to actually setup the PHY, we
1315 * just store the settings
1316 */
1317 if (!netif_device_present(gp->dev)) {
1318 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1319 gp->phy_mii.speed = speed;
1320 gp->phy_mii.duplex = duplex;
1321 return;
1322 }
1323
1324 /* Configure PHY & start aneg */
1325 gp->want_autoneg = autoneg;
1326 if (autoneg) {
1327 if (found_mii_phy(gp))
1328 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1329 gp->lstate = link_aneg;
1330 } else {
1331 if (found_mii_phy(gp))
1332 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1333 gp->lstate = link_force_ok;
1334 }
1335
1336 non_mii:
1337 gp->timer_ticks = 0;
1338 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1339 }
1340
1341 /* A link-up condition has occurred, initialize and enable the
1342 * rest of the chip.
1343 */
1344 static int gem_set_link_modes(struct gem *gp)
1345 {
1346 struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0);
1347 int full_duplex, speed, pause;
1348 u32 val;
1349
1350 full_duplex = 0;
1351 speed = SPEED_10;
1352 pause = 0;
1353
1354 if (found_mii_phy(gp)) {
1355 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1356 return 1;
1357 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1358 speed = gp->phy_mii.speed;
1359 pause = gp->phy_mii.pause;
1360 } else if (gp->phy_type == phy_serialink ||
1361 gp->phy_type == phy_serdes) {
1362 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1363
1364 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1365 full_duplex = 1;
1366 speed = SPEED_1000;
1367 }
1368
1369 netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",
1370 speed, (full_duplex ? "full" : "half"));
1371
1372
1373 /* We take the tx queue lock to avoid collisions between
1374 * this code, the tx path and the NAPI-driven error path
1375 */
1376 __netif_tx_lock(txq, smp_processor_id());
1377
1378 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1379 if (full_duplex) {
1380 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1381 } else {
1382 /* MAC_TXCFG_NBO must be zero. */
1383 }
1384 writel(val, gp->regs + MAC_TXCFG);
1385
1386 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1387 if (!full_duplex &&
1388 (gp->phy_type == phy_mii_mdio0 ||
1389 gp->phy_type == phy_mii_mdio1)) {
1390 val |= MAC_XIFCFG_DISE;
1391 } else if (full_duplex) {
1392 val |= MAC_XIFCFG_FLED;
1393 }
1394
1395 if (speed == SPEED_1000)
1396 val |= (MAC_XIFCFG_GMII);
1397
1398 writel(val, gp->regs + MAC_XIFCFG);
1399
1400 /* If gigabit and half-duplex, enable carrier extension
1401 * mode. Else, disable it.
1402 */
1403 if (speed == SPEED_1000 && !full_duplex) {
1404 val = readl(gp->regs + MAC_TXCFG);
1405 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1406
1407 val = readl(gp->regs + MAC_RXCFG);
1408 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1409 } else {
1410 val = readl(gp->regs + MAC_TXCFG);
1411 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1412
1413 val = readl(gp->regs + MAC_RXCFG);
1414 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1415 }
1416
1417 if (gp->phy_type == phy_serialink ||
1418 gp->phy_type == phy_serdes) {
1419 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1420
1421 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1422 pause = 1;
1423 }
1424
1425 if (!full_duplex)
1426 writel(512, gp->regs + MAC_STIME);
1427 else
1428 writel(64, gp->regs + MAC_STIME);
1429 val = readl(gp->regs + MAC_MCCFG);
1430 if (pause)
1431 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1432 else
1433 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1434 writel(val, gp->regs + MAC_MCCFG);
1435
1436 gem_start_dma(gp);
1437
1438 __netif_tx_unlock(txq);
1439
1440 if (netif_msg_link(gp)) {
1441 if (pause) {
1442 netdev_info(gp->dev,
1443 "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
1444 gp->rx_fifo_sz,
1445 gp->rx_pause_off,
1446 gp->rx_pause_on);
1447 } else {
1448 netdev_info(gp->dev, "Pause is disabled\n");
1449 }
1450 }
1451
1452 return 0;
1453 }
1454
1455 static int gem_mdio_link_not_up(struct gem *gp)
1456 {
1457 switch (gp->lstate) {
1458 case link_force_ret:
1459 netif_info(gp, link, gp->dev,
1460 "Autoneg failed again, keeping forced mode\n");
1461 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1462 gp->last_forced_speed, DUPLEX_HALF);
1463 gp->timer_ticks = 5;
1464 gp->lstate = link_force_ok;
1465 return 0;
1466 case link_aneg:
1467 /* We try forced modes after a failed aneg only on PHYs that don't
1468 * have "magic_aneg" bit set, which means they internally do the
1469 * while forced-mode thingy. On these, we just restart aneg
1470 */
1471 if (gp->phy_mii.def->magic_aneg)
1472 return 1;
1473 netif_info(gp, link, gp->dev, "switching to forced 100bt\n");
1474 /* Try forced modes. */
1475 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1476 DUPLEX_HALF);
1477 gp->timer_ticks = 5;
1478 gp->lstate = link_force_try;
1479 return 0;
1480 case link_force_try:
1481 /* Downgrade from 100 to 10 Mbps if necessary.
1482 * If already at 10Mbps, warn user about the
1483 * situation every 10 ticks.
1484 */
1485 if (gp->phy_mii.speed == SPEED_100) {
1486 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1487 DUPLEX_HALF);
1488 gp->timer_ticks = 5;
1489 netif_info(gp, link, gp->dev,
1490 "switching to forced 10bt\n");
1491 return 0;
1492 } else
1493 return 1;
1494 default:
1495 return 0;
1496 }
1497 }
1498
1499 static void gem_link_timer(struct timer_list *t)
1500 {
1501 struct gem *gp = from_timer(gp, t, link_timer);
1502 struct net_device *dev = gp->dev;
1503 int restart_aneg = 0;
1504
1505 /* There's no point doing anything if we're going to be reset */
1506 if (gp->reset_task_pending)
1507 return;
1508
1509 if (gp->phy_type == phy_serialink ||
1510 gp->phy_type == phy_serdes) {
1511 u32 val = readl(gp->regs + PCS_MIISTAT);
1512
1513 if (!(val & PCS_MIISTAT_LS))
1514 val = readl(gp->regs + PCS_MIISTAT);
1515
1516 if ((val & PCS_MIISTAT_LS) != 0) {
1517 if (gp->lstate == link_up)
1518 goto restart;
1519
1520 gp->lstate = link_up;
1521 netif_carrier_on(dev);
1522 (void)gem_set_link_modes(gp);
1523 }
1524 goto restart;
1525 }
1526 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1527 /* Ok, here we got a link. If we had it due to a forced
1528 * fallback, and we were configured for autoneg, we do
1529 * retry a short autoneg pass. If you know your hub is
1530 * broken, use ethtool ;)
1531 */
1532 if (gp->lstate == link_force_try && gp->want_autoneg) {
1533 gp->lstate = link_force_ret;
1534 gp->last_forced_speed = gp->phy_mii.speed;
1535 gp->timer_ticks = 5;
1536 if (netif_msg_link(gp))
1537 netdev_info(dev,
1538 "Got link after fallback, retrying autoneg once...\n");
1539 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1540 } else if (gp->lstate != link_up) {
1541 gp->lstate = link_up;
1542 netif_carrier_on(dev);
1543 if (gem_set_link_modes(gp))
1544 restart_aneg = 1;
1545 }
1546 } else {
1547 /* If the link was previously up, we restart the
1548 * whole process
1549 */
1550 if (gp->lstate == link_up) {
1551 gp->lstate = link_down;
1552 netif_info(gp, link, dev, "Link down\n");
1553 netif_carrier_off(dev);
1554 gem_schedule_reset(gp);
1555 /* The reset task will restart the timer */
1556 return;
1557 } else if (++gp->timer_ticks > 10) {
1558 if (found_mii_phy(gp))
1559 restart_aneg = gem_mdio_link_not_up(gp);
1560 else
1561 restart_aneg = 1;
1562 }
1563 }
1564 if (restart_aneg) {
1565 gem_begin_auto_negotiation(gp, NULL);
1566 return;
1567 }
1568 restart:
1569 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1570 }
1571
1572 static void gem_clean_rings(struct gem *gp)
1573 {
1574 struct gem_init_block *gb = gp->init_block;
1575 struct sk_buff *skb;
1576 int i;
1577 dma_addr_t dma_addr;
1578
1579 for (i = 0; i < RX_RING_SIZE; i++) {
1580 struct gem_rxd *rxd;
1581
1582 rxd = &gb->rxd[i];
1583 if (gp->rx_skbs[i] != NULL) {
1584 skb = gp->rx_skbs[i];
1585 dma_addr = le64_to_cpu(rxd->buffer);
1586 pci_unmap_page(gp->pdev, dma_addr,
1587 RX_BUF_ALLOC_SIZE(gp),
1588 PCI_DMA_FROMDEVICE);
1589 dev_kfree_skb_any(skb);
1590 gp->rx_skbs[i] = NULL;
1591 }
1592 rxd->status_word = 0;
1593 dma_wmb();
1594 rxd->buffer = 0;
1595 }
1596
1597 for (i = 0; i < TX_RING_SIZE; i++) {
1598 if (gp->tx_skbs[i] != NULL) {
1599 struct gem_txd *txd;
1600 int frag;
1601
1602 skb = gp->tx_skbs[i];
1603 gp->tx_skbs[i] = NULL;
1604
1605 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1606 int ent = i & (TX_RING_SIZE - 1);
1607
1608 txd = &gb->txd[ent];
1609 dma_addr = le64_to_cpu(txd->buffer);
1610 pci_unmap_page(gp->pdev, dma_addr,
1611 le64_to_cpu(txd->control_word) &
1612 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1613
1614 if (frag != skb_shinfo(skb)->nr_frags)
1615 i++;
1616 }
1617 dev_kfree_skb_any(skb);
1618 }
1619 }
1620 }
1621
1622 static void gem_init_rings(struct gem *gp)
1623 {
1624 struct gem_init_block *gb = gp->init_block;
1625 struct net_device *dev = gp->dev;
1626 int i;
1627 dma_addr_t dma_addr;
1628
1629 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1630
1631 gem_clean_rings(gp);
1632
1633 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1634 (unsigned)VLAN_ETH_FRAME_LEN);
1635
1636 for (i = 0; i < RX_RING_SIZE; i++) {
1637 struct sk_buff *skb;
1638 struct gem_rxd *rxd = &gb->rxd[i];
1639
1640 skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL);
1641 if (!skb) {
1642 rxd->buffer = 0;
1643 rxd->status_word = 0;
1644 continue;
1645 }
1646
1647 gp->rx_skbs[i] = skb;
1648 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1649 dma_addr = pci_map_page(gp->pdev,
1650 virt_to_page(skb->data),
1651 offset_in_page(skb->data),
1652 RX_BUF_ALLOC_SIZE(gp),
1653 PCI_DMA_FROMDEVICE);
1654 rxd->buffer = cpu_to_le64(dma_addr);
1655 dma_wmb();
1656 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1657 skb_reserve(skb, RX_OFFSET);
1658 }
1659
1660 for (i = 0; i < TX_RING_SIZE; i++) {
1661 struct gem_txd *txd = &gb->txd[i];
1662
1663 txd->control_word = 0;
1664 dma_wmb();
1665 txd->buffer = 0;
1666 }
1667 wmb();
1668 }
1669
1670 /* Init PHY interface and start link poll state machine */
1671 static void gem_init_phy(struct gem *gp)
1672 {
1673 u32 mifcfg;
1674
1675 /* Revert MIF CFG setting done on stop_phy */
1676 mifcfg = readl(gp->regs + MIF_CFG);
1677 mifcfg &= ~MIF_CFG_BBMODE;
1678 writel(mifcfg, gp->regs + MIF_CFG);
1679
1680 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1681 int i;
1682
1683 /* Those delay sucks, the HW seem to love them though, I'll
1684 * serisouly consider breaking some locks here to be able
1685 * to schedule instead
1686 */
1687 for (i = 0; i < 3; i++) {
1688 #ifdef CONFIG_PPC_PMAC
1689 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1690 msleep(20);
1691 #endif
1692 /* Some PHYs used by apple have problem getting back to us,
1693 * we do an additional reset here
1694 */
1695 sungem_phy_write(gp, MII_BMCR, BMCR_RESET);
1696 msleep(20);
1697 if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
1698 break;
1699 if (i == 2)
1700 netdev_warn(gp->dev, "GMAC PHY not responding !\n");
1701 }
1702 }
1703
1704 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1705 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1706 u32 val;
1707
1708 /* Init datapath mode register. */
1709 if (gp->phy_type == phy_mii_mdio0 ||
1710 gp->phy_type == phy_mii_mdio1) {
1711 val = PCS_DMODE_MGM;
1712 } else if (gp->phy_type == phy_serialink) {
1713 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1714 } else {
1715 val = PCS_DMODE_ESM;
1716 }
1717
1718 writel(val, gp->regs + PCS_DMODE);
1719 }
1720
1721 if (gp->phy_type == phy_mii_mdio0 ||
1722 gp->phy_type == phy_mii_mdio1) {
1723 /* Reset and detect MII PHY */
1724 sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1725
1726 /* Init PHY */
1727 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1728 gp->phy_mii.def->ops->init(&gp->phy_mii);
1729 } else {
1730 gem_pcs_reset(gp);
1731 gem_pcs_reinit_adv(gp);
1732 }
1733
1734 /* Default aneg parameters */
1735 gp->timer_ticks = 0;
1736 gp->lstate = link_down;
1737 netif_carrier_off(gp->dev);
1738
1739 /* Print things out */
1740 if (gp->phy_type == phy_mii_mdio0 ||
1741 gp->phy_type == phy_mii_mdio1)
1742 netdev_info(gp->dev, "Found %s PHY\n",
1743 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
1744
1745 gem_begin_auto_negotiation(gp, NULL);
1746 }
1747
1748 static void gem_init_dma(struct gem *gp)
1749 {
1750 u64 desc_dma = (u64) gp->gblock_dvma;
1751 u32 val;
1752
1753 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1754 writel(val, gp->regs + TXDMA_CFG);
1755
1756 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1757 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1758 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1759
1760 writel(0, gp->regs + TXDMA_KICK);
1761
1762 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1763 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1764 writel(val, gp->regs + RXDMA_CFG);
1765
1766 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1767 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1768
1769 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1770
1771 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1772 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1773 writel(val, gp->regs + RXDMA_PTHRESH);
1774
1775 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1776 writel(((5 & RXDMA_BLANK_IPKTS) |
1777 ((8 << 12) & RXDMA_BLANK_ITIME)),
1778 gp->regs + RXDMA_BLANK);
1779 else
1780 writel(((5 & RXDMA_BLANK_IPKTS) |
1781 ((4 << 12) & RXDMA_BLANK_ITIME)),
1782 gp->regs + RXDMA_BLANK);
1783 }
1784
1785 static u32 gem_setup_multicast(struct gem *gp)
1786 {
1787 u32 rxcfg = 0;
1788 int i;
1789
1790 if ((gp->dev->flags & IFF_ALLMULTI) ||
1791 (netdev_mc_count(gp->dev) > 256)) {
1792 for (i=0; i<16; i++)
1793 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1794 rxcfg |= MAC_RXCFG_HFE;
1795 } else if (gp->dev->flags & IFF_PROMISC) {
1796 rxcfg |= MAC_RXCFG_PROM;
1797 } else {
1798 u16 hash_table[16];
1799 u32 crc;
1800 struct netdev_hw_addr *ha;
1801 int i;
1802
1803 memset(hash_table, 0, sizeof(hash_table));
1804 netdev_for_each_mc_addr(ha, gp->dev) {
1805 crc = ether_crc_le(6, ha->addr);
1806 crc >>= 24;
1807 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1808 }
1809 for (i=0; i<16; i++)
1810 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1811 rxcfg |= MAC_RXCFG_HFE;
1812 }
1813
1814 return rxcfg;
1815 }
1816
1817 static void gem_init_mac(struct gem *gp)
1818 {
1819 unsigned char *e = &gp->dev->dev_addr[0];
1820
1821 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1822
1823 writel(0x00, gp->regs + MAC_IPG0);
1824 writel(0x08, gp->regs + MAC_IPG1);
1825 writel(0x04, gp->regs + MAC_IPG2);
1826 writel(0x40, gp->regs + MAC_STIME);
1827 writel(0x40, gp->regs + MAC_MINFSZ);
1828
1829 /* Ethernet payload + header + FCS + optional VLAN tag. */
1830 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1831
1832 writel(0x07, gp->regs + MAC_PASIZE);
1833 writel(0x04, gp->regs + MAC_JAMSIZE);
1834 writel(0x10, gp->regs + MAC_ATTLIM);
1835 writel(0x8808, gp->regs + MAC_MCTYPE);
1836
1837 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1838
1839 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1840 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1841 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1842
1843 writel(0, gp->regs + MAC_ADDR3);
1844 writel(0, gp->regs + MAC_ADDR4);
1845 writel(0, gp->regs + MAC_ADDR5);
1846
1847 writel(0x0001, gp->regs + MAC_ADDR6);
1848 writel(0xc200, gp->regs + MAC_ADDR7);
1849 writel(0x0180, gp->regs + MAC_ADDR8);
1850
1851 writel(0, gp->regs + MAC_AFILT0);
1852 writel(0, gp->regs + MAC_AFILT1);
1853 writel(0, gp->regs + MAC_AFILT2);
1854 writel(0, gp->regs + MAC_AF21MSK);
1855 writel(0, gp->regs + MAC_AF0MSK);
1856
1857 gp->mac_rx_cfg = gem_setup_multicast(gp);
1858 #ifdef STRIP_FCS
1859 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1860 #endif
1861 writel(0, gp->regs + MAC_NCOLL);
1862 writel(0, gp->regs + MAC_FASUCC);
1863 writel(0, gp->regs + MAC_ECOLL);
1864 writel(0, gp->regs + MAC_LCOLL);
1865 writel(0, gp->regs + MAC_DTIMER);
1866 writel(0, gp->regs + MAC_PATMPS);
1867 writel(0, gp->regs + MAC_RFCTR);
1868 writel(0, gp->regs + MAC_LERR);
1869 writel(0, gp->regs + MAC_AERR);
1870 writel(0, gp->regs + MAC_FCSERR);
1871 writel(0, gp->regs + MAC_RXCVERR);
1872
1873 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1874 * them once a link is established.
1875 */
1876 writel(0, gp->regs + MAC_TXCFG);
1877 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1878 writel(0, gp->regs + MAC_MCCFG);
1879 writel(0, gp->regs + MAC_XIFCFG);
1880
1881 /* Setup MAC interrupts. We want to get all of the interesting
1882 * counter expiration events, but we do not want to hear about
1883 * normal rx/tx as the DMA engine tells us that.
1884 */
1885 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1886 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1887
1888 /* Don't enable even the PAUSE interrupts for now, we
1889 * make no use of those events other than to record them.
1890 */
1891 writel(0xffffffff, gp->regs + MAC_MCMASK);
1892
1893 /* Don't enable GEM's WOL in normal operations
1894 */
1895 if (gp->has_wol)
1896 writel(0, gp->regs + WOL_WAKECSR);
1897 }
1898
1899 static void gem_init_pause_thresholds(struct gem *gp)
1900 {
1901 u32 cfg;
1902
1903 /* Calculate pause thresholds. Setting the OFF threshold to the
1904 * full RX fifo size effectively disables PAUSE generation which
1905 * is what we do for 10/100 only GEMs which have FIFOs too small
1906 * to make real gains from PAUSE.
1907 */
1908 if (gp->rx_fifo_sz <= (2 * 1024)) {
1909 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1910 } else {
1911 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1912 int off = (gp->rx_fifo_sz - (max_frame * 2));
1913 int on = off - max_frame;
1914
1915 gp->rx_pause_off = off;
1916 gp->rx_pause_on = on;
1917 }
1918
1919
1920 /* Configure the chip "burst" DMA mode & enable some
1921 * HW bug fixes on Apple version
1922 */
1923 cfg = 0;
1924 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1925 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1926 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1927 cfg |= GREG_CFG_IBURST;
1928 #endif
1929 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1930 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1931 writel(cfg, gp->regs + GREG_CFG);
1932
1933 /* If Infinite Burst didn't stick, then use different
1934 * thresholds (and Apple bug fixes don't exist)
1935 */
1936 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1937 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1938 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1939 writel(cfg, gp->regs + GREG_CFG);
1940 }
1941 }
1942
1943 static int gem_check_invariants(struct gem *gp)
1944 {
1945 struct pci_dev *pdev = gp->pdev;
1946 u32 mif_cfg;
1947
1948 /* On Apple's sungem, we can't rely on registers as the chip
1949 * was been powered down by the firmware. The PHY is looked
1950 * up later on.
1951 */
1952 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1953 gp->phy_type = phy_mii_mdio0;
1954 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1955 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1956 gp->swrst_base = 0;
1957
1958 mif_cfg = readl(gp->regs + MIF_CFG);
1959 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
1960 mif_cfg |= MIF_CFG_MDI0;
1961 writel(mif_cfg, gp->regs + MIF_CFG);
1962 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1963 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1964
1965 /* We hard-code the PHY address so we can properly bring it out of
1966 * reset later on, we can't really probe it at this point, though
1967 * that isn't an issue.
1968 */
1969 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1970 gp->mii_phy_addr = 1;
1971 else
1972 gp->mii_phy_addr = 0;
1973
1974 return 0;
1975 }
1976
1977 mif_cfg = readl(gp->regs + MIF_CFG);
1978
1979 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1980 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1981 /* One of the MII PHYs _must_ be present
1982 * as this chip has no gigabit PHY.
1983 */
1984 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1985 pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1986 mif_cfg);
1987 return -1;
1988 }
1989 }
1990
1991 /* Determine initial PHY interface type guess. MDIO1 is the
1992 * external PHY and thus takes precedence over MDIO0.
1993 */
1994
1995 if (mif_cfg & MIF_CFG_MDI1) {
1996 gp->phy_type = phy_mii_mdio1;
1997 mif_cfg |= MIF_CFG_PSELECT;
1998 writel(mif_cfg, gp->regs + MIF_CFG);
1999 } else if (mif_cfg & MIF_CFG_MDI0) {
2000 gp->phy_type = phy_mii_mdio0;
2001 mif_cfg &= ~MIF_CFG_PSELECT;
2002 writel(mif_cfg, gp->regs + MIF_CFG);
2003 } else {
2004 #ifdef CONFIG_SPARC
2005 const char *p;
2006
2007 p = of_get_property(gp->of_node, "shared-pins", NULL);
2008 if (p && !strcmp(p, "serdes"))
2009 gp->phy_type = phy_serdes;
2010 else
2011 #endif
2012 gp->phy_type = phy_serialink;
2013 }
2014 if (gp->phy_type == phy_mii_mdio1 ||
2015 gp->phy_type == phy_mii_mdio0) {
2016 int i;
2017
2018 for (i = 0; i < 32; i++) {
2019 gp->mii_phy_addr = i;
2020 if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
2021 break;
2022 }
2023 if (i == 32) {
2024 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2025 pr_err("RIO MII phy will not respond\n");
2026 return -1;
2027 }
2028 gp->phy_type = phy_serdes;
2029 }
2030 }
2031
2032 /* Fetch the FIFO configurations now too. */
2033 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2034 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2035
2036 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2037 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2038 if (gp->tx_fifo_sz != (9 * 1024) ||
2039 gp->rx_fifo_sz != (20 * 1024)) {
2040 pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2041 gp->tx_fifo_sz, gp->rx_fifo_sz);
2042 return -1;
2043 }
2044 gp->swrst_base = 0;
2045 } else {
2046 if (gp->tx_fifo_sz != (2 * 1024) ||
2047 gp->rx_fifo_sz != (2 * 1024)) {
2048 pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2049 gp->tx_fifo_sz, gp->rx_fifo_sz);
2050 return -1;
2051 }
2052 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2053 }
2054 }
2055
2056 return 0;
2057 }
2058
2059 static void gem_reinit_chip(struct gem *gp)
2060 {
2061 /* Reset the chip */
2062 gem_reset(gp);
2063
2064 /* Make sure ints are disabled */
2065 gem_disable_ints(gp);
2066
2067 /* Allocate & setup ring buffers */
2068 gem_init_rings(gp);
2069
2070 /* Configure pause thresholds */
2071 gem_init_pause_thresholds(gp);
2072
2073 /* Init DMA & MAC engines */
2074 gem_init_dma(gp);
2075 gem_init_mac(gp);
2076 }
2077
2078
2079 static void gem_stop_phy(struct gem *gp, int wol)
2080 {
2081 u32 mifcfg;
2082
2083 /* Let the chip settle down a bit, it seems that helps
2084 * for sleep mode on some models
2085 */
2086 msleep(10);
2087
2088 /* Make sure we aren't polling PHY status change. We
2089 * don't currently use that feature though
2090 */
2091 mifcfg = readl(gp->regs + MIF_CFG);
2092 mifcfg &= ~MIF_CFG_POLL;
2093 writel(mifcfg, gp->regs + MIF_CFG);
2094
2095 if (wol && gp->has_wol) {
2096 unsigned char *e = &gp->dev->dev_addr[0];
2097 u32 csr;
2098
2099 /* Setup wake-on-lan for MAGIC packet */
2100 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2101 gp->regs + MAC_RXCFG);
2102 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2103 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2104 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2105
2106 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2107 csr = WOL_WAKECSR_ENABLE;
2108 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2109 csr |= WOL_WAKECSR_MII;
2110 writel(csr, gp->regs + WOL_WAKECSR);
2111 } else {
2112 writel(0, gp->regs + MAC_RXCFG);
2113 (void)readl(gp->regs + MAC_RXCFG);
2114 /* Machine sleep will die in strange ways if we
2115 * dont wait a bit here, looks like the chip takes
2116 * some time to really shut down
2117 */
2118 msleep(10);
2119 }
2120
2121 writel(0, gp->regs + MAC_TXCFG);
2122 writel(0, gp->regs + MAC_XIFCFG);
2123 writel(0, gp->regs + TXDMA_CFG);
2124 writel(0, gp->regs + RXDMA_CFG);
2125
2126 if (!wol) {
2127 gem_reset(gp);
2128 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2129 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2130
2131 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2132 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2133
2134 /* According to Apple, we must set the MDIO pins to this begnign
2135 * state or we may 1) eat more current, 2) damage some PHYs
2136 */
2137 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2138 writel(0, gp->regs + MIF_BBCLK);
2139 writel(0, gp->regs + MIF_BBDATA);
2140 writel(0, gp->regs + MIF_BBOENAB);
2141 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2142 (void) readl(gp->regs + MAC_XIFCFG);
2143 }
2144 }
2145
2146 static int gem_do_start(struct net_device *dev)
2147 {
2148 struct gem *gp = netdev_priv(dev);
2149 int rc;
2150
2151 /* Enable the cell */
2152 gem_get_cell(gp);
2153
2154 /* Make sure PCI access and bus master are enabled */
2155 rc = pci_enable_device(gp->pdev);
2156 if (rc) {
2157 netdev_err(dev, "Failed to enable chip on PCI bus !\n");
2158
2159 /* Put cell and forget it for now, it will be considered as
2160 * still asleep, a new sleep cycle may bring it back
2161 */
2162 gem_put_cell(gp);
2163 return -ENXIO;
2164 }
2165 pci_set_master(gp->pdev);
2166
2167 /* Init & setup chip hardware */
2168 gem_reinit_chip(gp);
2169
2170 /* An interrupt might come in handy */
2171 rc = request_irq(gp->pdev->irq, gem_interrupt,
2172 IRQF_SHARED, dev->name, (void *)dev);
2173 if (rc) {
2174 netdev_err(dev, "failed to request irq !\n");
2175
2176 gem_reset(gp);
2177 gem_clean_rings(gp);
2178 gem_put_cell(gp);
2179 return rc;
2180 }
2181
2182 /* Mark us as attached again if we come from resume(), this has
2183 * no effect if we weren't detached and needs to be done now.
2184 */
2185 netif_device_attach(dev);
2186
2187 /* Restart NAPI & queues */
2188 gem_netif_start(gp);
2189
2190 /* Detect & init PHY, start autoneg etc... this will
2191 * eventually result in starting DMA operations when
2192 * the link is up
2193 */
2194 gem_init_phy(gp);
2195
2196 return 0;
2197 }
2198
2199 static void gem_do_stop(struct net_device *dev, int wol)
2200 {
2201 struct gem *gp = netdev_priv(dev);
2202
2203 /* Stop NAPI and stop tx queue */
2204 gem_netif_stop(gp);
2205
2206 /* Make sure ints are disabled. We don't care about
2207 * synchronizing as NAPI is disabled, thus a stray
2208 * interrupt will do nothing bad (our irq handler
2209 * just schedules NAPI)
2210 */
2211 gem_disable_ints(gp);
2212
2213 /* Stop the link timer */
2214 del_timer_sync(&gp->link_timer);
2215
2216 /* We cannot cancel the reset task while holding the
2217 * rtnl lock, we'd get an A->B / B->A deadlock stituation
2218 * if we did. This is not an issue however as the reset
2219 * task is synchronized vs. us (rtnl_lock) and will do
2220 * nothing if the device is down or suspended. We do
2221 * still clear reset_task_pending to avoid a spurrious
2222 * reset later on in case we do resume before it gets
2223 * scheduled.
2224 */
2225 gp->reset_task_pending = 0;
2226
2227 /* If we are going to sleep with WOL */
2228 gem_stop_dma(gp);
2229 msleep(10);
2230 if (!wol)
2231 gem_reset(gp);
2232 msleep(10);
2233
2234 /* Get rid of rings */
2235 gem_clean_rings(gp);
2236
2237 /* No irq needed anymore */
2238 free_irq(gp->pdev->irq, (void *) dev);
2239
2240 /* Shut the PHY down eventually and setup WOL */
2241 gem_stop_phy(gp, wol);
2242
2243 /* Make sure bus master is disabled */
2244 pci_disable_device(gp->pdev);
2245
2246 /* Cell not needed neither if no WOL */
2247 if (!wol)
2248 gem_put_cell(gp);
2249 }
2250
2251 static void gem_reset_task(struct work_struct *work)
2252 {
2253 struct gem *gp = container_of(work, struct gem, reset_task);
2254
2255 /* Lock out the network stack (essentially shield ourselves
2256 * against a racing open, close, control call, or suspend
2257 */
2258 rtnl_lock();
2259
2260 /* Skip the reset task if suspended or closed, or if it's
2261 * been cancelled by gem_do_stop (see comment there)
2262 */
2263 if (!netif_device_present(gp->dev) ||
2264 !netif_running(gp->dev) ||
2265 !gp->reset_task_pending) {
2266 rtnl_unlock();
2267 return;
2268 }
2269
2270 /* Stop the link timer */
2271 del_timer_sync(&gp->link_timer);
2272
2273 /* Stop NAPI and tx */
2274 gem_netif_stop(gp);
2275
2276 /* Reset the chip & rings */
2277 gem_reinit_chip(gp);
2278 if (gp->lstate == link_up)
2279 gem_set_link_modes(gp);
2280
2281 /* Restart NAPI and Tx */
2282 gem_netif_start(gp);
2283
2284 /* We are back ! */
2285 gp->reset_task_pending = 0;
2286
2287 /* If the link is not up, restart autoneg, else restart the
2288 * polling timer
2289 */
2290 if (gp->lstate != link_up)
2291 gem_begin_auto_negotiation(gp, NULL);
2292 else
2293 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
2294
2295 rtnl_unlock();
2296 }
2297
2298 static int gem_open(struct net_device *dev)
2299 {
2300 /* We allow open while suspended, we just do nothing,
2301 * the chip will be initialized in resume()
2302 */
2303 if (netif_device_present(dev))
2304 return gem_do_start(dev);
2305 return 0;
2306 }
2307
2308 static int gem_close(struct net_device *dev)
2309 {
2310 if (netif_device_present(dev))
2311 gem_do_stop(dev, 0);
2312
2313 return 0;
2314 }
2315
2316 #ifdef CONFIG_PM
2317 static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2318 {
2319 struct net_device *dev = pci_get_drvdata(pdev);
2320 struct gem *gp = netdev_priv(dev);
2321
2322 /* Lock the network stack first to avoid racing with open/close,
2323 * reset task and setting calls
2324 */
2325 rtnl_lock();
2326
2327 /* Not running, mark ourselves non-present, no need for
2328 * a lock here
2329 */
2330 if (!netif_running(dev)) {
2331 netif_device_detach(dev);
2332 rtnl_unlock();
2333 return 0;
2334 }
2335 netdev_info(dev, "suspending, WakeOnLan %s\n",
2336 (gp->wake_on_lan && netif_running(dev)) ?
2337 "enabled" : "disabled");
2338
2339 /* Tell the network stack we're gone. gem_do_stop() below will
2340 * synchronize with TX, stop NAPI etc...
2341 */
2342 netif_device_detach(dev);
2343
2344 /* Switch off chip, remember WOL setting */
2345 gp->asleep_wol = !!gp->wake_on_lan;
2346 gem_do_stop(dev, gp->asleep_wol);
2347
2348 /* Unlock the network stack */
2349 rtnl_unlock();
2350
2351 return 0;
2352 }
2353
2354 static int gem_resume(struct pci_dev *pdev)
2355 {
2356 struct net_device *dev = pci_get_drvdata(pdev);
2357 struct gem *gp = netdev_priv(dev);
2358
2359 /* See locking comment in gem_suspend */
2360 rtnl_lock();
2361
2362 /* Not running, mark ourselves present, no need for
2363 * a lock here
2364 */
2365 if (!netif_running(dev)) {
2366 netif_device_attach(dev);
2367 rtnl_unlock();
2368 return 0;
2369 }
2370
2371 /* Restart chip. If that fails there isn't much we can do, we
2372 * leave things stopped.
2373 */
2374 gem_do_start(dev);
2375
2376 /* If we had WOL enabled, the cell clock was never turned off during
2377 * sleep, so we end up beeing unbalanced. Fix that here
2378 */
2379 if (gp->asleep_wol)
2380 gem_put_cell(gp);
2381
2382 /* Unlock the network stack */
2383 rtnl_unlock();
2384
2385 return 0;
2386 }
2387 #endif /* CONFIG_PM */
2388
2389 static struct net_device_stats *gem_get_stats(struct net_device *dev)
2390 {
2391 struct gem *gp = netdev_priv(dev);
2392
2393 /* I have seen this being called while the PM was in progress,
2394 * so we shield against this. Let's also not poke at registers
2395 * while the reset task is going on.
2396 *
2397 * TODO: Move stats collection elsewhere (link timer ?) and
2398 * make this a nop to avoid all those synchro issues
2399 */
2400 if (!netif_device_present(dev) || !netif_running(dev))
2401 goto bail;
2402
2403 /* Better safe than sorry... */
2404 if (WARN_ON(!gp->cell_enabled))
2405 goto bail;
2406
2407 dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2408 writel(0, gp->regs + MAC_FCSERR);
2409
2410 dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);
2411 writel(0, gp->regs + MAC_AERR);
2412
2413 dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);
2414 writel(0, gp->regs + MAC_LERR);
2415
2416 dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2417 dev->stats.collisions +=
2418 (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));
2419 writel(0, gp->regs + MAC_ECOLL);
2420 writel(0, gp->regs + MAC_LCOLL);
2421 bail:
2422 return &dev->stats;
2423 }
2424
2425 static int gem_set_mac_address(struct net_device *dev, void *addr)
2426 {
2427 struct sockaddr *macaddr = (struct sockaddr *) addr;
2428 struct gem *gp = netdev_priv(dev);
2429 unsigned char *e = &dev->dev_addr[0];
2430
2431 if (!is_valid_ether_addr(macaddr->sa_data))
2432 return -EADDRNOTAVAIL;
2433
2434 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2435
2436 /* We'll just catch it later when the device is up'd or resumed */
2437 if (!netif_running(dev) || !netif_device_present(dev))
2438 return 0;
2439
2440 /* Better safe than sorry... */
2441 if (WARN_ON(!gp->cell_enabled))
2442 return 0;
2443
2444 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2445 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2446 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2447
2448 return 0;
2449 }
2450
2451 static void gem_set_multicast(struct net_device *dev)
2452 {
2453 struct gem *gp = netdev_priv(dev);
2454 u32 rxcfg, rxcfg_new;
2455 int limit = 10000;
2456
2457 if (!netif_running(dev) || !netif_device_present(dev))
2458 return;
2459
2460 /* Better safe than sorry... */
2461 if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled))
2462 return;
2463
2464 rxcfg = readl(gp->regs + MAC_RXCFG);
2465 rxcfg_new = gem_setup_multicast(gp);
2466 #ifdef STRIP_FCS
2467 rxcfg_new |= MAC_RXCFG_SFCS;
2468 #endif
2469 gp->mac_rx_cfg = rxcfg_new;
2470
2471 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2472 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2473 if (!limit--)
2474 break;
2475 udelay(10);
2476 }
2477
2478 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2479 rxcfg |= rxcfg_new;
2480
2481 writel(rxcfg, gp->regs + MAC_RXCFG);
2482 }
2483
2484 /* Jumbo-grams don't seem to work :-( */
2485 #define GEM_MIN_MTU ETH_MIN_MTU
2486 #if 1
2487 #define GEM_MAX_MTU ETH_DATA_LEN
2488 #else
2489 #define GEM_MAX_MTU 9000
2490 #endif
2491
2492 static int gem_change_mtu(struct net_device *dev, int new_mtu)
2493 {
2494 struct gem *gp = netdev_priv(dev);
2495
2496 dev->mtu = new_mtu;
2497
2498 /* We'll just catch it later when the device is up'd or resumed */
2499 if (!netif_running(dev) || !netif_device_present(dev))
2500 return 0;
2501
2502 /* Better safe than sorry... */
2503 if (WARN_ON(!gp->cell_enabled))
2504 return 0;
2505
2506 gem_netif_stop(gp);
2507 gem_reinit_chip(gp);
2508 if (gp->lstate == link_up)
2509 gem_set_link_modes(gp);
2510 gem_netif_start(gp);
2511
2512 return 0;
2513 }
2514
2515 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2516 {
2517 struct gem *gp = netdev_priv(dev);
2518
2519 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2520 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2521 strlcpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info));
2522 }
2523
2524 static int gem_get_link_ksettings(struct net_device *dev,
2525 struct ethtool_link_ksettings *cmd)
2526 {
2527 struct gem *gp = netdev_priv(dev);
2528 u32 supported, advertising;
2529
2530 if (gp->phy_type == phy_mii_mdio0 ||
2531 gp->phy_type == phy_mii_mdio1) {
2532 if (gp->phy_mii.def)
2533 supported = gp->phy_mii.def->features;
2534 else
2535 supported = (SUPPORTED_10baseT_Half |
2536 SUPPORTED_10baseT_Full);
2537
2538 /* XXX hardcoded stuff for now */
2539 cmd->base.port = PORT_MII;
2540 cmd->base.phy_address = 0; /* XXX fixed PHYAD */
2541
2542 /* Return current PHY settings */
2543 cmd->base.autoneg = gp->want_autoneg;
2544 cmd->base.speed = gp->phy_mii.speed;
2545 cmd->base.duplex = gp->phy_mii.duplex;
2546 advertising = gp->phy_mii.advertising;
2547
2548 /* If we started with a forced mode, we don't have a default
2549 * advertise set, we need to return something sensible so
2550 * userland can re-enable autoneg properly.
2551 */
2552 if (advertising == 0)
2553 advertising = supported;
2554 } else { // XXX PCS ?
2555 supported =
2556 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2557 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2558 SUPPORTED_Autoneg);
2559 advertising = supported;
2560 cmd->base.speed = 0;
2561 cmd->base.duplex = 0;
2562 cmd->base.port = 0;
2563 cmd->base.phy_address = 0;
2564 cmd->base.autoneg = 0;
2565
2566 /* serdes means usually a Fibre connector, with most fixed */
2567 if (gp->phy_type == phy_serdes) {
2568 cmd->base.port = PORT_FIBRE;
2569 supported = (SUPPORTED_1000baseT_Half |
2570 SUPPORTED_1000baseT_Full |
2571 SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2572 SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2573 advertising = supported;
2574 if (gp->lstate == link_up)
2575 cmd->base.speed = SPEED_1000;
2576 cmd->base.duplex = DUPLEX_FULL;
2577 cmd->base.autoneg = 1;
2578 }
2579 }
2580
2581 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2582 supported);
2583 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2584 advertising);
2585
2586 return 0;
2587 }
2588
2589 static int gem_set_link_ksettings(struct net_device *dev,
2590 const struct ethtool_link_ksettings *cmd)
2591 {
2592 struct gem *gp = netdev_priv(dev);
2593 u32 speed = cmd->base.speed;
2594 u32 advertising;
2595
2596 ethtool_convert_link_mode_to_legacy_u32(&advertising,
2597 cmd->link_modes.advertising);
2598
2599 /* Verify the settings we care about. */
2600 if (cmd->base.autoneg != AUTONEG_ENABLE &&
2601 cmd->base.autoneg != AUTONEG_DISABLE)
2602 return -EINVAL;
2603
2604 if (cmd->base.autoneg == AUTONEG_ENABLE &&
2605 advertising == 0)
2606 return -EINVAL;
2607
2608 if (cmd->base.autoneg == AUTONEG_DISABLE &&
2609 ((speed != SPEED_1000 &&
2610 speed != SPEED_100 &&
2611 speed != SPEED_10) ||
2612 (cmd->base.duplex != DUPLEX_HALF &&
2613 cmd->base.duplex != DUPLEX_FULL)))
2614 return -EINVAL;
2615
2616 /* Apply settings and restart link process. */
2617 if (netif_device_present(gp->dev)) {
2618 del_timer_sync(&gp->link_timer);
2619 gem_begin_auto_negotiation(gp, cmd);
2620 }
2621
2622 return 0;
2623 }
2624
2625 static int gem_nway_reset(struct net_device *dev)
2626 {
2627 struct gem *gp = netdev_priv(dev);
2628
2629 if (!gp->want_autoneg)
2630 return -EINVAL;
2631
2632 /* Restart link process */
2633 if (netif_device_present(gp->dev)) {
2634 del_timer_sync(&gp->link_timer);
2635 gem_begin_auto_negotiation(gp, NULL);
2636 }
2637
2638 return 0;
2639 }
2640
2641 static u32 gem_get_msglevel(struct net_device *dev)
2642 {
2643 struct gem *gp = netdev_priv(dev);
2644 return gp->msg_enable;
2645 }
2646
2647 static void gem_set_msglevel(struct net_device *dev, u32 value)
2648 {
2649 struct gem *gp = netdev_priv(dev);
2650 gp->msg_enable = value;
2651 }
2652
2653
2654 /* Add more when I understand how to program the chip */
2655 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2656
2657 #define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2658
2659 static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2660 {
2661 struct gem *gp = netdev_priv(dev);
2662
2663 /* Add more when I understand how to program the chip */
2664 if (gp->has_wol) {
2665 wol->supported = WOL_SUPPORTED_MASK;
2666 wol->wolopts = gp->wake_on_lan;
2667 } else {
2668 wol->supported = 0;
2669 wol->wolopts = 0;
2670 }
2671 }
2672
2673 static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2674 {
2675 struct gem *gp = netdev_priv(dev);
2676
2677 if (!gp->has_wol)
2678 return -EOPNOTSUPP;
2679 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2680 return 0;
2681 }
2682
2683 static const struct ethtool_ops gem_ethtool_ops = {
2684 .get_drvinfo = gem_get_drvinfo,
2685 .get_link = ethtool_op_get_link,
2686 .nway_reset = gem_nway_reset,
2687 .get_msglevel = gem_get_msglevel,
2688 .set_msglevel = gem_set_msglevel,
2689 .get_wol = gem_get_wol,
2690 .set_wol = gem_set_wol,
2691 .get_link_ksettings = gem_get_link_ksettings,
2692 .set_link_ksettings = gem_set_link_ksettings,
2693 };
2694
2695 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2696 {
2697 struct gem *gp = netdev_priv(dev);
2698 struct mii_ioctl_data *data = if_mii(ifr);
2699 int rc = -EOPNOTSUPP;
2700
2701 /* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that
2702 * netif_device_present() is true and holds rtnl_lock for us
2703 * so we have nothing to worry about
2704 */
2705
2706 switch (cmd) {
2707 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2708 data->phy_id = gp->mii_phy_addr;
2709 /* Fallthrough... */
2710
2711 case SIOCGMIIREG: /* Read MII PHY register. */
2712 data->val_out = __sungem_phy_read(gp, data->phy_id & 0x1f,
2713 data->reg_num & 0x1f);
2714 rc = 0;
2715 break;
2716
2717 case SIOCSMIIREG: /* Write MII PHY register. */
2718 __sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2719 data->val_in);
2720 rc = 0;
2721 break;
2722 }
2723 return rc;
2724 }
2725
2726 #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2727 /* Fetch MAC address from vital product data of PCI ROM. */
2728 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2729 {
2730 int this_offset;
2731
2732 for (this_offset = 0x20; this_offset < len; this_offset++) {
2733 void __iomem *p = rom_base + this_offset;
2734 int i;
2735
2736 if (readb(p + 0) != 0x90 ||
2737 readb(p + 1) != 0x00 ||
2738 readb(p + 2) != 0x09 ||
2739 readb(p + 3) != 0x4e ||
2740 readb(p + 4) != 0x41 ||
2741 readb(p + 5) != 0x06)
2742 continue;
2743
2744 this_offset += 6;
2745 p += 6;
2746
2747 for (i = 0; i < 6; i++)
2748 dev_addr[i] = readb(p + i);
2749 return 1;
2750 }
2751 return 0;
2752 }
2753
2754 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2755 {
2756 size_t size;
2757 void __iomem *p = pci_map_rom(pdev, &size);
2758
2759 if (p) {
2760 int found;
2761
2762 found = readb(p) == 0x55 &&
2763 readb(p + 1) == 0xaa &&
2764 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2765 pci_unmap_rom(pdev, p);
2766 if (found)
2767 return;
2768 }
2769
2770 /* Sun MAC prefix then 3 random bytes. */
2771 dev_addr[0] = 0x08;
2772 dev_addr[1] = 0x00;
2773 dev_addr[2] = 0x20;
2774 get_random_bytes(dev_addr + 3, 3);
2775 }
2776 #endif /* not Sparc and not PPC */
2777
2778 static int gem_get_device_address(struct gem *gp)
2779 {
2780 #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2781 struct net_device *dev = gp->dev;
2782 const unsigned char *addr;
2783
2784 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
2785 if (addr == NULL) {
2786 #ifdef CONFIG_SPARC
2787 addr = idprom->id_ethaddr;
2788 #else
2789 printk("\n");
2790 pr_err("%s: can't get mac-address\n", dev->name);
2791 return -1;
2792 #endif
2793 }
2794 memcpy(dev->dev_addr, addr, ETH_ALEN);
2795 #else
2796 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2797 #endif
2798 return 0;
2799 }
2800
2801 static void gem_remove_one(struct pci_dev *pdev)
2802 {
2803 struct net_device *dev = pci_get_drvdata(pdev);
2804
2805 if (dev) {
2806 struct gem *gp = netdev_priv(dev);
2807
2808 unregister_netdev(dev);
2809
2810 /* Ensure reset task is truly gone */
2811 cancel_work_sync(&gp->reset_task);
2812
2813 /* Free resources */
2814 pci_free_consistent(pdev,
2815 sizeof(struct gem_init_block),
2816 gp->init_block,
2817 gp->gblock_dvma);
2818 iounmap(gp->regs);
2819 pci_release_regions(pdev);
2820 free_netdev(dev);
2821 }
2822 }
2823
2824 static const struct net_device_ops gem_netdev_ops = {
2825 .ndo_open = gem_open,
2826 .ndo_stop = gem_close,
2827 .ndo_start_xmit = gem_start_xmit,
2828 .ndo_get_stats = gem_get_stats,
2829 .ndo_set_rx_mode = gem_set_multicast,
2830 .ndo_do_ioctl = gem_ioctl,
2831 .ndo_tx_timeout = gem_tx_timeout,
2832 .ndo_change_mtu = gem_change_mtu,
2833 .ndo_validate_addr = eth_validate_addr,
2834 .ndo_set_mac_address = gem_set_mac_address,
2835 #ifdef CONFIG_NET_POLL_CONTROLLER
2836 .ndo_poll_controller = gem_poll_controller,
2837 #endif
2838 };
2839
2840 static int gem_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2841 {
2842 unsigned long gemreg_base, gemreg_len;
2843 struct net_device *dev;
2844 struct gem *gp;
2845 int err, pci_using_dac;
2846
2847 printk_once(KERN_INFO "%s", version);
2848
2849 /* Apple gmac note: during probe, the chip is powered up by
2850 * the arch code to allow the code below to work (and to let
2851 * the chip be probed on the config space. It won't stay powered
2852 * up until the interface is brought up however, so we can't rely
2853 * on register configuration done at this point.
2854 */
2855 err = pci_enable_device(pdev);
2856 if (err) {
2857 pr_err("Cannot enable MMIO operation, aborting\n");
2858 return err;
2859 }
2860 pci_set_master(pdev);
2861
2862 /* Configure DMA attributes. */
2863
2864 /* All of the GEM documentation states that 64-bit DMA addressing
2865 * is fully supported and should work just fine. However the
2866 * front end for RIO based GEMs is different and only supports
2867 * 32-bit addressing.
2868 *
2869 * For now we assume the various PPC GEMs are 32-bit only as well.
2870 */
2871 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2872 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2873 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2874 pci_using_dac = 1;
2875 } else {
2876 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2877 if (err) {
2878 pr_err("No usable DMA configuration, aborting\n");
2879 goto err_disable_device;
2880 }
2881 pci_using_dac = 0;
2882 }
2883
2884 gemreg_base = pci_resource_start(pdev, 0);
2885 gemreg_len = pci_resource_len(pdev, 0);
2886
2887 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2888 pr_err("Cannot find proper PCI device base address, aborting\n");
2889 err = -ENODEV;
2890 goto err_disable_device;
2891 }
2892
2893 dev = alloc_etherdev(sizeof(*gp));
2894 if (!dev) {
2895 err = -ENOMEM;
2896 goto err_disable_device;
2897 }
2898 SET_NETDEV_DEV(dev, &pdev->dev);
2899
2900 gp = netdev_priv(dev);
2901
2902 err = pci_request_regions(pdev, DRV_NAME);
2903 if (err) {
2904 pr_err("Cannot obtain PCI resources, aborting\n");
2905 goto err_out_free_netdev;
2906 }
2907
2908 gp->pdev = pdev;
2909 gp->dev = dev;
2910
2911 gp->msg_enable = DEFAULT_MSG;
2912
2913 timer_setup(&gp->link_timer, gem_link_timer, 0);
2914
2915 INIT_WORK(&gp->reset_task, gem_reset_task);
2916
2917 gp->lstate = link_down;
2918 gp->timer_ticks = 0;
2919 netif_carrier_off(dev);
2920
2921 gp->regs = ioremap(gemreg_base, gemreg_len);
2922 if (!gp->regs) {
2923 pr_err("Cannot map device registers, aborting\n");
2924 err = -EIO;
2925 goto err_out_free_res;
2926 }
2927
2928 /* On Apple, we want a reference to the Open Firmware device-tree
2929 * node. We use it for clock control.
2930 */
2931 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
2932 gp->of_node = pci_device_to_OF_node(pdev);
2933 #endif
2934
2935 /* Only Apple version supports WOL afaik */
2936 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
2937 gp->has_wol = 1;
2938
2939 /* Make sure cell is enabled */
2940 gem_get_cell(gp);
2941
2942 /* Make sure everything is stopped and in init state */
2943 gem_reset(gp);
2944
2945 /* Fill up the mii_phy structure (even if we won't use it) */
2946 gp->phy_mii.dev = dev;
2947 gp->phy_mii.mdio_read = _sungem_phy_read;
2948 gp->phy_mii.mdio_write = _sungem_phy_write;
2949 #ifdef CONFIG_PPC_PMAC
2950 gp->phy_mii.platform_data = gp->of_node;
2951 #endif
2952 /* By default, we start with autoneg */
2953 gp->want_autoneg = 1;
2954
2955 /* Check fifo sizes, PHY type, etc... */
2956 if (gem_check_invariants(gp)) {
2957 err = -ENODEV;
2958 goto err_out_iounmap;
2959 }
2960
2961 /* It is guaranteed that the returned buffer will be at least
2962 * PAGE_SIZE aligned.
2963 */
2964 gp->init_block = (struct gem_init_block *)
2965 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
2966 &gp->gblock_dvma);
2967 if (!gp->init_block) {
2968 pr_err("Cannot allocate init block, aborting\n");
2969 err = -ENOMEM;
2970 goto err_out_iounmap;
2971 }
2972
2973 err = gem_get_device_address(gp);
2974 if (err)
2975 goto err_out_free_consistent;
2976
2977 dev->netdev_ops = &gem_netdev_ops;
2978 netif_napi_add(dev, &gp->napi, gem_poll, 64);
2979 dev->ethtool_ops = &gem_ethtool_ops;
2980 dev->watchdog_timeo = 5 * HZ;
2981 dev->dma = 0;
2982
2983 /* Set that now, in case PM kicks in now */
2984 pci_set_drvdata(pdev, dev);
2985
2986 /* We can do scatter/gather and HW checksum */
2987 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
2988 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
2989 if (pci_using_dac)
2990 dev->features |= NETIF_F_HIGHDMA;
2991
2992 /* MTU range: 68 - 1500 (Jumbo mode is broken) */
2993 dev->min_mtu = GEM_MIN_MTU;
2994 dev->max_mtu = GEM_MAX_MTU;
2995
2996 /* Register with kernel */
2997 if (register_netdev(dev)) {
2998 pr_err("Cannot register net device, aborting\n");
2999 err = -ENOMEM;
3000 goto err_out_free_consistent;
3001 }
3002
3003 /* Undo the get_cell with appropriate locking (we could use
3004 * ndo_init/uninit but that would be even more clumsy imho)
3005 */
3006 rtnl_lock();
3007 gem_put_cell(gp);
3008 rtnl_unlock();
3009
3010 netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3011 dev->dev_addr);
3012 return 0;
3013
3014 err_out_free_consistent:
3015 gem_remove_one(pdev);
3016 err_out_iounmap:
3017 gem_put_cell(gp);
3018 iounmap(gp->regs);
3019
3020 err_out_free_res:
3021 pci_release_regions(pdev);
3022
3023 err_out_free_netdev:
3024 free_netdev(dev);
3025 err_disable_device:
3026 pci_disable_device(pdev);
3027 return err;
3028
3029 }
3030
3031
3032 static struct pci_driver gem_driver = {
3033 .name = GEM_MODULE_NAME,
3034 .id_table = gem_pci_tbl,
3035 .probe = gem_init_one,
3036 .remove = gem_remove_one,
3037 #ifdef CONFIG_PM
3038 .suspend = gem_suspend,
3039 .resume = gem_resume,
3040 #endif /* CONFIG_PM */
3041 };
3042
3043 module_pci_driver(gem_driver);
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