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net: ethernet: ti: cpsw: remove intr dbg msg from poll handlers
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / ti / cpsw.c
1 /*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio.h>
33 #include <linux/of.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
38
39 #include <linux/pinctrl/consumer.h>
40
41 #include "cpsw.h"
42 #include "cpsw_ale.h"
43 #include "cpts.h"
44 #include "davinci_cpdma.h"
45
46 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55 #define cpsw_info(priv, type, format, ...) \
56 do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59 } while (0)
60
61 #define cpsw_err(priv, type, format, ...) \
62 do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65 } while (0)
66
67 #define cpsw_dbg(priv, type, format, ...) \
68 do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71 } while (0)
72
73 #define cpsw_notice(priv, type, format, ...) \
74 do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77 } while (0)
78
79 #define ALE_ALL_PORTS 0x7
80
81 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
85 #define CPSW_VERSION_1 0x19010a
86 #define CPSW_VERSION_2 0x19010c
87 #define CPSW_VERSION_3 0x19010f
88 #define CPSW_VERSION_4 0x190112
89
90 #define HOST_PORT_NUM 0
91 #define SLIVER_SIZE 0x40
92
93 #define CPSW1_HOST_PORT_OFFSET 0x028
94 #define CPSW1_SLAVE_OFFSET 0x050
95 #define CPSW1_SLAVE_SIZE 0x040
96 #define CPSW1_CPDMA_OFFSET 0x100
97 #define CPSW1_STATERAM_OFFSET 0x200
98 #define CPSW1_HW_STATS 0x400
99 #define CPSW1_CPTS_OFFSET 0x500
100 #define CPSW1_ALE_OFFSET 0x600
101 #define CPSW1_SLIVER_OFFSET 0x700
102
103 #define CPSW2_HOST_PORT_OFFSET 0x108
104 #define CPSW2_SLAVE_OFFSET 0x200
105 #define CPSW2_SLAVE_SIZE 0x100
106 #define CPSW2_CPDMA_OFFSET 0x800
107 #define CPSW2_HW_STATS 0x900
108 #define CPSW2_STATERAM_OFFSET 0xa00
109 #define CPSW2_CPTS_OFFSET 0xc00
110 #define CPSW2_ALE_OFFSET 0xd00
111 #define CPSW2_SLIVER_OFFSET 0xd80
112 #define CPSW2_BD_OFFSET 0x2000
113
114 #define CPDMA_RXTHRESH 0x0c0
115 #define CPDMA_RXFREE 0x0e0
116 #define CPDMA_TXHDP 0x00
117 #define CPDMA_RXHDP 0x20
118 #define CPDMA_TXCP 0x40
119 #define CPDMA_RXCP 0x60
120
121 #define CPSW_POLL_WEIGHT 64
122 #define CPSW_MIN_PACKET_SIZE 60
123 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125 #define RX_PRIORITY_MAPPING 0x76543210
126 #define TX_PRIORITY_MAPPING 0x33221100
127 #define CPDMA_TX_PRIORITY_MAP 0x76543210
128
129 #define CPSW_VLAN_AWARE BIT(1)
130 #define CPSW_ALE_VLAN_AWARE 1
131
132 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
135
136 #define CPSW_INTPACEEN (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT 63
139 #define CPSW_CMINTMIN_CNT 2
140 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
143 #define cpsw_slave_index(priv) \
144 ((priv->data.dual_emac) ? priv->emac_port : \
145 priv->data.active_slave)
146
147 static int debug_level;
148 module_param(debug_level, int, 0);
149 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
150
151 static int ale_ageout = 10;
152 module_param(ale_ageout, int, 0);
153 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
154
155 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
156 module_param(rx_packet_max, int, 0);
157 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
158
159 struct cpsw_wr_regs {
160 u32 id_ver;
161 u32 soft_reset;
162 u32 control;
163 u32 int_control;
164 u32 rx_thresh_en;
165 u32 rx_en;
166 u32 tx_en;
167 u32 misc_en;
168 u32 mem_allign1[8];
169 u32 rx_thresh_stat;
170 u32 rx_stat;
171 u32 tx_stat;
172 u32 misc_stat;
173 u32 mem_allign2[8];
174 u32 rx_imax;
175 u32 tx_imax;
176
177 };
178
179 struct cpsw_ss_regs {
180 u32 id_ver;
181 u32 control;
182 u32 soft_reset;
183 u32 stat_port_en;
184 u32 ptype;
185 u32 soft_idle;
186 u32 thru_rate;
187 u32 gap_thresh;
188 u32 tx_start_wds;
189 u32 flow_control;
190 u32 vlan_ltype;
191 u32 ts_ltype;
192 u32 dlr_ltype;
193 };
194
195 /* CPSW_PORT_V1 */
196 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
197 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
198 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
199 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
200 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
201 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
202 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
203 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
204
205 /* CPSW_PORT_V2 */
206 #define CPSW2_CONTROL 0x00 /* Control Register */
207 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
208 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
209 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
210 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
211 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
212 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
213
214 /* CPSW_PORT_V1 and V2 */
215 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
216 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
217 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
218
219 /* CPSW_PORT_V2 only */
220 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
221 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
222 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
226 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
227 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
228
229 /* Bit definitions for the CPSW2_CONTROL register */
230 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
231 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
232 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
233 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
234 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
235 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
236 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
237 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
238 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
239 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
240 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
241 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
242 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
243 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
244 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
245 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
246 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
247
248 #define CTRL_V2_TS_BITS \
249 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
250 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
251
252 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
253 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
254 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
255
256
257 #define CTRL_V3_TS_BITS \
258 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
259 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
260 TS_LTYPE1_EN)
261
262 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
263 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
264 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
265
266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
269 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270 #define TS_MSG_TYPE_EN_MASK (0xffff)
271
272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
274
275 /* Bit definitions for the CPSW1_TS_CTL register */
276 #define CPSW_V1_TS_RX_EN BIT(0)
277 #define CPSW_V1_TS_TX_EN BIT(4)
278 #define CPSW_V1_MSG_TYPE_OFS 16
279
280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
282
283 struct cpsw_host_regs {
284 u32 max_blks;
285 u32 blk_cnt;
286 u32 tx_in_ctl;
287 u32 port_vlan;
288 u32 tx_pri_map;
289 u32 cpdma_tx_pri_map;
290 u32 cpdma_rx_chan_map;
291 };
292
293 struct cpsw_sliver_regs {
294 u32 id_ver;
295 u32 mac_control;
296 u32 mac_status;
297 u32 soft_reset;
298 u32 rx_maxlen;
299 u32 __reserved_0;
300 u32 rx_pause;
301 u32 tx_pause;
302 u32 __reserved_1;
303 u32 rx_pri_map;
304 };
305
306 struct cpsw_hw_stats {
307 u32 rxgoodframes;
308 u32 rxbroadcastframes;
309 u32 rxmulticastframes;
310 u32 rxpauseframes;
311 u32 rxcrcerrors;
312 u32 rxaligncodeerrors;
313 u32 rxoversizedframes;
314 u32 rxjabberframes;
315 u32 rxundersizedframes;
316 u32 rxfragments;
317 u32 __pad_0[2];
318 u32 rxoctets;
319 u32 txgoodframes;
320 u32 txbroadcastframes;
321 u32 txmulticastframes;
322 u32 txpauseframes;
323 u32 txdeferredframes;
324 u32 txcollisionframes;
325 u32 txsinglecollframes;
326 u32 txmultcollframes;
327 u32 txexcessivecollisions;
328 u32 txlatecollisions;
329 u32 txunderrun;
330 u32 txcarriersenseerrors;
331 u32 txoctets;
332 u32 octetframes64;
333 u32 octetframes65t127;
334 u32 octetframes128t255;
335 u32 octetframes256t511;
336 u32 octetframes512t1023;
337 u32 octetframes1024tup;
338 u32 netoctets;
339 u32 rxsofoverruns;
340 u32 rxmofoverruns;
341 u32 rxdmaoverruns;
342 };
343
344 struct cpsw_slave {
345 void __iomem *regs;
346 struct cpsw_sliver_regs __iomem *sliver;
347 int slave_num;
348 u32 mac_control;
349 struct cpsw_slave_data *data;
350 struct phy_device *phy;
351 struct net_device *ndev;
352 u32 port_vlan;
353 u32 open_stat;
354 };
355
356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
357 {
358 return __raw_readl(slave->regs + offset);
359 }
360
361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
362 {
363 __raw_writel(val, slave->regs + offset);
364 }
365
366 struct cpsw_priv {
367 struct platform_device *pdev;
368 struct net_device *ndev;
369 struct napi_struct napi_rx;
370 struct napi_struct napi_tx;
371 struct device *dev;
372 struct cpsw_platform_data data;
373 struct cpsw_ss_regs __iomem *regs;
374 struct cpsw_wr_regs __iomem *wr_regs;
375 u8 __iomem *hw_stats;
376 struct cpsw_host_regs __iomem *host_port_regs;
377 u32 msg_enable;
378 u32 version;
379 u32 coal_intvl;
380 u32 bus_freq_mhz;
381 int rx_packet_max;
382 struct clk *clk;
383 u8 mac_addr[ETH_ALEN];
384 struct cpsw_slave *slaves;
385 struct cpdma_ctlr *dma;
386 struct cpdma_chan *txch, *rxch;
387 struct cpsw_ale *ale;
388 bool rx_pause;
389 bool tx_pause;
390 bool quirk_irq;
391 bool rx_irq_disabled;
392 bool tx_irq_disabled;
393 /* snapshot of IRQ numbers */
394 u32 irqs_table[4];
395 u32 num_irqs;
396 struct cpts *cpts;
397 u32 emac_port;
398 };
399
400 struct cpsw_stats {
401 char stat_string[ETH_GSTRING_LEN];
402 int type;
403 int sizeof_stat;
404 int stat_offset;
405 };
406
407 enum {
408 CPSW_STATS,
409 CPDMA_RX_STATS,
410 CPDMA_TX_STATS,
411 };
412
413 #define CPSW_STAT(m) CPSW_STATS, \
414 sizeof(((struct cpsw_hw_stats *)0)->m), \
415 offsetof(struct cpsw_hw_stats, m)
416 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
417 sizeof(((struct cpdma_chan_stats *)0)->m), \
418 offsetof(struct cpdma_chan_stats, m)
419 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
420 sizeof(((struct cpdma_chan_stats *)0)->m), \
421 offsetof(struct cpdma_chan_stats, m)
422
423 static const struct cpsw_stats cpsw_gstrings_stats[] = {
424 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
425 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
426 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
427 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
428 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
429 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
430 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
431 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
432 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
433 { "Rx Fragments", CPSW_STAT(rxfragments) },
434 { "Rx Octets", CPSW_STAT(rxoctets) },
435 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
436 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
437 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
438 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
439 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
440 { "Collisions", CPSW_STAT(txcollisionframes) },
441 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
442 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
443 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
444 { "Late Collisions", CPSW_STAT(txlatecollisions) },
445 { "Tx Underrun", CPSW_STAT(txunderrun) },
446 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
447 { "Tx Octets", CPSW_STAT(txoctets) },
448 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
449 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
450 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
451 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
452 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
453 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
454 { "Net Octets", CPSW_STAT(netoctets) },
455 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
456 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
457 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
458 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
459 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
460 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
461 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
462 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
463 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
464 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
465 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
466 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
467 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
468 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
469 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
470 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
471 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
472 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
473 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
474 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
475 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
476 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
477 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
478 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
479 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
480 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
481 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
482 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
483 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
484 };
485
486 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
487
488 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
489 #define for_each_slave(priv, func, arg...) \
490 do { \
491 struct cpsw_slave *slave; \
492 int n; \
493 if (priv->data.dual_emac) \
494 (func)((priv)->slaves + priv->emac_port, ##arg);\
495 else \
496 for (n = (priv)->data.slaves, \
497 slave = (priv)->slaves; \
498 n; n--) \
499 (func)(slave++, ##arg); \
500 } while (0)
501 #define cpsw_get_slave_ndev(priv, __slave_no__) \
502 ((__slave_no__ < priv->data.slaves) ? \
503 priv->slaves[__slave_no__].ndev : NULL)
504 #define cpsw_get_slave_priv(priv, __slave_no__) \
505 (((__slave_no__ < priv->data.slaves) && \
506 (priv->slaves[__slave_no__].ndev)) ? \
507 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
508
509 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
510 do { \
511 if (!priv->data.dual_emac) \
512 break; \
513 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
514 ndev = cpsw_get_slave_ndev(priv, 0); \
515 priv = netdev_priv(ndev); \
516 skb->dev = ndev; \
517 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
518 ndev = cpsw_get_slave_ndev(priv, 1); \
519 priv = netdev_priv(ndev); \
520 skb->dev = ndev; \
521 } \
522 } while (0)
523 #define cpsw_add_mcast(priv, addr) \
524 do { \
525 if (priv->data.dual_emac) { \
526 struct cpsw_slave *slave = priv->slaves + \
527 priv->emac_port; \
528 int slave_port = cpsw_get_slave_port(priv, \
529 slave->slave_num); \
530 cpsw_ale_add_mcast(priv->ale, addr, \
531 1 << slave_port | ALE_PORT_HOST, \
532 ALE_VLAN, slave->port_vlan, 0); \
533 } else { \
534 cpsw_ale_add_mcast(priv->ale, addr, \
535 ALE_ALL_PORTS, \
536 0, 0, 0); \
537 } \
538 } while (0)
539
540 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
541 {
542 return slave_num + 1;
543 }
544
545 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
546 {
547 struct cpsw_priv *priv = netdev_priv(ndev);
548 struct cpsw_ale *ale = priv->ale;
549 int i;
550
551 if (priv->data.dual_emac) {
552 bool flag = false;
553
554 /* Enabling promiscuous mode for one interface will be
555 * common for both the interface as the interface shares
556 * the same hardware resource.
557 */
558 for (i = 0; i < priv->data.slaves; i++)
559 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
560 flag = true;
561
562 if (!enable && flag) {
563 enable = true;
564 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
565 }
566
567 if (enable) {
568 /* Enable Bypass */
569 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
570
571 dev_dbg(&ndev->dev, "promiscuity enabled\n");
572 } else {
573 /* Disable Bypass */
574 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
575 dev_dbg(&ndev->dev, "promiscuity disabled\n");
576 }
577 } else {
578 if (enable) {
579 unsigned long timeout = jiffies + HZ;
580
581 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
582 for (i = 0; i <= priv->data.slaves; i++) {
583 cpsw_ale_control_set(ale, i,
584 ALE_PORT_NOLEARN, 1);
585 cpsw_ale_control_set(ale, i,
586 ALE_PORT_NO_SA_UPDATE, 1);
587 }
588
589 /* Clear All Untouched entries */
590 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
591 do {
592 cpu_relax();
593 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
594 break;
595 } while (time_after(timeout, jiffies));
596 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
597
598 /* Clear all mcast from ALE */
599 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
600
601 /* Flood All Unicast Packets to Host port */
602 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
603 dev_dbg(&ndev->dev, "promiscuity enabled\n");
604 } else {
605 /* Don't Flood All Unicast Packets to Host port */
606 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
607
608 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
609 for (i = 0; i <= priv->data.slaves; i++) {
610 cpsw_ale_control_set(ale, i,
611 ALE_PORT_NOLEARN, 0);
612 cpsw_ale_control_set(ale, i,
613 ALE_PORT_NO_SA_UPDATE, 0);
614 }
615 dev_dbg(&ndev->dev, "promiscuity disabled\n");
616 }
617 }
618 }
619
620 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
621 {
622 struct cpsw_priv *priv = netdev_priv(ndev);
623 int vid;
624
625 if (priv->data.dual_emac)
626 vid = priv->slaves[priv->emac_port].port_vlan;
627 else
628 vid = priv->data.default_vlan;
629
630 if (ndev->flags & IFF_PROMISC) {
631 /* Enable promiscuous mode */
632 cpsw_set_promiscious(ndev, true);
633 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
634 return;
635 } else {
636 /* Disable promiscuous mode */
637 cpsw_set_promiscious(ndev, false);
638 }
639
640 /* Restore allmulti on vlans if necessary */
641 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
642
643 /* Clear all mcast from ALE */
644 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS, vid);
645
646 if (!netdev_mc_empty(ndev)) {
647 struct netdev_hw_addr *ha;
648
649 /* program multicast address list into ALE register */
650 netdev_for_each_mc_addr(ha, ndev) {
651 cpsw_add_mcast(priv, (u8 *)ha->addr);
652 }
653 }
654 }
655
656 static void cpsw_intr_enable(struct cpsw_priv *priv)
657 {
658 __raw_writel(0xFF, &priv->wr_regs->tx_en);
659 __raw_writel(0xFF, &priv->wr_regs->rx_en);
660
661 cpdma_ctlr_int_ctrl(priv->dma, true);
662 return;
663 }
664
665 static void cpsw_intr_disable(struct cpsw_priv *priv)
666 {
667 __raw_writel(0, &priv->wr_regs->tx_en);
668 __raw_writel(0, &priv->wr_regs->rx_en);
669
670 cpdma_ctlr_int_ctrl(priv->dma, false);
671 return;
672 }
673
674 static void cpsw_tx_handler(void *token, int len, int status)
675 {
676 struct sk_buff *skb = token;
677 struct net_device *ndev = skb->dev;
678 struct cpsw_priv *priv = netdev_priv(ndev);
679
680 /* Check whether the queue is stopped due to stalled tx dma, if the
681 * queue is stopped then start the queue as we have free desc for tx
682 */
683 if (unlikely(netif_queue_stopped(ndev)))
684 netif_wake_queue(ndev);
685 cpts_tx_timestamp(priv->cpts, skb);
686 ndev->stats.tx_packets++;
687 ndev->stats.tx_bytes += len;
688 dev_kfree_skb_any(skb);
689 }
690
691 static void cpsw_rx_handler(void *token, int len, int status)
692 {
693 struct sk_buff *skb = token;
694 struct sk_buff *new_skb;
695 struct net_device *ndev = skb->dev;
696 struct cpsw_priv *priv = netdev_priv(ndev);
697 int ret = 0;
698
699 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
700
701 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
702 bool ndev_status = false;
703 struct cpsw_slave *slave = priv->slaves;
704 int n;
705
706 if (priv->data.dual_emac) {
707 /* In dual emac mode check for all interfaces */
708 for (n = priv->data.slaves; n; n--, slave++)
709 if (netif_running(slave->ndev))
710 ndev_status = true;
711 }
712
713 if (ndev_status && (status >= 0)) {
714 /* The packet received is for the interface which
715 * is already down and the other interface is up
716 * and running, instead of freeing which results
717 * in reducing of the number of rx descriptor in
718 * DMA engine, requeue skb back to cpdma.
719 */
720 new_skb = skb;
721 goto requeue;
722 }
723
724 /* the interface is going down, skbs are purged */
725 dev_kfree_skb_any(skb);
726 return;
727 }
728
729 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
730 if (new_skb) {
731 skb_put(skb, len);
732 cpts_rx_timestamp(priv->cpts, skb);
733 skb->protocol = eth_type_trans(skb, ndev);
734 netif_receive_skb(skb);
735 ndev->stats.rx_bytes += len;
736 ndev->stats.rx_packets++;
737 } else {
738 ndev->stats.rx_dropped++;
739 new_skb = skb;
740 }
741
742 requeue:
743 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
744 skb_tailroom(new_skb), 0);
745 if (WARN_ON(ret < 0))
746 dev_kfree_skb_any(new_skb);
747 }
748
749 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
750 {
751 struct cpsw_priv *priv = dev_id;
752
753 writel(0, &priv->wr_regs->tx_en);
754 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
755
756 if (priv->quirk_irq) {
757 disable_irq_nosync(priv->irqs_table[1]);
758 priv->tx_irq_disabled = true;
759 }
760
761 napi_schedule(&priv->napi_tx);
762 return IRQ_HANDLED;
763 }
764
765 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
766 {
767 struct cpsw_priv *priv = dev_id;
768
769 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
770 writel(0, &priv->wr_regs->rx_en);
771
772 if (priv->quirk_irq) {
773 disable_irq_nosync(priv->irqs_table[0]);
774 priv->rx_irq_disabled = true;
775 }
776
777 napi_schedule(&priv->napi_rx);
778 return IRQ_HANDLED;
779 }
780
781 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
782 {
783 struct cpsw_priv *priv = napi_to_priv(napi_tx);
784 int num_tx;
785
786 num_tx = cpdma_chan_process(priv->txch, budget);
787 if (num_tx < budget) {
788 napi_complete(napi_tx);
789 writel(0xff, &priv->wr_regs->tx_en);
790 if (priv->quirk_irq && priv->tx_irq_disabled) {
791 priv->tx_irq_disabled = false;
792 enable_irq(priv->irqs_table[1]);
793 }
794 }
795
796 return num_tx;
797 }
798
799 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
800 {
801 struct cpsw_priv *priv = napi_to_priv(napi_rx);
802 int num_rx;
803
804 num_rx = cpdma_chan_process(priv->rxch, budget);
805 if (num_rx < budget) {
806 napi_complete(napi_rx);
807 writel(0xff, &priv->wr_regs->rx_en);
808 if (priv->quirk_irq && priv->rx_irq_disabled) {
809 priv->rx_irq_disabled = false;
810 enable_irq(priv->irqs_table[0]);
811 }
812 }
813
814 return num_rx;
815 }
816
817 static inline void soft_reset(const char *module, void __iomem *reg)
818 {
819 unsigned long timeout = jiffies + HZ;
820
821 __raw_writel(1, reg);
822 do {
823 cpu_relax();
824 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
825
826 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
827 }
828
829 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
830 ((mac)[2] << 16) | ((mac)[3] << 24))
831 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
832
833 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
834 struct cpsw_priv *priv)
835 {
836 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
837 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
838 }
839
840 static void _cpsw_adjust_link(struct cpsw_slave *slave,
841 struct cpsw_priv *priv, bool *link)
842 {
843 struct phy_device *phy = slave->phy;
844 u32 mac_control = 0;
845 u32 slave_port;
846
847 if (!phy)
848 return;
849
850 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
851
852 if (phy->link) {
853 mac_control = priv->data.mac_control;
854
855 /* enable forwarding */
856 cpsw_ale_control_set(priv->ale, slave_port,
857 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
858
859 if (phy->speed == 1000)
860 mac_control |= BIT(7); /* GIGABITEN */
861 if (phy->duplex)
862 mac_control |= BIT(0); /* FULLDUPLEXEN */
863
864 /* set speed_in input in case RMII mode is used in 100Mbps */
865 if (phy->speed == 100)
866 mac_control |= BIT(15);
867 else if (phy->speed == 10)
868 mac_control |= BIT(18); /* In Band mode */
869
870 if (priv->rx_pause)
871 mac_control |= BIT(3);
872
873 if (priv->tx_pause)
874 mac_control |= BIT(4);
875
876 *link = true;
877 } else {
878 mac_control = 0;
879 /* disable forwarding */
880 cpsw_ale_control_set(priv->ale, slave_port,
881 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
882 }
883
884 if (mac_control != slave->mac_control) {
885 phy_print_status(phy);
886 __raw_writel(mac_control, &slave->sliver->mac_control);
887 }
888
889 slave->mac_control = mac_control;
890 }
891
892 static void cpsw_adjust_link(struct net_device *ndev)
893 {
894 struct cpsw_priv *priv = netdev_priv(ndev);
895 bool link = false;
896
897 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
898
899 if (link) {
900 netif_carrier_on(ndev);
901 if (netif_running(ndev))
902 netif_wake_queue(ndev);
903 } else {
904 netif_carrier_off(ndev);
905 netif_stop_queue(ndev);
906 }
907 }
908
909 static int cpsw_get_coalesce(struct net_device *ndev,
910 struct ethtool_coalesce *coal)
911 {
912 struct cpsw_priv *priv = netdev_priv(ndev);
913
914 coal->rx_coalesce_usecs = priv->coal_intvl;
915 return 0;
916 }
917
918 static int cpsw_set_coalesce(struct net_device *ndev,
919 struct ethtool_coalesce *coal)
920 {
921 struct cpsw_priv *priv = netdev_priv(ndev);
922 u32 int_ctrl;
923 u32 num_interrupts = 0;
924 u32 prescale = 0;
925 u32 addnl_dvdr = 1;
926 u32 coal_intvl = 0;
927
928 coal_intvl = coal->rx_coalesce_usecs;
929
930 int_ctrl = readl(&priv->wr_regs->int_control);
931 prescale = priv->bus_freq_mhz * 4;
932
933 if (!coal->rx_coalesce_usecs) {
934 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
935 goto update_return;
936 }
937
938 if (coal_intvl < CPSW_CMINTMIN_INTVL)
939 coal_intvl = CPSW_CMINTMIN_INTVL;
940
941 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
942 /* Interrupt pacer works with 4us Pulse, we can
943 * throttle further by dilating the 4us pulse.
944 */
945 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
946
947 if (addnl_dvdr > 1) {
948 prescale *= addnl_dvdr;
949 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
950 coal_intvl = (CPSW_CMINTMAX_INTVL
951 * addnl_dvdr);
952 } else {
953 addnl_dvdr = 1;
954 coal_intvl = CPSW_CMINTMAX_INTVL;
955 }
956 }
957
958 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
959 writel(num_interrupts, &priv->wr_regs->rx_imax);
960 writel(num_interrupts, &priv->wr_regs->tx_imax);
961
962 int_ctrl |= CPSW_INTPACEEN;
963 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
964 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
965
966 update_return:
967 writel(int_ctrl, &priv->wr_regs->int_control);
968
969 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
970 if (priv->data.dual_emac) {
971 int i;
972
973 for (i = 0; i < priv->data.slaves; i++) {
974 priv = netdev_priv(priv->slaves[i].ndev);
975 priv->coal_intvl = coal_intvl;
976 }
977 } else {
978 priv->coal_intvl = coal_intvl;
979 }
980
981 return 0;
982 }
983
984 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
985 {
986 switch (sset) {
987 case ETH_SS_STATS:
988 return CPSW_STATS_LEN;
989 default:
990 return -EOPNOTSUPP;
991 }
992 }
993
994 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
995 {
996 u8 *p = data;
997 int i;
998
999 switch (stringset) {
1000 case ETH_SS_STATS:
1001 for (i = 0; i < CPSW_STATS_LEN; i++) {
1002 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1003 ETH_GSTRING_LEN);
1004 p += ETH_GSTRING_LEN;
1005 }
1006 break;
1007 }
1008 }
1009
1010 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1011 struct ethtool_stats *stats, u64 *data)
1012 {
1013 struct cpsw_priv *priv = netdev_priv(ndev);
1014 struct cpdma_chan_stats rx_stats;
1015 struct cpdma_chan_stats tx_stats;
1016 u32 val;
1017 u8 *p;
1018 int i;
1019
1020 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1021 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1022 cpdma_chan_get_stats(priv->txch, &tx_stats);
1023
1024 for (i = 0; i < CPSW_STATS_LEN; i++) {
1025 switch (cpsw_gstrings_stats[i].type) {
1026 case CPSW_STATS:
1027 val = readl(priv->hw_stats +
1028 cpsw_gstrings_stats[i].stat_offset);
1029 data[i] = val;
1030 break;
1031
1032 case CPDMA_RX_STATS:
1033 p = (u8 *)&rx_stats +
1034 cpsw_gstrings_stats[i].stat_offset;
1035 data[i] = *(u32 *)p;
1036 break;
1037
1038 case CPDMA_TX_STATS:
1039 p = (u8 *)&tx_stats +
1040 cpsw_gstrings_stats[i].stat_offset;
1041 data[i] = *(u32 *)p;
1042 break;
1043 }
1044 }
1045 }
1046
1047 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1048 {
1049 u32 i;
1050 u32 usage_count = 0;
1051
1052 if (!priv->data.dual_emac)
1053 return 0;
1054
1055 for (i = 0; i < priv->data.slaves; i++)
1056 if (priv->slaves[i].open_stat)
1057 usage_count++;
1058
1059 return usage_count;
1060 }
1061
1062 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1063 struct sk_buff *skb)
1064 {
1065 return cpdma_chan_submit(priv->txch, skb, skb->data, skb->len,
1066 priv->emac_port + priv->data.dual_emac);
1067 }
1068
1069 static inline void cpsw_add_dual_emac_def_ale_entries(
1070 struct cpsw_priv *priv, struct cpsw_slave *slave,
1071 u32 slave_port)
1072 {
1073 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1074
1075 if (priv->version == CPSW_VERSION_1)
1076 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1077 else
1078 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1079 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1080 port_mask, port_mask, 0);
1081 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1082 port_mask, ALE_VLAN, slave->port_vlan, 0);
1083 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1084 HOST_PORT_NUM, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1085 }
1086
1087 static void soft_reset_slave(struct cpsw_slave *slave)
1088 {
1089 char name[32];
1090
1091 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1092 soft_reset(name, &slave->sliver->soft_reset);
1093 }
1094
1095 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1096 {
1097 u32 slave_port;
1098
1099 soft_reset_slave(slave);
1100
1101 /* setup priority mapping */
1102 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1103
1104 switch (priv->version) {
1105 case CPSW_VERSION_1:
1106 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1107 break;
1108 case CPSW_VERSION_2:
1109 case CPSW_VERSION_3:
1110 case CPSW_VERSION_4:
1111 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1112 break;
1113 }
1114
1115 /* setup max packet size, and mac address */
1116 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1117 cpsw_set_slave_mac(slave, priv);
1118
1119 slave->mac_control = 0; /* no link yet */
1120
1121 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1122
1123 if (priv->data.dual_emac)
1124 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1125 else
1126 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1127 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1128
1129 if (slave->data->phy_node) {
1130 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1131 &cpsw_adjust_link, 0, slave->data->phy_if);
1132 if (!slave->phy) {
1133 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1134 slave->data->phy_node->full_name,
1135 slave->slave_num);
1136 return;
1137 }
1138 } else {
1139 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1140 &cpsw_adjust_link, slave->data->phy_if);
1141 if (IS_ERR(slave->phy)) {
1142 dev_err(priv->dev,
1143 "phy \"%s\" not found on slave %d, err %ld\n",
1144 slave->data->phy_id, slave->slave_num,
1145 PTR_ERR(slave->phy));
1146 slave->phy = NULL;
1147 return;
1148 }
1149 }
1150
1151 phy_attached_info(slave->phy);
1152
1153 phy_start(slave->phy);
1154
1155 /* Configure GMII_SEL register */
1156 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, slave->slave_num);
1157 }
1158
1159 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1160 {
1161 const int vlan = priv->data.default_vlan;
1162 u32 reg;
1163 int i;
1164 int unreg_mcast_mask;
1165
1166 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1167 CPSW2_PORT_VLAN;
1168
1169 writel(vlan, &priv->host_port_regs->port_vlan);
1170
1171 for (i = 0; i < priv->data.slaves; i++)
1172 slave_write(priv->slaves + i, vlan, reg);
1173
1174 if (priv->ndev->flags & IFF_ALLMULTI)
1175 unreg_mcast_mask = ALE_ALL_PORTS;
1176 else
1177 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1178
1179 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS,
1180 ALE_ALL_PORTS, ALE_ALL_PORTS,
1181 unreg_mcast_mask);
1182 }
1183
1184 static void cpsw_init_host_port(struct cpsw_priv *priv)
1185 {
1186 u32 control_reg;
1187 u32 fifo_mode;
1188
1189 /* soft reset the controller and initialize ale */
1190 soft_reset("cpsw", &priv->regs->soft_reset);
1191 cpsw_ale_start(priv->ale);
1192
1193 /* switch to vlan unaware mode */
1194 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1195 CPSW_ALE_VLAN_AWARE);
1196 control_reg = readl(&priv->regs->control);
1197 control_reg |= CPSW_VLAN_AWARE;
1198 writel(control_reg, &priv->regs->control);
1199 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1200 CPSW_FIFO_NORMAL_MODE;
1201 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1202
1203 /* setup host port priority mapping */
1204 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1205 &priv->host_port_regs->cpdma_tx_pri_map);
1206 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1207
1208 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM,
1209 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1210
1211 if (!priv->data.dual_emac) {
1212 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
1213 0, 0);
1214 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1215 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1216 }
1217 }
1218
1219 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1220 {
1221 u32 slave_port;
1222
1223 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1224
1225 if (!slave->phy)
1226 return;
1227 phy_stop(slave->phy);
1228 phy_disconnect(slave->phy);
1229 slave->phy = NULL;
1230 cpsw_ale_control_set(priv->ale, slave_port,
1231 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1232 soft_reset_slave(slave);
1233 }
1234
1235 static int cpsw_ndo_open(struct net_device *ndev)
1236 {
1237 struct cpsw_priv *priv = netdev_priv(ndev);
1238 int i, ret;
1239 u32 reg;
1240
1241 ret = pm_runtime_get_sync(&priv->pdev->dev);
1242 if (ret < 0) {
1243 pm_runtime_put_noidle(&priv->pdev->dev);
1244 return ret;
1245 }
1246
1247 if (!cpsw_common_res_usage_state(priv))
1248 cpsw_intr_disable(priv);
1249 netif_carrier_off(ndev);
1250
1251 reg = priv->version;
1252
1253 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1254 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1255 CPSW_RTL_VERSION(reg));
1256
1257 /* initialize host and slave ports */
1258 if (!cpsw_common_res_usage_state(priv))
1259 cpsw_init_host_port(priv);
1260 for_each_slave(priv, cpsw_slave_open, priv);
1261
1262 /* Add default VLAN */
1263 if (!priv->data.dual_emac)
1264 cpsw_add_default_vlan(priv);
1265 else
1266 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1267 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1268
1269 if (!cpsw_common_res_usage_state(priv)) {
1270 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1271 int buf_num;
1272
1273 /* setup tx dma to fixed prio and zero offset */
1274 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1275 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1276
1277 /* disable priority elevation */
1278 __raw_writel(0, &priv->regs->ptype);
1279
1280 /* enable statistics collection only on all ports */
1281 __raw_writel(0x7, &priv->regs->stat_port_en);
1282
1283 /* Enable internal fifo flow control */
1284 writel(0x7, &priv->regs->flow_control);
1285
1286 napi_enable(&priv_sl0->napi_rx);
1287 napi_enable(&priv_sl0->napi_tx);
1288
1289 if (priv_sl0->tx_irq_disabled) {
1290 priv_sl0->tx_irq_disabled = false;
1291 enable_irq(priv->irqs_table[1]);
1292 }
1293
1294 if (priv_sl0->rx_irq_disabled) {
1295 priv_sl0->rx_irq_disabled = false;
1296 enable_irq(priv->irqs_table[0]);
1297 }
1298
1299 buf_num = cpdma_chan_get_rx_buf_num(priv->dma);
1300 for (i = 0; i < buf_num; i++) {
1301 struct sk_buff *skb;
1302
1303 ret = -ENOMEM;
1304 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1305 priv->rx_packet_max, GFP_KERNEL);
1306 if (!skb)
1307 goto err_cleanup;
1308 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1309 skb_tailroom(skb), 0);
1310 if (ret < 0) {
1311 kfree_skb(skb);
1312 goto err_cleanup;
1313 }
1314 }
1315 /* continue even if we didn't manage to submit all
1316 * receive descs
1317 */
1318 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1319
1320 if (cpts_register(&priv->pdev->dev, priv->cpts,
1321 priv->data.cpts_clock_mult,
1322 priv->data.cpts_clock_shift))
1323 dev_err(priv->dev, "error registering cpts device\n");
1324
1325 }
1326
1327 /* Enable Interrupt pacing if configured */
1328 if (priv->coal_intvl != 0) {
1329 struct ethtool_coalesce coal;
1330
1331 coal.rx_coalesce_usecs = priv->coal_intvl;
1332 cpsw_set_coalesce(ndev, &coal);
1333 }
1334
1335 cpdma_ctlr_start(priv->dma);
1336 cpsw_intr_enable(priv);
1337
1338 if (priv->data.dual_emac)
1339 priv->slaves[priv->emac_port].open_stat = true;
1340 return 0;
1341
1342 err_cleanup:
1343 cpdma_ctlr_stop(priv->dma);
1344 for_each_slave(priv, cpsw_slave_stop, priv);
1345 pm_runtime_put_sync(&priv->pdev->dev);
1346 netif_carrier_off(priv->ndev);
1347 return ret;
1348 }
1349
1350 static int cpsw_ndo_stop(struct net_device *ndev)
1351 {
1352 struct cpsw_priv *priv = netdev_priv(ndev);
1353
1354 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1355 netif_stop_queue(priv->ndev);
1356 netif_carrier_off(priv->ndev);
1357
1358 if (cpsw_common_res_usage_state(priv) <= 1) {
1359 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1360
1361 napi_disable(&priv_sl0->napi_rx);
1362 napi_disable(&priv_sl0->napi_tx);
1363 cpts_unregister(priv->cpts);
1364 cpsw_intr_disable(priv);
1365 cpdma_ctlr_stop(priv->dma);
1366 cpsw_ale_stop(priv->ale);
1367 }
1368 for_each_slave(priv, cpsw_slave_stop, priv);
1369 pm_runtime_put_sync(&priv->pdev->dev);
1370 if (priv->data.dual_emac)
1371 priv->slaves[priv->emac_port].open_stat = false;
1372 return 0;
1373 }
1374
1375 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1376 struct net_device *ndev)
1377 {
1378 struct cpsw_priv *priv = netdev_priv(ndev);
1379 int ret;
1380
1381 netif_trans_update(ndev);
1382
1383 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1384 cpsw_err(priv, tx_err, "packet pad failed\n");
1385 ndev->stats.tx_dropped++;
1386 return NETDEV_TX_OK;
1387 }
1388
1389 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1390 priv->cpts->tx_enable)
1391 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1392
1393 skb_tx_timestamp(skb);
1394
1395 ret = cpsw_tx_packet_submit(priv, skb);
1396 if (unlikely(ret != 0)) {
1397 cpsw_err(priv, tx_err, "desc submit failed\n");
1398 goto fail;
1399 }
1400
1401 /* If there is no more tx desc left free then we need to
1402 * tell the kernel to stop sending us tx frames.
1403 */
1404 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1405 netif_stop_queue(ndev);
1406
1407 return NETDEV_TX_OK;
1408 fail:
1409 ndev->stats.tx_dropped++;
1410 netif_stop_queue(ndev);
1411 return NETDEV_TX_BUSY;
1412 }
1413
1414 #ifdef CONFIG_TI_CPTS
1415
1416 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1417 {
1418 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1419 u32 ts_en, seq_id;
1420
1421 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1422 slave_write(slave, 0, CPSW1_TS_CTL);
1423 return;
1424 }
1425
1426 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1427 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1428
1429 if (priv->cpts->tx_enable)
1430 ts_en |= CPSW_V1_TS_TX_EN;
1431
1432 if (priv->cpts->rx_enable)
1433 ts_en |= CPSW_V1_TS_RX_EN;
1434
1435 slave_write(slave, ts_en, CPSW1_TS_CTL);
1436 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1437 }
1438
1439 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1440 {
1441 struct cpsw_slave *slave;
1442 u32 ctrl, mtype;
1443
1444 if (priv->data.dual_emac)
1445 slave = &priv->slaves[priv->emac_port];
1446 else
1447 slave = &priv->slaves[priv->data.active_slave];
1448
1449 ctrl = slave_read(slave, CPSW2_CONTROL);
1450 switch (priv->version) {
1451 case CPSW_VERSION_2:
1452 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1453
1454 if (priv->cpts->tx_enable)
1455 ctrl |= CTRL_V2_TX_TS_BITS;
1456
1457 if (priv->cpts->rx_enable)
1458 ctrl |= CTRL_V2_RX_TS_BITS;
1459 break;
1460 case CPSW_VERSION_3:
1461 default:
1462 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1463
1464 if (priv->cpts->tx_enable)
1465 ctrl |= CTRL_V3_TX_TS_BITS;
1466
1467 if (priv->cpts->rx_enable)
1468 ctrl |= CTRL_V3_RX_TS_BITS;
1469 break;
1470 }
1471
1472 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1473
1474 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1475 slave_write(slave, ctrl, CPSW2_CONTROL);
1476 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1477 }
1478
1479 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1480 {
1481 struct cpsw_priv *priv = netdev_priv(dev);
1482 struct cpts *cpts = priv->cpts;
1483 struct hwtstamp_config cfg;
1484
1485 if (priv->version != CPSW_VERSION_1 &&
1486 priv->version != CPSW_VERSION_2 &&
1487 priv->version != CPSW_VERSION_3)
1488 return -EOPNOTSUPP;
1489
1490 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1491 return -EFAULT;
1492
1493 /* reserved for future extensions */
1494 if (cfg.flags)
1495 return -EINVAL;
1496
1497 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1498 return -ERANGE;
1499
1500 switch (cfg.rx_filter) {
1501 case HWTSTAMP_FILTER_NONE:
1502 cpts->rx_enable = 0;
1503 break;
1504 case HWTSTAMP_FILTER_ALL:
1505 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1506 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1507 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1508 return -ERANGE;
1509 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1510 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1511 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1512 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1513 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1514 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1515 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1516 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1517 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1518 cpts->rx_enable = 1;
1519 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1520 break;
1521 default:
1522 return -ERANGE;
1523 }
1524
1525 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1526
1527 switch (priv->version) {
1528 case CPSW_VERSION_1:
1529 cpsw_hwtstamp_v1(priv);
1530 break;
1531 case CPSW_VERSION_2:
1532 case CPSW_VERSION_3:
1533 cpsw_hwtstamp_v2(priv);
1534 break;
1535 default:
1536 WARN_ON(1);
1537 }
1538
1539 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1540 }
1541
1542 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1543 {
1544 struct cpsw_priv *priv = netdev_priv(dev);
1545 struct cpts *cpts = priv->cpts;
1546 struct hwtstamp_config cfg;
1547
1548 if (priv->version != CPSW_VERSION_1 &&
1549 priv->version != CPSW_VERSION_2 &&
1550 priv->version != CPSW_VERSION_3)
1551 return -EOPNOTSUPP;
1552
1553 cfg.flags = 0;
1554 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1555 cfg.rx_filter = (cpts->rx_enable ?
1556 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1557
1558 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1559 }
1560
1561 #endif /*CONFIG_TI_CPTS*/
1562
1563 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1564 {
1565 struct cpsw_priv *priv = netdev_priv(dev);
1566 int slave_no = cpsw_slave_index(priv);
1567
1568 if (!netif_running(dev))
1569 return -EINVAL;
1570
1571 switch (cmd) {
1572 #ifdef CONFIG_TI_CPTS
1573 case SIOCSHWTSTAMP:
1574 return cpsw_hwtstamp_set(dev, req);
1575 case SIOCGHWTSTAMP:
1576 return cpsw_hwtstamp_get(dev, req);
1577 #endif
1578 }
1579
1580 if (!priv->slaves[slave_no].phy)
1581 return -EOPNOTSUPP;
1582 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1583 }
1584
1585 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1586 {
1587 struct cpsw_priv *priv = netdev_priv(ndev);
1588
1589 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1590 ndev->stats.tx_errors++;
1591 cpsw_intr_disable(priv);
1592 cpdma_chan_stop(priv->txch);
1593 cpdma_chan_start(priv->txch);
1594 cpsw_intr_enable(priv);
1595 }
1596
1597 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1598 {
1599 struct cpsw_priv *priv = netdev_priv(ndev);
1600 struct sockaddr *addr = (struct sockaddr *)p;
1601 int flags = 0;
1602 u16 vid = 0;
1603 int ret;
1604
1605 if (!is_valid_ether_addr(addr->sa_data))
1606 return -EADDRNOTAVAIL;
1607
1608 ret = pm_runtime_get_sync(&priv->pdev->dev);
1609 if (ret < 0) {
1610 pm_runtime_put_noidle(&priv->pdev->dev);
1611 return ret;
1612 }
1613
1614 if (priv->data.dual_emac) {
1615 vid = priv->slaves[priv->emac_port].port_vlan;
1616 flags = ALE_VLAN;
1617 }
1618
1619 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
1620 flags, vid);
1621 cpsw_ale_add_ucast(priv->ale, addr->sa_data, HOST_PORT_NUM,
1622 flags, vid);
1623
1624 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1625 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1626 for_each_slave(priv, cpsw_set_slave_mac, priv);
1627
1628 pm_runtime_put(&priv->pdev->dev);
1629
1630 return 0;
1631 }
1632
1633 #ifdef CONFIG_NET_POLL_CONTROLLER
1634 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1635 {
1636 struct cpsw_priv *priv = netdev_priv(ndev);
1637
1638 cpsw_intr_disable(priv);
1639 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1640 cpsw_tx_interrupt(priv->irqs_table[1], priv);
1641 cpsw_intr_enable(priv);
1642 }
1643 #endif
1644
1645 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1646 unsigned short vid)
1647 {
1648 int ret;
1649 int unreg_mcast_mask = 0;
1650 u32 port_mask;
1651
1652 if (priv->data.dual_emac) {
1653 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1654
1655 if (priv->ndev->flags & IFF_ALLMULTI)
1656 unreg_mcast_mask = port_mask;
1657 } else {
1658 port_mask = ALE_ALL_PORTS;
1659
1660 if (priv->ndev->flags & IFF_ALLMULTI)
1661 unreg_mcast_mask = ALE_ALL_PORTS;
1662 else
1663 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1664 }
1665
1666 ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1667 unreg_mcast_mask);
1668 if (ret != 0)
1669 return ret;
1670
1671 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1672 HOST_PORT_NUM, ALE_VLAN, vid);
1673 if (ret != 0)
1674 goto clean_vid;
1675
1676 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1677 port_mask, ALE_VLAN, vid, 0);
1678 if (ret != 0)
1679 goto clean_vlan_ucast;
1680 return 0;
1681
1682 clean_vlan_ucast:
1683 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1684 HOST_PORT_NUM, ALE_VLAN, vid);
1685 clean_vid:
1686 cpsw_ale_del_vlan(priv->ale, vid, 0);
1687 return ret;
1688 }
1689
1690 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1691 __be16 proto, u16 vid)
1692 {
1693 struct cpsw_priv *priv = netdev_priv(ndev);
1694 int ret;
1695
1696 if (vid == priv->data.default_vlan)
1697 return 0;
1698
1699 ret = pm_runtime_get_sync(&priv->pdev->dev);
1700 if (ret < 0) {
1701 pm_runtime_put_noidle(&priv->pdev->dev);
1702 return ret;
1703 }
1704
1705 if (priv->data.dual_emac) {
1706 /* In dual EMAC, reserved VLAN id should not be used for
1707 * creating VLAN interfaces as this can break the dual
1708 * EMAC port separation
1709 */
1710 int i;
1711
1712 for (i = 0; i < priv->data.slaves; i++) {
1713 if (vid == priv->slaves[i].port_vlan)
1714 return -EINVAL;
1715 }
1716 }
1717
1718 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1719 ret = cpsw_add_vlan_ale_entry(priv, vid);
1720
1721 pm_runtime_put(&priv->pdev->dev);
1722 return ret;
1723 }
1724
1725 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1726 __be16 proto, u16 vid)
1727 {
1728 struct cpsw_priv *priv = netdev_priv(ndev);
1729 int ret;
1730
1731 if (vid == priv->data.default_vlan)
1732 return 0;
1733
1734 ret = pm_runtime_get_sync(&priv->pdev->dev);
1735 if (ret < 0) {
1736 pm_runtime_put_noidle(&priv->pdev->dev);
1737 return ret;
1738 }
1739
1740 if (priv->data.dual_emac) {
1741 int i;
1742
1743 for (i = 0; i < priv->data.slaves; i++) {
1744 if (vid == priv->slaves[i].port_vlan)
1745 return -EINVAL;
1746 }
1747 }
1748
1749 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1750 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1751 if (ret != 0)
1752 return ret;
1753
1754 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1755 HOST_PORT_NUM, ALE_VLAN, vid);
1756 if (ret != 0)
1757 return ret;
1758
1759 ret = cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1760 0, ALE_VLAN, vid);
1761 pm_runtime_put(&priv->pdev->dev);
1762 return ret;
1763 }
1764
1765 static const struct net_device_ops cpsw_netdev_ops = {
1766 .ndo_open = cpsw_ndo_open,
1767 .ndo_stop = cpsw_ndo_stop,
1768 .ndo_start_xmit = cpsw_ndo_start_xmit,
1769 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
1770 .ndo_do_ioctl = cpsw_ndo_ioctl,
1771 .ndo_validate_addr = eth_validate_addr,
1772 .ndo_change_mtu = eth_change_mtu,
1773 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1774 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
1775 #ifdef CONFIG_NET_POLL_CONTROLLER
1776 .ndo_poll_controller = cpsw_ndo_poll_controller,
1777 #endif
1778 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1779 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
1780 };
1781
1782 static int cpsw_get_regs_len(struct net_device *ndev)
1783 {
1784 struct cpsw_priv *priv = netdev_priv(ndev);
1785
1786 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1787 }
1788
1789 static void cpsw_get_regs(struct net_device *ndev,
1790 struct ethtool_regs *regs, void *p)
1791 {
1792 struct cpsw_priv *priv = netdev_priv(ndev);
1793 u32 *reg = p;
1794
1795 /* update CPSW IP version */
1796 regs->version = priv->version;
1797
1798 cpsw_ale_dump(priv->ale, reg);
1799 }
1800
1801 static void cpsw_get_drvinfo(struct net_device *ndev,
1802 struct ethtool_drvinfo *info)
1803 {
1804 struct cpsw_priv *priv = netdev_priv(ndev);
1805
1806 strlcpy(info->driver, "cpsw", sizeof(info->driver));
1807 strlcpy(info->version, "1.0", sizeof(info->version));
1808 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1809 }
1810
1811 static u32 cpsw_get_msglevel(struct net_device *ndev)
1812 {
1813 struct cpsw_priv *priv = netdev_priv(ndev);
1814 return priv->msg_enable;
1815 }
1816
1817 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1818 {
1819 struct cpsw_priv *priv = netdev_priv(ndev);
1820 priv->msg_enable = value;
1821 }
1822
1823 static int cpsw_get_ts_info(struct net_device *ndev,
1824 struct ethtool_ts_info *info)
1825 {
1826 #ifdef CONFIG_TI_CPTS
1827 struct cpsw_priv *priv = netdev_priv(ndev);
1828
1829 info->so_timestamping =
1830 SOF_TIMESTAMPING_TX_HARDWARE |
1831 SOF_TIMESTAMPING_TX_SOFTWARE |
1832 SOF_TIMESTAMPING_RX_HARDWARE |
1833 SOF_TIMESTAMPING_RX_SOFTWARE |
1834 SOF_TIMESTAMPING_SOFTWARE |
1835 SOF_TIMESTAMPING_RAW_HARDWARE;
1836 info->phc_index = priv->cpts->phc_index;
1837 info->tx_types =
1838 (1 << HWTSTAMP_TX_OFF) |
1839 (1 << HWTSTAMP_TX_ON);
1840 info->rx_filters =
1841 (1 << HWTSTAMP_FILTER_NONE) |
1842 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1843 #else
1844 info->so_timestamping =
1845 SOF_TIMESTAMPING_TX_SOFTWARE |
1846 SOF_TIMESTAMPING_RX_SOFTWARE |
1847 SOF_TIMESTAMPING_SOFTWARE;
1848 info->phc_index = -1;
1849 info->tx_types = 0;
1850 info->rx_filters = 0;
1851 #endif
1852 return 0;
1853 }
1854
1855 static int cpsw_get_settings(struct net_device *ndev,
1856 struct ethtool_cmd *ecmd)
1857 {
1858 struct cpsw_priv *priv = netdev_priv(ndev);
1859 int slave_no = cpsw_slave_index(priv);
1860
1861 if (priv->slaves[slave_no].phy)
1862 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1863 else
1864 return -EOPNOTSUPP;
1865 }
1866
1867 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1868 {
1869 struct cpsw_priv *priv = netdev_priv(ndev);
1870 int slave_no = cpsw_slave_index(priv);
1871
1872 if (priv->slaves[slave_no].phy)
1873 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1874 else
1875 return -EOPNOTSUPP;
1876 }
1877
1878 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1879 {
1880 struct cpsw_priv *priv = netdev_priv(ndev);
1881 int slave_no = cpsw_slave_index(priv);
1882
1883 wol->supported = 0;
1884 wol->wolopts = 0;
1885
1886 if (priv->slaves[slave_no].phy)
1887 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1888 }
1889
1890 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1891 {
1892 struct cpsw_priv *priv = netdev_priv(ndev);
1893 int slave_no = cpsw_slave_index(priv);
1894
1895 if (priv->slaves[slave_no].phy)
1896 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1897 else
1898 return -EOPNOTSUPP;
1899 }
1900
1901 static void cpsw_get_pauseparam(struct net_device *ndev,
1902 struct ethtool_pauseparam *pause)
1903 {
1904 struct cpsw_priv *priv = netdev_priv(ndev);
1905
1906 pause->autoneg = AUTONEG_DISABLE;
1907 pause->rx_pause = priv->rx_pause ? true : false;
1908 pause->tx_pause = priv->tx_pause ? true : false;
1909 }
1910
1911 static int cpsw_set_pauseparam(struct net_device *ndev,
1912 struct ethtool_pauseparam *pause)
1913 {
1914 struct cpsw_priv *priv = netdev_priv(ndev);
1915 bool link;
1916
1917 priv->rx_pause = pause->rx_pause ? true : false;
1918 priv->tx_pause = pause->tx_pause ? true : false;
1919
1920 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1921 return 0;
1922 }
1923
1924 static int cpsw_ethtool_op_begin(struct net_device *ndev)
1925 {
1926 struct cpsw_priv *priv = netdev_priv(ndev);
1927 int ret;
1928
1929 ret = pm_runtime_get_sync(&priv->pdev->dev);
1930 if (ret < 0) {
1931 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
1932 pm_runtime_put_noidle(&priv->pdev->dev);
1933 }
1934
1935 return ret;
1936 }
1937
1938 static void cpsw_ethtool_op_complete(struct net_device *ndev)
1939 {
1940 struct cpsw_priv *priv = netdev_priv(ndev);
1941 int ret;
1942
1943 ret = pm_runtime_put(&priv->pdev->dev);
1944 if (ret < 0)
1945 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
1946 }
1947
1948 static const struct ethtool_ops cpsw_ethtool_ops = {
1949 .get_drvinfo = cpsw_get_drvinfo,
1950 .get_msglevel = cpsw_get_msglevel,
1951 .set_msglevel = cpsw_set_msglevel,
1952 .get_link = ethtool_op_get_link,
1953 .get_ts_info = cpsw_get_ts_info,
1954 .get_settings = cpsw_get_settings,
1955 .set_settings = cpsw_set_settings,
1956 .get_coalesce = cpsw_get_coalesce,
1957 .set_coalesce = cpsw_set_coalesce,
1958 .get_sset_count = cpsw_get_sset_count,
1959 .get_strings = cpsw_get_strings,
1960 .get_ethtool_stats = cpsw_get_ethtool_stats,
1961 .get_pauseparam = cpsw_get_pauseparam,
1962 .set_pauseparam = cpsw_set_pauseparam,
1963 .get_wol = cpsw_get_wol,
1964 .set_wol = cpsw_set_wol,
1965 .get_regs_len = cpsw_get_regs_len,
1966 .get_regs = cpsw_get_regs,
1967 .begin = cpsw_ethtool_op_begin,
1968 .complete = cpsw_ethtool_op_complete,
1969 };
1970
1971 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1972 u32 slave_reg_ofs, u32 sliver_reg_ofs)
1973 {
1974 void __iomem *regs = priv->regs;
1975 int slave_num = slave->slave_num;
1976 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1977
1978 slave->data = data;
1979 slave->regs = regs + slave_reg_ofs;
1980 slave->sliver = regs + sliver_reg_ofs;
1981 slave->port_vlan = data->dual_emac_res_vlan;
1982 }
1983
1984 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1985 struct platform_device *pdev)
1986 {
1987 struct device_node *node = pdev->dev.of_node;
1988 struct device_node *slave_node;
1989 int i = 0, ret;
1990 u32 prop;
1991
1992 if (!node)
1993 return -EINVAL;
1994
1995 if (of_property_read_u32(node, "slaves", &prop)) {
1996 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1997 return -EINVAL;
1998 }
1999 data->slaves = prop;
2000
2001 if (of_property_read_u32(node, "active_slave", &prop)) {
2002 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2003 return -EINVAL;
2004 }
2005 data->active_slave = prop;
2006
2007 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
2008 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
2009 return -EINVAL;
2010 }
2011 data->cpts_clock_mult = prop;
2012
2013 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
2014 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
2015 return -EINVAL;
2016 }
2017 data->cpts_clock_shift = prop;
2018
2019 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2020 * sizeof(struct cpsw_slave_data),
2021 GFP_KERNEL);
2022 if (!data->slave_data)
2023 return -ENOMEM;
2024
2025 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2026 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2027 return -EINVAL;
2028 }
2029 data->channels = prop;
2030
2031 if (of_property_read_u32(node, "ale_entries", &prop)) {
2032 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2033 return -EINVAL;
2034 }
2035 data->ale_entries = prop;
2036
2037 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2038 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2039 return -EINVAL;
2040 }
2041 data->bd_ram_size = prop;
2042
2043 if (of_property_read_u32(node, "mac_control", &prop)) {
2044 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2045 return -EINVAL;
2046 }
2047 data->mac_control = prop;
2048
2049 if (of_property_read_bool(node, "dual_emac"))
2050 data->dual_emac = 1;
2051
2052 /*
2053 * Populate all the child nodes here...
2054 */
2055 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2056 /* We do not want to force this, as in some cases may not have child */
2057 if (ret)
2058 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2059
2060 for_each_available_child_of_node(node, slave_node) {
2061 struct cpsw_slave_data *slave_data = data->slave_data + i;
2062 const void *mac_addr = NULL;
2063 int lenp;
2064 const __be32 *parp;
2065
2066 /* This is no slave child node, continue */
2067 if (strcmp(slave_node->name, "slave"))
2068 continue;
2069
2070 slave_data->phy_node = of_parse_phandle(slave_node,
2071 "phy-handle", 0);
2072 parp = of_get_property(slave_node, "phy_id", &lenp);
2073 if (slave_data->phy_node) {
2074 dev_dbg(&pdev->dev,
2075 "slave[%d] using phy-handle=\"%s\"\n",
2076 i, slave_data->phy_node->full_name);
2077 } else if (of_phy_is_fixed_link(slave_node)) {
2078 /* In the case of a fixed PHY, the DT node associated
2079 * to the PHY is the Ethernet MAC DT node.
2080 */
2081 ret = of_phy_register_fixed_link(slave_node);
2082 if (ret)
2083 return ret;
2084 slave_data->phy_node = of_node_get(slave_node);
2085 } else if (parp) {
2086 u32 phyid;
2087 struct device_node *mdio_node;
2088 struct platform_device *mdio;
2089
2090 if (lenp != (sizeof(__be32) * 2)) {
2091 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2092 goto no_phy_slave;
2093 }
2094 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2095 phyid = be32_to_cpup(parp+1);
2096 mdio = of_find_device_by_node(mdio_node);
2097 of_node_put(mdio_node);
2098 if (!mdio) {
2099 dev_err(&pdev->dev, "Missing mdio platform device\n");
2100 return -EINVAL;
2101 }
2102 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2103 PHY_ID_FMT, mdio->name, phyid);
2104 } else {
2105 dev_err(&pdev->dev,
2106 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2107 i);
2108 goto no_phy_slave;
2109 }
2110 slave_data->phy_if = of_get_phy_mode(slave_node);
2111 if (slave_data->phy_if < 0) {
2112 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2113 i);
2114 return slave_data->phy_if;
2115 }
2116
2117 no_phy_slave:
2118 mac_addr = of_get_mac_address(slave_node);
2119 if (mac_addr) {
2120 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2121 } else {
2122 ret = ti_cm_get_macid(&pdev->dev, i,
2123 slave_data->mac_addr);
2124 if (ret)
2125 return ret;
2126 }
2127 if (data->dual_emac) {
2128 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2129 &prop)) {
2130 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2131 slave_data->dual_emac_res_vlan = i+1;
2132 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2133 slave_data->dual_emac_res_vlan, i);
2134 } else {
2135 slave_data->dual_emac_res_vlan = prop;
2136 }
2137 }
2138
2139 i++;
2140 if (i == data->slaves)
2141 break;
2142 }
2143
2144 return 0;
2145 }
2146
2147 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2148 struct cpsw_priv *priv)
2149 {
2150 struct cpsw_platform_data *data = &priv->data;
2151 struct net_device *ndev;
2152 struct cpsw_priv *priv_sl2;
2153 int ret = 0, i;
2154
2155 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2156 if (!ndev) {
2157 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2158 return -ENOMEM;
2159 }
2160
2161 priv_sl2 = netdev_priv(ndev);
2162 priv_sl2->data = *data;
2163 priv_sl2->pdev = pdev;
2164 priv_sl2->ndev = ndev;
2165 priv_sl2->dev = &ndev->dev;
2166 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2167 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2168
2169 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2170 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2171 ETH_ALEN);
2172 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2173 } else {
2174 random_ether_addr(priv_sl2->mac_addr);
2175 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2176 }
2177 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2178
2179 priv_sl2->slaves = priv->slaves;
2180 priv_sl2->clk = priv->clk;
2181
2182 priv_sl2->coal_intvl = 0;
2183 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2184
2185 priv_sl2->regs = priv->regs;
2186 priv_sl2->host_port_regs = priv->host_port_regs;
2187 priv_sl2->wr_regs = priv->wr_regs;
2188 priv_sl2->hw_stats = priv->hw_stats;
2189 priv_sl2->dma = priv->dma;
2190 priv_sl2->txch = priv->txch;
2191 priv_sl2->rxch = priv->rxch;
2192 priv_sl2->ale = priv->ale;
2193 priv_sl2->emac_port = 1;
2194 priv->slaves[1].ndev = ndev;
2195 priv_sl2->cpts = priv->cpts;
2196 priv_sl2->version = priv->version;
2197
2198 for (i = 0; i < priv->num_irqs; i++) {
2199 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2200 priv_sl2->num_irqs = priv->num_irqs;
2201 }
2202 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2203
2204 ndev->netdev_ops = &cpsw_netdev_ops;
2205 ndev->ethtool_ops = &cpsw_ethtool_ops;
2206
2207 /* register the network device */
2208 SET_NETDEV_DEV(ndev, &pdev->dev);
2209 ret = register_netdev(ndev);
2210 if (ret) {
2211 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2212 free_netdev(ndev);
2213 ret = -ENODEV;
2214 }
2215
2216 return ret;
2217 }
2218
2219 #define CPSW_QUIRK_IRQ BIT(0)
2220
2221 static struct platform_device_id cpsw_devtype[] = {
2222 {
2223 /* keep it for existing comaptibles */
2224 .name = "cpsw",
2225 .driver_data = CPSW_QUIRK_IRQ,
2226 }, {
2227 .name = "am335x-cpsw",
2228 .driver_data = CPSW_QUIRK_IRQ,
2229 }, {
2230 .name = "am4372-cpsw",
2231 .driver_data = 0,
2232 }, {
2233 .name = "dra7-cpsw",
2234 .driver_data = 0,
2235 }, {
2236 /* sentinel */
2237 }
2238 };
2239 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2240
2241 enum ti_cpsw_type {
2242 CPSW = 0,
2243 AM335X_CPSW,
2244 AM4372_CPSW,
2245 DRA7_CPSW,
2246 };
2247
2248 static const struct of_device_id cpsw_of_mtable[] = {
2249 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2250 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2251 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2252 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2253 { /* sentinel */ },
2254 };
2255 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2256
2257 static int cpsw_probe(struct platform_device *pdev)
2258 {
2259 struct cpsw_platform_data *data;
2260 struct net_device *ndev;
2261 struct cpsw_priv *priv;
2262 struct cpdma_params dma_params;
2263 struct cpsw_ale_params ale_params;
2264 void __iomem *ss_regs;
2265 struct resource *res, *ss_res;
2266 const struct of_device_id *of_id;
2267 struct gpio_descs *mode;
2268 u32 slave_offset, sliver_offset, slave_size;
2269 int ret = 0, i;
2270 int irq;
2271
2272 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2273 if (!ndev) {
2274 dev_err(&pdev->dev, "error allocating net_device\n");
2275 return -ENOMEM;
2276 }
2277
2278 platform_set_drvdata(pdev, ndev);
2279 priv = netdev_priv(ndev);
2280 priv->pdev = pdev;
2281 priv->ndev = ndev;
2282 priv->dev = &ndev->dev;
2283 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2284 priv->rx_packet_max = max(rx_packet_max, 128);
2285 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2286 if (!priv->cpts) {
2287 dev_err(&pdev->dev, "error allocating cpts\n");
2288 ret = -ENOMEM;
2289 goto clean_ndev_ret;
2290 }
2291
2292 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2293 if (IS_ERR(mode)) {
2294 ret = PTR_ERR(mode);
2295 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2296 goto clean_ndev_ret;
2297 }
2298
2299 /*
2300 * This may be required here for child devices.
2301 */
2302 pm_runtime_enable(&pdev->dev);
2303
2304 /* Select default pin state */
2305 pinctrl_pm_select_default_state(&pdev->dev);
2306
2307 if (cpsw_probe_dt(&priv->data, pdev)) {
2308 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2309 ret = -ENODEV;
2310 goto clean_runtime_disable_ret;
2311 }
2312 data = &priv->data;
2313
2314 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2315 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2316 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2317 } else {
2318 eth_random_addr(priv->mac_addr);
2319 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2320 }
2321
2322 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2323
2324 priv->slaves = devm_kzalloc(&pdev->dev,
2325 sizeof(struct cpsw_slave) * data->slaves,
2326 GFP_KERNEL);
2327 if (!priv->slaves) {
2328 ret = -ENOMEM;
2329 goto clean_runtime_disable_ret;
2330 }
2331 for (i = 0; i < data->slaves; i++)
2332 priv->slaves[i].slave_num = i;
2333
2334 priv->slaves[0].ndev = ndev;
2335 priv->emac_port = 0;
2336
2337 priv->clk = devm_clk_get(&pdev->dev, "fck");
2338 if (IS_ERR(priv->clk)) {
2339 dev_err(priv->dev, "fck is not found\n");
2340 ret = -ENODEV;
2341 goto clean_runtime_disable_ret;
2342 }
2343 priv->coal_intvl = 0;
2344 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2345
2346 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2347 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2348 if (IS_ERR(ss_regs)) {
2349 ret = PTR_ERR(ss_regs);
2350 goto clean_runtime_disable_ret;
2351 }
2352 priv->regs = ss_regs;
2353
2354 /* Need to enable clocks with runtime PM api to access module
2355 * registers
2356 */
2357 ret = pm_runtime_get_sync(&pdev->dev);
2358 if (ret < 0) {
2359 pm_runtime_put_noidle(&pdev->dev);
2360 goto clean_runtime_disable_ret;
2361 }
2362 priv->version = readl(&priv->regs->id_ver);
2363 pm_runtime_put_sync(&pdev->dev);
2364
2365 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2366 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2367 if (IS_ERR(priv->wr_regs)) {
2368 ret = PTR_ERR(priv->wr_regs);
2369 goto clean_runtime_disable_ret;
2370 }
2371
2372 memset(&dma_params, 0, sizeof(dma_params));
2373 memset(&ale_params, 0, sizeof(ale_params));
2374
2375 switch (priv->version) {
2376 case CPSW_VERSION_1:
2377 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2378 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2379 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
2380 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2381 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2382 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2383 slave_offset = CPSW1_SLAVE_OFFSET;
2384 slave_size = CPSW1_SLAVE_SIZE;
2385 sliver_offset = CPSW1_SLIVER_OFFSET;
2386 dma_params.desc_mem_phys = 0;
2387 break;
2388 case CPSW_VERSION_2:
2389 case CPSW_VERSION_3:
2390 case CPSW_VERSION_4:
2391 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2392 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2393 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
2394 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2395 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2396 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2397 slave_offset = CPSW2_SLAVE_OFFSET;
2398 slave_size = CPSW2_SLAVE_SIZE;
2399 sliver_offset = CPSW2_SLIVER_OFFSET;
2400 dma_params.desc_mem_phys =
2401 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2402 break;
2403 default:
2404 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2405 ret = -ENODEV;
2406 goto clean_runtime_disable_ret;
2407 }
2408 for (i = 0; i < priv->data.slaves; i++) {
2409 struct cpsw_slave *slave = &priv->slaves[i];
2410 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2411 slave_offset += slave_size;
2412 sliver_offset += SLIVER_SIZE;
2413 }
2414
2415 dma_params.dev = &pdev->dev;
2416 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2417 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2418 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2419 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2420 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
2421
2422 dma_params.num_chan = data->channels;
2423 dma_params.has_soft_reset = true;
2424 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2425 dma_params.desc_mem_size = data->bd_ram_size;
2426 dma_params.desc_align = 16;
2427 dma_params.has_ext_regs = true;
2428 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
2429
2430 priv->dma = cpdma_ctlr_create(&dma_params);
2431 if (!priv->dma) {
2432 dev_err(priv->dev, "error initializing dma\n");
2433 ret = -ENOMEM;
2434 goto clean_runtime_disable_ret;
2435 }
2436
2437 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2438 cpsw_tx_handler);
2439 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2440 cpsw_rx_handler);
2441
2442 if (WARN_ON(!priv->txch || !priv->rxch)) {
2443 dev_err(priv->dev, "error initializing dma channels\n");
2444 ret = -ENOMEM;
2445 goto clean_dma_ret;
2446 }
2447
2448 ale_params.dev = &ndev->dev;
2449 ale_params.ale_ageout = ale_ageout;
2450 ale_params.ale_entries = data->ale_entries;
2451 ale_params.ale_ports = data->slaves;
2452
2453 priv->ale = cpsw_ale_create(&ale_params);
2454 if (!priv->ale) {
2455 dev_err(priv->dev, "error initializing ale engine\n");
2456 ret = -ENODEV;
2457 goto clean_dma_ret;
2458 }
2459
2460 ndev->irq = platform_get_irq(pdev, 1);
2461 if (ndev->irq < 0) {
2462 dev_err(priv->dev, "error getting irq resource\n");
2463 ret = ndev->irq;
2464 goto clean_ale_ret;
2465 }
2466
2467 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2468 if (of_id) {
2469 pdev->id_entry = of_id->data;
2470 if (pdev->id_entry->driver_data)
2471 priv->quirk_irq = true;
2472 }
2473
2474 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2475 * MISC IRQs which are always kept disabled with this driver so
2476 * we will not request them.
2477 *
2478 * If anyone wants to implement support for those, make sure to
2479 * first request and append them to irqs_table array.
2480 */
2481
2482 /* RX IRQ */
2483 irq = platform_get_irq(pdev, 1);
2484 if (irq < 0) {
2485 ret = irq;
2486 goto clean_ale_ret;
2487 }
2488
2489 priv->irqs_table[0] = irq;
2490 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2491 0, dev_name(&pdev->dev), priv);
2492 if (ret < 0) {
2493 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2494 goto clean_ale_ret;
2495 }
2496
2497 /* TX IRQ */
2498 irq = platform_get_irq(pdev, 2);
2499 if (irq < 0) {
2500 ret = irq;
2501 goto clean_ale_ret;
2502 }
2503
2504 priv->irqs_table[1] = irq;
2505 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2506 0, dev_name(&pdev->dev), priv);
2507 if (ret < 0) {
2508 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2509 goto clean_ale_ret;
2510 }
2511 priv->num_irqs = 2;
2512
2513 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2514
2515 ndev->netdev_ops = &cpsw_netdev_ops;
2516 ndev->ethtool_ops = &cpsw_ethtool_ops;
2517 netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2518 netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2519
2520 /* register the network device */
2521 SET_NETDEV_DEV(ndev, &pdev->dev);
2522 ret = register_netdev(ndev);
2523 if (ret) {
2524 dev_err(priv->dev, "error registering net device\n");
2525 ret = -ENODEV;
2526 goto clean_ale_ret;
2527 }
2528
2529 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2530 &ss_res->start, ndev->irq);
2531
2532 if (priv->data.dual_emac) {
2533 ret = cpsw_probe_dual_emac(pdev, priv);
2534 if (ret) {
2535 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2536 goto clean_ale_ret;
2537 }
2538 }
2539
2540 return 0;
2541
2542 clean_ale_ret:
2543 cpsw_ale_destroy(priv->ale);
2544 clean_dma_ret:
2545 cpdma_ctlr_destroy(priv->dma);
2546 clean_runtime_disable_ret:
2547 pm_runtime_disable(&pdev->dev);
2548 clean_ndev_ret:
2549 free_netdev(priv->ndev);
2550 return ret;
2551 }
2552
2553 static int cpsw_remove(struct platform_device *pdev)
2554 {
2555 struct net_device *ndev = platform_get_drvdata(pdev);
2556 struct cpsw_priv *priv = netdev_priv(ndev);
2557 int ret;
2558
2559 ret = pm_runtime_get_sync(&pdev->dev);
2560 if (ret < 0) {
2561 pm_runtime_put_noidle(&pdev->dev);
2562 return ret;
2563 }
2564
2565 if (priv->data.dual_emac)
2566 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2567 unregister_netdev(ndev);
2568
2569 cpsw_ale_destroy(priv->ale);
2570 cpdma_ctlr_destroy(priv->dma);
2571 of_platform_depopulate(&pdev->dev);
2572 pm_runtime_put_sync(&pdev->dev);
2573 pm_runtime_disable(&pdev->dev);
2574 if (priv->data.dual_emac)
2575 free_netdev(cpsw_get_slave_ndev(priv, 1));
2576 free_netdev(ndev);
2577 return 0;
2578 }
2579
2580 #ifdef CONFIG_PM_SLEEP
2581 static int cpsw_suspend(struct device *dev)
2582 {
2583 struct platform_device *pdev = to_platform_device(dev);
2584 struct net_device *ndev = platform_get_drvdata(pdev);
2585 struct cpsw_priv *priv = netdev_priv(ndev);
2586
2587 if (priv->data.dual_emac) {
2588 int i;
2589
2590 for (i = 0; i < priv->data.slaves; i++) {
2591 if (netif_running(priv->slaves[i].ndev))
2592 cpsw_ndo_stop(priv->slaves[i].ndev);
2593 }
2594 } else {
2595 if (netif_running(ndev))
2596 cpsw_ndo_stop(ndev);
2597 }
2598
2599 /* Select sleep pin state */
2600 pinctrl_pm_select_sleep_state(&pdev->dev);
2601
2602 return 0;
2603 }
2604
2605 static int cpsw_resume(struct device *dev)
2606 {
2607 struct platform_device *pdev = to_platform_device(dev);
2608 struct net_device *ndev = platform_get_drvdata(pdev);
2609 struct cpsw_priv *priv = netdev_priv(ndev);
2610
2611 /* Select default pin state */
2612 pinctrl_pm_select_default_state(&pdev->dev);
2613
2614 if (priv->data.dual_emac) {
2615 int i;
2616
2617 for (i = 0; i < priv->data.slaves; i++) {
2618 if (netif_running(priv->slaves[i].ndev))
2619 cpsw_ndo_open(priv->slaves[i].ndev);
2620 }
2621 } else {
2622 if (netif_running(ndev))
2623 cpsw_ndo_open(ndev);
2624 }
2625 return 0;
2626 }
2627 #endif
2628
2629 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2630
2631 static struct platform_driver cpsw_driver = {
2632 .driver = {
2633 .name = "cpsw",
2634 .pm = &cpsw_pm_ops,
2635 .of_match_table = cpsw_of_mtable,
2636 },
2637 .probe = cpsw_probe,
2638 .remove = cpsw_remove,
2639 };
2640
2641 module_platform_driver(cpsw_driver);
2642
2643 MODULE_LICENSE("GPL");
2644 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2645 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2646 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
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