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net: ethernet: ti: cpsw: remove unused priv lock
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / ti / cpsw.c
1 /*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio.h>
33 #include <linux/of.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
38
39 #include <linux/pinctrl/consumer.h>
40
41 #include "cpsw.h"
42 #include "cpsw_ale.h"
43 #include "cpts.h"
44 #include "davinci_cpdma.h"
45
46 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55 #define cpsw_info(priv, type, format, ...) \
56 do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59 } while (0)
60
61 #define cpsw_err(priv, type, format, ...) \
62 do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65 } while (0)
66
67 #define cpsw_dbg(priv, type, format, ...) \
68 do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71 } while (0)
72
73 #define cpsw_notice(priv, type, format, ...) \
74 do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77 } while (0)
78
79 #define ALE_ALL_PORTS 0x7
80
81 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
85 #define CPSW_VERSION_1 0x19010a
86 #define CPSW_VERSION_2 0x19010c
87 #define CPSW_VERSION_3 0x19010f
88 #define CPSW_VERSION_4 0x190112
89
90 #define HOST_PORT_NUM 0
91 #define SLIVER_SIZE 0x40
92
93 #define CPSW1_HOST_PORT_OFFSET 0x028
94 #define CPSW1_SLAVE_OFFSET 0x050
95 #define CPSW1_SLAVE_SIZE 0x040
96 #define CPSW1_CPDMA_OFFSET 0x100
97 #define CPSW1_STATERAM_OFFSET 0x200
98 #define CPSW1_HW_STATS 0x400
99 #define CPSW1_CPTS_OFFSET 0x500
100 #define CPSW1_ALE_OFFSET 0x600
101 #define CPSW1_SLIVER_OFFSET 0x700
102
103 #define CPSW2_HOST_PORT_OFFSET 0x108
104 #define CPSW2_SLAVE_OFFSET 0x200
105 #define CPSW2_SLAVE_SIZE 0x100
106 #define CPSW2_CPDMA_OFFSET 0x800
107 #define CPSW2_HW_STATS 0x900
108 #define CPSW2_STATERAM_OFFSET 0xa00
109 #define CPSW2_CPTS_OFFSET 0xc00
110 #define CPSW2_ALE_OFFSET 0xd00
111 #define CPSW2_SLIVER_OFFSET 0xd80
112 #define CPSW2_BD_OFFSET 0x2000
113
114 #define CPDMA_RXTHRESH 0x0c0
115 #define CPDMA_RXFREE 0x0e0
116 #define CPDMA_TXHDP 0x00
117 #define CPDMA_RXHDP 0x20
118 #define CPDMA_TXCP 0x40
119 #define CPDMA_RXCP 0x60
120
121 #define CPSW_POLL_WEIGHT 64
122 #define CPSW_MIN_PACKET_SIZE 60
123 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125 #define RX_PRIORITY_MAPPING 0x76543210
126 #define TX_PRIORITY_MAPPING 0x33221100
127 #define CPDMA_TX_PRIORITY_MAP 0x76543210
128
129 #define CPSW_VLAN_AWARE BIT(1)
130 #define CPSW_ALE_VLAN_AWARE 1
131
132 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
135
136 #define CPSW_INTPACEEN (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT 63
139 #define CPSW_CMINTMIN_CNT 2
140 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
143 #define cpsw_slave_index(priv) \
144 ((priv->data.dual_emac) ? priv->emac_port : \
145 priv->data.active_slave)
146
147 static int debug_level;
148 module_param(debug_level, int, 0);
149 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
150
151 static int ale_ageout = 10;
152 module_param(ale_ageout, int, 0);
153 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
154
155 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
156 module_param(rx_packet_max, int, 0);
157 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
158
159 struct cpsw_wr_regs {
160 u32 id_ver;
161 u32 soft_reset;
162 u32 control;
163 u32 int_control;
164 u32 rx_thresh_en;
165 u32 rx_en;
166 u32 tx_en;
167 u32 misc_en;
168 u32 mem_allign1[8];
169 u32 rx_thresh_stat;
170 u32 rx_stat;
171 u32 tx_stat;
172 u32 misc_stat;
173 u32 mem_allign2[8];
174 u32 rx_imax;
175 u32 tx_imax;
176
177 };
178
179 struct cpsw_ss_regs {
180 u32 id_ver;
181 u32 control;
182 u32 soft_reset;
183 u32 stat_port_en;
184 u32 ptype;
185 u32 soft_idle;
186 u32 thru_rate;
187 u32 gap_thresh;
188 u32 tx_start_wds;
189 u32 flow_control;
190 u32 vlan_ltype;
191 u32 ts_ltype;
192 u32 dlr_ltype;
193 };
194
195 /* CPSW_PORT_V1 */
196 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
197 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
198 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
199 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
200 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
201 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
202 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
203 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
204
205 /* CPSW_PORT_V2 */
206 #define CPSW2_CONTROL 0x00 /* Control Register */
207 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
208 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
209 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
210 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
211 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
212 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
213
214 /* CPSW_PORT_V1 and V2 */
215 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
216 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
217 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
218
219 /* CPSW_PORT_V2 only */
220 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
221 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
222 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
226 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
227 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
228
229 /* Bit definitions for the CPSW2_CONTROL register */
230 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
231 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
232 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
233 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
234 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
235 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
236 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
237 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
238 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
239 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
240 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
241 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
242 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
243 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
244 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
245 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
246 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
247
248 #define CTRL_V2_TS_BITS \
249 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
250 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
251
252 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
253 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
254 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
255
256
257 #define CTRL_V3_TS_BITS \
258 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
259 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
260 TS_LTYPE1_EN)
261
262 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
263 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
264 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
265
266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
269 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270 #define TS_MSG_TYPE_EN_MASK (0xffff)
271
272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
274
275 /* Bit definitions for the CPSW1_TS_CTL register */
276 #define CPSW_V1_TS_RX_EN BIT(0)
277 #define CPSW_V1_TS_TX_EN BIT(4)
278 #define CPSW_V1_MSG_TYPE_OFS 16
279
280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
282
283 struct cpsw_host_regs {
284 u32 max_blks;
285 u32 blk_cnt;
286 u32 tx_in_ctl;
287 u32 port_vlan;
288 u32 tx_pri_map;
289 u32 cpdma_tx_pri_map;
290 u32 cpdma_rx_chan_map;
291 };
292
293 struct cpsw_sliver_regs {
294 u32 id_ver;
295 u32 mac_control;
296 u32 mac_status;
297 u32 soft_reset;
298 u32 rx_maxlen;
299 u32 __reserved_0;
300 u32 rx_pause;
301 u32 tx_pause;
302 u32 __reserved_1;
303 u32 rx_pri_map;
304 };
305
306 struct cpsw_hw_stats {
307 u32 rxgoodframes;
308 u32 rxbroadcastframes;
309 u32 rxmulticastframes;
310 u32 rxpauseframes;
311 u32 rxcrcerrors;
312 u32 rxaligncodeerrors;
313 u32 rxoversizedframes;
314 u32 rxjabberframes;
315 u32 rxundersizedframes;
316 u32 rxfragments;
317 u32 __pad_0[2];
318 u32 rxoctets;
319 u32 txgoodframes;
320 u32 txbroadcastframes;
321 u32 txmulticastframes;
322 u32 txpauseframes;
323 u32 txdeferredframes;
324 u32 txcollisionframes;
325 u32 txsinglecollframes;
326 u32 txmultcollframes;
327 u32 txexcessivecollisions;
328 u32 txlatecollisions;
329 u32 txunderrun;
330 u32 txcarriersenseerrors;
331 u32 txoctets;
332 u32 octetframes64;
333 u32 octetframes65t127;
334 u32 octetframes128t255;
335 u32 octetframes256t511;
336 u32 octetframes512t1023;
337 u32 octetframes1024tup;
338 u32 netoctets;
339 u32 rxsofoverruns;
340 u32 rxmofoverruns;
341 u32 rxdmaoverruns;
342 };
343
344 struct cpsw_slave {
345 void __iomem *regs;
346 struct cpsw_sliver_regs __iomem *sliver;
347 int slave_num;
348 u32 mac_control;
349 struct cpsw_slave_data *data;
350 struct phy_device *phy;
351 struct net_device *ndev;
352 u32 port_vlan;
353 u32 open_stat;
354 };
355
356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
357 {
358 return __raw_readl(slave->regs + offset);
359 }
360
361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
362 {
363 __raw_writel(val, slave->regs + offset);
364 }
365
366 struct cpsw_priv {
367 struct platform_device *pdev;
368 struct net_device *ndev;
369 struct napi_struct napi_rx;
370 struct napi_struct napi_tx;
371 struct device *dev;
372 struct cpsw_platform_data data;
373 struct cpsw_ss_regs __iomem *regs;
374 struct cpsw_wr_regs __iomem *wr_regs;
375 u8 __iomem *hw_stats;
376 struct cpsw_host_regs __iomem *host_port_regs;
377 u32 msg_enable;
378 u32 version;
379 u32 coal_intvl;
380 u32 bus_freq_mhz;
381 int rx_packet_max;
382 struct clk *clk;
383 u8 mac_addr[ETH_ALEN];
384 struct cpsw_slave *slaves;
385 struct cpdma_ctlr *dma;
386 struct cpdma_chan *txch, *rxch;
387 struct cpsw_ale *ale;
388 bool rx_pause;
389 bool tx_pause;
390 bool quirk_irq;
391 bool rx_irq_disabled;
392 bool tx_irq_disabled;
393 /* snapshot of IRQ numbers */
394 u32 irqs_table[4];
395 u32 num_irqs;
396 struct cpts *cpts;
397 u32 emac_port;
398 };
399
400 struct cpsw_stats {
401 char stat_string[ETH_GSTRING_LEN];
402 int type;
403 int sizeof_stat;
404 int stat_offset;
405 };
406
407 enum {
408 CPSW_STATS,
409 CPDMA_RX_STATS,
410 CPDMA_TX_STATS,
411 };
412
413 #define CPSW_STAT(m) CPSW_STATS, \
414 sizeof(((struct cpsw_hw_stats *)0)->m), \
415 offsetof(struct cpsw_hw_stats, m)
416 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
417 sizeof(((struct cpdma_chan_stats *)0)->m), \
418 offsetof(struct cpdma_chan_stats, m)
419 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
420 sizeof(((struct cpdma_chan_stats *)0)->m), \
421 offsetof(struct cpdma_chan_stats, m)
422
423 static const struct cpsw_stats cpsw_gstrings_stats[] = {
424 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
425 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
426 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
427 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
428 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
429 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
430 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
431 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
432 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
433 { "Rx Fragments", CPSW_STAT(rxfragments) },
434 { "Rx Octets", CPSW_STAT(rxoctets) },
435 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
436 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
437 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
438 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
439 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
440 { "Collisions", CPSW_STAT(txcollisionframes) },
441 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
442 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
443 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
444 { "Late Collisions", CPSW_STAT(txlatecollisions) },
445 { "Tx Underrun", CPSW_STAT(txunderrun) },
446 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
447 { "Tx Octets", CPSW_STAT(txoctets) },
448 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
449 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
450 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
451 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
452 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
453 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
454 { "Net Octets", CPSW_STAT(netoctets) },
455 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
456 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
457 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
458 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
459 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
460 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
461 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
462 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
463 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
464 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
465 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
466 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
467 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
468 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
469 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
470 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
471 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
472 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
473 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
474 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
475 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
476 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
477 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
478 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
479 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
480 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
481 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
482 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
483 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
484 };
485
486 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
487
488 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
489 #define for_each_slave(priv, func, arg...) \
490 do { \
491 struct cpsw_slave *slave; \
492 int n; \
493 if (priv->data.dual_emac) \
494 (func)((priv)->slaves + priv->emac_port, ##arg);\
495 else \
496 for (n = (priv)->data.slaves, \
497 slave = (priv)->slaves; \
498 n; n--) \
499 (func)(slave++, ##arg); \
500 } while (0)
501 #define cpsw_get_slave_ndev(priv, __slave_no__) \
502 ((__slave_no__ < priv->data.slaves) ? \
503 priv->slaves[__slave_no__].ndev : NULL)
504 #define cpsw_get_slave_priv(priv, __slave_no__) \
505 (((__slave_no__ < priv->data.slaves) && \
506 (priv->slaves[__slave_no__].ndev)) ? \
507 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
508
509 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
510 do { \
511 if (!priv->data.dual_emac) \
512 break; \
513 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
514 ndev = cpsw_get_slave_ndev(priv, 0); \
515 priv = netdev_priv(ndev); \
516 skb->dev = ndev; \
517 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
518 ndev = cpsw_get_slave_ndev(priv, 1); \
519 priv = netdev_priv(ndev); \
520 skb->dev = ndev; \
521 } \
522 } while (0)
523 #define cpsw_add_mcast(priv, addr) \
524 do { \
525 if (priv->data.dual_emac) { \
526 struct cpsw_slave *slave = priv->slaves + \
527 priv->emac_port; \
528 int slave_port = cpsw_get_slave_port(priv, \
529 slave->slave_num); \
530 cpsw_ale_add_mcast(priv->ale, addr, \
531 1 << slave_port | ALE_PORT_HOST, \
532 ALE_VLAN, slave->port_vlan, 0); \
533 } else { \
534 cpsw_ale_add_mcast(priv->ale, addr, \
535 ALE_ALL_PORTS, \
536 0, 0, 0); \
537 } \
538 } while (0)
539
540 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
541 {
542 return slave_num + 1;
543 }
544
545 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
546 {
547 struct cpsw_priv *priv = netdev_priv(ndev);
548 struct cpsw_ale *ale = priv->ale;
549 int i;
550
551 if (priv->data.dual_emac) {
552 bool flag = false;
553
554 /* Enabling promiscuous mode for one interface will be
555 * common for both the interface as the interface shares
556 * the same hardware resource.
557 */
558 for (i = 0; i < priv->data.slaves; i++)
559 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
560 flag = true;
561
562 if (!enable && flag) {
563 enable = true;
564 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
565 }
566
567 if (enable) {
568 /* Enable Bypass */
569 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
570
571 dev_dbg(&ndev->dev, "promiscuity enabled\n");
572 } else {
573 /* Disable Bypass */
574 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
575 dev_dbg(&ndev->dev, "promiscuity disabled\n");
576 }
577 } else {
578 if (enable) {
579 unsigned long timeout = jiffies + HZ;
580
581 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
582 for (i = 0; i <= priv->data.slaves; i++) {
583 cpsw_ale_control_set(ale, i,
584 ALE_PORT_NOLEARN, 1);
585 cpsw_ale_control_set(ale, i,
586 ALE_PORT_NO_SA_UPDATE, 1);
587 }
588
589 /* Clear All Untouched entries */
590 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
591 do {
592 cpu_relax();
593 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
594 break;
595 } while (time_after(timeout, jiffies));
596 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
597
598 /* Clear all mcast from ALE */
599 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
600
601 /* Flood All Unicast Packets to Host port */
602 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
603 dev_dbg(&ndev->dev, "promiscuity enabled\n");
604 } else {
605 /* Don't Flood All Unicast Packets to Host port */
606 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
607
608 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
609 for (i = 0; i <= priv->data.slaves; i++) {
610 cpsw_ale_control_set(ale, i,
611 ALE_PORT_NOLEARN, 0);
612 cpsw_ale_control_set(ale, i,
613 ALE_PORT_NO_SA_UPDATE, 0);
614 }
615 dev_dbg(&ndev->dev, "promiscuity disabled\n");
616 }
617 }
618 }
619
620 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
621 {
622 struct cpsw_priv *priv = netdev_priv(ndev);
623 int vid;
624
625 if (priv->data.dual_emac)
626 vid = priv->slaves[priv->emac_port].port_vlan;
627 else
628 vid = priv->data.default_vlan;
629
630 if (ndev->flags & IFF_PROMISC) {
631 /* Enable promiscuous mode */
632 cpsw_set_promiscious(ndev, true);
633 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
634 return;
635 } else {
636 /* Disable promiscuous mode */
637 cpsw_set_promiscious(ndev, false);
638 }
639
640 /* Restore allmulti on vlans if necessary */
641 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
642
643 /* Clear all mcast from ALE */
644 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS, vid);
645
646 if (!netdev_mc_empty(ndev)) {
647 struct netdev_hw_addr *ha;
648
649 /* program multicast address list into ALE register */
650 netdev_for_each_mc_addr(ha, ndev) {
651 cpsw_add_mcast(priv, (u8 *)ha->addr);
652 }
653 }
654 }
655
656 static void cpsw_intr_enable(struct cpsw_priv *priv)
657 {
658 __raw_writel(0xFF, &priv->wr_regs->tx_en);
659 __raw_writel(0xFF, &priv->wr_regs->rx_en);
660
661 cpdma_ctlr_int_ctrl(priv->dma, true);
662 return;
663 }
664
665 static void cpsw_intr_disable(struct cpsw_priv *priv)
666 {
667 __raw_writel(0, &priv->wr_regs->tx_en);
668 __raw_writel(0, &priv->wr_regs->rx_en);
669
670 cpdma_ctlr_int_ctrl(priv->dma, false);
671 return;
672 }
673
674 static void cpsw_tx_handler(void *token, int len, int status)
675 {
676 struct sk_buff *skb = token;
677 struct net_device *ndev = skb->dev;
678 struct cpsw_priv *priv = netdev_priv(ndev);
679
680 /* Check whether the queue is stopped due to stalled tx dma, if the
681 * queue is stopped then start the queue as we have free desc for tx
682 */
683 if (unlikely(netif_queue_stopped(ndev)))
684 netif_wake_queue(ndev);
685 cpts_tx_timestamp(priv->cpts, skb);
686 ndev->stats.tx_packets++;
687 ndev->stats.tx_bytes += len;
688 dev_kfree_skb_any(skb);
689 }
690
691 static void cpsw_rx_handler(void *token, int len, int status)
692 {
693 struct sk_buff *skb = token;
694 struct sk_buff *new_skb;
695 struct net_device *ndev = skb->dev;
696 struct cpsw_priv *priv = netdev_priv(ndev);
697 int ret = 0;
698
699 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
700
701 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
702 bool ndev_status = false;
703 struct cpsw_slave *slave = priv->slaves;
704 int n;
705
706 if (priv->data.dual_emac) {
707 /* In dual emac mode check for all interfaces */
708 for (n = priv->data.slaves; n; n--, slave++)
709 if (netif_running(slave->ndev))
710 ndev_status = true;
711 }
712
713 if (ndev_status && (status >= 0)) {
714 /* The packet received is for the interface which
715 * is already down and the other interface is up
716 * and running, instead of freeing which results
717 * in reducing of the number of rx descriptor in
718 * DMA engine, requeue skb back to cpdma.
719 */
720 new_skb = skb;
721 goto requeue;
722 }
723
724 /* the interface is going down, skbs are purged */
725 dev_kfree_skb_any(skb);
726 return;
727 }
728
729 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
730 if (new_skb) {
731 skb_put(skb, len);
732 cpts_rx_timestamp(priv->cpts, skb);
733 skb->protocol = eth_type_trans(skb, ndev);
734 netif_receive_skb(skb);
735 ndev->stats.rx_bytes += len;
736 ndev->stats.rx_packets++;
737 } else {
738 ndev->stats.rx_dropped++;
739 new_skb = skb;
740 }
741
742 requeue:
743 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
744 skb_tailroom(new_skb), 0);
745 if (WARN_ON(ret < 0))
746 dev_kfree_skb_any(new_skb);
747 }
748
749 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
750 {
751 struct cpsw_priv *priv = dev_id;
752
753 writel(0, &priv->wr_regs->tx_en);
754 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
755
756 if (priv->quirk_irq) {
757 disable_irq_nosync(priv->irqs_table[1]);
758 priv->tx_irq_disabled = true;
759 }
760
761 napi_schedule(&priv->napi_tx);
762 return IRQ_HANDLED;
763 }
764
765 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
766 {
767 struct cpsw_priv *priv = dev_id;
768
769 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
770 writel(0, &priv->wr_regs->rx_en);
771
772 if (priv->quirk_irq) {
773 disable_irq_nosync(priv->irqs_table[0]);
774 priv->rx_irq_disabled = true;
775 }
776
777 napi_schedule(&priv->napi_rx);
778 return IRQ_HANDLED;
779 }
780
781 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
782 {
783 struct cpsw_priv *priv = napi_to_priv(napi_tx);
784 int num_tx;
785
786 num_tx = cpdma_chan_process(priv->txch, budget);
787 if (num_tx < budget) {
788 napi_complete(napi_tx);
789 writel(0xff, &priv->wr_regs->tx_en);
790 if (priv->quirk_irq && priv->tx_irq_disabled) {
791 priv->tx_irq_disabled = false;
792 enable_irq(priv->irqs_table[1]);
793 }
794 }
795
796 if (num_tx)
797 cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
798
799 return num_tx;
800 }
801
802 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
803 {
804 struct cpsw_priv *priv = napi_to_priv(napi_rx);
805 int num_rx;
806
807 num_rx = cpdma_chan_process(priv->rxch, budget);
808 if (num_rx < budget) {
809 napi_complete(napi_rx);
810 writel(0xff, &priv->wr_regs->rx_en);
811 if (priv->quirk_irq && priv->rx_irq_disabled) {
812 priv->rx_irq_disabled = false;
813 enable_irq(priv->irqs_table[0]);
814 }
815 }
816
817 if (num_rx)
818 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
819
820 return num_rx;
821 }
822
823 static inline void soft_reset(const char *module, void __iomem *reg)
824 {
825 unsigned long timeout = jiffies + HZ;
826
827 __raw_writel(1, reg);
828 do {
829 cpu_relax();
830 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
831
832 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
833 }
834
835 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
836 ((mac)[2] << 16) | ((mac)[3] << 24))
837 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
838
839 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
840 struct cpsw_priv *priv)
841 {
842 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
843 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
844 }
845
846 static void _cpsw_adjust_link(struct cpsw_slave *slave,
847 struct cpsw_priv *priv, bool *link)
848 {
849 struct phy_device *phy = slave->phy;
850 u32 mac_control = 0;
851 u32 slave_port;
852
853 if (!phy)
854 return;
855
856 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
857
858 if (phy->link) {
859 mac_control = priv->data.mac_control;
860
861 /* enable forwarding */
862 cpsw_ale_control_set(priv->ale, slave_port,
863 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
864
865 if (phy->speed == 1000)
866 mac_control |= BIT(7); /* GIGABITEN */
867 if (phy->duplex)
868 mac_control |= BIT(0); /* FULLDUPLEXEN */
869
870 /* set speed_in input in case RMII mode is used in 100Mbps */
871 if (phy->speed == 100)
872 mac_control |= BIT(15);
873 else if (phy->speed == 10)
874 mac_control |= BIT(18); /* In Band mode */
875
876 if (priv->rx_pause)
877 mac_control |= BIT(3);
878
879 if (priv->tx_pause)
880 mac_control |= BIT(4);
881
882 *link = true;
883 } else {
884 mac_control = 0;
885 /* disable forwarding */
886 cpsw_ale_control_set(priv->ale, slave_port,
887 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
888 }
889
890 if (mac_control != slave->mac_control) {
891 phy_print_status(phy);
892 __raw_writel(mac_control, &slave->sliver->mac_control);
893 }
894
895 slave->mac_control = mac_control;
896 }
897
898 static void cpsw_adjust_link(struct net_device *ndev)
899 {
900 struct cpsw_priv *priv = netdev_priv(ndev);
901 bool link = false;
902
903 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
904
905 if (link) {
906 netif_carrier_on(ndev);
907 if (netif_running(ndev))
908 netif_wake_queue(ndev);
909 } else {
910 netif_carrier_off(ndev);
911 netif_stop_queue(ndev);
912 }
913 }
914
915 static int cpsw_get_coalesce(struct net_device *ndev,
916 struct ethtool_coalesce *coal)
917 {
918 struct cpsw_priv *priv = netdev_priv(ndev);
919
920 coal->rx_coalesce_usecs = priv->coal_intvl;
921 return 0;
922 }
923
924 static int cpsw_set_coalesce(struct net_device *ndev,
925 struct ethtool_coalesce *coal)
926 {
927 struct cpsw_priv *priv = netdev_priv(ndev);
928 u32 int_ctrl;
929 u32 num_interrupts = 0;
930 u32 prescale = 0;
931 u32 addnl_dvdr = 1;
932 u32 coal_intvl = 0;
933
934 coal_intvl = coal->rx_coalesce_usecs;
935
936 int_ctrl = readl(&priv->wr_regs->int_control);
937 prescale = priv->bus_freq_mhz * 4;
938
939 if (!coal->rx_coalesce_usecs) {
940 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
941 goto update_return;
942 }
943
944 if (coal_intvl < CPSW_CMINTMIN_INTVL)
945 coal_intvl = CPSW_CMINTMIN_INTVL;
946
947 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
948 /* Interrupt pacer works with 4us Pulse, we can
949 * throttle further by dilating the 4us pulse.
950 */
951 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
952
953 if (addnl_dvdr > 1) {
954 prescale *= addnl_dvdr;
955 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
956 coal_intvl = (CPSW_CMINTMAX_INTVL
957 * addnl_dvdr);
958 } else {
959 addnl_dvdr = 1;
960 coal_intvl = CPSW_CMINTMAX_INTVL;
961 }
962 }
963
964 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
965 writel(num_interrupts, &priv->wr_regs->rx_imax);
966 writel(num_interrupts, &priv->wr_regs->tx_imax);
967
968 int_ctrl |= CPSW_INTPACEEN;
969 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
970 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
971
972 update_return:
973 writel(int_ctrl, &priv->wr_regs->int_control);
974
975 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
976 if (priv->data.dual_emac) {
977 int i;
978
979 for (i = 0; i < priv->data.slaves; i++) {
980 priv = netdev_priv(priv->slaves[i].ndev);
981 priv->coal_intvl = coal_intvl;
982 }
983 } else {
984 priv->coal_intvl = coal_intvl;
985 }
986
987 return 0;
988 }
989
990 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
991 {
992 switch (sset) {
993 case ETH_SS_STATS:
994 return CPSW_STATS_LEN;
995 default:
996 return -EOPNOTSUPP;
997 }
998 }
999
1000 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1001 {
1002 u8 *p = data;
1003 int i;
1004
1005 switch (stringset) {
1006 case ETH_SS_STATS:
1007 for (i = 0; i < CPSW_STATS_LEN; i++) {
1008 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1009 ETH_GSTRING_LEN);
1010 p += ETH_GSTRING_LEN;
1011 }
1012 break;
1013 }
1014 }
1015
1016 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1017 struct ethtool_stats *stats, u64 *data)
1018 {
1019 struct cpsw_priv *priv = netdev_priv(ndev);
1020 struct cpdma_chan_stats rx_stats;
1021 struct cpdma_chan_stats tx_stats;
1022 u32 val;
1023 u8 *p;
1024 int i;
1025
1026 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1027 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1028 cpdma_chan_get_stats(priv->txch, &tx_stats);
1029
1030 for (i = 0; i < CPSW_STATS_LEN; i++) {
1031 switch (cpsw_gstrings_stats[i].type) {
1032 case CPSW_STATS:
1033 val = readl(priv->hw_stats +
1034 cpsw_gstrings_stats[i].stat_offset);
1035 data[i] = val;
1036 break;
1037
1038 case CPDMA_RX_STATS:
1039 p = (u8 *)&rx_stats +
1040 cpsw_gstrings_stats[i].stat_offset;
1041 data[i] = *(u32 *)p;
1042 break;
1043
1044 case CPDMA_TX_STATS:
1045 p = (u8 *)&tx_stats +
1046 cpsw_gstrings_stats[i].stat_offset;
1047 data[i] = *(u32 *)p;
1048 break;
1049 }
1050 }
1051 }
1052
1053 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1054 {
1055 u32 i;
1056 u32 usage_count = 0;
1057
1058 if (!priv->data.dual_emac)
1059 return 0;
1060
1061 for (i = 0; i < priv->data.slaves; i++)
1062 if (priv->slaves[i].open_stat)
1063 usage_count++;
1064
1065 return usage_count;
1066 }
1067
1068 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1069 struct cpsw_priv *priv, struct sk_buff *skb)
1070 {
1071 if (!priv->data.dual_emac)
1072 return cpdma_chan_submit(priv->txch, skb, skb->data,
1073 skb->len, 0);
1074
1075 if (ndev == cpsw_get_slave_ndev(priv, 0))
1076 return cpdma_chan_submit(priv->txch, skb, skb->data,
1077 skb->len, 1);
1078 else
1079 return cpdma_chan_submit(priv->txch, skb, skb->data,
1080 skb->len, 2);
1081 }
1082
1083 static inline void cpsw_add_dual_emac_def_ale_entries(
1084 struct cpsw_priv *priv, struct cpsw_slave *slave,
1085 u32 slave_port)
1086 {
1087 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1088
1089 if (priv->version == CPSW_VERSION_1)
1090 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1091 else
1092 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1093 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1094 port_mask, port_mask, 0);
1095 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1096 port_mask, ALE_VLAN, slave->port_vlan, 0);
1097 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1098 HOST_PORT_NUM, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1099 }
1100
1101 static void soft_reset_slave(struct cpsw_slave *slave)
1102 {
1103 char name[32];
1104
1105 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1106 soft_reset(name, &slave->sliver->soft_reset);
1107 }
1108
1109 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1110 {
1111 u32 slave_port;
1112
1113 soft_reset_slave(slave);
1114
1115 /* setup priority mapping */
1116 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1117
1118 switch (priv->version) {
1119 case CPSW_VERSION_1:
1120 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1121 break;
1122 case CPSW_VERSION_2:
1123 case CPSW_VERSION_3:
1124 case CPSW_VERSION_4:
1125 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1126 break;
1127 }
1128
1129 /* setup max packet size, and mac address */
1130 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1131 cpsw_set_slave_mac(slave, priv);
1132
1133 slave->mac_control = 0; /* no link yet */
1134
1135 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1136
1137 if (priv->data.dual_emac)
1138 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1139 else
1140 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1141 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1142
1143 if (slave->data->phy_node) {
1144 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1145 &cpsw_adjust_link, 0, slave->data->phy_if);
1146 if (!slave->phy) {
1147 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1148 slave->data->phy_node->full_name,
1149 slave->slave_num);
1150 return;
1151 }
1152 } else {
1153 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1154 &cpsw_adjust_link, slave->data->phy_if);
1155 if (IS_ERR(slave->phy)) {
1156 dev_err(priv->dev,
1157 "phy \"%s\" not found on slave %d, err %ld\n",
1158 slave->data->phy_id, slave->slave_num,
1159 PTR_ERR(slave->phy));
1160 slave->phy = NULL;
1161 return;
1162 }
1163 }
1164
1165 phy_attached_info(slave->phy);
1166
1167 phy_start(slave->phy);
1168
1169 /* Configure GMII_SEL register */
1170 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, slave->slave_num);
1171 }
1172
1173 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1174 {
1175 const int vlan = priv->data.default_vlan;
1176 u32 reg;
1177 int i;
1178 int unreg_mcast_mask;
1179
1180 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1181 CPSW2_PORT_VLAN;
1182
1183 writel(vlan, &priv->host_port_regs->port_vlan);
1184
1185 for (i = 0; i < priv->data.slaves; i++)
1186 slave_write(priv->slaves + i, vlan, reg);
1187
1188 if (priv->ndev->flags & IFF_ALLMULTI)
1189 unreg_mcast_mask = ALE_ALL_PORTS;
1190 else
1191 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1192
1193 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS,
1194 ALE_ALL_PORTS, ALE_ALL_PORTS,
1195 unreg_mcast_mask);
1196 }
1197
1198 static void cpsw_init_host_port(struct cpsw_priv *priv)
1199 {
1200 u32 control_reg;
1201 u32 fifo_mode;
1202
1203 /* soft reset the controller and initialize ale */
1204 soft_reset("cpsw", &priv->regs->soft_reset);
1205 cpsw_ale_start(priv->ale);
1206
1207 /* switch to vlan unaware mode */
1208 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1209 CPSW_ALE_VLAN_AWARE);
1210 control_reg = readl(&priv->regs->control);
1211 control_reg |= CPSW_VLAN_AWARE;
1212 writel(control_reg, &priv->regs->control);
1213 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1214 CPSW_FIFO_NORMAL_MODE;
1215 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1216
1217 /* setup host port priority mapping */
1218 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1219 &priv->host_port_regs->cpdma_tx_pri_map);
1220 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1221
1222 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM,
1223 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1224
1225 if (!priv->data.dual_emac) {
1226 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
1227 0, 0);
1228 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1229 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1230 }
1231 }
1232
1233 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1234 {
1235 u32 slave_port;
1236
1237 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1238
1239 if (!slave->phy)
1240 return;
1241 phy_stop(slave->phy);
1242 phy_disconnect(slave->phy);
1243 slave->phy = NULL;
1244 cpsw_ale_control_set(priv->ale, slave_port,
1245 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1246 }
1247
1248 static int cpsw_ndo_open(struct net_device *ndev)
1249 {
1250 struct cpsw_priv *priv = netdev_priv(ndev);
1251 int i, ret;
1252 u32 reg;
1253
1254 pm_runtime_get_sync(&priv->pdev->dev);
1255
1256 if (!cpsw_common_res_usage_state(priv))
1257 cpsw_intr_disable(priv);
1258 netif_carrier_off(ndev);
1259
1260 reg = priv->version;
1261
1262 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1263 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1264 CPSW_RTL_VERSION(reg));
1265
1266 /* initialize host and slave ports */
1267 if (!cpsw_common_res_usage_state(priv))
1268 cpsw_init_host_port(priv);
1269 for_each_slave(priv, cpsw_slave_open, priv);
1270
1271 /* Add default VLAN */
1272 if (!priv->data.dual_emac)
1273 cpsw_add_default_vlan(priv);
1274 else
1275 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1276 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1277
1278 if (!cpsw_common_res_usage_state(priv)) {
1279 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1280
1281 /* setup tx dma to fixed prio and zero offset */
1282 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1283 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1284
1285 /* disable priority elevation */
1286 __raw_writel(0, &priv->regs->ptype);
1287
1288 /* enable statistics collection only on all ports */
1289 __raw_writel(0x7, &priv->regs->stat_port_en);
1290
1291 /* Enable internal fifo flow control */
1292 writel(0x7, &priv->regs->flow_control);
1293
1294 napi_enable(&priv_sl0->napi_rx);
1295 napi_enable(&priv_sl0->napi_tx);
1296
1297 if (priv_sl0->tx_irq_disabled) {
1298 priv_sl0->tx_irq_disabled = false;
1299 enable_irq(priv->irqs_table[1]);
1300 }
1301
1302 if (priv_sl0->rx_irq_disabled) {
1303 priv_sl0->rx_irq_disabled = false;
1304 enable_irq(priv->irqs_table[0]);
1305 }
1306
1307 if (WARN_ON(!priv->data.rx_descs))
1308 priv->data.rx_descs = 128;
1309
1310 for (i = 0; i < priv->data.rx_descs; i++) {
1311 struct sk_buff *skb;
1312
1313 ret = -ENOMEM;
1314 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1315 priv->rx_packet_max, GFP_KERNEL);
1316 if (!skb)
1317 goto err_cleanup;
1318 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1319 skb_tailroom(skb), 0);
1320 if (ret < 0) {
1321 kfree_skb(skb);
1322 goto err_cleanup;
1323 }
1324 }
1325 /* continue even if we didn't manage to submit all
1326 * receive descs
1327 */
1328 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1329
1330 if (cpts_register(&priv->pdev->dev, priv->cpts,
1331 priv->data.cpts_clock_mult,
1332 priv->data.cpts_clock_shift))
1333 dev_err(priv->dev, "error registering cpts device\n");
1334
1335 }
1336
1337 /* Enable Interrupt pacing if configured */
1338 if (priv->coal_intvl != 0) {
1339 struct ethtool_coalesce coal;
1340
1341 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1342 cpsw_set_coalesce(ndev, &coal);
1343 }
1344
1345 cpdma_ctlr_start(priv->dma);
1346 cpsw_intr_enable(priv);
1347
1348 if (priv->data.dual_emac)
1349 priv->slaves[priv->emac_port].open_stat = true;
1350 return 0;
1351
1352 err_cleanup:
1353 cpdma_ctlr_stop(priv->dma);
1354 for_each_slave(priv, cpsw_slave_stop, priv);
1355 pm_runtime_put_sync(&priv->pdev->dev);
1356 netif_carrier_off(priv->ndev);
1357 return ret;
1358 }
1359
1360 static int cpsw_ndo_stop(struct net_device *ndev)
1361 {
1362 struct cpsw_priv *priv = netdev_priv(ndev);
1363
1364 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1365 netif_stop_queue(priv->ndev);
1366 netif_carrier_off(priv->ndev);
1367
1368 if (cpsw_common_res_usage_state(priv) <= 1) {
1369 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1370
1371 napi_disable(&priv_sl0->napi_rx);
1372 napi_disable(&priv_sl0->napi_tx);
1373 cpts_unregister(priv->cpts);
1374 cpsw_intr_disable(priv);
1375 cpdma_ctlr_stop(priv->dma);
1376 cpsw_ale_stop(priv->ale);
1377 }
1378 for_each_slave(priv, cpsw_slave_stop, priv);
1379 pm_runtime_put_sync(&priv->pdev->dev);
1380 if (priv->data.dual_emac)
1381 priv->slaves[priv->emac_port].open_stat = false;
1382 return 0;
1383 }
1384
1385 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1386 struct net_device *ndev)
1387 {
1388 struct cpsw_priv *priv = netdev_priv(ndev);
1389 int ret;
1390
1391 netif_trans_update(ndev);
1392
1393 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1394 cpsw_err(priv, tx_err, "packet pad failed\n");
1395 ndev->stats.tx_dropped++;
1396 return NETDEV_TX_OK;
1397 }
1398
1399 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1400 priv->cpts->tx_enable)
1401 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1402
1403 skb_tx_timestamp(skb);
1404
1405 ret = cpsw_tx_packet_submit(ndev, priv, skb);
1406 if (unlikely(ret != 0)) {
1407 cpsw_err(priv, tx_err, "desc submit failed\n");
1408 goto fail;
1409 }
1410
1411 /* If there is no more tx desc left free then we need to
1412 * tell the kernel to stop sending us tx frames.
1413 */
1414 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1415 netif_stop_queue(ndev);
1416
1417 return NETDEV_TX_OK;
1418 fail:
1419 ndev->stats.tx_dropped++;
1420 netif_stop_queue(ndev);
1421 return NETDEV_TX_BUSY;
1422 }
1423
1424 #ifdef CONFIG_TI_CPTS
1425
1426 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1427 {
1428 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1429 u32 ts_en, seq_id;
1430
1431 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1432 slave_write(slave, 0, CPSW1_TS_CTL);
1433 return;
1434 }
1435
1436 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1437 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1438
1439 if (priv->cpts->tx_enable)
1440 ts_en |= CPSW_V1_TS_TX_EN;
1441
1442 if (priv->cpts->rx_enable)
1443 ts_en |= CPSW_V1_TS_RX_EN;
1444
1445 slave_write(slave, ts_en, CPSW1_TS_CTL);
1446 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1447 }
1448
1449 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1450 {
1451 struct cpsw_slave *slave;
1452 u32 ctrl, mtype;
1453
1454 if (priv->data.dual_emac)
1455 slave = &priv->slaves[priv->emac_port];
1456 else
1457 slave = &priv->slaves[priv->data.active_slave];
1458
1459 ctrl = slave_read(slave, CPSW2_CONTROL);
1460 switch (priv->version) {
1461 case CPSW_VERSION_2:
1462 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1463
1464 if (priv->cpts->tx_enable)
1465 ctrl |= CTRL_V2_TX_TS_BITS;
1466
1467 if (priv->cpts->rx_enable)
1468 ctrl |= CTRL_V2_RX_TS_BITS;
1469 break;
1470 case CPSW_VERSION_3:
1471 default:
1472 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1473
1474 if (priv->cpts->tx_enable)
1475 ctrl |= CTRL_V3_TX_TS_BITS;
1476
1477 if (priv->cpts->rx_enable)
1478 ctrl |= CTRL_V3_RX_TS_BITS;
1479 break;
1480 }
1481
1482 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1483
1484 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1485 slave_write(slave, ctrl, CPSW2_CONTROL);
1486 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1487 }
1488
1489 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1490 {
1491 struct cpsw_priv *priv = netdev_priv(dev);
1492 struct cpts *cpts = priv->cpts;
1493 struct hwtstamp_config cfg;
1494
1495 if (priv->version != CPSW_VERSION_1 &&
1496 priv->version != CPSW_VERSION_2 &&
1497 priv->version != CPSW_VERSION_3)
1498 return -EOPNOTSUPP;
1499
1500 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1501 return -EFAULT;
1502
1503 /* reserved for future extensions */
1504 if (cfg.flags)
1505 return -EINVAL;
1506
1507 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1508 return -ERANGE;
1509
1510 switch (cfg.rx_filter) {
1511 case HWTSTAMP_FILTER_NONE:
1512 cpts->rx_enable = 0;
1513 break;
1514 case HWTSTAMP_FILTER_ALL:
1515 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1516 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1517 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1518 return -ERANGE;
1519 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1520 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1521 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1522 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1523 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1524 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1525 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1526 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1527 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1528 cpts->rx_enable = 1;
1529 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1530 break;
1531 default:
1532 return -ERANGE;
1533 }
1534
1535 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1536
1537 switch (priv->version) {
1538 case CPSW_VERSION_1:
1539 cpsw_hwtstamp_v1(priv);
1540 break;
1541 case CPSW_VERSION_2:
1542 case CPSW_VERSION_3:
1543 cpsw_hwtstamp_v2(priv);
1544 break;
1545 default:
1546 WARN_ON(1);
1547 }
1548
1549 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1550 }
1551
1552 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1553 {
1554 struct cpsw_priv *priv = netdev_priv(dev);
1555 struct cpts *cpts = priv->cpts;
1556 struct hwtstamp_config cfg;
1557
1558 if (priv->version != CPSW_VERSION_1 &&
1559 priv->version != CPSW_VERSION_2 &&
1560 priv->version != CPSW_VERSION_3)
1561 return -EOPNOTSUPP;
1562
1563 cfg.flags = 0;
1564 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1565 cfg.rx_filter = (cpts->rx_enable ?
1566 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1567
1568 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1569 }
1570
1571 #endif /*CONFIG_TI_CPTS*/
1572
1573 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1574 {
1575 struct cpsw_priv *priv = netdev_priv(dev);
1576 int slave_no = cpsw_slave_index(priv);
1577
1578 if (!netif_running(dev))
1579 return -EINVAL;
1580
1581 switch (cmd) {
1582 #ifdef CONFIG_TI_CPTS
1583 case SIOCSHWTSTAMP:
1584 return cpsw_hwtstamp_set(dev, req);
1585 case SIOCGHWTSTAMP:
1586 return cpsw_hwtstamp_get(dev, req);
1587 #endif
1588 }
1589
1590 if (!priv->slaves[slave_no].phy)
1591 return -EOPNOTSUPP;
1592 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1593 }
1594
1595 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1596 {
1597 struct cpsw_priv *priv = netdev_priv(ndev);
1598
1599 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1600 ndev->stats.tx_errors++;
1601 cpsw_intr_disable(priv);
1602 cpdma_chan_stop(priv->txch);
1603 cpdma_chan_start(priv->txch);
1604 cpsw_intr_enable(priv);
1605 }
1606
1607 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1608 {
1609 struct cpsw_priv *priv = netdev_priv(ndev);
1610 struct sockaddr *addr = (struct sockaddr *)p;
1611 int flags = 0;
1612 u16 vid = 0;
1613
1614 if (!is_valid_ether_addr(addr->sa_data))
1615 return -EADDRNOTAVAIL;
1616
1617 if (priv->data.dual_emac) {
1618 vid = priv->slaves[priv->emac_port].port_vlan;
1619 flags = ALE_VLAN;
1620 }
1621
1622 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
1623 flags, vid);
1624 cpsw_ale_add_ucast(priv->ale, addr->sa_data, HOST_PORT_NUM,
1625 flags, vid);
1626
1627 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1628 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1629 for_each_slave(priv, cpsw_set_slave_mac, priv);
1630
1631 return 0;
1632 }
1633
1634 #ifdef CONFIG_NET_POLL_CONTROLLER
1635 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1636 {
1637 struct cpsw_priv *priv = netdev_priv(ndev);
1638
1639 cpsw_intr_disable(priv);
1640 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1641 cpsw_tx_interrupt(priv->irqs_table[1], priv);
1642 cpsw_intr_enable(priv);
1643 }
1644 #endif
1645
1646 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1647 unsigned short vid)
1648 {
1649 int ret;
1650 int unreg_mcast_mask = 0;
1651 u32 port_mask;
1652
1653 if (priv->data.dual_emac) {
1654 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1655
1656 if (priv->ndev->flags & IFF_ALLMULTI)
1657 unreg_mcast_mask = port_mask;
1658 } else {
1659 port_mask = ALE_ALL_PORTS;
1660
1661 if (priv->ndev->flags & IFF_ALLMULTI)
1662 unreg_mcast_mask = ALE_ALL_PORTS;
1663 else
1664 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1665 }
1666
1667 ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1668 unreg_mcast_mask);
1669 if (ret != 0)
1670 return ret;
1671
1672 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1673 HOST_PORT_NUM, ALE_VLAN, vid);
1674 if (ret != 0)
1675 goto clean_vid;
1676
1677 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1678 port_mask, ALE_VLAN, vid, 0);
1679 if (ret != 0)
1680 goto clean_vlan_ucast;
1681 return 0;
1682
1683 clean_vlan_ucast:
1684 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1685 HOST_PORT_NUM, ALE_VLAN, vid);
1686 clean_vid:
1687 cpsw_ale_del_vlan(priv->ale, vid, 0);
1688 return ret;
1689 }
1690
1691 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1692 __be16 proto, u16 vid)
1693 {
1694 struct cpsw_priv *priv = netdev_priv(ndev);
1695
1696 if (vid == priv->data.default_vlan)
1697 return 0;
1698
1699 if (priv->data.dual_emac) {
1700 /* In dual EMAC, reserved VLAN id should not be used for
1701 * creating VLAN interfaces as this can break the dual
1702 * EMAC port separation
1703 */
1704 int i;
1705
1706 for (i = 0; i < priv->data.slaves; i++) {
1707 if (vid == priv->slaves[i].port_vlan)
1708 return -EINVAL;
1709 }
1710 }
1711
1712 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1713 return cpsw_add_vlan_ale_entry(priv, vid);
1714 }
1715
1716 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1717 __be16 proto, u16 vid)
1718 {
1719 struct cpsw_priv *priv = netdev_priv(ndev);
1720 int ret;
1721
1722 if (vid == priv->data.default_vlan)
1723 return 0;
1724
1725 if (priv->data.dual_emac) {
1726 int i;
1727
1728 for (i = 0; i < priv->data.slaves; i++) {
1729 if (vid == priv->slaves[i].port_vlan)
1730 return -EINVAL;
1731 }
1732 }
1733
1734 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1735 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1736 if (ret != 0)
1737 return ret;
1738
1739 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1740 HOST_PORT_NUM, ALE_VLAN, vid);
1741 if (ret != 0)
1742 return ret;
1743
1744 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1745 0, ALE_VLAN, vid);
1746 }
1747
1748 static const struct net_device_ops cpsw_netdev_ops = {
1749 .ndo_open = cpsw_ndo_open,
1750 .ndo_stop = cpsw_ndo_stop,
1751 .ndo_start_xmit = cpsw_ndo_start_xmit,
1752 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
1753 .ndo_do_ioctl = cpsw_ndo_ioctl,
1754 .ndo_validate_addr = eth_validate_addr,
1755 .ndo_change_mtu = eth_change_mtu,
1756 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1757 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
1758 #ifdef CONFIG_NET_POLL_CONTROLLER
1759 .ndo_poll_controller = cpsw_ndo_poll_controller,
1760 #endif
1761 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1762 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
1763 };
1764
1765 static int cpsw_get_regs_len(struct net_device *ndev)
1766 {
1767 struct cpsw_priv *priv = netdev_priv(ndev);
1768
1769 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1770 }
1771
1772 static void cpsw_get_regs(struct net_device *ndev,
1773 struct ethtool_regs *regs, void *p)
1774 {
1775 struct cpsw_priv *priv = netdev_priv(ndev);
1776 u32 *reg = p;
1777
1778 /* update CPSW IP version */
1779 regs->version = priv->version;
1780
1781 cpsw_ale_dump(priv->ale, reg);
1782 }
1783
1784 static void cpsw_get_drvinfo(struct net_device *ndev,
1785 struct ethtool_drvinfo *info)
1786 {
1787 struct cpsw_priv *priv = netdev_priv(ndev);
1788
1789 strlcpy(info->driver, "cpsw", sizeof(info->driver));
1790 strlcpy(info->version, "1.0", sizeof(info->version));
1791 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1792 }
1793
1794 static u32 cpsw_get_msglevel(struct net_device *ndev)
1795 {
1796 struct cpsw_priv *priv = netdev_priv(ndev);
1797 return priv->msg_enable;
1798 }
1799
1800 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1801 {
1802 struct cpsw_priv *priv = netdev_priv(ndev);
1803 priv->msg_enable = value;
1804 }
1805
1806 static int cpsw_get_ts_info(struct net_device *ndev,
1807 struct ethtool_ts_info *info)
1808 {
1809 #ifdef CONFIG_TI_CPTS
1810 struct cpsw_priv *priv = netdev_priv(ndev);
1811
1812 info->so_timestamping =
1813 SOF_TIMESTAMPING_TX_HARDWARE |
1814 SOF_TIMESTAMPING_TX_SOFTWARE |
1815 SOF_TIMESTAMPING_RX_HARDWARE |
1816 SOF_TIMESTAMPING_RX_SOFTWARE |
1817 SOF_TIMESTAMPING_SOFTWARE |
1818 SOF_TIMESTAMPING_RAW_HARDWARE;
1819 info->phc_index = priv->cpts->phc_index;
1820 info->tx_types =
1821 (1 << HWTSTAMP_TX_OFF) |
1822 (1 << HWTSTAMP_TX_ON);
1823 info->rx_filters =
1824 (1 << HWTSTAMP_FILTER_NONE) |
1825 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1826 #else
1827 info->so_timestamping =
1828 SOF_TIMESTAMPING_TX_SOFTWARE |
1829 SOF_TIMESTAMPING_RX_SOFTWARE |
1830 SOF_TIMESTAMPING_SOFTWARE;
1831 info->phc_index = -1;
1832 info->tx_types = 0;
1833 info->rx_filters = 0;
1834 #endif
1835 return 0;
1836 }
1837
1838 static int cpsw_get_settings(struct net_device *ndev,
1839 struct ethtool_cmd *ecmd)
1840 {
1841 struct cpsw_priv *priv = netdev_priv(ndev);
1842 int slave_no = cpsw_slave_index(priv);
1843
1844 if (priv->slaves[slave_no].phy)
1845 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1846 else
1847 return -EOPNOTSUPP;
1848 }
1849
1850 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1851 {
1852 struct cpsw_priv *priv = netdev_priv(ndev);
1853 int slave_no = cpsw_slave_index(priv);
1854
1855 if (priv->slaves[slave_no].phy)
1856 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1857 else
1858 return -EOPNOTSUPP;
1859 }
1860
1861 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1862 {
1863 struct cpsw_priv *priv = netdev_priv(ndev);
1864 int slave_no = cpsw_slave_index(priv);
1865
1866 wol->supported = 0;
1867 wol->wolopts = 0;
1868
1869 if (priv->slaves[slave_no].phy)
1870 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1871 }
1872
1873 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1874 {
1875 struct cpsw_priv *priv = netdev_priv(ndev);
1876 int slave_no = cpsw_slave_index(priv);
1877
1878 if (priv->slaves[slave_no].phy)
1879 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1880 else
1881 return -EOPNOTSUPP;
1882 }
1883
1884 static void cpsw_get_pauseparam(struct net_device *ndev,
1885 struct ethtool_pauseparam *pause)
1886 {
1887 struct cpsw_priv *priv = netdev_priv(ndev);
1888
1889 pause->autoneg = AUTONEG_DISABLE;
1890 pause->rx_pause = priv->rx_pause ? true : false;
1891 pause->tx_pause = priv->tx_pause ? true : false;
1892 }
1893
1894 static int cpsw_set_pauseparam(struct net_device *ndev,
1895 struct ethtool_pauseparam *pause)
1896 {
1897 struct cpsw_priv *priv = netdev_priv(ndev);
1898 bool link;
1899
1900 priv->rx_pause = pause->rx_pause ? true : false;
1901 priv->tx_pause = pause->tx_pause ? true : false;
1902
1903 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1904
1905 return 0;
1906 }
1907
1908 static const struct ethtool_ops cpsw_ethtool_ops = {
1909 .get_drvinfo = cpsw_get_drvinfo,
1910 .get_msglevel = cpsw_get_msglevel,
1911 .set_msglevel = cpsw_set_msglevel,
1912 .get_link = ethtool_op_get_link,
1913 .get_ts_info = cpsw_get_ts_info,
1914 .get_settings = cpsw_get_settings,
1915 .set_settings = cpsw_set_settings,
1916 .get_coalesce = cpsw_get_coalesce,
1917 .set_coalesce = cpsw_set_coalesce,
1918 .get_sset_count = cpsw_get_sset_count,
1919 .get_strings = cpsw_get_strings,
1920 .get_ethtool_stats = cpsw_get_ethtool_stats,
1921 .get_pauseparam = cpsw_get_pauseparam,
1922 .set_pauseparam = cpsw_set_pauseparam,
1923 .get_wol = cpsw_get_wol,
1924 .set_wol = cpsw_set_wol,
1925 .get_regs_len = cpsw_get_regs_len,
1926 .get_regs = cpsw_get_regs,
1927 };
1928
1929 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1930 u32 slave_reg_ofs, u32 sliver_reg_ofs)
1931 {
1932 void __iomem *regs = priv->regs;
1933 int slave_num = slave->slave_num;
1934 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1935
1936 slave->data = data;
1937 slave->regs = regs + slave_reg_ofs;
1938 slave->sliver = regs + sliver_reg_ofs;
1939 slave->port_vlan = data->dual_emac_res_vlan;
1940 }
1941
1942 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1943 struct platform_device *pdev)
1944 {
1945 struct device_node *node = pdev->dev.of_node;
1946 struct device_node *slave_node;
1947 int i = 0, ret;
1948 u32 prop;
1949
1950 if (!node)
1951 return -EINVAL;
1952
1953 if (of_property_read_u32(node, "slaves", &prop)) {
1954 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1955 return -EINVAL;
1956 }
1957 data->slaves = prop;
1958
1959 if (of_property_read_u32(node, "active_slave", &prop)) {
1960 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1961 return -EINVAL;
1962 }
1963 data->active_slave = prop;
1964
1965 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1966 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1967 return -EINVAL;
1968 }
1969 data->cpts_clock_mult = prop;
1970
1971 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1972 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1973 return -EINVAL;
1974 }
1975 data->cpts_clock_shift = prop;
1976
1977 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1978 * sizeof(struct cpsw_slave_data),
1979 GFP_KERNEL);
1980 if (!data->slave_data)
1981 return -ENOMEM;
1982
1983 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1984 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1985 return -EINVAL;
1986 }
1987 data->channels = prop;
1988
1989 if (of_property_read_u32(node, "ale_entries", &prop)) {
1990 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1991 return -EINVAL;
1992 }
1993 data->ale_entries = prop;
1994
1995 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1996 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1997 return -EINVAL;
1998 }
1999 data->bd_ram_size = prop;
2000
2001 if (of_property_read_u32(node, "rx_descs", &prop)) {
2002 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
2003 return -EINVAL;
2004 }
2005 data->rx_descs = prop;
2006
2007 if (of_property_read_u32(node, "mac_control", &prop)) {
2008 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2009 return -EINVAL;
2010 }
2011 data->mac_control = prop;
2012
2013 if (of_property_read_bool(node, "dual_emac"))
2014 data->dual_emac = 1;
2015
2016 /*
2017 * Populate all the child nodes here...
2018 */
2019 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2020 /* We do not want to force this, as in some cases may not have child */
2021 if (ret)
2022 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2023
2024 for_each_child_of_node(node, slave_node) {
2025 struct cpsw_slave_data *slave_data = data->slave_data + i;
2026 const void *mac_addr = NULL;
2027 int lenp;
2028 const __be32 *parp;
2029
2030 /* This is no slave child node, continue */
2031 if (strcmp(slave_node->name, "slave"))
2032 continue;
2033
2034 slave_data->phy_node = of_parse_phandle(slave_node,
2035 "phy-handle", 0);
2036 parp = of_get_property(slave_node, "phy_id", &lenp);
2037 if (slave_data->phy_node) {
2038 dev_dbg(&pdev->dev,
2039 "slave[%d] using phy-handle=\"%s\"\n",
2040 i, slave_data->phy_node->full_name);
2041 } else if (of_phy_is_fixed_link(slave_node)) {
2042 /* In the case of a fixed PHY, the DT node associated
2043 * to the PHY is the Ethernet MAC DT node.
2044 */
2045 ret = of_phy_register_fixed_link(slave_node);
2046 if (ret)
2047 return ret;
2048 slave_data->phy_node = of_node_get(slave_node);
2049 } else if (parp) {
2050 u32 phyid;
2051 struct device_node *mdio_node;
2052 struct platform_device *mdio;
2053
2054 if (lenp != (sizeof(__be32) * 2)) {
2055 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2056 goto no_phy_slave;
2057 }
2058 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2059 phyid = be32_to_cpup(parp+1);
2060 mdio = of_find_device_by_node(mdio_node);
2061 of_node_put(mdio_node);
2062 if (!mdio) {
2063 dev_err(&pdev->dev, "Missing mdio platform device\n");
2064 return -EINVAL;
2065 }
2066 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2067 PHY_ID_FMT, mdio->name, phyid);
2068 } else {
2069 dev_err(&pdev->dev,
2070 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2071 i);
2072 goto no_phy_slave;
2073 }
2074 slave_data->phy_if = of_get_phy_mode(slave_node);
2075 if (slave_data->phy_if < 0) {
2076 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2077 i);
2078 return slave_data->phy_if;
2079 }
2080
2081 no_phy_slave:
2082 mac_addr = of_get_mac_address(slave_node);
2083 if (mac_addr) {
2084 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2085 } else {
2086 ret = ti_cm_get_macid(&pdev->dev, i,
2087 slave_data->mac_addr);
2088 if (ret)
2089 return ret;
2090 }
2091 if (data->dual_emac) {
2092 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2093 &prop)) {
2094 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2095 slave_data->dual_emac_res_vlan = i+1;
2096 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2097 slave_data->dual_emac_res_vlan, i);
2098 } else {
2099 slave_data->dual_emac_res_vlan = prop;
2100 }
2101 }
2102
2103 i++;
2104 if (i == data->slaves)
2105 break;
2106 }
2107
2108 return 0;
2109 }
2110
2111 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2112 struct cpsw_priv *priv)
2113 {
2114 struct cpsw_platform_data *data = &priv->data;
2115 struct net_device *ndev;
2116 struct cpsw_priv *priv_sl2;
2117 int ret = 0, i;
2118
2119 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2120 if (!ndev) {
2121 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2122 return -ENOMEM;
2123 }
2124
2125 priv_sl2 = netdev_priv(ndev);
2126 priv_sl2->data = *data;
2127 priv_sl2->pdev = pdev;
2128 priv_sl2->ndev = ndev;
2129 priv_sl2->dev = &ndev->dev;
2130 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2131 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2132
2133 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2134 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2135 ETH_ALEN);
2136 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2137 } else {
2138 random_ether_addr(priv_sl2->mac_addr);
2139 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2140 }
2141 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2142
2143 priv_sl2->slaves = priv->slaves;
2144 priv_sl2->clk = priv->clk;
2145
2146 priv_sl2->coal_intvl = 0;
2147 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2148
2149 priv_sl2->regs = priv->regs;
2150 priv_sl2->host_port_regs = priv->host_port_regs;
2151 priv_sl2->wr_regs = priv->wr_regs;
2152 priv_sl2->hw_stats = priv->hw_stats;
2153 priv_sl2->dma = priv->dma;
2154 priv_sl2->txch = priv->txch;
2155 priv_sl2->rxch = priv->rxch;
2156 priv_sl2->ale = priv->ale;
2157 priv_sl2->emac_port = 1;
2158 priv->slaves[1].ndev = ndev;
2159 priv_sl2->cpts = priv->cpts;
2160 priv_sl2->version = priv->version;
2161
2162 for (i = 0; i < priv->num_irqs; i++) {
2163 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2164 priv_sl2->num_irqs = priv->num_irqs;
2165 }
2166 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2167
2168 ndev->netdev_ops = &cpsw_netdev_ops;
2169 ndev->ethtool_ops = &cpsw_ethtool_ops;
2170
2171 /* register the network device */
2172 SET_NETDEV_DEV(ndev, &pdev->dev);
2173 ret = register_netdev(ndev);
2174 if (ret) {
2175 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2176 free_netdev(ndev);
2177 ret = -ENODEV;
2178 }
2179
2180 return ret;
2181 }
2182
2183 #define CPSW_QUIRK_IRQ BIT(0)
2184
2185 static struct platform_device_id cpsw_devtype[] = {
2186 {
2187 /* keep it for existing comaptibles */
2188 .name = "cpsw",
2189 .driver_data = CPSW_QUIRK_IRQ,
2190 }, {
2191 .name = "am335x-cpsw",
2192 .driver_data = CPSW_QUIRK_IRQ,
2193 }, {
2194 .name = "am4372-cpsw",
2195 .driver_data = 0,
2196 }, {
2197 .name = "dra7-cpsw",
2198 .driver_data = 0,
2199 }, {
2200 /* sentinel */
2201 }
2202 };
2203 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2204
2205 enum ti_cpsw_type {
2206 CPSW = 0,
2207 AM335X_CPSW,
2208 AM4372_CPSW,
2209 DRA7_CPSW,
2210 };
2211
2212 static const struct of_device_id cpsw_of_mtable[] = {
2213 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2214 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2215 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2216 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2217 { /* sentinel */ },
2218 };
2219 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2220
2221 static int cpsw_probe(struct platform_device *pdev)
2222 {
2223 struct cpsw_platform_data *data;
2224 struct net_device *ndev;
2225 struct cpsw_priv *priv;
2226 struct cpdma_params dma_params;
2227 struct cpsw_ale_params ale_params;
2228 void __iomem *ss_regs;
2229 struct resource *res, *ss_res;
2230 const struct of_device_id *of_id;
2231 struct gpio_descs *mode;
2232 u32 slave_offset, sliver_offset, slave_size;
2233 int ret = 0, i;
2234 int irq;
2235
2236 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2237 if (!ndev) {
2238 dev_err(&pdev->dev, "error allocating net_device\n");
2239 return -ENOMEM;
2240 }
2241
2242 platform_set_drvdata(pdev, ndev);
2243 priv = netdev_priv(ndev);
2244 priv->pdev = pdev;
2245 priv->ndev = ndev;
2246 priv->dev = &ndev->dev;
2247 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2248 priv->rx_packet_max = max(rx_packet_max, 128);
2249 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2250 if (!priv->cpts) {
2251 dev_err(&pdev->dev, "error allocating cpts\n");
2252 ret = -ENOMEM;
2253 goto clean_ndev_ret;
2254 }
2255
2256 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2257 if (IS_ERR(mode)) {
2258 ret = PTR_ERR(mode);
2259 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2260 goto clean_ndev_ret;
2261 }
2262
2263 /*
2264 * This may be required here for child devices.
2265 */
2266 pm_runtime_enable(&pdev->dev);
2267
2268 /* Select default pin state */
2269 pinctrl_pm_select_default_state(&pdev->dev);
2270
2271 if (cpsw_probe_dt(&priv->data, pdev)) {
2272 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2273 ret = -ENODEV;
2274 goto clean_runtime_disable_ret;
2275 }
2276 data = &priv->data;
2277
2278 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2279 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2280 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2281 } else {
2282 eth_random_addr(priv->mac_addr);
2283 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2284 }
2285
2286 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2287
2288 priv->slaves = devm_kzalloc(&pdev->dev,
2289 sizeof(struct cpsw_slave) * data->slaves,
2290 GFP_KERNEL);
2291 if (!priv->slaves) {
2292 ret = -ENOMEM;
2293 goto clean_runtime_disable_ret;
2294 }
2295 for (i = 0; i < data->slaves; i++)
2296 priv->slaves[i].slave_num = i;
2297
2298 priv->slaves[0].ndev = ndev;
2299 priv->emac_port = 0;
2300
2301 priv->clk = devm_clk_get(&pdev->dev, "fck");
2302 if (IS_ERR(priv->clk)) {
2303 dev_err(priv->dev, "fck is not found\n");
2304 ret = -ENODEV;
2305 goto clean_runtime_disable_ret;
2306 }
2307 priv->coal_intvl = 0;
2308 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2309
2310 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2311 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2312 if (IS_ERR(ss_regs)) {
2313 ret = PTR_ERR(ss_regs);
2314 goto clean_runtime_disable_ret;
2315 }
2316 priv->regs = ss_regs;
2317
2318 /* Need to enable clocks with runtime PM api to access module
2319 * registers
2320 */
2321 pm_runtime_get_sync(&pdev->dev);
2322 priv->version = readl(&priv->regs->id_ver);
2323 pm_runtime_put_sync(&pdev->dev);
2324
2325 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2326 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2327 if (IS_ERR(priv->wr_regs)) {
2328 ret = PTR_ERR(priv->wr_regs);
2329 goto clean_runtime_disable_ret;
2330 }
2331
2332 memset(&dma_params, 0, sizeof(dma_params));
2333 memset(&ale_params, 0, sizeof(ale_params));
2334
2335 switch (priv->version) {
2336 case CPSW_VERSION_1:
2337 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2338 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2339 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
2340 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2341 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2342 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2343 slave_offset = CPSW1_SLAVE_OFFSET;
2344 slave_size = CPSW1_SLAVE_SIZE;
2345 sliver_offset = CPSW1_SLIVER_OFFSET;
2346 dma_params.desc_mem_phys = 0;
2347 break;
2348 case CPSW_VERSION_2:
2349 case CPSW_VERSION_3:
2350 case CPSW_VERSION_4:
2351 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2352 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2353 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
2354 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2355 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2356 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2357 slave_offset = CPSW2_SLAVE_OFFSET;
2358 slave_size = CPSW2_SLAVE_SIZE;
2359 sliver_offset = CPSW2_SLIVER_OFFSET;
2360 dma_params.desc_mem_phys =
2361 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2362 break;
2363 default:
2364 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2365 ret = -ENODEV;
2366 goto clean_runtime_disable_ret;
2367 }
2368 for (i = 0; i < priv->data.slaves; i++) {
2369 struct cpsw_slave *slave = &priv->slaves[i];
2370 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2371 slave_offset += slave_size;
2372 sliver_offset += SLIVER_SIZE;
2373 }
2374
2375 dma_params.dev = &pdev->dev;
2376 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2377 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2378 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2379 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2380 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
2381
2382 dma_params.num_chan = data->channels;
2383 dma_params.has_soft_reset = true;
2384 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2385 dma_params.desc_mem_size = data->bd_ram_size;
2386 dma_params.desc_align = 16;
2387 dma_params.has_ext_regs = true;
2388 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
2389
2390 priv->dma = cpdma_ctlr_create(&dma_params);
2391 if (!priv->dma) {
2392 dev_err(priv->dev, "error initializing dma\n");
2393 ret = -ENOMEM;
2394 goto clean_runtime_disable_ret;
2395 }
2396
2397 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2398 cpsw_tx_handler);
2399 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2400 cpsw_rx_handler);
2401
2402 if (WARN_ON(!priv->txch || !priv->rxch)) {
2403 dev_err(priv->dev, "error initializing dma channels\n");
2404 ret = -ENOMEM;
2405 goto clean_dma_ret;
2406 }
2407
2408 ale_params.dev = &ndev->dev;
2409 ale_params.ale_ageout = ale_ageout;
2410 ale_params.ale_entries = data->ale_entries;
2411 ale_params.ale_ports = data->slaves;
2412
2413 priv->ale = cpsw_ale_create(&ale_params);
2414 if (!priv->ale) {
2415 dev_err(priv->dev, "error initializing ale engine\n");
2416 ret = -ENODEV;
2417 goto clean_dma_ret;
2418 }
2419
2420 ndev->irq = platform_get_irq(pdev, 1);
2421 if (ndev->irq < 0) {
2422 dev_err(priv->dev, "error getting irq resource\n");
2423 ret = ndev->irq;
2424 goto clean_ale_ret;
2425 }
2426
2427 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2428 if (of_id) {
2429 pdev->id_entry = of_id->data;
2430 if (pdev->id_entry->driver_data)
2431 priv->quirk_irq = true;
2432 }
2433
2434 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2435 * MISC IRQs which are always kept disabled with this driver so
2436 * we will not request them.
2437 *
2438 * If anyone wants to implement support for those, make sure to
2439 * first request and append them to irqs_table array.
2440 */
2441
2442 /* RX IRQ */
2443 irq = platform_get_irq(pdev, 1);
2444 if (irq < 0) {
2445 ret = irq;
2446 goto clean_ale_ret;
2447 }
2448
2449 priv->irqs_table[0] = irq;
2450 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2451 0, dev_name(&pdev->dev), priv);
2452 if (ret < 0) {
2453 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2454 goto clean_ale_ret;
2455 }
2456
2457 /* TX IRQ */
2458 irq = platform_get_irq(pdev, 2);
2459 if (irq < 0) {
2460 ret = irq;
2461 goto clean_ale_ret;
2462 }
2463
2464 priv->irqs_table[1] = irq;
2465 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2466 0, dev_name(&pdev->dev), priv);
2467 if (ret < 0) {
2468 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2469 goto clean_ale_ret;
2470 }
2471 priv->num_irqs = 2;
2472
2473 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2474
2475 ndev->netdev_ops = &cpsw_netdev_ops;
2476 ndev->ethtool_ops = &cpsw_ethtool_ops;
2477 netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2478 netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2479
2480 /* register the network device */
2481 SET_NETDEV_DEV(ndev, &pdev->dev);
2482 ret = register_netdev(ndev);
2483 if (ret) {
2484 dev_err(priv->dev, "error registering net device\n");
2485 ret = -ENODEV;
2486 goto clean_ale_ret;
2487 }
2488
2489 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2490 &ss_res->start, ndev->irq);
2491
2492 if (priv->data.dual_emac) {
2493 ret = cpsw_probe_dual_emac(pdev, priv);
2494 if (ret) {
2495 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2496 goto clean_ale_ret;
2497 }
2498 }
2499
2500 return 0;
2501
2502 clean_ale_ret:
2503 cpsw_ale_destroy(priv->ale);
2504 clean_dma_ret:
2505 cpdma_chan_destroy(priv->txch);
2506 cpdma_chan_destroy(priv->rxch);
2507 cpdma_ctlr_destroy(priv->dma);
2508 clean_runtime_disable_ret:
2509 pm_runtime_disable(&pdev->dev);
2510 clean_ndev_ret:
2511 free_netdev(priv->ndev);
2512 return ret;
2513 }
2514
2515 static int cpsw_remove_child_device(struct device *dev, void *c)
2516 {
2517 struct platform_device *pdev = to_platform_device(dev);
2518
2519 of_device_unregister(pdev);
2520
2521 return 0;
2522 }
2523
2524 static int cpsw_remove(struct platform_device *pdev)
2525 {
2526 struct net_device *ndev = platform_get_drvdata(pdev);
2527 struct cpsw_priv *priv = netdev_priv(ndev);
2528
2529 if (priv->data.dual_emac)
2530 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2531 unregister_netdev(ndev);
2532
2533 cpsw_ale_destroy(priv->ale);
2534 cpdma_chan_destroy(priv->txch);
2535 cpdma_chan_destroy(priv->rxch);
2536 cpdma_ctlr_destroy(priv->dma);
2537 pm_runtime_disable(&pdev->dev);
2538 device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2539 if (priv->data.dual_emac)
2540 free_netdev(cpsw_get_slave_ndev(priv, 1));
2541 free_netdev(ndev);
2542 return 0;
2543 }
2544
2545 #ifdef CONFIG_PM_SLEEP
2546 static int cpsw_suspend(struct device *dev)
2547 {
2548 struct platform_device *pdev = to_platform_device(dev);
2549 struct net_device *ndev = platform_get_drvdata(pdev);
2550 struct cpsw_priv *priv = netdev_priv(ndev);
2551
2552 if (priv->data.dual_emac) {
2553 int i;
2554
2555 for (i = 0; i < priv->data.slaves; i++) {
2556 if (netif_running(priv->slaves[i].ndev))
2557 cpsw_ndo_stop(priv->slaves[i].ndev);
2558 soft_reset_slave(priv->slaves + i);
2559 }
2560 } else {
2561 if (netif_running(ndev))
2562 cpsw_ndo_stop(ndev);
2563 for_each_slave(priv, soft_reset_slave);
2564 }
2565
2566 pm_runtime_put_sync(&pdev->dev);
2567
2568 /* Select sleep pin state */
2569 pinctrl_pm_select_sleep_state(&pdev->dev);
2570
2571 return 0;
2572 }
2573
2574 static int cpsw_resume(struct device *dev)
2575 {
2576 struct platform_device *pdev = to_platform_device(dev);
2577 struct net_device *ndev = platform_get_drvdata(pdev);
2578 struct cpsw_priv *priv = netdev_priv(ndev);
2579
2580 pm_runtime_get_sync(&pdev->dev);
2581
2582 /* Select default pin state */
2583 pinctrl_pm_select_default_state(&pdev->dev);
2584
2585 if (priv->data.dual_emac) {
2586 int i;
2587
2588 for (i = 0; i < priv->data.slaves; i++) {
2589 if (netif_running(priv->slaves[i].ndev))
2590 cpsw_ndo_open(priv->slaves[i].ndev);
2591 }
2592 } else {
2593 if (netif_running(ndev))
2594 cpsw_ndo_open(ndev);
2595 }
2596 return 0;
2597 }
2598 #endif
2599
2600 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2601
2602 static struct platform_driver cpsw_driver = {
2603 .driver = {
2604 .name = "cpsw",
2605 .pm = &cpsw_pm_ops,
2606 .of_match_table = cpsw_of_mtable,
2607 },
2608 .probe = cpsw_probe,
2609 .remove = cpsw_remove,
2610 };
2611
2612 module_platform_driver(cpsw_driver);
2613
2614 MODULE_LICENSE("GPL");
2615 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2616 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2617 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
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