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net: ethernet: ti: cpsw: combine budget and weight split and check
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / ti / cpsw.c
1 /*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio.h>
33 #include <linux/of.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
38
39 #include <linux/pinctrl/consumer.h>
40
41 #include "cpsw.h"
42 #include "cpsw_ale.h"
43 #include "cpts.h"
44 #include "davinci_cpdma.h"
45
46 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55 #define cpsw_info(priv, type, format, ...) \
56 do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59 } while (0)
60
61 #define cpsw_err(priv, type, format, ...) \
62 do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65 } while (0)
66
67 #define cpsw_dbg(priv, type, format, ...) \
68 do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71 } while (0)
72
73 #define cpsw_notice(priv, type, format, ...) \
74 do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77 } while (0)
78
79 #define ALE_ALL_PORTS 0x7
80
81 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
85 #define CPSW_VERSION_1 0x19010a
86 #define CPSW_VERSION_2 0x19010c
87 #define CPSW_VERSION_3 0x19010f
88 #define CPSW_VERSION_4 0x190112
89
90 #define HOST_PORT_NUM 0
91 #define SLIVER_SIZE 0x40
92
93 #define CPSW1_HOST_PORT_OFFSET 0x028
94 #define CPSW1_SLAVE_OFFSET 0x050
95 #define CPSW1_SLAVE_SIZE 0x040
96 #define CPSW1_CPDMA_OFFSET 0x100
97 #define CPSW1_STATERAM_OFFSET 0x200
98 #define CPSW1_HW_STATS 0x400
99 #define CPSW1_CPTS_OFFSET 0x500
100 #define CPSW1_ALE_OFFSET 0x600
101 #define CPSW1_SLIVER_OFFSET 0x700
102
103 #define CPSW2_HOST_PORT_OFFSET 0x108
104 #define CPSW2_SLAVE_OFFSET 0x200
105 #define CPSW2_SLAVE_SIZE 0x100
106 #define CPSW2_CPDMA_OFFSET 0x800
107 #define CPSW2_HW_STATS 0x900
108 #define CPSW2_STATERAM_OFFSET 0xa00
109 #define CPSW2_CPTS_OFFSET 0xc00
110 #define CPSW2_ALE_OFFSET 0xd00
111 #define CPSW2_SLIVER_OFFSET 0xd80
112 #define CPSW2_BD_OFFSET 0x2000
113
114 #define CPDMA_RXTHRESH 0x0c0
115 #define CPDMA_RXFREE 0x0e0
116 #define CPDMA_TXHDP 0x00
117 #define CPDMA_RXHDP 0x20
118 #define CPDMA_TXCP 0x40
119 #define CPDMA_RXCP 0x60
120
121 #define CPSW_POLL_WEIGHT 64
122 #define CPSW_MIN_PACKET_SIZE 60
123 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125 #define RX_PRIORITY_MAPPING 0x76543210
126 #define TX_PRIORITY_MAPPING 0x33221100
127 #define CPDMA_TX_PRIORITY_MAP 0x01234567
128
129 #define CPSW_VLAN_AWARE BIT(1)
130 #define CPSW_ALE_VLAN_AWARE 1
131
132 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
135
136 #define CPSW_INTPACEEN (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT 63
139 #define CPSW_CMINTMIN_CNT 2
140 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
143 #define cpsw_slave_index(cpsw, priv) \
144 ((cpsw->data.dual_emac) ? priv->emac_port : \
145 cpsw->data.active_slave)
146 #define IRQ_NUM 2
147 #define CPSW_MAX_QUEUES 8
148
149 static int debug_level;
150 module_param(debug_level, int, 0);
151 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
152
153 static int ale_ageout = 10;
154 module_param(ale_ageout, int, 0);
155 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
156
157 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
158 module_param(rx_packet_max, int, 0);
159 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
160
161 struct cpsw_wr_regs {
162 u32 id_ver;
163 u32 soft_reset;
164 u32 control;
165 u32 int_control;
166 u32 rx_thresh_en;
167 u32 rx_en;
168 u32 tx_en;
169 u32 misc_en;
170 u32 mem_allign1[8];
171 u32 rx_thresh_stat;
172 u32 rx_stat;
173 u32 tx_stat;
174 u32 misc_stat;
175 u32 mem_allign2[8];
176 u32 rx_imax;
177 u32 tx_imax;
178
179 };
180
181 struct cpsw_ss_regs {
182 u32 id_ver;
183 u32 control;
184 u32 soft_reset;
185 u32 stat_port_en;
186 u32 ptype;
187 u32 soft_idle;
188 u32 thru_rate;
189 u32 gap_thresh;
190 u32 tx_start_wds;
191 u32 flow_control;
192 u32 vlan_ltype;
193 u32 ts_ltype;
194 u32 dlr_ltype;
195 };
196
197 /* CPSW_PORT_V1 */
198 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
199 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
200 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
201 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
202 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
203 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
204 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
205 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
206
207 /* CPSW_PORT_V2 */
208 #define CPSW2_CONTROL 0x00 /* Control Register */
209 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
210 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
211 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
212 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
213 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
214 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
215
216 /* CPSW_PORT_V1 and V2 */
217 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
218 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
219 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
220
221 /* CPSW_PORT_V2 only */
222 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
226 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
227 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
228 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
229 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
230
231 /* Bit definitions for the CPSW2_CONTROL register */
232 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
233 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
234 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
235 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
236 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
237 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
238 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
239 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
240 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
241 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
242 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
243 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
244 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
245 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
246 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
247 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
248 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
249
250 #define CTRL_V2_TS_BITS \
251 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
252 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
253
254 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
255 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
256 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
257
258
259 #define CTRL_V3_TS_BITS \
260 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
261 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
262 TS_LTYPE1_EN)
263
264 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
265 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
266 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
267
268 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
269 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
270 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
271 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
272 #define TS_MSG_TYPE_EN_MASK (0xffff)
273
274 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
275 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
276
277 /* Bit definitions for the CPSW1_TS_CTL register */
278 #define CPSW_V1_TS_RX_EN BIT(0)
279 #define CPSW_V1_TS_TX_EN BIT(4)
280 #define CPSW_V1_MSG_TYPE_OFS 16
281
282 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
283 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
284
285 struct cpsw_host_regs {
286 u32 max_blks;
287 u32 blk_cnt;
288 u32 tx_in_ctl;
289 u32 port_vlan;
290 u32 tx_pri_map;
291 u32 cpdma_tx_pri_map;
292 u32 cpdma_rx_chan_map;
293 };
294
295 struct cpsw_sliver_regs {
296 u32 id_ver;
297 u32 mac_control;
298 u32 mac_status;
299 u32 soft_reset;
300 u32 rx_maxlen;
301 u32 __reserved_0;
302 u32 rx_pause;
303 u32 tx_pause;
304 u32 __reserved_1;
305 u32 rx_pri_map;
306 };
307
308 struct cpsw_hw_stats {
309 u32 rxgoodframes;
310 u32 rxbroadcastframes;
311 u32 rxmulticastframes;
312 u32 rxpauseframes;
313 u32 rxcrcerrors;
314 u32 rxaligncodeerrors;
315 u32 rxoversizedframes;
316 u32 rxjabberframes;
317 u32 rxundersizedframes;
318 u32 rxfragments;
319 u32 __pad_0[2];
320 u32 rxoctets;
321 u32 txgoodframes;
322 u32 txbroadcastframes;
323 u32 txmulticastframes;
324 u32 txpauseframes;
325 u32 txdeferredframes;
326 u32 txcollisionframes;
327 u32 txsinglecollframes;
328 u32 txmultcollframes;
329 u32 txexcessivecollisions;
330 u32 txlatecollisions;
331 u32 txunderrun;
332 u32 txcarriersenseerrors;
333 u32 txoctets;
334 u32 octetframes64;
335 u32 octetframes65t127;
336 u32 octetframes128t255;
337 u32 octetframes256t511;
338 u32 octetframes512t1023;
339 u32 octetframes1024tup;
340 u32 netoctets;
341 u32 rxsofoverruns;
342 u32 rxmofoverruns;
343 u32 rxdmaoverruns;
344 };
345
346 struct cpsw_slave {
347 void __iomem *regs;
348 struct cpsw_sliver_regs __iomem *sliver;
349 int slave_num;
350 u32 mac_control;
351 struct cpsw_slave_data *data;
352 struct phy_device *phy;
353 struct net_device *ndev;
354 u32 port_vlan;
355 u32 open_stat;
356 };
357
358 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
359 {
360 return __raw_readl(slave->regs + offset);
361 }
362
363 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
364 {
365 __raw_writel(val, slave->regs + offset);
366 }
367
368 struct cpsw_vector {
369 struct cpdma_chan *ch;
370 int budget;
371 };
372
373 struct cpsw_common {
374 struct device *dev;
375 struct cpsw_platform_data data;
376 struct napi_struct napi_rx;
377 struct napi_struct napi_tx;
378 struct cpsw_ss_regs __iomem *regs;
379 struct cpsw_wr_regs __iomem *wr_regs;
380 u8 __iomem *hw_stats;
381 struct cpsw_host_regs __iomem *host_port_regs;
382 u32 version;
383 u32 coal_intvl;
384 u32 bus_freq_mhz;
385 int rx_packet_max;
386 struct cpsw_slave *slaves;
387 struct cpdma_ctlr *dma;
388 struct cpsw_vector txv[CPSW_MAX_QUEUES];
389 struct cpsw_vector rxv[CPSW_MAX_QUEUES];
390 struct cpsw_ale *ale;
391 bool quirk_irq;
392 bool rx_irq_disabled;
393 bool tx_irq_disabled;
394 u32 irqs_table[IRQ_NUM];
395 struct cpts *cpts;
396 int rx_ch_num, tx_ch_num;
397 };
398
399 struct cpsw_priv {
400 struct net_device *ndev;
401 struct device *dev;
402 u32 msg_enable;
403 u8 mac_addr[ETH_ALEN];
404 bool rx_pause;
405 bool tx_pause;
406 u32 emac_port;
407 struct cpsw_common *cpsw;
408 };
409
410 struct cpsw_stats {
411 char stat_string[ETH_GSTRING_LEN];
412 int type;
413 int sizeof_stat;
414 int stat_offset;
415 };
416
417 enum {
418 CPSW_STATS,
419 CPDMA_RX_STATS,
420 CPDMA_TX_STATS,
421 };
422
423 #define CPSW_STAT(m) CPSW_STATS, \
424 sizeof(((struct cpsw_hw_stats *)0)->m), \
425 offsetof(struct cpsw_hw_stats, m)
426 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
427 sizeof(((struct cpdma_chan_stats *)0)->m), \
428 offsetof(struct cpdma_chan_stats, m)
429 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
430 sizeof(((struct cpdma_chan_stats *)0)->m), \
431 offsetof(struct cpdma_chan_stats, m)
432
433 static const struct cpsw_stats cpsw_gstrings_stats[] = {
434 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
435 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
436 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
437 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
438 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
439 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
440 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
441 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
442 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
443 { "Rx Fragments", CPSW_STAT(rxfragments) },
444 { "Rx Octets", CPSW_STAT(rxoctets) },
445 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
446 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
447 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
448 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
449 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
450 { "Collisions", CPSW_STAT(txcollisionframes) },
451 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
452 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
453 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
454 { "Late Collisions", CPSW_STAT(txlatecollisions) },
455 { "Tx Underrun", CPSW_STAT(txunderrun) },
456 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
457 { "Tx Octets", CPSW_STAT(txoctets) },
458 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
459 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
460 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
461 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
462 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
463 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
464 { "Net Octets", CPSW_STAT(netoctets) },
465 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
466 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
467 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
468 };
469
470 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
471 { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
472 { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
473 { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
474 { "misqueued", CPDMA_RX_STAT(misqueued) },
475 { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
476 { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
477 { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
478 { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
479 { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
480 { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
481 { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
482 { "requeue", CPDMA_RX_STAT(requeue) },
483 { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
484 };
485
486 #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats)
487 #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats)
488
489 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
490 #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
491 #define for_each_slave(priv, func, arg...) \
492 do { \
493 struct cpsw_slave *slave; \
494 struct cpsw_common *cpsw = (priv)->cpsw; \
495 int n; \
496 if (cpsw->data.dual_emac) \
497 (func)((cpsw)->slaves + priv->emac_port, ##arg);\
498 else \
499 for (n = cpsw->data.slaves, \
500 slave = cpsw->slaves; \
501 n; n--) \
502 (func)(slave++, ##arg); \
503 } while (0)
504
505 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \
506 do { \
507 if (!cpsw->data.dual_emac) \
508 break; \
509 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
510 ndev = cpsw->slaves[0].ndev; \
511 skb->dev = ndev; \
512 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
513 ndev = cpsw->slaves[1].ndev; \
514 skb->dev = ndev; \
515 } \
516 } while (0)
517 #define cpsw_add_mcast(cpsw, priv, addr) \
518 do { \
519 if (cpsw->data.dual_emac) { \
520 struct cpsw_slave *slave = cpsw->slaves + \
521 priv->emac_port; \
522 int slave_port = cpsw_get_slave_port( \
523 slave->slave_num); \
524 cpsw_ale_add_mcast(cpsw->ale, addr, \
525 1 << slave_port | ALE_PORT_HOST, \
526 ALE_VLAN, slave->port_vlan, 0); \
527 } else { \
528 cpsw_ale_add_mcast(cpsw->ale, addr, \
529 ALE_ALL_PORTS, \
530 0, 0, 0); \
531 } \
532 } while (0)
533
534 static inline int cpsw_get_slave_port(u32 slave_num)
535 {
536 return slave_num + 1;
537 }
538
539 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
540 {
541 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
542 struct cpsw_ale *ale = cpsw->ale;
543 int i;
544
545 if (cpsw->data.dual_emac) {
546 bool flag = false;
547
548 /* Enabling promiscuous mode for one interface will be
549 * common for both the interface as the interface shares
550 * the same hardware resource.
551 */
552 for (i = 0; i < cpsw->data.slaves; i++)
553 if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
554 flag = true;
555
556 if (!enable && flag) {
557 enable = true;
558 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
559 }
560
561 if (enable) {
562 /* Enable Bypass */
563 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
564
565 dev_dbg(&ndev->dev, "promiscuity enabled\n");
566 } else {
567 /* Disable Bypass */
568 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
569 dev_dbg(&ndev->dev, "promiscuity disabled\n");
570 }
571 } else {
572 if (enable) {
573 unsigned long timeout = jiffies + HZ;
574
575 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
576 for (i = 0; i <= cpsw->data.slaves; i++) {
577 cpsw_ale_control_set(ale, i,
578 ALE_PORT_NOLEARN, 1);
579 cpsw_ale_control_set(ale, i,
580 ALE_PORT_NO_SA_UPDATE, 1);
581 }
582
583 /* Clear All Untouched entries */
584 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
585 do {
586 cpu_relax();
587 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
588 break;
589 } while (time_after(timeout, jiffies));
590 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
591
592 /* Clear all mcast from ALE */
593 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
594
595 /* Flood All Unicast Packets to Host port */
596 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
597 dev_dbg(&ndev->dev, "promiscuity enabled\n");
598 } else {
599 /* Don't Flood All Unicast Packets to Host port */
600 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
601
602 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
603 for (i = 0; i <= cpsw->data.slaves; i++) {
604 cpsw_ale_control_set(ale, i,
605 ALE_PORT_NOLEARN, 0);
606 cpsw_ale_control_set(ale, i,
607 ALE_PORT_NO_SA_UPDATE, 0);
608 }
609 dev_dbg(&ndev->dev, "promiscuity disabled\n");
610 }
611 }
612 }
613
614 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
615 {
616 struct cpsw_priv *priv = netdev_priv(ndev);
617 struct cpsw_common *cpsw = priv->cpsw;
618 int vid;
619
620 if (cpsw->data.dual_emac)
621 vid = cpsw->slaves[priv->emac_port].port_vlan;
622 else
623 vid = cpsw->data.default_vlan;
624
625 if (ndev->flags & IFF_PROMISC) {
626 /* Enable promiscuous mode */
627 cpsw_set_promiscious(ndev, true);
628 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
629 return;
630 } else {
631 /* Disable promiscuous mode */
632 cpsw_set_promiscious(ndev, false);
633 }
634
635 /* Restore allmulti on vlans if necessary */
636 cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
637
638 /* Clear all mcast from ALE */
639 cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
640
641 if (!netdev_mc_empty(ndev)) {
642 struct netdev_hw_addr *ha;
643
644 /* program multicast address list into ALE register */
645 netdev_for_each_mc_addr(ha, ndev) {
646 cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
647 }
648 }
649 }
650
651 static void cpsw_intr_enable(struct cpsw_common *cpsw)
652 {
653 __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
654 __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
655
656 cpdma_ctlr_int_ctrl(cpsw->dma, true);
657 return;
658 }
659
660 static void cpsw_intr_disable(struct cpsw_common *cpsw)
661 {
662 __raw_writel(0, &cpsw->wr_regs->tx_en);
663 __raw_writel(0, &cpsw->wr_regs->rx_en);
664
665 cpdma_ctlr_int_ctrl(cpsw->dma, false);
666 return;
667 }
668
669 static void cpsw_tx_handler(void *token, int len, int status)
670 {
671 struct netdev_queue *txq;
672 struct sk_buff *skb = token;
673 struct net_device *ndev = skb->dev;
674 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
675
676 /* Check whether the queue is stopped due to stalled tx dma, if the
677 * queue is stopped then start the queue as we have free desc for tx
678 */
679 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
680 if (unlikely(netif_tx_queue_stopped(txq)))
681 netif_tx_wake_queue(txq);
682
683 cpts_tx_timestamp(cpsw->cpts, skb);
684 ndev->stats.tx_packets++;
685 ndev->stats.tx_bytes += len;
686 dev_kfree_skb_any(skb);
687 }
688
689 static void cpsw_rx_handler(void *token, int len, int status)
690 {
691 struct cpdma_chan *ch;
692 struct sk_buff *skb = token;
693 struct sk_buff *new_skb;
694 struct net_device *ndev = skb->dev;
695 int ret = 0;
696 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
697
698 cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
699
700 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
701 bool ndev_status = false;
702 struct cpsw_slave *slave = cpsw->slaves;
703 int n;
704
705 if (cpsw->data.dual_emac) {
706 /* In dual emac mode check for all interfaces */
707 for (n = cpsw->data.slaves; n; n--, slave++)
708 if (netif_running(slave->ndev))
709 ndev_status = true;
710 }
711
712 if (ndev_status && (status >= 0)) {
713 /* The packet received is for the interface which
714 * is already down and the other interface is up
715 * and running, instead of freeing which results
716 * in reducing of the number of rx descriptor in
717 * DMA engine, requeue skb back to cpdma.
718 */
719 new_skb = skb;
720 goto requeue;
721 }
722
723 /* the interface is going down, skbs are purged */
724 dev_kfree_skb_any(skb);
725 return;
726 }
727
728 new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
729 if (new_skb) {
730 skb_copy_queue_mapping(new_skb, skb);
731 skb_put(skb, len);
732 cpts_rx_timestamp(cpsw->cpts, skb);
733 skb->protocol = eth_type_trans(skb, ndev);
734 netif_receive_skb(skb);
735 ndev->stats.rx_bytes += len;
736 ndev->stats.rx_packets++;
737 kmemleak_not_leak(new_skb);
738 } else {
739 ndev->stats.rx_dropped++;
740 new_skb = skb;
741 }
742
743 requeue:
744 if (netif_dormant(ndev)) {
745 dev_kfree_skb_any(new_skb);
746 return;
747 }
748
749 ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
750 ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
751 skb_tailroom(new_skb), 0);
752 if (WARN_ON(ret < 0))
753 dev_kfree_skb_any(new_skb);
754 }
755
756 static void cpsw_split_res(struct net_device *ndev)
757 {
758 struct cpsw_priv *priv = netdev_priv(ndev);
759 u32 consumed_rate = 0, bigest_rate = 0;
760 struct cpsw_common *cpsw = priv->cpsw;
761 struct cpsw_vector *txv = cpsw->txv;
762 int i, ch_weight, rlim_ch_num = 0;
763 int budget, bigest_rate_ch = 0;
764 struct cpsw_slave *slave;
765 u32 ch_rate, max_rate;
766 int ch_budget = 0;
767
768 for (i = 0; i < cpsw->tx_ch_num; i++) {
769 ch_rate = cpdma_chan_get_rate(txv[i].ch);
770 if (!ch_rate)
771 continue;
772
773 rlim_ch_num++;
774 consumed_rate += ch_rate;
775 }
776
777 if (cpsw->tx_ch_num == rlim_ch_num) {
778 max_rate = consumed_rate;
779 } else if (!rlim_ch_num) {
780 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
781 bigest_rate = 0;
782 max_rate = consumed_rate;
783 } else {
784 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
785 max_rate = slave->phy->speed * 1000;
786
787 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
788 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
789 (cpsw->tx_ch_num - rlim_ch_num);
790 bigest_rate = (max_rate - consumed_rate) /
791 (cpsw->tx_ch_num - rlim_ch_num);
792 }
793
794 /* split tx weight/budget */
795 budget = CPSW_POLL_WEIGHT;
796 for (i = 0; i < cpsw->tx_ch_num; i++) {
797 ch_rate = cpdma_chan_get_rate(txv[i].ch);
798 if (ch_rate) {
799 txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
800 if (!txv[i].budget)
801 txv[i].budget++;
802 if (ch_rate > bigest_rate) {
803 bigest_rate_ch = i;
804 bigest_rate = ch_rate;
805 }
806
807 ch_weight = (ch_rate * 100) / max_rate;
808 if (!ch_weight)
809 ch_weight++;
810 cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
811 } else {
812 txv[i].budget = ch_budget;
813 if (!bigest_rate_ch)
814 bigest_rate_ch = i;
815 cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
816 }
817
818 budget -= txv[i].budget;
819 }
820
821 if (budget)
822 txv[bigest_rate_ch].budget += budget;
823
824 /* split rx budget */
825 budget = CPSW_POLL_WEIGHT;
826 ch_budget = budget / cpsw->rx_ch_num;
827 for (i = 0; i < cpsw->rx_ch_num; i++) {
828 cpsw->rxv[i].budget = ch_budget;
829 budget -= ch_budget;
830 }
831
832 if (budget)
833 cpsw->rxv[0].budget += budget;
834 }
835
836 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
837 {
838 struct cpsw_common *cpsw = dev_id;
839
840 writel(0, &cpsw->wr_regs->tx_en);
841 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
842
843 if (cpsw->quirk_irq) {
844 disable_irq_nosync(cpsw->irqs_table[1]);
845 cpsw->tx_irq_disabled = true;
846 }
847
848 napi_schedule(&cpsw->napi_tx);
849 return IRQ_HANDLED;
850 }
851
852 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
853 {
854 struct cpsw_common *cpsw = dev_id;
855
856 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
857 writel(0, &cpsw->wr_regs->rx_en);
858
859 if (cpsw->quirk_irq) {
860 disable_irq_nosync(cpsw->irqs_table[0]);
861 cpsw->rx_irq_disabled = true;
862 }
863
864 napi_schedule(&cpsw->napi_rx);
865 return IRQ_HANDLED;
866 }
867
868 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
869 {
870 u32 ch_map;
871 int num_tx, cur_budget, ch;
872 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
873 struct cpsw_vector *txv;
874
875 /* process every unprocessed channel */
876 ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
877 for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
878 if (!(ch_map & 0x01))
879 continue;
880
881 txv = &cpsw->txv[ch];
882 if (unlikely(txv->budget > budget - num_tx))
883 cur_budget = budget - num_tx;
884 else
885 cur_budget = txv->budget;
886
887 num_tx += cpdma_chan_process(txv->ch, cur_budget);
888 if (num_tx >= budget)
889 break;
890 }
891
892 if (num_tx < budget) {
893 napi_complete(napi_tx);
894 writel(0xff, &cpsw->wr_regs->tx_en);
895 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
896 cpsw->tx_irq_disabled = false;
897 enable_irq(cpsw->irqs_table[1]);
898 }
899 }
900
901 return num_tx;
902 }
903
904 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
905 {
906 u32 ch_map;
907 int num_rx, cur_budget, ch;
908 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
909 struct cpsw_vector *rxv;
910
911 /* process every unprocessed channel */
912 ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
913 for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
914 if (!(ch_map & 0x01))
915 continue;
916
917 rxv = &cpsw->rxv[ch];
918 if (unlikely(rxv->budget > budget - num_rx))
919 cur_budget = budget - num_rx;
920 else
921 cur_budget = rxv->budget;
922
923 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
924 if (num_rx >= budget)
925 break;
926 }
927
928 if (num_rx < budget) {
929 napi_complete(napi_rx);
930 writel(0xff, &cpsw->wr_regs->rx_en);
931 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
932 cpsw->rx_irq_disabled = false;
933 enable_irq(cpsw->irqs_table[0]);
934 }
935 }
936
937 return num_rx;
938 }
939
940 static inline void soft_reset(const char *module, void __iomem *reg)
941 {
942 unsigned long timeout = jiffies + HZ;
943
944 __raw_writel(1, reg);
945 do {
946 cpu_relax();
947 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
948
949 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
950 }
951
952 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
953 ((mac)[2] << 16) | ((mac)[3] << 24))
954 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
955
956 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
957 struct cpsw_priv *priv)
958 {
959 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
960 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
961 }
962
963 static void _cpsw_adjust_link(struct cpsw_slave *slave,
964 struct cpsw_priv *priv, bool *link)
965 {
966 struct phy_device *phy = slave->phy;
967 u32 mac_control = 0;
968 u32 slave_port;
969 struct cpsw_common *cpsw = priv->cpsw;
970
971 if (!phy)
972 return;
973
974 slave_port = cpsw_get_slave_port(slave->slave_num);
975
976 if (phy->link) {
977 mac_control = cpsw->data.mac_control;
978
979 /* enable forwarding */
980 cpsw_ale_control_set(cpsw->ale, slave_port,
981 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
982
983 if (phy->speed == 1000)
984 mac_control |= BIT(7); /* GIGABITEN */
985 if (phy->duplex)
986 mac_control |= BIT(0); /* FULLDUPLEXEN */
987
988 /* set speed_in input in case RMII mode is used in 100Mbps */
989 if (phy->speed == 100)
990 mac_control |= BIT(15);
991 else if (phy->speed == 10)
992 mac_control |= BIT(18); /* In Band mode */
993
994 if (priv->rx_pause)
995 mac_control |= BIT(3);
996
997 if (priv->tx_pause)
998 mac_control |= BIT(4);
999
1000 *link = true;
1001 } else {
1002 mac_control = 0;
1003 /* disable forwarding */
1004 cpsw_ale_control_set(cpsw->ale, slave_port,
1005 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1006 }
1007
1008 if (mac_control != slave->mac_control) {
1009 phy_print_status(phy);
1010 __raw_writel(mac_control, &slave->sliver->mac_control);
1011 }
1012
1013 slave->mac_control = mac_control;
1014 }
1015
1016 static void cpsw_adjust_link(struct net_device *ndev)
1017 {
1018 struct cpsw_priv *priv = netdev_priv(ndev);
1019 bool link = false;
1020
1021 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1022
1023 if (link) {
1024 cpsw_split_res(priv->ndev);
1025 netif_carrier_on(ndev);
1026 if (netif_running(ndev))
1027 netif_tx_wake_all_queues(ndev);
1028 } else {
1029 netif_carrier_off(ndev);
1030 netif_tx_stop_all_queues(ndev);
1031 }
1032 }
1033
1034 static int cpsw_get_coalesce(struct net_device *ndev,
1035 struct ethtool_coalesce *coal)
1036 {
1037 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1038
1039 coal->rx_coalesce_usecs = cpsw->coal_intvl;
1040 return 0;
1041 }
1042
1043 static int cpsw_set_coalesce(struct net_device *ndev,
1044 struct ethtool_coalesce *coal)
1045 {
1046 struct cpsw_priv *priv = netdev_priv(ndev);
1047 u32 int_ctrl;
1048 u32 num_interrupts = 0;
1049 u32 prescale = 0;
1050 u32 addnl_dvdr = 1;
1051 u32 coal_intvl = 0;
1052 struct cpsw_common *cpsw = priv->cpsw;
1053
1054 coal_intvl = coal->rx_coalesce_usecs;
1055
1056 int_ctrl = readl(&cpsw->wr_regs->int_control);
1057 prescale = cpsw->bus_freq_mhz * 4;
1058
1059 if (!coal->rx_coalesce_usecs) {
1060 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1061 goto update_return;
1062 }
1063
1064 if (coal_intvl < CPSW_CMINTMIN_INTVL)
1065 coal_intvl = CPSW_CMINTMIN_INTVL;
1066
1067 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1068 /* Interrupt pacer works with 4us Pulse, we can
1069 * throttle further by dilating the 4us pulse.
1070 */
1071 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1072
1073 if (addnl_dvdr > 1) {
1074 prescale *= addnl_dvdr;
1075 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1076 coal_intvl = (CPSW_CMINTMAX_INTVL
1077 * addnl_dvdr);
1078 } else {
1079 addnl_dvdr = 1;
1080 coal_intvl = CPSW_CMINTMAX_INTVL;
1081 }
1082 }
1083
1084 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1085 writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1086 writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1087
1088 int_ctrl |= CPSW_INTPACEEN;
1089 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1090 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1091
1092 update_return:
1093 writel(int_ctrl, &cpsw->wr_regs->int_control);
1094
1095 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1096 cpsw->coal_intvl = coal_intvl;
1097
1098 return 0;
1099 }
1100
1101 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1102 {
1103 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1104
1105 switch (sset) {
1106 case ETH_SS_STATS:
1107 return (CPSW_STATS_COMMON_LEN +
1108 (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1109 CPSW_STATS_CH_LEN);
1110 default:
1111 return -EOPNOTSUPP;
1112 }
1113 }
1114
1115 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1116 {
1117 int ch_stats_len;
1118 int line;
1119 int i;
1120
1121 ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1122 for (i = 0; i < ch_stats_len; i++) {
1123 line = i % CPSW_STATS_CH_LEN;
1124 snprintf(*p, ETH_GSTRING_LEN,
1125 "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1126 i / CPSW_STATS_CH_LEN,
1127 cpsw_gstrings_ch_stats[line].stat_string);
1128 *p += ETH_GSTRING_LEN;
1129 }
1130 }
1131
1132 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1133 {
1134 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1135 u8 *p = data;
1136 int i;
1137
1138 switch (stringset) {
1139 case ETH_SS_STATS:
1140 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1141 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1142 ETH_GSTRING_LEN);
1143 p += ETH_GSTRING_LEN;
1144 }
1145
1146 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1147 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1148 break;
1149 }
1150 }
1151
1152 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1153 struct ethtool_stats *stats, u64 *data)
1154 {
1155 u8 *p;
1156 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1157 struct cpdma_chan_stats ch_stats;
1158 int i, l, ch;
1159
1160 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1161 for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1162 data[l] = readl(cpsw->hw_stats +
1163 cpsw_gstrings_stats[l].stat_offset);
1164
1165 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1166 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1167 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1168 p = (u8 *)&ch_stats +
1169 cpsw_gstrings_ch_stats[i].stat_offset;
1170 data[l] = *(u32 *)p;
1171 }
1172 }
1173
1174 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1175 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1176 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1177 p = (u8 *)&ch_stats +
1178 cpsw_gstrings_ch_stats[i].stat_offset;
1179 data[l] = *(u32 *)p;
1180 }
1181 }
1182 }
1183
1184 static int cpsw_common_res_usage_state(struct cpsw_common *cpsw)
1185 {
1186 u32 i;
1187 u32 usage_count = 0;
1188
1189 if (!cpsw->data.dual_emac)
1190 return 0;
1191
1192 for (i = 0; i < cpsw->data.slaves; i++)
1193 if (cpsw->slaves[i].open_stat)
1194 usage_count++;
1195
1196 return usage_count;
1197 }
1198
1199 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1200 struct sk_buff *skb,
1201 struct cpdma_chan *txch)
1202 {
1203 struct cpsw_common *cpsw = priv->cpsw;
1204
1205 return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1206 priv->emac_port + cpsw->data.dual_emac);
1207 }
1208
1209 static inline void cpsw_add_dual_emac_def_ale_entries(
1210 struct cpsw_priv *priv, struct cpsw_slave *slave,
1211 u32 slave_port)
1212 {
1213 struct cpsw_common *cpsw = priv->cpsw;
1214 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1215
1216 if (cpsw->version == CPSW_VERSION_1)
1217 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1218 else
1219 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1220 cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1221 port_mask, port_mask, 0);
1222 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1223 port_mask, ALE_VLAN, slave->port_vlan, 0);
1224 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1225 HOST_PORT_NUM, ALE_VLAN |
1226 ALE_SECURE, slave->port_vlan);
1227 }
1228
1229 static void soft_reset_slave(struct cpsw_slave *slave)
1230 {
1231 char name[32];
1232
1233 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1234 soft_reset(name, &slave->sliver->soft_reset);
1235 }
1236
1237 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1238 {
1239 u32 slave_port;
1240 struct cpsw_common *cpsw = priv->cpsw;
1241
1242 soft_reset_slave(slave);
1243
1244 /* setup priority mapping */
1245 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1246
1247 switch (cpsw->version) {
1248 case CPSW_VERSION_1:
1249 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1250 break;
1251 case CPSW_VERSION_2:
1252 case CPSW_VERSION_3:
1253 case CPSW_VERSION_4:
1254 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1255 break;
1256 }
1257
1258 /* setup max packet size, and mac address */
1259 __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1260 cpsw_set_slave_mac(slave, priv);
1261
1262 slave->mac_control = 0; /* no link yet */
1263
1264 slave_port = cpsw_get_slave_port(slave->slave_num);
1265
1266 if (cpsw->data.dual_emac)
1267 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1268 else
1269 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1270 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1271
1272 if (slave->data->phy_node) {
1273 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1274 &cpsw_adjust_link, 0, slave->data->phy_if);
1275 if (!slave->phy) {
1276 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1277 slave->data->phy_node->full_name,
1278 slave->slave_num);
1279 return;
1280 }
1281 } else {
1282 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1283 &cpsw_adjust_link, slave->data->phy_if);
1284 if (IS_ERR(slave->phy)) {
1285 dev_err(priv->dev,
1286 "phy \"%s\" not found on slave %d, err %ld\n",
1287 slave->data->phy_id, slave->slave_num,
1288 PTR_ERR(slave->phy));
1289 slave->phy = NULL;
1290 return;
1291 }
1292 }
1293
1294 phy_attached_info(slave->phy);
1295
1296 phy_start(slave->phy);
1297
1298 /* Configure GMII_SEL register */
1299 cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1300 }
1301
1302 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1303 {
1304 struct cpsw_common *cpsw = priv->cpsw;
1305 const int vlan = cpsw->data.default_vlan;
1306 u32 reg;
1307 int i;
1308 int unreg_mcast_mask;
1309
1310 reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1311 CPSW2_PORT_VLAN;
1312
1313 writel(vlan, &cpsw->host_port_regs->port_vlan);
1314
1315 for (i = 0; i < cpsw->data.slaves; i++)
1316 slave_write(cpsw->slaves + i, vlan, reg);
1317
1318 if (priv->ndev->flags & IFF_ALLMULTI)
1319 unreg_mcast_mask = ALE_ALL_PORTS;
1320 else
1321 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1322
1323 cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1324 ALE_ALL_PORTS, ALE_ALL_PORTS,
1325 unreg_mcast_mask);
1326 }
1327
1328 static void cpsw_init_host_port(struct cpsw_priv *priv)
1329 {
1330 u32 fifo_mode;
1331 u32 control_reg;
1332 struct cpsw_common *cpsw = priv->cpsw;
1333
1334 /* soft reset the controller and initialize ale */
1335 soft_reset("cpsw", &cpsw->regs->soft_reset);
1336 cpsw_ale_start(cpsw->ale);
1337
1338 /* switch to vlan unaware mode */
1339 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1340 CPSW_ALE_VLAN_AWARE);
1341 control_reg = readl(&cpsw->regs->control);
1342 control_reg |= CPSW_VLAN_AWARE;
1343 writel(control_reg, &cpsw->regs->control);
1344 fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1345 CPSW_FIFO_NORMAL_MODE;
1346 writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1347
1348 /* setup host port priority mapping */
1349 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1350 &cpsw->host_port_regs->cpdma_tx_pri_map);
1351 __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1352
1353 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1354 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1355
1356 if (!cpsw->data.dual_emac) {
1357 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1358 0, 0);
1359 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1360 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1361 }
1362 }
1363
1364 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1365 {
1366 struct cpsw_common *cpsw = priv->cpsw;
1367 struct sk_buff *skb;
1368 int ch_buf_num;
1369 int ch, i, ret;
1370
1371 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1372 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1373 for (i = 0; i < ch_buf_num; i++) {
1374 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1375 cpsw->rx_packet_max,
1376 GFP_KERNEL);
1377 if (!skb) {
1378 cpsw_err(priv, ifup, "cannot allocate skb\n");
1379 return -ENOMEM;
1380 }
1381
1382 skb_set_queue_mapping(skb, ch);
1383 ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1384 skb->data, skb_tailroom(skb),
1385 0);
1386 if (ret < 0) {
1387 cpsw_err(priv, ifup,
1388 "cannot submit skb to channel %d rx, error %d\n",
1389 ch, ret);
1390 kfree_skb(skb);
1391 return ret;
1392 }
1393 kmemleak_not_leak(skb);
1394 }
1395
1396 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1397 ch, ch_buf_num);
1398 }
1399
1400 return 0;
1401 }
1402
1403 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1404 {
1405 u32 slave_port;
1406
1407 slave_port = cpsw_get_slave_port(slave->slave_num);
1408
1409 if (!slave->phy)
1410 return;
1411 phy_stop(slave->phy);
1412 phy_disconnect(slave->phy);
1413 slave->phy = NULL;
1414 cpsw_ale_control_set(cpsw->ale, slave_port,
1415 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1416 soft_reset_slave(slave);
1417 }
1418
1419 static int cpsw_ndo_open(struct net_device *ndev)
1420 {
1421 struct cpsw_priv *priv = netdev_priv(ndev);
1422 struct cpsw_common *cpsw = priv->cpsw;
1423 int ret;
1424 u32 reg;
1425
1426 ret = pm_runtime_get_sync(cpsw->dev);
1427 if (ret < 0) {
1428 pm_runtime_put_noidle(cpsw->dev);
1429 return ret;
1430 }
1431
1432 if (!cpsw_common_res_usage_state(cpsw))
1433 cpsw_intr_disable(cpsw);
1434 netif_carrier_off(ndev);
1435
1436 /* Notify the stack of the actual queue counts. */
1437 ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1438 if (ret) {
1439 dev_err(priv->dev, "cannot set real number of tx queues\n");
1440 goto err_cleanup;
1441 }
1442
1443 ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1444 if (ret) {
1445 dev_err(priv->dev, "cannot set real number of rx queues\n");
1446 goto err_cleanup;
1447 }
1448
1449 reg = cpsw->version;
1450
1451 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1452 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1453 CPSW_RTL_VERSION(reg));
1454
1455 /* initialize host and slave ports */
1456 if (!cpsw_common_res_usage_state(cpsw))
1457 cpsw_init_host_port(priv);
1458 for_each_slave(priv, cpsw_slave_open, priv);
1459
1460 /* Add default VLAN */
1461 if (!cpsw->data.dual_emac)
1462 cpsw_add_default_vlan(priv);
1463 else
1464 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1465 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1466
1467 if (!cpsw_common_res_usage_state(cpsw)) {
1468 /* disable priority elevation */
1469 __raw_writel(0, &cpsw->regs->ptype);
1470
1471 /* enable statistics collection only on all ports */
1472 __raw_writel(0x7, &cpsw->regs->stat_port_en);
1473
1474 /* Enable internal fifo flow control */
1475 writel(0x7, &cpsw->regs->flow_control);
1476
1477 napi_enable(&cpsw->napi_rx);
1478 napi_enable(&cpsw->napi_tx);
1479
1480 if (cpsw->tx_irq_disabled) {
1481 cpsw->tx_irq_disabled = false;
1482 enable_irq(cpsw->irqs_table[1]);
1483 }
1484
1485 if (cpsw->rx_irq_disabled) {
1486 cpsw->rx_irq_disabled = false;
1487 enable_irq(cpsw->irqs_table[0]);
1488 }
1489
1490 ret = cpsw_fill_rx_channels(priv);
1491 if (ret < 0)
1492 goto err_cleanup;
1493
1494 if (cpts_register(cpsw->cpts))
1495 dev_err(priv->dev, "error registering cpts device\n");
1496
1497 }
1498
1499 /* Enable Interrupt pacing if configured */
1500 if (cpsw->coal_intvl != 0) {
1501 struct ethtool_coalesce coal;
1502
1503 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1504 cpsw_set_coalesce(ndev, &coal);
1505 }
1506
1507 cpdma_ctlr_start(cpsw->dma);
1508 cpsw_intr_enable(cpsw);
1509
1510 if (cpsw->data.dual_emac)
1511 cpsw->slaves[priv->emac_port].open_stat = true;
1512
1513 return 0;
1514
1515 err_cleanup:
1516 cpdma_ctlr_stop(cpsw->dma);
1517 for_each_slave(priv, cpsw_slave_stop, cpsw);
1518 pm_runtime_put_sync(cpsw->dev);
1519 netif_carrier_off(priv->ndev);
1520 return ret;
1521 }
1522
1523 static int cpsw_ndo_stop(struct net_device *ndev)
1524 {
1525 struct cpsw_priv *priv = netdev_priv(ndev);
1526 struct cpsw_common *cpsw = priv->cpsw;
1527
1528 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1529 netif_tx_stop_all_queues(priv->ndev);
1530 netif_carrier_off(priv->ndev);
1531
1532 if (cpsw_common_res_usage_state(cpsw) <= 1) {
1533 napi_disable(&cpsw->napi_rx);
1534 napi_disable(&cpsw->napi_tx);
1535 cpts_unregister(cpsw->cpts);
1536 cpsw_intr_disable(cpsw);
1537 cpdma_ctlr_stop(cpsw->dma);
1538 cpsw_ale_stop(cpsw->ale);
1539 }
1540 for_each_slave(priv, cpsw_slave_stop, cpsw);
1541 pm_runtime_put_sync(cpsw->dev);
1542 if (cpsw->data.dual_emac)
1543 cpsw->slaves[priv->emac_port].open_stat = false;
1544 return 0;
1545 }
1546
1547 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1548 struct net_device *ndev)
1549 {
1550 struct cpsw_priv *priv = netdev_priv(ndev);
1551 struct cpsw_common *cpsw = priv->cpsw;
1552 struct netdev_queue *txq;
1553 struct cpdma_chan *txch;
1554 int ret, q_idx;
1555
1556 netif_trans_update(ndev);
1557
1558 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1559 cpsw_err(priv, tx_err, "packet pad failed\n");
1560 ndev->stats.tx_dropped++;
1561 return NETDEV_TX_OK;
1562 }
1563
1564 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1565 cpts_is_tx_enabled(cpsw->cpts))
1566 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1567
1568 skb_tx_timestamp(skb);
1569
1570 q_idx = skb_get_queue_mapping(skb);
1571 if (q_idx >= cpsw->tx_ch_num)
1572 q_idx = q_idx % cpsw->tx_ch_num;
1573
1574 txch = cpsw->txv[q_idx].ch;
1575 ret = cpsw_tx_packet_submit(priv, skb, txch);
1576 if (unlikely(ret != 0)) {
1577 cpsw_err(priv, tx_err, "desc submit failed\n");
1578 goto fail;
1579 }
1580
1581 /* If there is no more tx desc left free then we need to
1582 * tell the kernel to stop sending us tx frames.
1583 */
1584 if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1585 txq = netdev_get_tx_queue(ndev, q_idx);
1586 netif_tx_stop_queue(txq);
1587 }
1588
1589 return NETDEV_TX_OK;
1590 fail:
1591 ndev->stats.tx_dropped++;
1592 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
1593 netif_tx_stop_queue(txq);
1594 return NETDEV_TX_BUSY;
1595 }
1596
1597 #if IS_ENABLED(CONFIG_TI_CPTS)
1598
1599 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1600 {
1601 struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1602 u32 ts_en, seq_id;
1603
1604 if (!cpts_is_tx_enabled(cpsw->cpts) &&
1605 !cpts_is_rx_enabled(cpsw->cpts)) {
1606 slave_write(slave, 0, CPSW1_TS_CTL);
1607 return;
1608 }
1609
1610 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1611 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1612
1613 if (cpts_is_tx_enabled(cpsw->cpts))
1614 ts_en |= CPSW_V1_TS_TX_EN;
1615
1616 if (cpts_is_rx_enabled(cpsw->cpts))
1617 ts_en |= CPSW_V1_TS_RX_EN;
1618
1619 slave_write(slave, ts_en, CPSW1_TS_CTL);
1620 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1621 }
1622
1623 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1624 {
1625 struct cpsw_slave *slave;
1626 struct cpsw_common *cpsw = priv->cpsw;
1627 u32 ctrl, mtype;
1628
1629 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1630
1631 ctrl = slave_read(slave, CPSW2_CONTROL);
1632 switch (cpsw->version) {
1633 case CPSW_VERSION_2:
1634 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1635
1636 if (cpts_is_tx_enabled(cpsw->cpts))
1637 ctrl |= CTRL_V2_TX_TS_BITS;
1638
1639 if (cpts_is_rx_enabled(cpsw->cpts))
1640 ctrl |= CTRL_V2_RX_TS_BITS;
1641 break;
1642 case CPSW_VERSION_3:
1643 default:
1644 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1645
1646 if (cpts_is_tx_enabled(cpsw->cpts))
1647 ctrl |= CTRL_V3_TX_TS_BITS;
1648
1649 if (cpts_is_rx_enabled(cpsw->cpts))
1650 ctrl |= CTRL_V3_RX_TS_BITS;
1651 break;
1652 }
1653
1654 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1655
1656 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1657 slave_write(slave, ctrl, CPSW2_CONTROL);
1658 __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
1659 }
1660
1661 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1662 {
1663 struct cpsw_priv *priv = netdev_priv(dev);
1664 struct hwtstamp_config cfg;
1665 struct cpsw_common *cpsw = priv->cpsw;
1666 struct cpts *cpts = cpsw->cpts;
1667
1668 if (cpsw->version != CPSW_VERSION_1 &&
1669 cpsw->version != CPSW_VERSION_2 &&
1670 cpsw->version != CPSW_VERSION_3)
1671 return -EOPNOTSUPP;
1672
1673 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1674 return -EFAULT;
1675
1676 /* reserved for future extensions */
1677 if (cfg.flags)
1678 return -EINVAL;
1679
1680 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1681 return -ERANGE;
1682
1683 switch (cfg.rx_filter) {
1684 case HWTSTAMP_FILTER_NONE:
1685 cpts_rx_enable(cpts, 0);
1686 break;
1687 case HWTSTAMP_FILTER_ALL:
1688 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1689 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1690 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1691 return -ERANGE;
1692 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1693 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1694 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1695 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1696 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1697 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1698 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1699 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1700 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1701 cpts_rx_enable(cpts, 1);
1702 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1703 break;
1704 default:
1705 return -ERANGE;
1706 }
1707
1708 cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
1709
1710 switch (cpsw->version) {
1711 case CPSW_VERSION_1:
1712 cpsw_hwtstamp_v1(cpsw);
1713 break;
1714 case CPSW_VERSION_2:
1715 case CPSW_VERSION_3:
1716 cpsw_hwtstamp_v2(priv);
1717 break;
1718 default:
1719 WARN_ON(1);
1720 }
1721
1722 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1723 }
1724
1725 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1726 {
1727 struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1728 struct cpts *cpts = cpsw->cpts;
1729 struct hwtstamp_config cfg;
1730
1731 if (cpsw->version != CPSW_VERSION_1 &&
1732 cpsw->version != CPSW_VERSION_2 &&
1733 cpsw->version != CPSW_VERSION_3)
1734 return -EOPNOTSUPP;
1735
1736 cfg.flags = 0;
1737 cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1738 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1739 cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
1740 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1741
1742 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1743 }
1744 #else
1745 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1746 {
1747 return -EOPNOTSUPP;
1748 }
1749
1750 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1751 {
1752 return -EOPNOTSUPP;
1753 }
1754 #endif /*CONFIG_TI_CPTS*/
1755
1756 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1757 {
1758 struct cpsw_priv *priv = netdev_priv(dev);
1759 struct cpsw_common *cpsw = priv->cpsw;
1760 int slave_no = cpsw_slave_index(cpsw, priv);
1761
1762 if (!netif_running(dev))
1763 return -EINVAL;
1764
1765 switch (cmd) {
1766 case SIOCSHWTSTAMP:
1767 return cpsw_hwtstamp_set(dev, req);
1768 case SIOCGHWTSTAMP:
1769 return cpsw_hwtstamp_get(dev, req);
1770 }
1771
1772 if (!cpsw->slaves[slave_no].phy)
1773 return -EOPNOTSUPP;
1774 return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1775 }
1776
1777 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1778 {
1779 struct cpsw_priv *priv = netdev_priv(ndev);
1780 struct cpsw_common *cpsw = priv->cpsw;
1781 int ch;
1782
1783 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1784 ndev->stats.tx_errors++;
1785 cpsw_intr_disable(cpsw);
1786 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1787 cpdma_chan_stop(cpsw->txv[ch].ch);
1788 cpdma_chan_start(cpsw->txv[ch].ch);
1789 }
1790
1791 cpsw_intr_enable(cpsw);
1792 }
1793
1794 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1795 {
1796 struct cpsw_priv *priv = netdev_priv(ndev);
1797 struct sockaddr *addr = (struct sockaddr *)p;
1798 struct cpsw_common *cpsw = priv->cpsw;
1799 int flags = 0;
1800 u16 vid = 0;
1801 int ret;
1802
1803 if (!is_valid_ether_addr(addr->sa_data))
1804 return -EADDRNOTAVAIL;
1805
1806 ret = pm_runtime_get_sync(cpsw->dev);
1807 if (ret < 0) {
1808 pm_runtime_put_noidle(cpsw->dev);
1809 return ret;
1810 }
1811
1812 if (cpsw->data.dual_emac) {
1813 vid = cpsw->slaves[priv->emac_port].port_vlan;
1814 flags = ALE_VLAN;
1815 }
1816
1817 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1818 flags, vid);
1819 cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1820 flags, vid);
1821
1822 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1823 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1824 for_each_slave(priv, cpsw_set_slave_mac, priv);
1825
1826 pm_runtime_put(cpsw->dev);
1827
1828 return 0;
1829 }
1830
1831 #ifdef CONFIG_NET_POLL_CONTROLLER
1832 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1833 {
1834 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1835
1836 cpsw_intr_disable(cpsw);
1837 cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1838 cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1839 cpsw_intr_enable(cpsw);
1840 }
1841 #endif
1842
1843 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1844 unsigned short vid)
1845 {
1846 int ret;
1847 int unreg_mcast_mask = 0;
1848 u32 port_mask;
1849 struct cpsw_common *cpsw = priv->cpsw;
1850
1851 if (cpsw->data.dual_emac) {
1852 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1853
1854 if (priv->ndev->flags & IFF_ALLMULTI)
1855 unreg_mcast_mask = port_mask;
1856 } else {
1857 port_mask = ALE_ALL_PORTS;
1858
1859 if (priv->ndev->flags & IFF_ALLMULTI)
1860 unreg_mcast_mask = ALE_ALL_PORTS;
1861 else
1862 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1863 }
1864
1865 ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1866 unreg_mcast_mask);
1867 if (ret != 0)
1868 return ret;
1869
1870 ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1871 HOST_PORT_NUM, ALE_VLAN, vid);
1872 if (ret != 0)
1873 goto clean_vid;
1874
1875 ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1876 port_mask, ALE_VLAN, vid, 0);
1877 if (ret != 0)
1878 goto clean_vlan_ucast;
1879 return 0;
1880
1881 clean_vlan_ucast:
1882 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1883 HOST_PORT_NUM, ALE_VLAN, vid);
1884 clean_vid:
1885 cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1886 return ret;
1887 }
1888
1889 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1890 __be16 proto, u16 vid)
1891 {
1892 struct cpsw_priv *priv = netdev_priv(ndev);
1893 struct cpsw_common *cpsw = priv->cpsw;
1894 int ret;
1895
1896 if (vid == cpsw->data.default_vlan)
1897 return 0;
1898
1899 ret = pm_runtime_get_sync(cpsw->dev);
1900 if (ret < 0) {
1901 pm_runtime_put_noidle(cpsw->dev);
1902 return ret;
1903 }
1904
1905 if (cpsw->data.dual_emac) {
1906 /* In dual EMAC, reserved VLAN id should not be used for
1907 * creating VLAN interfaces as this can break the dual
1908 * EMAC port separation
1909 */
1910 int i;
1911
1912 for (i = 0; i < cpsw->data.slaves; i++) {
1913 if (vid == cpsw->slaves[i].port_vlan)
1914 return -EINVAL;
1915 }
1916 }
1917
1918 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1919 ret = cpsw_add_vlan_ale_entry(priv, vid);
1920
1921 pm_runtime_put(cpsw->dev);
1922 return ret;
1923 }
1924
1925 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1926 __be16 proto, u16 vid)
1927 {
1928 struct cpsw_priv *priv = netdev_priv(ndev);
1929 struct cpsw_common *cpsw = priv->cpsw;
1930 int ret;
1931
1932 if (vid == cpsw->data.default_vlan)
1933 return 0;
1934
1935 ret = pm_runtime_get_sync(cpsw->dev);
1936 if (ret < 0) {
1937 pm_runtime_put_noidle(cpsw->dev);
1938 return ret;
1939 }
1940
1941 if (cpsw->data.dual_emac) {
1942 int i;
1943
1944 for (i = 0; i < cpsw->data.slaves; i++) {
1945 if (vid == cpsw->slaves[i].port_vlan)
1946 return -EINVAL;
1947 }
1948 }
1949
1950 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1951 ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1952 if (ret != 0)
1953 return ret;
1954
1955 ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1956 HOST_PORT_NUM, ALE_VLAN, vid);
1957 if (ret != 0)
1958 return ret;
1959
1960 ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
1961 0, ALE_VLAN, vid);
1962 pm_runtime_put(cpsw->dev);
1963 return ret;
1964 }
1965
1966 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
1967 {
1968 struct cpsw_priv *priv = netdev_priv(ndev);
1969 struct cpsw_common *cpsw = priv->cpsw;
1970 u32 min_rate;
1971 u32 ch_rate;
1972 int ret;
1973
1974 ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
1975 if (ch_rate == rate)
1976 return 0;
1977
1978 ch_rate = rate * 1000;
1979 min_rate = cpdma_chan_get_min_rate(cpsw->dma);
1980 if ((ch_rate < min_rate && ch_rate)) {
1981 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
1982 min_rate);
1983 return -EINVAL;
1984 }
1985
1986 if (rate > 2000) {
1987 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
1988 return -EINVAL;
1989 }
1990
1991 ret = pm_runtime_get_sync(cpsw->dev);
1992 if (ret < 0) {
1993 pm_runtime_put_noidle(cpsw->dev);
1994 return ret;
1995 }
1996
1997 ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
1998 pm_runtime_put(cpsw->dev);
1999
2000 if (ret)
2001 return ret;
2002
2003 cpsw_split_res(ndev);
2004 return ret;
2005 }
2006
2007 static const struct net_device_ops cpsw_netdev_ops = {
2008 .ndo_open = cpsw_ndo_open,
2009 .ndo_stop = cpsw_ndo_stop,
2010 .ndo_start_xmit = cpsw_ndo_start_xmit,
2011 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2012 .ndo_do_ioctl = cpsw_ndo_ioctl,
2013 .ndo_validate_addr = eth_validate_addr,
2014 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
2015 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
2016 .ndo_set_tx_maxrate = cpsw_ndo_set_tx_maxrate,
2017 #ifdef CONFIG_NET_POLL_CONTROLLER
2018 .ndo_poll_controller = cpsw_ndo_poll_controller,
2019 #endif
2020 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
2021 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
2022 };
2023
2024 static int cpsw_get_regs_len(struct net_device *ndev)
2025 {
2026 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2027
2028 return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2029 }
2030
2031 static void cpsw_get_regs(struct net_device *ndev,
2032 struct ethtool_regs *regs, void *p)
2033 {
2034 u32 *reg = p;
2035 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2036
2037 /* update CPSW IP version */
2038 regs->version = cpsw->version;
2039
2040 cpsw_ale_dump(cpsw->ale, reg);
2041 }
2042
2043 static void cpsw_get_drvinfo(struct net_device *ndev,
2044 struct ethtool_drvinfo *info)
2045 {
2046 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2047 struct platform_device *pdev = to_platform_device(cpsw->dev);
2048
2049 strlcpy(info->driver, "cpsw", sizeof(info->driver));
2050 strlcpy(info->version, "1.0", sizeof(info->version));
2051 strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2052 }
2053
2054 static u32 cpsw_get_msglevel(struct net_device *ndev)
2055 {
2056 struct cpsw_priv *priv = netdev_priv(ndev);
2057 return priv->msg_enable;
2058 }
2059
2060 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2061 {
2062 struct cpsw_priv *priv = netdev_priv(ndev);
2063 priv->msg_enable = value;
2064 }
2065
2066 #if IS_ENABLED(CONFIG_TI_CPTS)
2067 static int cpsw_get_ts_info(struct net_device *ndev,
2068 struct ethtool_ts_info *info)
2069 {
2070 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2071
2072 info->so_timestamping =
2073 SOF_TIMESTAMPING_TX_HARDWARE |
2074 SOF_TIMESTAMPING_TX_SOFTWARE |
2075 SOF_TIMESTAMPING_RX_HARDWARE |
2076 SOF_TIMESTAMPING_RX_SOFTWARE |
2077 SOF_TIMESTAMPING_SOFTWARE |
2078 SOF_TIMESTAMPING_RAW_HARDWARE;
2079 info->phc_index = cpsw->cpts->phc_index;
2080 info->tx_types =
2081 (1 << HWTSTAMP_TX_OFF) |
2082 (1 << HWTSTAMP_TX_ON);
2083 info->rx_filters =
2084 (1 << HWTSTAMP_FILTER_NONE) |
2085 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2086 return 0;
2087 }
2088 #else
2089 static int cpsw_get_ts_info(struct net_device *ndev,
2090 struct ethtool_ts_info *info)
2091 {
2092 info->so_timestamping =
2093 SOF_TIMESTAMPING_TX_SOFTWARE |
2094 SOF_TIMESTAMPING_RX_SOFTWARE |
2095 SOF_TIMESTAMPING_SOFTWARE;
2096 info->phc_index = -1;
2097 info->tx_types = 0;
2098 info->rx_filters = 0;
2099 return 0;
2100 }
2101 #endif
2102
2103 static int cpsw_get_link_ksettings(struct net_device *ndev,
2104 struct ethtool_link_ksettings *ecmd)
2105 {
2106 struct cpsw_priv *priv = netdev_priv(ndev);
2107 struct cpsw_common *cpsw = priv->cpsw;
2108 int slave_no = cpsw_slave_index(cpsw, priv);
2109
2110 if (cpsw->slaves[slave_no].phy)
2111 return phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy,
2112 ecmd);
2113 else
2114 return -EOPNOTSUPP;
2115 }
2116
2117 static int cpsw_set_link_ksettings(struct net_device *ndev,
2118 const struct ethtool_link_ksettings *ecmd)
2119 {
2120 struct cpsw_priv *priv = netdev_priv(ndev);
2121 struct cpsw_common *cpsw = priv->cpsw;
2122 int slave_no = cpsw_slave_index(cpsw, priv);
2123
2124 if (cpsw->slaves[slave_no].phy)
2125 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2126 ecmd);
2127 else
2128 return -EOPNOTSUPP;
2129 }
2130
2131 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2132 {
2133 struct cpsw_priv *priv = netdev_priv(ndev);
2134 struct cpsw_common *cpsw = priv->cpsw;
2135 int slave_no = cpsw_slave_index(cpsw, priv);
2136
2137 wol->supported = 0;
2138 wol->wolopts = 0;
2139
2140 if (cpsw->slaves[slave_no].phy)
2141 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2142 }
2143
2144 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2145 {
2146 struct cpsw_priv *priv = netdev_priv(ndev);
2147 struct cpsw_common *cpsw = priv->cpsw;
2148 int slave_no = cpsw_slave_index(cpsw, priv);
2149
2150 if (cpsw->slaves[slave_no].phy)
2151 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2152 else
2153 return -EOPNOTSUPP;
2154 }
2155
2156 static void cpsw_get_pauseparam(struct net_device *ndev,
2157 struct ethtool_pauseparam *pause)
2158 {
2159 struct cpsw_priv *priv = netdev_priv(ndev);
2160
2161 pause->autoneg = AUTONEG_DISABLE;
2162 pause->rx_pause = priv->rx_pause ? true : false;
2163 pause->tx_pause = priv->tx_pause ? true : false;
2164 }
2165
2166 static int cpsw_set_pauseparam(struct net_device *ndev,
2167 struct ethtool_pauseparam *pause)
2168 {
2169 struct cpsw_priv *priv = netdev_priv(ndev);
2170 bool link;
2171
2172 priv->rx_pause = pause->rx_pause ? true : false;
2173 priv->tx_pause = pause->tx_pause ? true : false;
2174
2175 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2176 return 0;
2177 }
2178
2179 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2180 {
2181 struct cpsw_priv *priv = netdev_priv(ndev);
2182 struct cpsw_common *cpsw = priv->cpsw;
2183 int ret;
2184
2185 ret = pm_runtime_get_sync(cpsw->dev);
2186 if (ret < 0) {
2187 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2188 pm_runtime_put_noidle(cpsw->dev);
2189 }
2190
2191 return ret;
2192 }
2193
2194 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2195 {
2196 struct cpsw_priv *priv = netdev_priv(ndev);
2197 int ret;
2198
2199 ret = pm_runtime_put(priv->cpsw->dev);
2200 if (ret < 0)
2201 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2202 }
2203
2204 static void cpsw_get_channels(struct net_device *ndev,
2205 struct ethtool_channels *ch)
2206 {
2207 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2208
2209 ch->max_combined = 0;
2210 ch->max_rx = CPSW_MAX_QUEUES;
2211 ch->max_tx = CPSW_MAX_QUEUES;
2212 ch->max_other = 0;
2213 ch->other_count = 0;
2214 ch->rx_count = cpsw->rx_ch_num;
2215 ch->tx_count = cpsw->tx_ch_num;
2216 ch->combined_count = 0;
2217 }
2218
2219 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2220 struct ethtool_channels *ch)
2221 {
2222 if (ch->combined_count)
2223 return -EINVAL;
2224
2225 /* verify we have at least one channel in each direction */
2226 if (!ch->rx_count || !ch->tx_count)
2227 return -EINVAL;
2228
2229 if (ch->rx_count > cpsw->data.channels ||
2230 ch->tx_count > cpsw->data.channels)
2231 return -EINVAL;
2232
2233 return 0;
2234 }
2235
2236 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2237 {
2238 int (*poll)(struct napi_struct *, int);
2239 struct cpsw_common *cpsw = priv->cpsw;
2240 void (*handler)(void *, int, int);
2241 struct netdev_queue *queue;
2242 struct cpsw_vector *vec;
2243 int ret, *ch;
2244
2245 if (rx) {
2246 ch = &cpsw->rx_ch_num;
2247 vec = cpsw->rxv;
2248 handler = cpsw_rx_handler;
2249 poll = cpsw_rx_poll;
2250 } else {
2251 ch = &cpsw->tx_ch_num;
2252 vec = cpsw->txv;
2253 handler = cpsw_tx_handler;
2254 poll = cpsw_tx_poll;
2255 }
2256
2257 while (*ch < ch_num) {
2258 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2259 queue = netdev_get_tx_queue(priv->ndev, *ch);
2260 queue->tx_maxrate = 0;
2261
2262 if (IS_ERR(vec[*ch].ch))
2263 return PTR_ERR(vec[*ch].ch);
2264
2265 if (!vec[*ch].ch)
2266 return -EINVAL;
2267
2268 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2269 (rx ? "rx" : "tx"));
2270 (*ch)++;
2271 }
2272
2273 while (*ch > ch_num) {
2274 (*ch)--;
2275
2276 ret = cpdma_chan_destroy(vec[*ch].ch);
2277 if (ret)
2278 return ret;
2279
2280 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2281 (rx ? "rx" : "tx"));
2282 }
2283
2284 return 0;
2285 }
2286
2287 static int cpsw_update_channels(struct cpsw_priv *priv,
2288 struct ethtool_channels *ch)
2289 {
2290 int ret;
2291
2292 ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2293 if (ret)
2294 return ret;
2295
2296 ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2297 if (ret)
2298 return ret;
2299
2300 return 0;
2301 }
2302
2303 static int cpsw_set_channels(struct net_device *ndev,
2304 struct ethtool_channels *chs)
2305 {
2306 struct cpsw_priv *priv = netdev_priv(ndev);
2307 struct cpsw_common *cpsw = priv->cpsw;
2308 struct cpsw_slave *slave;
2309 int i, ret;
2310
2311 ret = cpsw_check_ch_settings(cpsw, chs);
2312 if (ret < 0)
2313 return ret;
2314
2315 /* Disable NAPI scheduling */
2316 cpsw_intr_disable(cpsw);
2317
2318 /* Stop all transmit queues for every network device.
2319 * Disable re-using rx descriptors with dormant_on.
2320 */
2321 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2322 if (!(slave->ndev && netif_running(slave->ndev)))
2323 continue;
2324
2325 netif_tx_stop_all_queues(slave->ndev);
2326 netif_dormant_on(slave->ndev);
2327 }
2328
2329 /* Handle rest of tx packets and stop cpdma channels */
2330 cpdma_ctlr_stop(cpsw->dma);
2331 ret = cpsw_update_channels(priv, chs);
2332 if (ret)
2333 goto err;
2334
2335 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2336 if (!(slave->ndev && netif_running(slave->ndev)))
2337 continue;
2338
2339 /* Inform stack about new count of queues */
2340 ret = netif_set_real_num_tx_queues(slave->ndev,
2341 cpsw->tx_ch_num);
2342 if (ret) {
2343 dev_err(priv->dev, "cannot set real number of tx queues\n");
2344 goto err;
2345 }
2346
2347 ret = netif_set_real_num_rx_queues(slave->ndev,
2348 cpsw->rx_ch_num);
2349 if (ret) {
2350 dev_err(priv->dev, "cannot set real number of rx queues\n");
2351 goto err;
2352 }
2353
2354 /* Enable rx packets handling */
2355 netif_dormant_off(slave->ndev);
2356 }
2357
2358 if (cpsw_common_res_usage_state(cpsw)) {
2359 ret = cpsw_fill_rx_channels(priv);
2360 if (ret)
2361 goto err;
2362
2363 cpsw_split_res(ndev);
2364
2365 /* After this receive is started */
2366 cpdma_ctlr_start(cpsw->dma);
2367 cpsw_intr_enable(cpsw);
2368 }
2369
2370 /* Resume transmit for every affected interface */
2371 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2372 if (!(slave->ndev && netif_running(slave->ndev)))
2373 continue;
2374 netif_tx_start_all_queues(slave->ndev);
2375 }
2376 return 0;
2377 err:
2378 dev_err(priv->dev, "cannot update channels number, closing device\n");
2379 dev_close(ndev);
2380 return ret;
2381 }
2382
2383 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2384 {
2385 struct cpsw_priv *priv = netdev_priv(ndev);
2386 struct cpsw_common *cpsw = priv->cpsw;
2387 int slave_no = cpsw_slave_index(cpsw, priv);
2388
2389 if (cpsw->slaves[slave_no].phy)
2390 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2391 else
2392 return -EOPNOTSUPP;
2393 }
2394
2395 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2396 {
2397 struct cpsw_priv *priv = netdev_priv(ndev);
2398 struct cpsw_common *cpsw = priv->cpsw;
2399 int slave_no = cpsw_slave_index(cpsw, priv);
2400
2401 if (cpsw->slaves[slave_no].phy)
2402 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2403 else
2404 return -EOPNOTSUPP;
2405 }
2406
2407 static int cpsw_nway_reset(struct net_device *ndev)
2408 {
2409 struct cpsw_priv *priv = netdev_priv(ndev);
2410 struct cpsw_common *cpsw = priv->cpsw;
2411 int slave_no = cpsw_slave_index(cpsw, priv);
2412
2413 if (cpsw->slaves[slave_no].phy)
2414 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2415 else
2416 return -EOPNOTSUPP;
2417 }
2418
2419 static const struct ethtool_ops cpsw_ethtool_ops = {
2420 .get_drvinfo = cpsw_get_drvinfo,
2421 .get_msglevel = cpsw_get_msglevel,
2422 .set_msglevel = cpsw_set_msglevel,
2423 .get_link = ethtool_op_get_link,
2424 .get_ts_info = cpsw_get_ts_info,
2425 .get_coalesce = cpsw_get_coalesce,
2426 .set_coalesce = cpsw_set_coalesce,
2427 .get_sset_count = cpsw_get_sset_count,
2428 .get_strings = cpsw_get_strings,
2429 .get_ethtool_stats = cpsw_get_ethtool_stats,
2430 .get_pauseparam = cpsw_get_pauseparam,
2431 .set_pauseparam = cpsw_set_pauseparam,
2432 .get_wol = cpsw_get_wol,
2433 .set_wol = cpsw_set_wol,
2434 .get_regs_len = cpsw_get_regs_len,
2435 .get_regs = cpsw_get_regs,
2436 .begin = cpsw_ethtool_op_begin,
2437 .complete = cpsw_ethtool_op_complete,
2438 .get_channels = cpsw_get_channels,
2439 .set_channels = cpsw_set_channels,
2440 .get_link_ksettings = cpsw_get_link_ksettings,
2441 .set_link_ksettings = cpsw_set_link_ksettings,
2442 .get_eee = cpsw_get_eee,
2443 .set_eee = cpsw_set_eee,
2444 .nway_reset = cpsw_nway_reset,
2445 };
2446
2447 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2448 u32 slave_reg_ofs, u32 sliver_reg_ofs)
2449 {
2450 void __iomem *regs = cpsw->regs;
2451 int slave_num = slave->slave_num;
2452 struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num;
2453
2454 slave->data = data;
2455 slave->regs = regs + slave_reg_ofs;
2456 slave->sliver = regs + sliver_reg_ofs;
2457 slave->port_vlan = data->dual_emac_res_vlan;
2458 }
2459
2460 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2461 struct platform_device *pdev)
2462 {
2463 struct device_node *node = pdev->dev.of_node;
2464 struct device_node *slave_node;
2465 int i = 0, ret;
2466 u32 prop;
2467
2468 if (!node)
2469 return -EINVAL;
2470
2471 if (of_property_read_u32(node, "slaves", &prop)) {
2472 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2473 return -EINVAL;
2474 }
2475 data->slaves = prop;
2476
2477 if (of_property_read_u32(node, "active_slave", &prop)) {
2478 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2479 return -EINVAL;
2480 }
2481 data->active_slave = prop;
2482
2483 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2484 * sizeof(struct cpsw_slave_data),
2485 GFP_KERNEL);
2486 if (!data->slave_data)
2487 return -ENOMEM;
2488
2489 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2490 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2491 return -EINVAL;
2492 }
2493 data->channels = prop;
2494
2495 if (of_property_read_u32(node, "ale_entries", &prop)) {
2496 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2497 return -EINVAL;
2498 }
2499 data->ale_entries = prop;
2500
2501 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2502 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2503 return -EINVAL;
2504 }
2505 data->bd_ram_size = prop;
2506
2507 if (of_property_read_u32(node, "mac_control", &prop)) {
2508 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2509 return -EINVAL;
2510 }
2511 data->mac_control = prop;
2512
2513 if (of_property_read_bool(node, "dual_emac"))
2514 data->dual_emac = 1;
2515
2516 /*
2517 * Populate all the child nodes here...
2518 */
2519 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2520 /* We do not want to force this, as in some cases may not have child */
2521 if (ret)
2522 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2523
2524 for_each_available_child_of_node(node, slave_node) {
2525 struct cpsw_slave_data *slave_data = data->slave_data + i;
2526 const void *mac_addr = NULL;
2527 int lenp;
2528 const __be32 *parp;
2529
2530 /* This is no slave child node, continue */
2531 if (strcmp(slave_node->name, "slave"))
2532 continue;
2533
2534 slave_data->phy_node = of_parse_phandle(slave_node,
2535 "phy-handle", 0);
2536 parp = of_get_property(slave_node, "phy_id", &lenp);
2537 if (slave_data->phy_node) {
2538 dev_dbg(&pdev->dev,
2539 "slave[%d] using phy-handle=\"%s\"\n",
2540 i, slave_data->phy_node->full_name);
2541 } else if (of_phy_is_fixed_link(slave_node)) {
2542 /* In the case of a fixed PHY, the DT node associated
2543 * to the PHY is the Ethernet MAC DT node.
2544 */
2545 ret = of_phy_register_fixed_link(slave_node);
2546 if (ret) {
2547 if (ret != -EPROBE_DEFER)
2548 dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2549 return ret;
2550 }
2551 slave_data->phy_node = of_node_get(slave_node);
2552 } else if (parp) {
2553 u32 phyid;
2554 struct device_node *mdio_node;
2555 struct platform_device *mdio;
2556
2557 if (lenp != (sizeof(__be32) * 2)) {
2558 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2559 goto no_phy_slave;
2560 }
2561 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2562 phyid = be32_to_cpup(parp+1);
2563 mdio = of_find_device_by_node(mdio_node);
2564 of_node_put(mdio_node);
2565 if (!mdio) {
2566 dev_err(&pdev->dev, "Missing mdio platform device\n");
2567 return -EINVAL;
2568 }
2569 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2570 PHY_ID_FMT, mdio->name, phyid);
2571 put_device(&mdio->dev);
2572 } else {
2573 dev_err(&pdev->dev,
2574 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2575 i);
2576 goto no_phy_slave;
2577 }
2578 slave_data->phy_if = of_get_phy_mode(slave_node);
2579 if (slave_data->phy_if < 0) {
2580 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2581 i);
2582 return slave_data->phy_if;
2583 }
2584
2585 no_phy_slave:
2586 mac_addr = of_get_mac_address(slave_node);
2587 if (mac_addr) {
2588 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2589 } else {
2590 ret = ti_cm_get_macid(&pdev->dev, i,
2591 slave_data->mac_addr);
2592 if (ret)
2593 return ret;
2594 }
2595 if (data->dual_emac) {
2596 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2597 &prop)) {
2598 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2599 slave_data->dual_emac_res_vlan = i+1;
2600 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2601 slave_data->dual_emac_res_vlan, i);
2602 } else {
2603 slave_data->dual_emac_res_vlan = prop;
2604 }
2605 }
2606
2607 i++;
2608 if (i == data->slaves)
2609 break;
2610 }
2611
2612 return 0;
2613 }
2614
2615 static void cpsw_remove_dt(struct platform_device *pdev)
2616 {
2617 struct net_device *ndev = platform_get_drvdata(pdev);
2618 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2619 struct cpsw_platform_data *data = &cpsw->data;
2620 struct device_node *node = pdev->dev.of_node;
2621 struct device_node *slave_node;
2622 int i = 0;
2623
2624 for_each_available_child_of_node(node, slave_node) {
2625 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2626
2627 if (strcmp(slave_node->name, "slave"))
2628 continue;
2629
2630 if (of_phy_is_fixed_link(slave_node))
2631 of_phy_deregister_fixed_link(slave_node);
2632
2633 of_node_put(slave_data->phy_node);
2634
2635 i++;
2636 if (i == data->slaves)
2637 break;
2638 }
2639
2640 of_platform_depopulate(&pdev->dev);
2641 }
2642
2643 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2644 {
2645 struct cpsw_common *cpsw = priv->cpsw;
2646 struct cpsw_platform_data *data = &cpsw->data;
2647 struct net_device *ndev;
2648 struct cpsw_priv *priv_sl2;
2649 int ret = 0;
2650
2651 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2652 if (!ndev) {
2653 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2654 return -ENOMEM;
2655 }
2656
2657 priv_sl2 = netdev_priv(ndev);
2658 priv_sl2->cpsw = cpsw;
2659 priv_sl2->ndev = ndev;
2660 priv_sl2->dev = &ndev->dev;
2661 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2662
2663 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2664 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2665 ETH_ALEN);
2666 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2667 priv_sl2->mac_addr);
2668 } else {
2669 random_ether_addr(priv_sl2->mac_addr);
2670 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2671 priv_sl2->mac_addr);
2672 }
2673 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2674
2675 priv_sl2->emac_port = 1;
2676 cpsw->slaves[1].ndev = ndev;
2677 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2678
2679 ndev->netdev_ops = &cpsw_netdev_ops;
2680 ndev->ethtool_ops = &cpsw_ethtool_ops;
2681
2682 /* register the network device */
2683 SET_NETDEV_DEV(ndev, cpsw->dev);
2684 ret = register_netdev(ndev);
2685 if (ret) {
2686 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2687 free_netdev(ndev);
2688 ret = -ENODEV;
2689 }
2690
2691 return ret;
2692 }
2693
2694 #define CPSW_QUIRK_IRQ BIT(0)
2695
2696 static struct platform_device_id cpsw_devtype[] = {
2697 {
2698 /* keep it for existing comaptibles */
2699 .name = "cpsw",
2700 .driver_data = CPSW_QUIRK_IRQ,
2701 }, {
2702 .name = "am335x-cpsw",
2703 .driver_data = CPSW_QUIRK_IRQ,
2704 }, {
2705 .name = "am4372-cpsw",
2706 .driver_data = 0,
2707 }, {
2708 .name = "dra7-cpsw",
2709 .driver_data = 0,
2710 }, {
2711 /* sentinel */
2712 }
2713 };
2714 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2715
2716 enum ti_cpsw_type {
2717 CPSW = 0,
2718 AM335X_CPSW,
2719 AM4372_CPSW,
2720 DRA7_CPSW,
2721 };
2722
2723 static const struct of_device_id cpsw_of_mtable[] = {
2724 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2725 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2726 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2727 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2728 { /* sentinel */ },
2729 };
2730 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2731
2732 static int cpsw_probe(struct platform_device *pdev)
2733 {
2734 struct clk *clk;
2735 struct cpsw_platform_data *data;
2736 struct net_device *ndev;
2737 struct cpsw_priv *priv;
2738 struct cpdma_params dma_params;
2739 struct cpsw_ale_params ale_params;
2740 void __iomem *ss_regs;
2741 void __iomem *cpts_regs;
2742 struct resource *res, *ss_res;
2743 const struct of_device_id *of_id;
2744 struct gpio_descs *mode;
2745 u32 slave_offset, sliver_offset, slave_size;
2746 struct cpsw_common *cpsw;
2747 int ret = 0, i;
2748 int irq;
2749
2750 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2751 if (!cpsw)
2752 return -ENOMEM;
2753
2754 cpsw->dev = &pdev->dev;
2755
2756 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2757 if (!ndev) {
2758 dev_err(&pdev->dev, "error allocating net_device\n");
2759 return -ENOMEM;
2760 }
2761
2762 platform_set_drvdata(pdev, ndev);
2763 priv = netdev_priv(ndev);
2764 priv->cpsw = cpsw;
2765 priv->ndev = ndev;
2766 priv->dev = &ndev->dev;
2767 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2768 cpsw->rx_packet_max = max(rx_packet_max, 128);
2769
2770 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2771 if (IS_ERR(mode)) {
2772 ret = PTR_ERR(mode);
2773 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2774 goto clean_ndev_ret;
2775 }
2776
2777 /*
2778 * This may be required here for child devices.
2779 */
2780 pm_runtime_enable(&pdev->dev);
2781
2782 /* Select default pin state */
2783 pinctrl_pm_select_default_state(&pdev->dev);
2784
2785 /* Need to enable clocks with runtime PM api to access module
2786 * registers
2787 */
2788 ret = pm_runtime_get_sync(&pdev->dev);
2789 if (ret < 0) {
2790 pm_runtime_put_noidle(&pdev->dev);
2791 goto clean_runtime_disable_ret;
2792 }
2793
2794 ret = cpsw_probe_dt(&cpsw->data, pdev);
2795 if (ret)
2796 goto clean_dt_ret;
2797
2798 data = &cpsw->data;
2799 cpsw->rx_ch_num = 1;
2800 cpsw->tx_ch_num = 1;
2801
2802 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2803 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2804 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2805 } else {
2806 eth_random_addr(priv->mac_addr);
2807 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2808 }
2809
2810 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2811
2812 cpsw->slaves = devm_kzalloc(&pdev->dev,
2813 sizeof(struct cpsw_slave) * data->slaves,
2814 GFP_KERNEL);
2815 if (!cpsw->slaves) {
2816 ret = -ENOMEM;
2817 goto clean_dt_ret;
2818 }
2819 for (i = 0; i < data->slaves; i++)
2820 cpsw->slaves[i].slave_num = i;
2821
2822 cpsw->slaves[0].ndev = ndev;
2823 priv->emac_port = 0;
2824
2825 clk = devm_clk_get(&pdev->dev, "fck");
2826 if (IS_ERR(clk)) {
2827 dev_err(priv->dev, "fck is not found\n");
2828 ret = -ENODEV;
2829 goto clean_dt_ret;
2830 }
2831 cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2832
2833 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2834 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2835 if (IS_ERR(ss_regs)) {
2836 ret = PTR_ERR(ss_regs);
2837 goto clean_dt_ret;
2838 }
2839 cpsw->regs = ss_regs;
2840
2841 cpsw->version = readl(&cpsw->regs->id_ver);
2842
2843 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2844 cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2845 if (IS_ERR(cpsw->wr_regs)) {
2846 ret = PTR_ERR(cpsw->wr_regs);
2847 goto clean_dt_ret;
2848 }
2849
2850 memset(&dma_params, 0, sizeof(dma_params));
2851 memset(&ale_params, 0, sizeof(ale_params));
2852
2853 switch (cpsw->version) {
2854 case CPSW_VERSION_1:
2855 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2856 cpts_regs = ss_regs + CPSW1_CPTS_OFFSET;
2857 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
2858 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2859 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2860 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2861 slave_offset = CPSW1_SLAVE_OFFSET;
2862 slave_size = CPSW1_SLAVE_SIZE;
2863 sliver_offset = CPSW1_SLIVER_OFFSET;
2864 dma_params.desc_mem_phys = 0;
2865 break;
2866 case CPSW_VERSION_2:
2867 case CPSW_VERSION_3:
2868 case CPSW_VERSION_4:
2869 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2870 cpts_regs = ss_regs + CPSW2_CPTS_OFFSET;
2871 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
2872 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2873 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2874 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2875 slave_offset = CPSW2_SLAVE_OFFSET;
2876 slave_size = CPSW2_SLAVE_SIZE;
2877 sliver_offset = CPSW2_SLIVER_OFFSET;
2878 dma_params.desc_mem_phys =
2879 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2880 break;
2881 default:
2882 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
2883 ret = -ENODEV;
2884 goto clean_dt_ret;
2885 }
2886 for (i = 0; i < cpsw->data.slaves; i++) {
2887 struct cpsw_slave *slave = &cpsw->slaves[i];
2888
2889 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
2890 slave_offset += slave_size;
2891 sliver_offset += SLIVER_SIZE;
2892 }
2893
2894 dma_params.dev = &pdev->dev;
2895 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2896 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2897 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2898 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2899 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
2900
2901 dma_params.num_chan = data->channels;
2902 dma_params.has_soft_reset = true;
2903 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2904 dma_params.desc_mem_size = data->bd_ram_size;
2905 dma_params.desc_align = 16;
2906 dma_params.has_ext_regs = true;
2907 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
2908 dma_params.bus_freq_mhz = cpsw->bus_freq_mhz;
2909
2910 cpsw->dma = cpdma_ctlr_create(&dma_params);
2911 if (!cpsw->dma) {
2912 dev_err(priv->dev, "error initializing dma\n");
2913 ret = -ENOMEM;
2914 goto clean_dt_ret;
2915 }
2916
2917 cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
2918 cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
2919 if (WARN_ON(!cpsw->rxv[0].ch || !cpsw->txv[0].ch)) {
2920 dev_err(priv->dev, "error initializing dma channels\n");
2921 ret = -ENOMEM;
2922 goto clean_dma_ret;
2923 }
2924
2925 ale_params.dev = &ndev->dev;
2926 ale_params.ale_ageout = ale_ageout;
2927 ale_params.ale_entries = data->ale_entries;
2928 ale_params.ale_ports = data->slaves;
2929
2930 cpsw->ale = cpsw_ale_create(&ale_params);
2931 if (!cpsw->ale) {
2932 dev_err(priv->dev, "error initializing ale engine\n");
2933 ret = -ENODEV;
2934 goto clean_dma_ret;
2935 }
2936
2937 cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
2938 if (IS_ERR(cpsw->cpts)) {
2939 ret = PTR_ERR(cpsw->cpts);
2940 goto clean_ale_ret;
2941 }
2942
2943 ndev->irq = platform_get_irq(pdev, 1);
2944 if (ndev->irq < 0) {
2945 dev_err(priv->dev, "error getting irq resource\n");
2946 ret = ndev->irq;
2947 goto clean_ale_ret;
2948 }
2949
2950 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2951 if (of_id) {
2952 pdev->id_entry = of_id->data;
2953 if (pdev->id_entry->driver_data)
2954 cpsw->quirk_irq = true;
2955 }
2956
2957 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2958 * MISC IRQs which are always kept disabled with this driver so
2959 * we will not request them.
2960 *
2961 * If anyone wants to implement support for those, make sure to
2962 * first request and append them to irqs_table array.
2963 */
2964
2965 /* RX IRQ */
2966 irq = platform_get_irq(pdev, 1);
2967 if (irq < 0) {
2968 ret = irq;
2969 goto clean_ale_ret;
2970 }
2971
2972 cpsw->irqs_table[0] = irq;
2973 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2974 0, dev_name(&pdev->dev), cpsw);
2975 if (ret < 0) {
2976 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2977 goto clean_ale_ret;
2978 }
2979
2980 /* TX IRQ */
2981 irq = platform_get_irq(pdev, 2);
2982 if (irq < 0) {
2983 ret = irq;
2984 goto clean_ale_ret;
2985 }
2986
2987 cpsw->irqs_table[1] = irq;
2988 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2989 0, dev_name(&pdev->dev), cpsw);
2990 if (ret < 0) {
2991 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2992 goto clean_ale_ret;
2993 }
2994
2995 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2996
2997 ndev->netdev_ops = &cpsw_netdev_ops;
2998 ndev->ethtool_ops = &cpsw_ethtool_ops;
2999 netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
3000 netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
3001
3002 /* register the network device */
3003 SET_NETDEV_DEV(ndev, &pdev->dev);
3004 ret = register_netdev(ndev);
3005 if (ret) {
3006 dev_err(priv->dev, "error registering net device\n");
3007 ret = -ENODEV;
3008 goto clean_ale_ret;
3009 }
3010
3011 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
3012 &ss_res->start, ndev->irq);
3013
3014 if (cpsw->data.dual_emac) {
3015 ret = cpsw_probe_dual_emac(priv);
3016 if (ret) {
3017 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3018 goto clean_unregister_netdev_ret;
3019 }
3020 }
3021
3022 pm_runtime_put(&pdev->dev);
3023
3024 return 0;
3025
3026 clean_unregister_netdev_ret:
3027 unregister_netdev(ndev);
3028 clean_ale_ret:
3029 cpsw_ale_destroy(cpsw->ale);
3030 clean_dma_ret:
3031 cpdma_ctlr_destroy(cpsw->dma);
3032 clean_dt_ret:
3033 cpsw_remove_dt(pdev);
3034 pm_runtime_put_sync(&pdev->dev);
3035 clean_runtime_disable_ret:
3036 pm_runtime_disable(&pdev->dev);
3037 clean_ndev_ret:
3038 free_netdev(priv->ndev);
3039 return ret;
3040 }
3041
3042 static int cpsw_remove(struct platform_device *pdev)
3043 {
3044 struct net_device *ndev = platform_get_drvdata(pdev);
3045 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3046 int ret;
3047
3048 ret = pm_runtime_get_sync(&pdev->dev);
3049 if (ret < 0) {
3050 pm_runtime_put_noidle(&pdev->dev);
3051 return ret;
3052 }
3053
3054 if (cpsw->data.dual_emac)
3055 unregister_netdev(cpsw->slaves[1].ndev);
3056 unregister_netdev(ndev);
3057
3058 cpts_release(cpsw->cpts);
3059 cpsw_ale_destroy(cpsw->ale);
3060 cpdma_ctlr_destroy(cpsw->dma);
3061 cpsw_remove_dt(pdev);
3062 pm_runtime_put_sync(&pdev->dev);
3063 pm_runtime_disable(&pdev->dev);
3064 if (cpsw->data.dual_emac)
3065 free_netdev(cpsw->slaves[1].ndev);
3066 free_netdev(ndev);
3067 return 0;
3068 }
3069
3070 #ifdef CONFIG_PM_SLEEP
3071 static int cpsw_suspend(struct device *dev)
3072 {
3073 struct platform_device *pdev = to_platform_device(dev);
3074 struct net_device *ndev = platform_get_drvdata(pdev);
3075 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3076
3077 if (cpsw->data.dual_emac) {
3078 int i;
3079
3080 for (i = 0; i < cpsw->data.slaves; i++) {
3081 if (netif_running(cpsw->slaves[i].ndev))
3082 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3083 }
3084 } else {
3085 if (netif_running(ndev))
3086 cpsw_ndo_stop(ndev);
3087 }
3088
3089 /* Select sleep pin state */
3090 pinctrl_pm_select_sleep_state(dev);
3091
3092 return 0;
3093 }
3094
3095 static int cpsw_resume(struct device *dev)
3096 {
3097 struct platform_device *pdev = to_platform_device(dev);
3098 struct net_device *ndev = platform_get_drvdata(pdev);
3099 struct cpsw_common *cpsw = netdev_priv(ndev);
3100
3101 /* Select default pin state */
3102 pinctrl_pm_select_default_state(dev);
3103
3104 /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3105 rtnl_lock();
3106 if (cpsw->data.dual_emac) {
3107 int i;
3108
3109 for (i = 0; i < cpsw->data.slaves; i++) {
3110 if (netif_running(cpsw->slaves[i].ndev))
3111 cpsw_ndo_open(cpsw->slaves[i].ndev);
3112 }
3113 } else {
3114 if (netif_running(ndev))
3115 cpsw_ndo_open(ndev);
3116 }
3117 rtnl_unlock();
3118
3119 return 0;
3120 }
3121 #endif
3122
3123 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3124
3125 static struct platform_driver cpsw_driver = {
3126 .driver = {
3127 .name = "cpsw",
3128 .pm = &cpsw_pm_ops,
3129 .of_match_table = cpsw_of_mtable,
3130 },
3131 .probe = cpsw_probe,
3132 .remove = cpsw_remove,
3133 };
3134
3135 module_platform_driver(cpsw_driver);
3136
3137 MODULE_LICENSE("GPL");
3138 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3139 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3140 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
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