drivers/net/ethernet/ti/cpts.h

   1 /*
   2  * TI Common Platform Time Sync
   3  *
   4  * Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #ifndef _TI_CPTS_H_
  21 #define _TI_CPTS_H_
  22
  23 #if IS_ENABLED(CONFIG_TI_CPTS)
  24
  25 #include <linux/clk.h>
  26 #include <linux/clkdev.h>
  27 #include <linux/clocksource.h>
  28 #include <linux/device.h>
  29 #include <linux/list.h>
  30 #include <linux/of.h>
  31 #include <linux/ptp_clock_kernel.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ptp_classify.h>
  34 #include <linux/timecounter.h>
  35
  36 struct cpsw_cpts {
  37         u32 idver;                /* Identification and version */
  38         u32 control;              /* Time sync control */
  39         u32 res1;
  40         u32 ts_push;              /* Time stamp event push */
  41         u32 ts_load_val;          /* Time stamp load value */
  42         u32 ts_load_en;           /* Time stamp load enable */
  43         u32 res2[2];
  44         u32 intstat_raw;          /* Time sync interrupt status raw */
  45         u32 intstat_masked;       /* Time sync interrupt status masked */
  46         u32 int_enable;           /* Time sync interrupt enable */
  47         u32 res3;
  48         u32 event_pop;            /* Event interrupt pop */
  49         u32 event_low;            /* 32 Bit Event Time Stamp */
  50         u32 event_high;           /* Event Type Fields */
  51 };
  52
  53 /* Bit definitions for the IDVER register */
  54 #define TX_IDENT_SHIFT       (16)    /* TX Identification Value */
  55 #define TX_IDENT_MASK        (0xffff)
  56 #define RTL_VER_SHIFT        (11)    /* RTL Version Value */
  57 #define RTL_VER_MASK         (0x1f)
  58 #define MAJOR_VER_SHIFT      (8)     /* Major Version Value */
  59 #define MAJOR_VER_MASK       (0x7)
  60 #define MINOR_VER_SHIFT      (0)     /* Minor Version Value */
  61 #define MINOR_VER_MASK       (0xff)
  62
  63 /* Bit definitions for the CONTROL register */
  64 #define HW4_TS_PUSH_EN       (1<<11) /* Hardware push 4 enable */
  65 #define HW3_TS_PUSH_EN       (1<<10) /* Hardware push 3 enable */
  66 #define HW2_TS_PUSH_EN       (1<<9)  /* Hardware push 2 enable */
  67 #define HW1_TS_PUSH_EN       (1<<8)  /* Hardware push 1 enable */
  68 #define INT_TEST             (1<<1)  /* Interrupt Test */
  69 #define CPTS_EN              (1<<0)  /* Time Sync Enable */
  70
  71 /*
  72  * Definitions for the single bit resisters:
  73  * TS_PUSH TS_LOAD_EN  INTSTAT_RAW INTSTAT_MASKED INT_ENABLE EVENT_POP
  74  */
  75 #define TS_PUSH             (1<<0)  /* Time stamp event push */
  76 #define TS_LOAD_EN          (1<<0)  /* Time Stamp Load */
  77 #define TS_PEND_RAW         (1<<0)  /* int read (before enable) */
  78 #define TS_PEND             (1<<0)  /* masked interrupt read (after enable) */
  79 #define TS_PEND_EN          (1<<0)  /* masked interrupt enable */
  80 #define EVENT_POP           (1<<0)  /* writing discards one event */
  81
  82 /* Bit definitions for the EVENT_HIGH register */
  83 #define PORT_NUMBER_SHIFT    (24)    /* Indicates Ethernet port or HW pin */
  84 #define PORT_NUMBER_MASK     (0x1f)
  85 #define EVENT_TYPE_SHIFT     (20)    /* Time sync event type */
  86 #define EVENT_TYPE_MASK      (0xf)
  87 #define MESSAGE_TYPE_SHIFT   (16)    /* PTP message type */
  88 #define MESSAGE_TYPE_MASK    (0xf)
  89 #define SEQUENCE_ID_SHIFT    (0)     /* PTP message sequence ID */
  90 #define SEQUENCE_ID_MASK     (0xffff)
  91
  92 enum {
  93         CPTS_EV_PUSH, /* Time Stamp Push Event */
  94         CPTS_EV_ROLL, /* Time Stamp Rollover Event */
  95         CPTS_EV_HALF, /* Time Stamp Half Rollover Event */
  96         CPTS_EV_HW,   /* Hardware Time Stamp Push Event */
  97         CPTS_EV_RX,   /* Ethernet Receive Event */
  98         CPTS_EV_TX,   /* Ethernet Transmit Event */
  99 };
 100
 101 #define CPTS_FIFO_DEPTH 16
 102 #define CPTS_MAX_EVENTS 32
 103
 104 struct cpts_event {
 105         struct list_head list;
 106         unsigned long tmo;
 107         u32 high;
 108         u32 low;
 109 };
 110
 111 struct cpts {
 112         struct device *dev;
 113         struct cpsw_cpts __iomem *reg;
 114         int tx_enable;
 115         int rx_enable;
 116         struct ptp_clock_info info;
 117         struct ptp_clock *clock;
 118         spinlock_t lock; /* protects time registers */
 119         u32 cc_mult; /* for the nominal frequency */
 120         struct cyclecounter cc;
 121         struct timecounter tc;
 122         struct delayed_work overflow_work;
 123         int phc_index;
 124         struct clk *refclk;
 125         struct list_head events;
 126         struct list_head pool;
 127         struct cpts_event pool_data[CPTS_MAX_EVENTS];
 128         unsigned long ov_check_period;
 129 };
 130
 131 void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb);
 132 void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb);
 133 int cpts_register(struct cpts *cpts);
 134 void cpts_unregister(struct cpts *cpts);
 135 struct cpts *cpts_create(struct device *dev, void __iomem *regs,
 136                          struct device_node *node);
 137 void cpts_release(struct cpts *cpts);
 138
 139 static inline void cpts_rx_enable(struct cpts *cpts, int enable)
 140 {
 141         cpts->rx_enable = enable;
 142 }
 143
 144 static inline bool cpts_is_rx_enabled(struct cpts *cpts)
 145 {
 146         return !!cpts->rx_enable;
 147 }
 148
 149 static inline void cpts_tx_enable(struct cpts *cpts, int enable)
 150 {
 151         cpts->tx_enable = enable;
 152 }
 153
 154 static inline bool cpts_is_tx_enabled(struct cpts *cpts)
 155 {
 156         return !!cpts->tx_enable;
 157 }
 158
 159 static inline bool cpts_can_timestamp(struct cpts *cpts, struct sk_buff *skb)
 160 {
 161         unsigned int class = ptp_classify_raw(skb);
 162
 163         if (class == PTP_CLASS_NONE)
 164                 return false;
 165
 166         return true;
 167 }
 168
 169 #else
 170 struct cpts;
 171
 172 static inline void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb)
 173 {
 174 }
 175 static inline void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb)
 176 {
 177 }
 178
 179 static inline
 180 struct cpts *cpts_create(struct device *dev, void __iomem *regs,
 181                          struct device_node *node)
 182 {
 183         return NULL;
 184 }
 185
 186 static inline void cpts_release(struct cpts *cpts)
 187 {
 188 }
 189
 190 static inline int
 191 cpts_register(struct cpts *cpts)
 192 {
 193         return 0;
 194 }
 195
 196 static inline void cpts_unregister(struct cpts *cpts)
 197 {
 198 }
 199
 200 static inline void cpts_rx_enable(struct cpts *cpts, int enable)
 201 {
 202 }
 203
 204 static inline bool cpts_is_rx_enabled(struct cpts *cpts)
 205 {
 206         return false;
 207 }
 208
 209 static inline void cpts_tx_enable(struct cpts *cpts, int enable)
 210 {
 211 }
 212
 213 static inline bool cpts_is_tx_enabled(struct cpts *cpts)
 214 {
 215         return false;
 216 }
 217
 218 static inline bool cpts_can_timestamp(struct cpts *cpts, struct sk_buff *skb)
 219 {
 220         return false;
 221 }
 222 #endif
 223
 224
 225 #endif