2 * DaVinci Ethernet Medium Access Controller
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 * Copyright (C) 2009 Texas Instruments.
8 * ---------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/spinlock.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/clk.h>
54 #include <linux/platform_device.h>
55 #include <linux/semaphore.h>
56 #include <linux/phy.h>
57 #include <linux/bitops.h>
59 #include <linux/uaccess.h>
60 #include <linux/davinci_emac.h>
62 #include <linux/of_address.h>
63 #include <linux/of_irq.h>
64 #include <linux/of_net.h>
71 #include "davinci_cpdma.h"
73 static int debug_level
;
74 module_param(debug_level
, int, 0);
75 MODULE_PARM_DESC(debug_level
, "DaVinci EMAC debug level (NETIF_MSG bits)");
77 /* Netif debug messages possible */
78 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
86 NETIF_MSG_TX_QUEUED | \
89 NETIF_MSG_RX_STATUS | \
95 #define EMAC_MAJOR_VERSION 6
96 #define EMAC_MINOR_VERSION 1
97 #define EMAC_MODULE_VERSION "6.1"
98 MODULE_VERSION(EMAC_MODULE_VERSION
);
99 static const char emac_version_string
[] = "TI DaVinci EMAC Linux v6.1";
101 /* Configuration items */
102 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
103 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
104 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
105 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
106 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
107 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
108 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
109 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
110 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
111 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
112 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
113 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
115 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
116 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
118 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
119 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
120 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
121 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
122 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
123 #define EMAC_DEF_RX_NUM_DESC (128)
124 #define EMAC_DEF_TX_NUM_DESC (128)
125 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
126 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
127 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
129 /* Buffer descriptor parameters */
130 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
131 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
133 /* EMAC register related defines */
134 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
135 #define EMAC_NUM_MULTICAST_BITS (64)
136 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
137 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
138 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
139 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
140 #define EMAC_INT_MASK_CLEAR (0xFF)
142 /* RX MBP register bit positions */
143 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
144 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
145 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
146 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
147 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
148 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
149 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
150 #define EMAC_RXMBP_PROMCH_SHIFT (16)
151 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
152 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
153 #define EMAC_RXMBP_BROADCH_SHIFT (8)
154 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
155 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
156 #define EMAC_RXMBP_MULTICH_SHIFT (0)
157 #define EMAC_RXMBP_MULTICH_MASK (0x7)
158 #define EMAC_RXMBP_CHMASK (0x7)
160 /* EMAC register definitions/bit maps used */
161 # define EMAC_MBP_RXPROMISC (0x00200000)
162 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
163 # define EMAC_MBP_RXBCAST (0x00002000)
164 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
165 # define EMAC_MBP_RXMCAST (0x00000020)
166 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
168 /* EMAC mac_control register */
169 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
170 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
171 #define EMAC_MACCONTROL_GMIIEN BIT(5)
172 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
173 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
174 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
176 /* GIGABIT MODE related bits */
177 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
178 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
180 /* EMAC mac_status register */
181 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
182 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
183 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
184 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
185 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
186 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
187 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
188 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
190 /* EMAC RX register masks */
191 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
192 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
194 /* MAC_IN_VECTOR (0x180) register bit fields */
195 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
196 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
197 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
198 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
200 /** NOTE:: For DM646x the IN_VECTOR has changed */
201 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
202 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
203 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
204 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
206 /* CPPI bit positions */
207 #define EMAC_CPPI_SOP_BIT BIT(31)
208 #define EMAC_CPPI_EOP_BIT BIT(30)
209 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
210 #define EMAC_CPPI_EOQ_BIT BIT(28)
211 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
212 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
213 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
214 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
215 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
217 /* Max hardware defines */
218 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
219 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
221 /* EMAC Peripheral Device Register Memory Layout structure */
222 #define EMAC_MACINVECTOR 0x90
224 #define EMAC_DM646X_MACEOIVECTOR 0x94
226 #define EMAC_MACINTSTATRAW 0xB0
227 #define EMAC_MACINTSTATMASKED 0xB4
228 #define EMAC_MACINTMASKSET 0xB8
229 #define EMAC_MACINTMASKCLEAR 0xBC
231 #define EMAC_RXMBPENABLE 0x100
232 #define EMAC_RXUNICASTSET 0x104
233 #define EMAC_RXUNICASTCLEAR 0x108
234 #define EMAC_RXMAXLEN 0x10C
235 #define EMAC_RXBUFFEROFFSET 0x110
236 #define EMAC_RXFILTERLOWTHRESH 0x114
238 #define EMAC_MACCONTROL 0x160
239 #define EMAC_MACSTATUS 0x164
240 #define EMAC_EMCONTROL 0x168
241 #define EMAC_FIFOCONTROL 0x16C
242 #define EMAC_MACCONFIG 0x170
243 #define EMAC_SOFTRESET 0x174
244 #define EMAC_MACSRCADDRLO 0x1D0
245 #define EMAC_MACSRCADDRHI 0x1D4
246 #define EMAC_MACHASH1 0x1D8
247 #define EMAC_MACHASH2 0x1DC
248 #define EMAC_MACADDRLO 0x500
249 #define EMAC_MACADDRHI 0x504
250 #define EMAC_MACINDEX 0x508
252 /* EMAC statistics registers */
253 #define EMAC_RXGOODFRAMES 0x200
254 #define EMAC_RXBCASTFRAMES 0x204
255 #define EMAC_RXMCASTFRAMES 0x208
256 #define EMAC_RXPAUSEFRAMES 0x20C
257 #define EMAC_RXCRCERRORS 0x210
258 #define EMAC_RXALIGNCODEERRORS 0x214
259 #define EMAC_RXOVERSIZED 0x218
260 #define EMAC_RXJABBER 0x21C
261 #define EMAC_RXUNDERSIZED 0x220
262 #define EMAC_RXFRAGMENTS 0x224
263 #define EMAC_RXFILTERED 0x228
264 #define EMAC_RXQOSFILTERED 0x22C
265 #define EMAC_RXOCTETS 0x230
266 #define EMAC_TXGOODFRAMES 0x234
267 #define EMAC_TXBCASTFRAMES 0x238
268 #define EMAC_TXMCASTFRAMES 0x23C
269 #define EMAC_TXPAUSEFRAMES 0x240
270 #define EMAC_TXDEFERRED 0x244
271 #define EMAC_TXCOLLISION 0x248
272 #define EMAC_TXSINGLECOLL 0x24C
273 #define EMAC_TXMULTICOLL 0x250
274 #define EMAC_TXEXCESSIVECOLL 0x254
275 #define EMAC_TXLATECOLL 0x258
276 #define EMAC_TXUNDERRUN 0x25C
277 #define EMAC_TXCARRIERSENSE 0x260
278 #define EMAC_TXOCTETS 0x264
279 #define EMAC_NETOCTETS 0x280
280 #define EMAC_RXSOFOVERRUNS 0x284
281 #define EMAC_RXMOFOVERRUNS 0x288
282 #define EMAC_RXDMAOVERRUNS 0x28C
284 /* EMAC DM644x control registers */
285 #define EMAC_CTRL_EWCTL (0x4)
286 #define EMAC_CTRL_EWINTTCNT (0x8)
288 /* EMAC DM644x control module masks */
289 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
290 #define EMAC_DM644X_INTMIN_INTVL 0x1
291 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
293 /* EMAC DM646X control module registers */
294 #define EMAC_DM646X_CMINTCTRL 0x0C
295 #define EMAC_DM646X_CMRXINTEN 0x14
296 #define EMAC_DM646X_CMTXINTEN 0x18
297 #define EMAC_DM646X_CMRXINTMAX 0x70
298 #define EMAC_DM646X_CMTXINTMAX 0x74
300 /* EMAC DM646X control module masks */
301 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
302 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
303 #define EMAC_DM646X_CMINTMAX_CNT 63
304 #define EMAC_DM646X_CMINTMIN_CNT 2
305 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
306 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
309 /* EMAC EOI codes for C0 */
310 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
311 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
313 /* EMAC Stats Clear Mask */
314 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
316 /* emac_priv: EMAC private data structure
318 * EMAC adapter private data structure
322 struct net_device
*ndev
;
323 struct platform_device
*pdev
;
324 struct napi_struct napi
;
326 void __iomem
*remap_addr
;
328 void __iomem
*emac_base
;
329 void __iomem
*ctrl_base
;
330 struct cpdma_ctlr
*dma
;
331 struct cpdma_chan
*txchan
;
332 struct cpdma_chan
*rxchan
;
333 u32 link
; /* 1=link on, 0=link off */
334 u32 speed
; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
335 u32 duplex
; /* Link duplex: 0=Half, 1=Full */
344 u32 multicast_hash_cnt
[EMAC_NUM_MULTICAST_BITS
];
349 struct device_node
*phy_node
;
351 struct phy_device
*phydev
;
353 /*platform specific members*/
354 void (*int_enable
) (void);
355 void (*int_disable
) (void);
358 /* clock frequency for EMAC */
359 static struct clk
*emac_clk
;
360 static unsigned long emac_bus_frequency
;
362 /* EMAC TX Host Error description strings */
363 static char *emac_txhost_errcodes
[16] = {
364 "No error", "SOP error", "Ownership bit not set in SOP buffer",
365 "Zero Next Buffer Descriptor Pointer Without EOP",
366 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
367 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
368 "Reserved", "Reserved", "Reserved", "Reserved"
371 /* EMAC RX Host Error description strings */
372 static char *emac_rxhost_errcodes
[16] = {
373 "No error", "Reserved", "Ownership bit not set in input buffer",
374 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
375 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
376 "Reserved", "Reserved", "Reserved", "Reserved"
380 #define emac_read(reg) ioread32(priv->emac_base + (reg))
381 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
383 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
384 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
387 * emac_dump_regs - Dump important EMAC registers to debug terminal
388 * @priv: The DaVinci EMAC private adapter structure
390 * Executes ethtool set cmd & sets phy mode
393 static void emac_dump_regs(struct emac_priv
*priv
)
395 struct device
*emac_dev
= &priv
->ndev
->dev
;
397 /* Print important registers in EMAC */
398 dev_info(emac_dev
, "EMAC Basic registers\n");
399 if (priv
->version
== EMAC_VERSION_1
) {
400 dev_info(emac_dev
, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
401 emac_ctrl_read(EMAC_CTRL_EWCTL
),
402 emac_ctrl_read(EMAC_CTRL_EWINTTCNT
));
404 dev_info(emac_dev
, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
405 emac_read(EMAC_EMCONTROL
), emac_read(EMAC_FIFOCONTROL
));
406 dev_info(emac_dev
, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
407 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE
),
408 emac_read(EMAC_RXUNICASTSET
), emac_read(EMAC_RXMAXLEN
));
409 dev_info(emac_dev
, "EMAC: MacControl:%08X, MacStatus: %08X, "\
410 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL
),
411 emac_read(EMAC_MACSTATUS
), emac_read(EMAC_MACCONFIG
));
412 dev_info(emac_dev
, "EMAC Statistics\n");
413 dev_info(emac_dev
, "EMAC: rx_good_frames:%d\n",
414 emac_read(EMAC_RXGOODFRAMES
));
415 dev_info(emac_dev
, "EMAC: rx_broadcast_frames:%d\n",
416 emac_read(EMAC_RXBCASTFRAMES
));
417 dev_info(emac_dev
, "EMAC: rx_multicast_frames:%d\n",
418 emac_read(EMAC_RXMCASTFRAMES
));
419 dev_info(emac_dev
, "EMAC: rx_pause_frames:%d\n",
420 emac_read(EMAC_RXPAUSEFRAMES
));
421 dev_info(emac_dev
, "EMAC: rx_crcerrors:%d\n",
422 emac_read(EMAC_RXCRCERRORS
));
423 dev_info(emac_dev
, "EMAC: rx_align_code_errors:%d\n",
424 emac_read(EMAC_RXALIGNCODEERRORS
));
425 dev_info(emac_dev
, "EMAC: rx_oversized_frames:%d\n",
426 emac_read(EMAC_RXOVERSIZED
));
427 dev_info(emac_dev
, "EMAC: rx_jabber_frames:%d\n",
428 emac_read(EMAC_RXJABBER
));
429 dev_info(emac_dev
, "EMAC: rx_undersized_frames:%d\n",
430 emac_read(EMAC_RXUNDERSIZED
));
431 dev_info(emac_dev
, "EMAC: rx_fragments:%d\n",
432 emac_read(EMAC_RXFRAGMENTS
));
433 dev_info(emac_dev
, "EMAC: rx_filtered_frames:%d\n",
434 emac_read(EMAC_RXFILTERED
));
435 dev_info(emac_dev
, "EMAC: rx_qos_filtered_frames:%d\n",
436 emac_read(EMAC_RXQOSFILTERED
));
437 dev_info(emac_dev
, "EMAC: rx_octets:%d\n",
438 emac_read(EMAC_RXOCTETS
));
439 dev_info(emac_dev
, "EMAC: tx_goodframes:%d\n",
440 emac_read(EMAC_TXGOODFRAMES
));
441 dev_info(emac_dev
, "EMAC: tx_bcastframes:%d\n",
442 emac_read(EMAC_TXBCASTFRAMES
));
443 dev_info(emac_dev
, "EMAC: tx_mcastframes:%d\n",
444 emac_read(EMAC_TXMCASTFRAMES
));
445 dev_info(emac_dev
, "EMAC: tx_pause_frames:%d\n",
446 emac_read(EMAC_TXPAUSEFRAMES
));
447 dev_info(emac_dev
, "EMAC: tx_deferred_frames:%d\n",
448 emac_read(EMAC_TXDEFERRED
));
449 dev_info(emac_dev
, "EMAC: tx_collision_frames:%d\n",
450 emac_read(EMAC_TXCOLLISION
));
451 dev_info(emac_dev
, "EMAC: tx_single_coll_frames:%d\n",
452 emac_read(EMAC_TXSINGLECOLL
));
453 dev_info(emac_dev
, "EMAC: tx_mult_coll_frames:%d\n",
454 emac_read(EMAC_TXMULTICOLL
));
455 dev_info(emac_dev
, "EMAC: tx_excessive_collisions:%d\n",
456 emac_read(EMAC_TXEXCESSIVECOLL
));
457 dev_info(emac_dev
, "EMAC: tx_late_collisions:%d\n",
458 emac_read(EMAC_TXLATECOLL
));
459 dev_info(emac_dev
, "EMAC: tx_underrun:%d\n",
460 emac_read(EMAC_TXUNDERRUN
));
461 dev_info(emac_dev
, "EMAC: tx_carrier_sense_errors:%d\n",
462 emac_read(EMAC_TXCARRIERSENSE
));
463 dev_info(emac_dev
, "EMAC: tx_octets:%d\n",
464 emac_read(EMAC_TXOCTETS
));
465 dev_info(emac_dev
, "EMAC: net_octets:%d\n",
466 emac_read(EMAC_NETOCTETS
));
467 dev_info(emac_dev
, "EMAC: rx_sof_overruns:%d\n",
468 emac_read(EMAC_RXSOFOVERRUNS
));
469 dev_info(emac_dev
, "EMAC: rx_mof_overruns:%d\n",
470 emac_read(EMAC_RXMOFOVERRUNS
));
471 dev_info(emac_dev
, "EMAC: rx_dma_overruns:%d\n",
472 emac_read(EMAC_RXDMAOVERRUNS
));
474 cpdma_ctlr_dump(priv
->dma
);
478 * emac_get_drvinfo - Get EMAC driver information
479 * @ndev: The DaVinci EMAC network adapter
480 * @info: ethtool info structure containing name and version
482 * Returns EMAC driver information (name and version)
485 static void emac_get_drvinfo(struct net_device
*ndev
,
486 struct ethtool_drvinfo
*info
)
488 strcpy(info
->driver
, emac_version_string
);
489 strcpy(info
->version
, EMAC_MODULE_VERSION
);
493 * emac_get_settings - Get EMAC settings
494 * @ndev: The DaVinci EMAC network adapter
495 * @ecmd: ethtool command
497 * Executes ethool get command
500 static int emac_get_settings(struct net_device
*ndev
,
501 struct ethtool_cmd
*ecmd
)
503 struct emac_priv
*priv
= netdev_priv(ndev
);
505 return phy_ethtool_gset(priv
->phydev
, ecmd
);
512 * emac_set_settings - Set EMAC settings
513 * @ndev: The DaVinci EMAC network adapter
514 * @ecmd: ethtool command
516 * Executes ethool set command
519 static int emac_set_settings(struct net_device
*ndev
, struct ethtool_cmd
*ecmd
)
521 struct emac_priv
*priv
= netdev_priv(ndev
);
523 return phy_ethtool_sset(priv
->phydev
, ecmd
);
530 * emac_get_coalesce - Get interrupt coalesce settings for this device
531 * @ndev : The DaVinci EMAC network adapter
532 * @coal : ethtool coalesce settings structure
534 * Fetch the current interrupt coalesce settings
537 static int emac_get_coalesce(struct net_device
*ndev
,
538 struct ethtool_coalesce
*coal
)
540 struct emac_priv
*priv
= netdev_priv(ndev
);
542 coal
->rx_coalesce_usecs
= priv
->coal_intvl
;
548 * emac_set_coalesce - Set interrupt coalesce settings for this device
549 * @ndev : The DaVinci EMAC network adapter
550 * @coal : ethtool coalesce settings structure
552 * Set interrupt coalesce parameters
555 static int emac_set_coalesce(struct net_device
*ndev
,
556 struct ethtool_coalesce
*coal
)
558 struct emac_priv
*priv
= netdev_priv(ndev
);
559 u32 int_ctrl
, num_interrupts
= 0;
560 u32 prescale
= 0, addnl_dvdr
= 1, coal_intvl
= 0;
562 if (!coal
->rx_coalesce_usecs
)
565 coal_intvl
= coal
->rx_coalesce_usecs
;
567 switch (priv
->version
) {
569 int_ctrl
= emac_ctrl_read(EMAC_DM646X_CMINTCTRL
);
570 prescale
= priv
->bus_freq_mhz
* 4;
572 if (coal_intvl
< EMAC_DM646X_CMINTMIN_INTVL
)
573 coal_intvl
= EMAC_DM646X_CMINTMIN_INTVL
;
575 if (coal_intvl
> EMAC_DM646X_CMINTMAX_INTVL
) {
577 * Interrupt pacer works with 4us Pulse, we can
578 * throttle further by dilating the 4us pulse.
580 addnl_dvdr
= EMAC_DM646X_INTPRESCALE_MASK
/ prescale
;
582 if (addnl_dvdr
> 1) {
583 prescale
*= addnl_dvdr
;
584 if (coal_intvl
> (EMAC_DM646X_CMINTMAX_INTVL
586 coal_intvl
= (EMAC_DM646X_CMINTMAX_INTVL
590 coal_intvl
= EMAC_DM646X_CMINTMAX_INTVL
;
594 num_interrupts
= (1000 * addnl_dvdr
) / coal_intvl
;
596 int_ctrl
|= EMAC_DM646X_INTPACEEN
;
597 int_ctrl
&= (~EMAC_DM646X_INTPRESCALE_MASK
);
598 int_ctrl
|= (prescale
& EMAC_DM646X_INTPRESCALE_MASK
);
599 emac_ctrl_write(EMAC_DM646X_CMINTCTRL
, int_ctrl
);
601 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX
, num_interrupts
);
602 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX
, num_interrupts
);
606 int_ctrl
= emac_ctrl_read(EMAC_CTRL_EWINTTCNT
);
607 int_ctrl
&= (~EMAC_DM644X_EWINTCNT_MASK
);
608 prescale
= coal_intvl
* priv
->bus_freq_mhz
;
609 if (prescale
> EMAC_DM644X_EWINTCNT_MASK
) {
610 prescale
= EMAC_DM644X_EWINTCNT_MASK
;
611 coal_intvl
= prescale
/ priv
->bus_freq_mhz
;
613 emac_ctrl_write(EMAC_CTRL_EWINTTCNT
, (int_ctrl
| prescale
));
618 printk(KERN_INFO
"Set coalesce to %d usecs.\n", coal_intvl
);
619 priv
->coal_intvl
= coal_intvl
;
626 /* ethtool_ops: DaVinci EMAC Ethtool structure
628 * Ethtool support for EMAC adapter
630 static const struct ethtool_ops ethtool_ops
= {
631 .get_drvinfo
= emac_get_drvinfo
,
632 .get_settings
= emac_get_settings
,
633 .set_settings
= emac_set_settings
,
634 .get_link
= ethtool_op_get_link
,
635 .get_coalesce
= emac_get_coalesce
,
636 .set_coalesce
= emac_set_coalesce
,
637 .get_ts_info
= ethtool_op_get_ts_info
,
641 * emac_update_phystatus - Update Phy status
642 * @priv: The DaVinci EMAC private adapter structure
644 * Updates phy status and takes action for network queue if required
645 * based upon link status
648 static void emac_update_phystatus(struct emac_priv
*priv
)
653 struct net_device
*ndev
= priv
->ndev
;
655 mac_control
= emac_read(EMAC_MACCONTROL
);
656 cur_duplex
= (mac_control
& EMAC_MACCONTROL_FULLDUPLEXEN
) ?
657 DUPLEX_FULL
: DUPLEX_HALF
;
659 new_duplex
= priv
->phydev
->duplex
;
661 new_duplex
= DUPLEX_FULL
;
663 /* We get called only if link has changed (speed/duplex/status) */
664 if ((priv
->link
) && (new_duplex
!= cur_duplex
)) {
665 priv
->duplex
= new_duplex
;
666 if (DUPLEX_FULL
== priv
->duplex
)
667 mac_control
|= (EMAC_MACCONTROL_FULLDUPLEXEN
);
669 mac_control
&= ~(EMAC_MACCONTROL_FULLDUPLEXEN
);
672 if (priv
->speed
== SPEED_1000
&& (priv
->version
== EMAC_VERSION_2
)) {
673 mac_control
= emac_read(EMAC_MACCONTROL
);
674 mac_control
|= (EMAC_DM646X_MACCONTORL_GIG
|
675 EMAC_DM646X_MACCONTORL_GIGFORCE
);
677 /* Clear the GIG bit and GIGFORCE bit */
678 mac_control
&= ~(EMAC_DM646X_MACCONTORL_GIGFORCE
|
679 EMAC_DM646X_MACCONTORL_GIG
);
681 if (priv
->rmii_en
&& (priv
->speed
== SPEED_100
))
682 mac_control
|= EMAC_MACCONTROL_RMIISPEED_MASK
;
684 mac_control
&= ~EMAC_MACCONTROL_RMIISPEED_MASK
;
687 /* Update mac_control if changed */
688 emac_write(EMAC_MACCONTROL
, mac_control
);
692 if (!netif_carrier_ok(ndev
))
693 netif_carrier_on(ndev
);
694 /* reactivate the transmit queue if it is stopped */
695 if (netif_running(ndev
) && netif_queue_stopped(ndev
))
696 netif_wake_queue(ndev
);
699 if (netif_carrier_ok(ndev
))
700 netif_carrier_off(ndev
);
701 if (!netif_queue_stopped(ndev
))
702 netif_stop_queue(ndev
);
707 * hash_get - Calculate hash value from mac address
708 * @addr: mac address to delete from hash table
710 * Calculates hash value from mac address
713 static u32
hash_get(u8
*addr
)
720 for (cnt
= 0; cnt
< 2; cnt
++) {
722 hash
^= (tmpval
>> 2) ^ (tmpval
<< 4);
724 hash
^= (tmpval
>> 4) ^ (tmpval
<< 2);
726 hash
^= (tmpval
>> 6) ^ (tmpval
);
733 * hash_add - Hash function to add mac addr from hash table
734 * @priv: The DaVinci EMAC private adapter structure
735 * @mac_addr: mac address to delete from hash table
737 * Adds mac address to the internal hash table
740 static int hash_add(struct emac_priv
*priv
, u8
*mac_addr
)
742 struct device
*emac_dev
= &priv
->ndev
->dev
;
745 u32 hash_value
= hash_get(mac_addr
);
747 if (hash_value
>= EMAC_NUM_MULTICAST_BITS
) {
748 if (netif_msg_drv(priv
)) {
749 dev_err(emac_dev
, "DaVinci EMAC: hash_add(): Invalid "\
750 "Hash %08x, should not be greater than %08x",
751 hash_value
, (EMAC_NUM_MULTICAST_BITS
- 1));
756 /* set the hash bit only if not previously set */
757 if (priv
->multicast_hash_cnt
[hash_value
] == 0) {
758 rc
= 1; /* hash value changed */
759 if (hash_value
< 32) {
760 hash_bit
= BIT(hash_value
);
761 priv
->mac_hash1
|= hash_bit
;
763 hash_bit
= BIT((hash_value
- 32));
764 priv
->mac_hash2
|= hash_bit
;
768 /* incr counter for num of mcast addr's mapped to "this" hash bit */
769 ++priv
->multicast_hash_cnt
[hash_value
];
775 * hash_del - Hash function to delete mac addr from hash table
776 * @priv: The DaVinci EMAC private adapter structure
777 * @mac_addr: mac address to delete from hash table
779 * Removes mac address from the internal hash table
782 static int hash_del(struct emac_priv
*priv
, u8
*mac_addr
)
787 hash_value
= hash_get(mac_addr
);
788 if (priv
->multicast_hash_cnt
[hash_value
] > 0) {
789 /* dec cntr for num of mcast addr's mapped to this hash bit */
790 --priv
->multicast_hash_cnt
[hash_value
];
793 /* if counter still > 0, at least one multicast address refers
794 * to this hash bit. so return 0 */
795 if (priv
->multicast_hash_cnt
[hash_value
] > 0)
798 if (hash_value
< 32) {
799 hash_bit
= BIT(hash_value
);
800 priv
->mac_hash1
&= ~hash_bit
;
802 hash_bit
= BIT((hash_value
- 32));
803 priv
->mac_hash2
&= ~hash_bit
;
806 /* return 1 to indicate change in mac_hash registers reqd */
810 /* EMAC multicast operation */
811 #define EMAC_MULTICAST_ADD 0
812 #define EMAC_MULTICAST_DEL 1
813 #define EMAC_ALL_MULTI_SET 2
814 #define EMAC_ALL_MULTI_CLR 3
817 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
818 * @priv: The DaVinci EMAC private adapter structure
819 * @action: multicast operation to perform
820 * mac_addr: mac address to set
822 * Set multicast addresses in EMAC adapter - internal function
825 static void emac_add_mcast(struct emac_priv
*priv
, u32 action
, u8
*mac_addr
)
827 struct device
*emac_dev
= &priv
->ndev
->dev
;
831 case EMAC_MULTICAST_ADD
:
832 update
= hash_add(priv
, mac_addr
);
834 case EMAC_MULTICAST_DEL
:
835 update
= hash_del(priv
, mac_addr
);
837 case EMAC_ALL_MULTI_SET
:
839 priv
->mac_hash1
= EMAC_ALL_MULTI_REG_VALUE
;
840 priv
->mac_hash2
= EMAC_ALL_MULTI_REG_VALUE
;
842 case EMAC_ALL_MULTI_CLR
:
846 memset(&(priv
->multicast_hash_cnt
[0]), 0,
847 sizeof(priv
->multicast_hash_cnt
[0]) *
848 EMAC_NUM_MULTICAST_BITS
);
851 if (netif_msg_drv(priv
))
852 dev_err(emac_dev
, "DaVinci EMAC: add_mcast"\
853 ": bad operation %d", action
);
857 /* write to the hardware only if the register status chances */
859 emac_write(EMAC_MACHASH1
, priv
->mac_hash1
);
860 emac_write(EMAC_MACHASH2
, priv
->mac_hash2
);
865 * emac_dev_mcast_set - Set multicast address in the EMAC adapter
866 * @ndev: The DaVinci EMAC network adapter
868 * Set multicast addresses in EMAC adapter
871 static void emac_dev_mcast_set(struct net_device
*ndev
)
874 struct emac_priv
*priv
= netdev_priv(ndev
);
876 mbp_enable
= emac_read(EMAC_RXMBPENABLE
);
877 if (ndev
->flags
& IFF_PROMISC
) {
878 mbp_enable
&= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH
));
879 mbp_enable
|= (EMAC_MBP_RXPROMISC
);
881 mbp_enable
= (mbp_enable
& ~EMAC_MBP_RXPROMISC
);
882 if ((ndev
->flags
& IFF_ALLMULTI
) ||
883 netdev_mc_count(ndev
) > EMAC_DEF_MAX_MULTICAST_ADDRESSES
) {
884 mbp_enable
= (mbp_enable
| EMAC_MBP_RXMCAST
);
885 emac_add_mcast(priv
, EMAC_ALL_MULTI_SET
, NULL
);
887 if (!netdev_mc_empty(ndev
)) {
888 struct netdev_hw_addr
*ha
;
890 mbp_enable
= (mbp_enable
| EMAC_MBP_RXMCAST
);
891 emac_add_mcast(priv
, EMAC_ALL_MULTI_CLR
, NULL
);
892 /* program multicast address list into EMAC hardware */
893 netdev_for_each_mc_addr(ha
, ndev
) {
894 emac_add_mcast(priv
, EMAC_MULTICAST_ADD
,
898 mbp_enable
= (mbp_enable
& ~EMAC_MBP_RXMCAST
);
899 emac_add_mcast(priv
, EMAC_ALL_MULTI_CLR
, NULL
);
902 /* Set mbp config register */
903 emac_write(EMAC_RXMBPENABLE
, mbp_enable
);
906 /*************************************************************************
907 * EMAC Hardware manipulation
908 *************************************************************************/
911 * emac_int_disable - Disable EMAC module interrupt (from adapter)
912 * @priv: The DaVinci EMAC private adapter structure
914 * Disable EMAC interrupt on the adapter
917 static void emac_int_disable(struct emac_priv
*priv
)
919 if (priv
->version
== EMAC_VERSION_2
) {
922 local_irq_save(flags
);
924 /* Program C0_Int_En to zero to turn off
925 * interrupts to the CPU */
926 emac_ctrl_write(EMAC_DM646X_CMRXINTEN
, 0x0);
927 emac_ctrl_write(EMAC_DM646X_CMTXINTEN
, 0x0);
928 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
929 if (priv
->int_disable
)
932 local_irq_restore(flags
);
935 /* Set DM644x control registers for interrupt control */
936 emac_ctrl_write(EMAC_CTRL_EWCTL
, 0x0);
941 * emac_int_enable - Enable EMAC module interrupt (from adapter)
942 * @priv: The DaVinci EMAC private adapter structure
944 * Enable EMAC interrupt on the adapter
947 static void emac_int_enable(struct emac_priv
*priv
)
949 if (priv
->version
== EMAC_VERSION_2
) {
950 if (priv
->int_enable
)
953 emac_ctrl_write(EMAC_DM646X_CMRXINTEN
, 0xff);
954 emac_ctrl_write(EMAC_DM646X_CMTXINTEN
, 0xff);
956 /* In addition to turning on interrupt Enable, we need
957 * ack by writing appropriate values to the EOI
960 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
962 /* ack rxen only then a new pulse will be generated */
963 emac_write(EMAC_DM646X_MACEOIVECTOR
,
964 EMAC_DM646X_MAC_EOI_C0_RXEN
);
966 /* ack txen- only then a new pulse will be generated */
967 emac_write(EMAC_DM646X_MACEOIVECTOR
,
968 EMAC_DM646X_MAC_EOI_C0_TXEN
);
971 /* Set DM644x control registers for interrupt control */
972 emac_ctrl_write(EMAC_CTRL_EWCTL
, 0x1);
977 * emac_irq - EMAC interrupt handler
978 * @irq: interrupt number
979 * @dev_id: EMAC network adapter data structure ptr
981 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
982 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
984 * Returns interrupt handled condition
986 static irqreturn_t
emac_irq(int irq
, void *dev_id
)
988 struct net_device
*ndev
= (struct net_device
*)dev_id
;
989 struct emac_priv
*priv
= netdev_priv(ndev
);
992 if (likely(netif_running(priv
->ndev
))) {
993 emac_int_disable(priv
);
994 napi_schedule(&priv
->napi
);
996 /* we are closing down, so dont process anything */
1001 static struct sk_buff
*emac_rx_alloc(struct emac_priv
*priv
)
1003 struct sk_buff
*skb
= netdev_alloc_skb(priv
->ndev
, priv
->rx_buf_size
);
1006 skb_reserve(skb
, NET_IP_ALIGN
);
1010 static void emac_rx_handler(void *token
, int len
, int status
)
1012 struct sk_buff
*skb
= token
;
1013 struct net_device
*ndev
= skb
->dev
;
1014 struct emac_priv
*priv
= netdev_priv(ndev
);
1015 struct device
*emac_dev
= &ndev
->dev
;
1018 /* free and bail if we are shutting down */
1019 if (unlikely(!netif_running(ndev
))) {
1020 dev_kfree_skb_any(skb
);
1024 /* recycle on receive error */
1026 ndev
->stats
.rx_errors
++;
1030 /* feed received packet up the stack */
1032 skb
->protocol
= eth_type_trans(skb
, ndev
);
1033 netif_receive_skb(skb
);
1034 ndev
->stats
.rx_bytes
+= len
;
1035 ndev
->stats
.rx_packets
++;
1037 /* alloc a new packet for receive */
1038 skb
= emac_rx_alloc(priv
);
1040 if (netif_msg_rx_err(priv
) && net_ratelimit())
1041 dev_err(emac_dev
, "failed rx buffer alloc\n");
1046 ret
= cpdma_chan_submit(priv
->rxchan
, skb
, skb
->data
,
1047 skb_tailroom(skb
), GFP_KERNEL
);
1049 WARN_ON(ret
== -ENOMEM
);
1050 if (unlikely(ret
< 0))
1051 dev_kfree_skb_any(skb
);
1054 static void emac_tx_handler(void *token
, int len
, int status
)
1056 struct sk_buff
*skb
= token
;
1057 struct net_device
*ndev
= skb
->dev
;
1058 struct emac_priv
*priv
= netdev_priv(ndev
);
1060 atomic_dec(&priv
->cur_tx
);
1062 if (unlikely(netif_queue_stopped(ndev
)))
1063 netif_start_queue(ndev
);
1064 ndev
->stats
.tx_packets
++;
1065 ndev
->stats
.tx_bytes
+= len
;
1066 dev_kfree_skb_any(skb
);
1070 * emac_dev_xmit - EMAC Transmit function
1072 * @ndev: The DaVinci EMAC network adapter
1074 * Called by the system to transmit a packet - we queue the packet in
1075 * EMAC hardware transmit queue
1077 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1079 static int emac_dev_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
1081 struct device
*emac_dev
= &ndev
->dev
;
1083 struct emac_priv
*priv
= netdev_priv(ndev
);
1085 /* If no link, return */
1086 if (unlikely(!priv
->link
)) {
1087 if (netif_msg_tx_err(priv
) && net_ratelimit())
1088 dev_err(emac_dev
, "DaVinci EMAC: No link to transmit");
1092 ret_code
= skb_padto(skb
, EMAC_DEF_MIN_ETHPKTSIZE
);
1093 if (unlikely(ret_code
< 0)) {
1094 if (netif_msg_tx_err(priv
) && net_ratelimit())
1095 dev_err(emac_dev
, "DaVinci EMAC: packet pad failed");
1099 skb_tx_timestamp(skb
);
1101 ret_code
= cpdma_chan_submit(priv
->txchan
, skb
, skb
->data
, skb
->len
,
1103 if (unlikely(ret_code
!= 0)) {
1104 if (netif_msg_tx_err(priv
) && net_ratelimit())
1105 dev_err(emac_dev
, "DaVinci EMAC: desc submit failed");
1109 if (atomic_inc_return(&priv
->cur_tx
) >= EMAC_DEF_TX_NUM_DESC
)
1110 netif_stop_queue(ndev
);
1112 return NETDEV_TX_OK
;
1115 ndev
->stats
.tx_dropped
++;
1116 netif_stop_queue(ndev
);
1117 return NETDEV_TX_BUSY
;
1121 * emac_dev_tx_timeout - EMAC Transmit timeout function
1122 * @ndev: The DaVinci EMAC network adapter
1124 * Called when system detects that a skb timeout period has expired
1125 * potentially due to a fault in the adapter in not being able to send
1126 * it out on the wire. We teardown the TX channel assuming a hardware
1127 * error and re-initialize the TX channel for hardware operation
1130 static void emac_dev_tx_timeout(struct net_device
*ndev
)
1132 struct emac_priv
*priv
= netdev_priv(ndev
);
1133 struct device
*emac_dev
= &ndev
->dev
;
1135 if (netif_msg_tx_err(priv
))
1136 dev_err(emac_dev
, "DaVinci EMAC: xmit timeout, restarting TX");
1138 emac_dump_regs(priv
);
1140 ndev
->stats
.tx_errors
++;
1141 emac_int_disable(priv
);
1142 cpdma_chan_stop(priv
->txchan
);
1143 cpdma_chan_start(priv
->txchan
);
1144 emac_int_enable(priv
);
1148 * emac_set_type0addr - Set EMAC Type0 mac address
1149 * @priv: The DaVinci EMAC private adapter structure
1150 * @ch: RX channel number
1151 * @mac_addr: MAC address to set in device
1153 * Called internally to set Type0 mac address of the adapter (Device)
1155 * Returns success (0) or appropriate error code (none as of now)
1157 static void emac_set_type0addr(struct emac_priv
*priv
, u32 ch
, char *mac_addr
)
1160 val
= ((mac_addr
[5] << 8) | (mac_addr
[4]));
1161 emac_write(EMAC_MACSRCADDRLO
, val
);
1163 val
= ((mac_addr
[3] << 24) | (mac_addr
[2] << 16) | \
1164 (mac_addr
[1] << 8) | (mac_addr
[0]));
1165 emac_write(EMAC_MACSRCADDRHI
, val
);
1166 val
= emac_read(EMAC_RXUNICASTSET
);
1168 emac_write(EMAC_RXUNICASTSET
, val
);
1169 val
= emac_read(EMAC_RXUNICASTCLEAR
);
1171 emac_write(EMAC_RXUNICASTCLEAR
, val
);
1175 * emac_set_type1addr - Set EMAC Type1 mac address
1176 * @priv: The DaVinci EMAC private adapter structure
1177 * @ch: RX channel number
1178 * @mac_addr: MAC address to set in device
1180 * Called internally to set Type1 mac address of the adapter (Device)
1182 * Returns success (0) or appropriate error code (none as of now)
1184 static void emac_set_type1addr(struct emac_priv
*priv
, u32 ch
, char *mac_addr
)
1187 emac_write(EMAC_MACINDEX
, ch
);
1188 val
= ((mac_addr
[5] << 8) | mac_addr
[4]);
1189 emac_write(EMAC_MACADDRLO
, val
);
1190 val
= ((mac_addr
[3] << 24) | (mac_addr
[2] << 16) | \
1191 (mac_addr
[1] << 8) | (mac_addr
[0]));
1192 emac_write(EMAC_MACADDRHI
, val
);
1193 emac_set_type0addr(priv
, ch
, mac_addr
);
1197 * emac_set_type2addr - Set EMAC Type2 mac address
1198 * @priv: The DaVinci EMAC private adapter structure
1199 * @ch: RX channel number
1200 * @mac_addr: MAC address to set in device
1201 * @index: index into RX address entries
1202 * @match: match parameter for RX address matching logic
1204 * Called internally to set Type2 mac address of the adapter (Device)
1206 * Returns success (0) or appropriate error code (none as of now)
1208 static void emac_set_type2addr(struct emac_priv
*priv
, u32 ch
,
1209 char *mac_addr
, int index
, int match
)
1212 emac_write(EMAC_MACINDEX
, index
);
1213 val
= ((mac_addr
[3] << 24) | (mac_addr
[2] << 16) | \
1214 (mac_addr
[1] << 8) | (mac_addr
[0]));
1215 emac_write(EMAC_MACADDRHI
, val
);
1216 val
= ((mac_addr
[5] << 8) | mac_addr
[4] | ((ch
& 0x7) << 16) | \
1217 (match
<< 19) | BIT(20));
1218 emac_write(EMAC_MACADDRLO
, val
);
1219 emac_set_type0addr(priv
, ch
, mac_addr
);
1223 * emac_setmac - Set mac address in the adapter (internal function)
1224 * @priv: The DaVinci EMAC private adapter structure
1225 * @ch: RX channel number
1226 * @mac_addr: MAC address to set in device
1228 * Called internally to set the mac address of the adapter (Device)
1230 * Returns success (0) or appropriate error code (none as of now)
1232 static void emac_setmac(struct emac_priv
*priv
, u32 ch
, char *mac_addr
)
1234 struct device
*emac_dev
= &priv
->ndev
->dev
;
1236 if (priv
->rx_addr_type
== 0) {
1237 emac_set_type0addr(priv
, ch
, mac_addr
);
1238 } else if (priv
->rx_addr_type
== 1) {
1240 for (cnt
= 0; cnt
< EMAC_MAX_TXRX_CHANNELS
; cnt
++)
1241 emac_set_type1addr(priv
, ch
, mac_addr
);
1242 } else if (priv
->rx_addr_type
== 2) {
1243 emac_set_type2addr(priv
, ch
, mac_addr
, ch
, 1);
1244 emac_set_type0addr(priv
, ch
, mac_addr
);
1246 if (netif_msg_drv(priv
))
1247 dev_err(emac_dev
, "DaVinci EMAC: Wrong addressing\n");
1252 * emac_dev_setmac_addr - Set mac address in the adapter
1253 * @ndev: The DaVinci EMAC network adapter
1254 * @addr: MAC address to set in device
1256 * Called by the system to set the mac address of the adapter (Device)
1258 * Returns success (0) or appropriate error code (none as of now)
1260 static int emac_dev_setmac_addr(struct net_device
*ndev
, void *addr
)
1262 struct emac_priv
*priv
= netdev_priv(ndev
);
1263 struct device
*emac_dev
= &priv
->ndev
->dev
;
1264 struct sockaddr
*sa
= addr
;
1266 if (!is_valid_ether_addr(sa
->sa_data
))
1267 return -EADDRNOTAVAIL
;
1269 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1270 memcpy(priv
->mac_addr
, sa
->sa_data
, ndev
->addr_len
);
1271 memcpy(ndev
->dev_addr
, sa
->sa_data
, ndev
->addr_len
);
1272 ndev
->addr_assign_type
&= ~NET_ADDR_RANDOM
;
1274 /* MAC address is configured only after the interface is enabled. */
1275 if (netif_running(ndev
)) {
1276 emac_setmac(priv
, EMAC_DEF_RX_CH
, priv
->mac_addr
);
1279 if (netif_msg_drv(priv
))
1280 dev_notice(emac_dev
, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1287 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
1288 * @priv: The DaVinci EMAC private adapter structure
1290 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1291 * for packet reception and enables device interrupts and then NAPI
1293 * Returns success (0) or appropriate error code (none right now)
1295 static int emac_hw_enable(struct emac_priv
*priv
)
1297 u32 val
, mbp_enable
, mac_control
;
1300 emac_write(EMAC_SOFTRESET
, 1);
1301 while (emac_read(EMAC_SOFTRESET
))
1304 /* Disable interrupt & Set pacing for more interrupts initially */
1305 emac_int_disable(priv
);
1307 /* Full duplex enable bit set when auto negotiation happens */
1309 (((EMAC_DEF_TXPRIO_FIXED
) ? (EMAC_MACCONTROL_TXPTYPE
) : 0x0) |
1310 ((priv
->speed
== 1000) ? EMAC_MACCONTROL_GIGABITEN
: 0x0) |
1311 ((EMAC_DEF_TXPACING_EN
) ? (EMAC_MACCONTROL_TXPACEEN
) : 0x0) |
1312 ((priv
->duplex
== DUPLEX_FULL
) ? 0x1 : 0));
1313 emac_write(EMAC_MACCONTROL
, mac_control
);
1316 (((EMAC_DEF_PASS_CRC
) ? (EMAC_RXMBP_PASSCRC_MASK
) : 0x0) |
1317 ((EMAC_DEF_QOS_EN
) ? (EMAC_RXMBP_QOSEN_MASK
) : 0x0) |
1318 ((EMAC_DEF_NO_BUFF_CHAIN
) ? (EMAC_RXMBP_NOCHAIN_MASK
) : 0x0) |
1319 ((EMAC_DEF_MACCTRL_FRAME_EN
) ? (EMAC_RXMBP_CMFEN_MASK
) : 0x0) |
1320 ((EMAC_DEF_SHORT_FRAME_EN
) ? (EMAC_RXMBP_CSFEN_MASK
) : 0x0) |
1321 ((EMAC_DEF_ERROR_FRAME_EN
) ? (EMAC_RXMBP_CEFEN_MASK
) : 0x0) |
1322 ((EMAC_DEF_PROM_EN
) ? (EMAC_RXMBP_CAFEN_MASK
) : 0x0) |
1323 ((EMAC_DEF_PROM_CH
& EMAC_RXMBP_CHMASK
) << \
1324 EMAC_RXMBP_PROMCH_SHIFT
) |
1325 ((EMAC_DEF_BCAST_EN
) ? (EMAC_RXMBP_BROADEN_MASK
) : 0x0) |
1326 ((EMAC_DEF_BCAST_CH
& EMAC_RXMBP_CHMASK
) << \
1327 EMAC_RXMBP_BROADCH_SHIFT
) |
1328 ((EMAC_DEF_MCAST_EN
) ? (EMAC_RXMBP_MULTIEN_MASK
) : 0x0) |
1329 ((EMAC_DEF_MCAST_CH
& EMAC_RXMBP_CHMASK
) << \
1330 EMAC_RXMBP_MULTICH_SHIFT
));
1331 emac_write(EMAC_RXMBPENABLE
, mbp_enable
);
1332 emac_write(EMAC_RXMAXLEN
, (EMAC_DEF_MAX_FRAME_SIZE
&
1333 EMAC_RX_MAX_LEN_MASK
));
1334 emac_write(EMAC_RXBUFFEROFFSET
, (EMAC_DEF_BUFFER_OFFSET
&
1335 EMAC_RX_BUFFER_OFFSET_MASK
));
1336 emac_write(EMAC_RXFILTERLOWTHRESH
, 0);
1337 emac_write(EMAC_RXUNICASTCLEAR
, EMAC_RX_UNICAST_CLEAR_ALL
);
1338 priv
->rx_addr_type
= (emac_read(EMAC_MACCONFIG
) >> 8) & 0xFF;
1340 emac_write(EMAC_MACINTMASKSET
, EMAC_MAC_HOST_ERR_INTMASK_VAL
);
1342 emac_setmac(priv
, EMAC_DEF_RX_CH
, priv
->mac_addr
);
1345 val
= emac_read(EMAC_MACCONTROL
);
1346 val
|= (EMAC_MACCONTROL_GMIIEN
);
1347 emac_write(EMAC_MACCONTROL
, val
);
1349 /* Enable NAPI and interrupts */
1350 napi_enable(&priv
->napi
);
1351 emac_int_enable(priv
);
1357 * emac_poll - EMAC NAPI Poll function
1358 * @ndev: The DaVinci EMAC network adapter
1359 * @budget: Number of receive packets to process (as told by NAPI layer)
1361 * NAPI Poll function implemented to process packets as per budget. We check
1362 * the type of interrupt on the device and accordingly call the TX or RX
1363 * packet processing functions. We follow the budget for RX processing and
1364 * also put a cap on number of TX pkts processed through config param. The
1365 * NAPI schedule function is called if more packets pending.
1367 * Returns number of packets received (in most cases; else TX pkts - rarely)
1369 static int emac_poll(struct napi_struct
*napi
, int budget
)
1372 struct emac_priv
*priv
= container_of(napi
, struct emac_priv
, napi
);
1373 struct net_device
*ndev
= priv
->ndev
;
1374 struct device
*emac_dev
= &ndev
->dev
;
1376 u32 num_tx_pkts
= 0, num_rx_pkts
= 0;
1378 /* Check interrupt vectors and call packet processing */
1379 status
= emac_read(EMAC_MACINVECTOR
);
1381 mask
= EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC
;
1383 if (priv
->version
== EMAC_VERSION_2
)
1384 mask
= EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC
;
1386 if (status
& mask
) {
1387 num_tx_pkts
= cpdma_chan_process(priv
->txchan
,
1388 EMAC_DEF_TX_MAX_SERVICE
);
1389 } /* TX processing */
1391 mask
= EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC
;
1393 if (priv
->version
== EMAC_VERSION_2
)
1394 mask
= EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC
;
1396 if (status
& mask
) {
1397 num_rx_pkts
= cpdma_chan_process(priv
->rxchan
, budget
);
1398 } /* RX processing */
1400 mask
= EMAC_DM644X_MAC_IN_VECTOR_HOST_INT
;
1401 if (priv
->version
== EMAC_VERSION_2
)
1402 mask
= EMAC_DM646X_MAC_IN_VECTOR_HOST_INT
;
1404 if (unlikely(status
& mask
)) {
1406 dev_err(emac_dev
, "DaVinci EMAC: Fatal Hardware Error\n");
1407 netif_stop_queue(ndev
);
1408 napi_disable(&priv
->napi
);
1410 status
= emac_read(EMAC_MACSTATUS
);
1411 cause
= ((status
& EMAC_MACSTATUS_TXERRCODE_MASK
) >>
1412 EMAC_MACSTATUS_TXERRCODE_SHIFT
);
1414 ch
= ((status
& EMAC_MACSTATUS_TXERRCH_MASK
) >>
1415 EMAC_MACSTATUS_TXERRCH_SHIFT
);
1416 if (net_ratelimit()) {
1417 dev_err(emac_dev
, "TX Host error %s on ch=%d\n",
1418 &emac_txhost_errcodes
[cause
][0], ch
);
1421 cause
= ((status
& EMAC_MACSTATUS_RXERRCODE_MASK
) >>
1422 EMAC_MACSTATUS_RXERRCODE_SHIFT
);
1424 ch
= ((status
& EMAC_MACSTATUS_RXERRCH_MASK
) >>
1425 EMAC_MACSTATUS_RXERRCH_SHIFT
);
1426 if (netif_msg_hw(priv
) && net_ratelimit())
1427 dev_err(emac_dev
, "RX Host error %s on ch=%d\n",
1428 &emac_rxhost_errcodes
[cause
][0], ch
);
1430 } else if (num_rx_pkts
< budget
) {
1431 napi_complete(napi
);
1432 emac_int_enable(priv
);
1438 #ifdef CONFIG_NET_POLL_CONTROLLER
1440 * emac_poll_controller - EMAC Poll controller function
1441 * @ndev: The DaVinci EMAC network adapter
1443 * Polled functionality used by netconsole and others in non interrupt mode
1446 void emac_poll_controller(struct net_device
*ndev
)
1448 struct emac_priv
*priv
= netdev_priv(ndev
);
1450 emac_int_disable(priv
);
1451 emac_irq(ndev
->irq
, ndev
);
1452 emac_int_enable(priv
);
1456 static void emac_adjust_link(struct net_device
*ndev
)
1458 struct emac_priv
*priv
= netdev_priv(ndev
);
1459 struct phy_device
*phydev
= priv
->phydev
;
1460 unsigned long flags
;
1463 spin_lock_irqsave(&priv
->lock
, flags
);
1466 /* check the mode of operation - full/half duplex */
1467 if (phydev
->duplex
!= priv
->duplex
) {
1469 priv
->duplex
= phydev
->duplex
;
1471 if (phydev
->speed
!= priv
->speed
) {
1473 priv
->speed
= phydev
->speed
;
1480 } else if (priv
->link
) {
1487 emac_update_phystatus(priv
);
1488 phy_print_status(priv
->phydev
);
1491 spin_unlock_irqrestore(&priv
->lock
, flags
);
1494 /*************************************************************************
1495 * Linux Driver Model
1496 *************************************************************************/
1499 * emac_devioctl - EMAC adapter ioctl
1500 * @ndev: The DaVinci EMAC network adapter
1501 * @ifrq: request parameter
1502 * @cmd: command parameter
1504 * EMAC driver ioctl function
1506 * Returns success(0) or appropriate error code
1508 static int emac_devioctl(struct net_device
*ndev
, struct ifreq
*ifrq
, int cmd
)
1510 struct emac_priv
*priv
= netdev_priv(ndev
);
1512 if (!(netif_running(ndev
)))
1515 /* TODO: Add phy read and write and private statistics get feature */
1517 return phy_mii_ioctl(priv
->phydev
, ifrq
, cmd
);
1520 static int match_first_device(struct device
*dev
, void *data
)
1522 return !strncmp(dev_name(dev
), "davinci_mdio", 12);
1526 * emac_dev_open - EMAC device open
1527 * @ndev: The DaVinci EMAC network adapter
1529 * Called when system wants to start the interface. We init TX/RX channels
1530 * and enable the hardware for packet reception/transmission and start the
1533 * Returns 0 for a successful open, or appropriate error code
1535 static int emac_dev_open(struct net_device
*ndev
)
1537 struct device
*emac_dev
= &ndev
->dev
;
1539 struct resource
*res
;
1543 struct emac_priv
*priv
= netdev_priv(ndev
);
1545 netif_carrier_off(ndev
);
1546 for (cnt
= 0; cnt
< ETH_ALEN
; cnt
++)
1547 ndev
->dev_addr
[cnt
] = priv
->mac_addr
[cnt
];
1549 /* Configuration items */
1550 priv
->rx_buf_size
= EMAC_DEF_MAX_FRAME_SIZE
+ NET_IP_ALIGN
;
1552 priv
->mac_hash1
= 0;
1553 priv
->mac_hash2
= 0;
1554 emac_write(EMAC_MACHASH1
, 0);
1555 emac_write(EMAC_MACHASH2
, 0);
1557 for (i
= 0; i
< EMAC_DEF_RX_NUM_DESC
; i
++) {
1558 struct sk_buff
*skb
= emac_rx_alloc(priv
);
1563 ret
= cpdma_chan_submit(priv
->rxchan
, skb
, skb
->data
,
1564 skb_tailroom(skb
), GFP_KERNEL
);
1565 if (WARN_ON(ret
< 0))
1571 while ((res
= platform_get_resource(priv
->pdev
, IORESOURCE_IRQ
, k
))) {
1572 for (i
= res
->start
; i
<= res
->end
; i
++) {
1573 if (request_irq(i
, emac_irq
, IRQF_DISABLED
,
1580 /* Start/Enable EMAC hardware */
1581 emac_hw_enable(priv
);
1583 /* Enable Interrupt pacing if configured */
1584 if (priv
->coal_intvl
!= 0) {
1585 struct ethtool_coalesce coal
;
1587 coal
.rx_coalesce_usecs
= (priv
->coal_intvl
<< 4);
1588 emac_set_coalesce(ndev
, &coal
);
1591 cpdma_ctlr_start(priv
->dma
);
1593 priv
->phydev
= NULL
;
1594 /* use the first phy on the bus if pdata did not give us a phy id */
1595 if (!priv
->phy_id
) {
1598 phy
= bus_find_device(&mdio_bus_type
, NULL
, NULL
,
1599 match_first_device
);
1601 priv
->phy_id
= dev_name(phy
);
1604 if (priv
->phy_id
&& *priv
->phy_id
) {
1605 priv
->phydev
= phy_connect(ndev
, priv
->phy_id
,
1606 &emac_adjust_link
, 0,
1607 PHY_INTERFACE_MODE_MII
);
1609 if (IS_ERR(priv
->phydev
)) {
1610 dev_err(emac_dev
, "could not connect to phy %s\n",
1612 ret
= PTR_ERR(priv
->phydev
);
1613 priv
->phydev
= NULL
;
1621 dev_info(emac_dev
, "attached PHY driver [%s] "
1622 "(mii_bus:phy_addr=%s, id=%x)\n",
1623 priv
->phydev
->drv
->name
, dev_name(&priv
->phydev
->dev
),
1624 priv
->phydev
->phy_id
);
1626 /* No PHY , fix the link, speed and duplex settings */
1627 dev_notice(emac_dev
, "no phy, defaulting to 100/full\n");
1629 priv
->speed
= SPEED_100
;
1630 priv
->duplex
= DUPLEX_FULL
;
1631 emac_update_phystatus(priv
);
1634 if (!netif_running(ndev
)) /* debug only - to avoid compiler warning */
1635 emac_dump_regs(priv
);
1637 if (netif_msg_drv(priv
))
1638 dev_notice(emac_dev
, "DaVinci EMAC: Opened %s\n", ndev
->name
);
1641 phy_start(priv
->phydev
);
1647 dev_err(emac_dev
, "DaVinci EMAC: request_irq() failed");
1649 for (q
= k
; k
>= 0; k
--) {
1650 for (m
= i
; m
>= res
->start
; m
--)
1652 res
= platform_get_resource(priv
->pdev
, IORESOURCE_IRQ
, k
-1);
1659 * emac_dev_stop - EMAC device stop
1660 * @ndev: The DaVinci EMAC network adapter
1662 * Called when system wants to stop or down the interface. We stop the network
1663 * queue, disable interrupts and cleanup TX/RX channels.
1665 * We return the statistics in net_device_stats structure pulled from emac
1667 static int emac_dev_stop(struct net_device
*ndev
)
1669 struct resource
*res
;
1672 struct emac_priv
*priv
= netdev_priv(ndev
);
1673 struct device
*emac_dev
= &ndev
->dev
;
1675 /* inform the upper layers. */
1676 netif_stop_queue(ndev
);
1677 napi_disable(&priv
->napi
);
1679 netif_carrier_off(ndev
);
1680 emac_int_disable(priv
);
1681 cpdma_ctlr_stop(priv
->dma
);
1682 emac_write(EMAC_SOFTRESET
, 1);
1685 phy_disconnect(priv
->phydev
);
1688 while ((res
= platform_get_resource(priv
->pdev
, IORESOURCE_IRQ
, i
))) {
1689 for (irq_num
= res
->start
; irq_num
<= res
->end
; irq_num
++)
1690 free_irq(irq_num
, priv
->ndev
);
1694 if (netif_msg_drv(priv
))
1695 dev_notice(emac_dev
, "DaVinci EMAC: %s stopped\n", ndev
->name
);
1701 * emac_dev_getnetstats - EMAC get statistics function
1702 * @ndev: The DaVinci EMAC network adapter
1704 * Called when system wants to get statistics from the device.
1706 * We return the statistics in net_device_stats structure pulled from emac
1708 static struct net_device_stats
*emac_dev_getnetstats(struct net_device
*ndev
)
1710 struct emac_priv
*priv
= netdev_priv(ndev
);
1712 u32 stats_clear_mask
;
1714 /* update emac hardware stats and reset the registers*/
1716 mac_control
= emac_read(EMAC_MACCONTROL
);
1718 if (mac_control
& EMAC_MACCONTROL_GMIIEN
)
1719 stats_clear_mask
= EMAC_STATS_CLR_MASK
;
1721 stats_clear_mask
= 0;
1723 ndev
->stats
.multicast
+= emac_read(EMAC_RXMCASTFRAMES
);
1724 emac_write(EMAC_RXMCASTFRAMES
, stats_clear_mask
);
1726 ndev
->stats
.collisions
+= (emac_read(EMAC_TXCOLLISION
) +
1727 emac_read(EMAC_TXSINGLECOLL
) +
1728 emac_read(EMAC_TXMULTICOLL
));
1729 emac_write(EMAC_TXCOLLISION
, stats_clear_mask
);
1730 emac_write(EMAC_TXSINGLECOLL
, stats_clear_mask
);
1731 emac_write(EMAC_TXMULTICOLL
, stats_clear_mask
);
1733 ndev
->stats
.rx_length_errors
+= (emac_read(EMAC_RXOVERSIZED
) +
1734 emac_read(EMAC_RXJABBER
) +
1735 emac_read(EMAC_RXUNDERSIZED
));
1736 emac_write(EMAC_RXOVERSIZED
, stats_clear_mask
);
1737 emac_write(EMAC_RXJABBER
, stats_clear_mask
);
1738 emac_write(EMAC_RXUNDERSIZED
, stats_clear_mask
);
1740 ndev
->stats
.rx_over_errors
+= (emac_read(EMAC_RXSOFOVERRUNS
) +
1741 emac_read(EMAC_RXMOFOVERRUNS
));
1742 emac_write(EMAC_RXSOFOVERRUNS
, stats_clear_mask
);
1743 emac_write(EMAC_RXMOFOVERRUNS
, stats_clear_mask
);
1745 ndev
->stats
.rx_fifo_errors
+= emac_read(EMAC_RXDMAOVERRUNS
);
1746 emac_write(EMAC_RXDMAOVERRUNS
, stats_clear_mask
);
1748 ndev
->stats
.tx_carrier_errors
+=
1749 emac_read(EMAC_TXCARRIERSENSE
);
1750 emac_write(EMAC_TXCARRIERSENSE
, stats_clear_mask
);
1752 ndev
->stats
.tx_fifo_errors
+= emac_read(EMAC_TXUNDERRUN
);
1753 emac_write(EMAC_TXUNDERRUN
, stats_clear_mask
);
1755 return &ndev
->stats
;
1758 static const struct net_device_ops emac_netdev_ops
= {
1759 .ndo_open
= emac_dev_open
,
1760 .ndo_stop
= emac_dev_stop
,
1761 .ndo_start_xmit
= emac_dev_xmit
,
1762 .ndo_set_rx_mode
= emac_dev_mcast_set
,
1763 .ndo_set_mac_address
= emac_dev_setmac_addr
,
1764 .ndo_do_ioctl
= emac_devioctl
,
1765 .ndo_tx_timeout
= emac_dev_tx_timeout
,
1766 .ndo_get_stats
= emac_dev_getnetstats
,
1767 #ifdef CONFIG_NET_POLL_CONTROLLER
1768 .ndo_poll_controller
= emac_poll_controller
,
1773 static struct emac_platform_data
1774 *davinci_emac_of_get_pdata(struct platform_device
*pdev
,
1775 struct emac_priv
*priv
)
1777 struct device_node
*np
;
1778 struct emac_platform_data
*pdata
= NULL
;
1783 pdata
= pdev
->dev
.platform_data
;
1785 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1790 np
= pdev
->dev
.of_node
;
1794 pdata
->version
= EMAC_VERSION_2
;
1796 if (!is_valid_ether_addr(pdata
->mac_addr
)) {
1797 mac_addr
= of_get_mac_address(np
);
1799 memcpy(pdata
->mac_addr
, mac_addr
, ETH_ALEN
);
1802 ret
= of_property_read_u32(np
, "ti,davinci-ctrl-reg-offset", &data
);
1804 pdata
->ctrl_reg_offset
= data
;
1806 ret
= of_property_read_u32(np
, "ti,davinci-ctrl-mod-reg-offset",
1809 pdata
->ctrl_mod_reg_offset
= data
;
1811 ret
= of_property_read_u32(np
, "ti,davinci-ctrl-ram-offset", &data
);
1813 pdata
->ctrl_ram_offset
= data
;
1815 ret
= of_property_read_u32(np
, "ti,davinci-ctrl-ram-size", &data
);
1817 pdata
->ctrl_ram_size
= data
;
1819 ret
= of_property_read_u32(np
, "ti,davinci-rmii-en", &data
);
1821 pdata
->rmii_en
= data
;
1823 ret
= of_property_read_u32(np
, "ti,davinci-no-bd-ram", &data
);
1825 pdata
->no_bd_ram
= data
;
1827 priv
->phy_node
= of_parse_phandle(np
, "phy-handle", 0);
1828 if (!priv
->phy_node
)
1831 pdev
->dev
.platform_data
= pdata
;
1836 static struct emac_platform_data
1837 *davinci_emac_of_get_pdata(struct platform_device
*pdev
,
1838 struct emac_priv
*priv
)
1840 return pdev
->dev
.platform_data
;
1844 * davinci_emac_probe - EMAC device probe
1845 * @pdev: The DaVinci EMAC device that we are removing
1847 * Called when probing for emac devicesr. We get details of instances and
1848 * resource information from platform init and register a network device
1849 * and allocate resources necessary for driver to perform
1851 static int __devinit
davinci_emac_probe(struct platform_device
*pdev
)
1854 struct resource
*res
;
1855 struct net_device
*ndev
;
1856 struct emac_priv
*priv
;
1857 unsigned long size
, hw_ram_addr
;
1858 struct emac_platform_data
*pdata
;
1859 struct device
*emac_dev
;
1860 struct cpdma_params dma_params
;
1862 /* obtain emac clock from kernel */
1863 emac_clk
= clk_get(&pdev
->dev
, NULL
);
1864 if (IS_ERR(emac_clk
)) {
1865 dev_err(&pdev
->dev
, "failed to get EMAC clock\n");
1868 emac_bus_frequency
= clk_get_rate(emac_clk
);
1869 /* TODO: Probe PHY here if possible */
1871 ndev
= alloc_etherdev(sizeof(struct emac_priv
));
1877 platform_set_drvdata(pdev
, ndev
);
1878 priv
= netdev_priv(ndev
);
1881 priv
->msg_enable
= netif_msg_init(debug_level
, DAVINCI_EMAC_DEBUG
);
1883 spin_lock_init(&priv
->lock
);
1885 pdata
= davinci_emac_of_get_pdata(pdev
, priv
);
1887 dev_err(&pdev
->dev
, "no platform data\n");
1892 /* MAC addr and PHY mask , RMII enable info from platform_data */
1893 memcpy(priv
->mac_addr
, pdata
->mac_addr
, 6);
1894 priv
->phy_id
= pdata
->phy_id
;
1895 priv
->rmii_en
= pdata
->rmii_en
;
1896 priv
->version
= pdata
->version
;
1897 priv
->int_enable
= pdata
->interrupt_enable
;
1898 priv
->int_disable
= pdata
->interrupt_disable
;
1900 priv
->coal_intvl
= 0;
1901 priv
->bus_freq_mhz
= (u32
)(emac_bus_frequency
/ 1000000);
1903 emac_dev
= &ndev
->dev
;
1904 /* Get EMAC platform data */
1905 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1907 dev_err(&pdev
->dev
,"error getting res\n");
1912 priv
->emac_base_phys
= res
->start
+ pdata
->ctrl_reg_offset
;
1913 size
= resource_size(res
);
1914 if (!request_mem_region(res
->start
, size
, ndev
->name
)) {
1915 dev_err(&pdev
->dev
, "failed request_mem_region() for regs\n");
1920 priv
->remap_addr
= ioremap(res
->start
, size
);
1921 if (!priv
->remap_addr
) {
1922 dev_err(&pdev
->dev
, "unable to map IO\n");
1924 release_mem_region(res
->start
, size
);
1927 priv
->emac_base
= priv
->remap_addr
+ pdata
->ctrl_reg_offset
;
1928 ndev
->base_addr
= (unsigned long)priv
->remap_addr
;
1930 priv
->ctrl_base
= priv
->remap_addr
+ pdata
->ctrl_mod_reg_offset
;
1932 hw_ram_addr
= pdata
->hw_ram_addr
;
1934 hw_ram_addr
= (u32 __force
)res
->start
+ pdata
->ctrl_ram_offset
;
1936 memset(&dma_params
, 0, sizeof(dma_params
));
1937 dma_params
.dev
= emac_dev
;
1938 dma_params
.dmaregs
= priv
->emac_base
;
1939 dma_params
.rxthresh
= priv
->emac_base
+ 0x120;
1940 dma_params
.rxfree
= priv
->emac_base
+ 0x140;
1941 dma_params
.txhdp
= priv
->emac_base
+ 0x600;
1942 dma_params
.rxhdp
= priv
->emac_base
+ 0x620;
1943 dma_params
.txcp
= priv
->emac_base
+ 0x640;
1944 dma_params
.rxcp
= priv
->emac_base
+ 0x660;
1945 dma_params
.num_chan
= EMAC_MAX_TXRX_CHANNELS
;
1946 dma_params
.min_packet_size
= EMAC_DEF_MIN_ETHPKTSIZE
;
1947 dma_params
.desc_hw_addr
= hw_ram_addr
;
1948 dma_params
.desc_mem_size
= pdata
->ctrl_ram_size
;
1949 dma_params
.desc_align
= 16;
1951 dma_params
.desc_mem_phys
= pdata
->no_bd_ram
? 0 :
1952 (u32 __force
)res
->start
+ pdata
->ctrl_ram_offset
;
1954 priv
->dma
= cpdma_ctlr_create(&dma_params
);
1956 dev_err(&pdev
->dev
, "error initializing DMA\n");
1961 priv
->txchan
= cpdma_chan_create(priv
->dma
, tx_chan_num(EMAC_DEF_TX_CH
),
1963 priv
->rxchan
= cpdma_chan_create(priv
->dma
, rx_chan_num(EMAC_DEF_RX_CH
),
1965 if (WARN_ON(!priv
->txchan
|| !priv
->rxchan
)) {
1970 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1972 dev_err(&pdev
->dev
, "error getting irq res\n");
1976 ndev
->irq
= res
->start
;
1978 if (!is_valid_ether_addr(priv
->mac_addr
)) {
1979 /* Use random MAC if none passed */
1980 eth_hw_addr_random(ndev
);
1981 memcpy(priv
->mac_addr
, ndev
->dev_addr
, ndev
->addr_len
);
1982 dev_warn(&pdev
->dev
, "using random MAC addr: %pM\n",
1986 ndev
->netdev_ops
= &emac_netdev_ops
;
1987 SET_ETHTOOL_OPS(ndev
, ðtool_ops
);
1988 netif_napi_add(ndev
, &priv
->napi
, emac_poll
, EMAC_POLL_WEIGHT
);
1990 clk_enable(emac_clk
);
1992 /* register the network device */
1993 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1994 rc
= register_netdev(ndev
);
1996 dev_err(&pdev
->dev
, "error in register_netdev\n");
1998 goto netdev_reg_err
;
2002 if (netif_msg_probe(priv
)) {
2003 dev_notice(emac_dev
, "DaVinci EMAC Probe found device "\
2004 "(regs: %p, irq: %d)\n",
2005 (void *)priv
->emac_base_phys
, ndev
->irq
);
2010 clk_disable(emac_clk
);
2013 cpdma_chan_destroy(priv
->txchan
);
2015 cpdma_chan_destroy(priv
->rxchan
);
2016 cpdma_ctlr_destroy(priv
->dma
);
2018 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2019 release_mem_region(res
->start
, resource_size(res
));
2020 iounmap(priv
->remap_addr
);
2030 * davinci_emac_remove - EMAC device remove
2031 * @pdev: The DaVinci EMAC device that we are removing
2033 * Called when removing the device driver. We disable clock usage and release
2034 * the resources taken up by the driver and unregister network device
2036 static int __devexit
davinci_emac_remove(struct platform_device
*pdev
)
2038 struct resource
*res
;
2039 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2040 struct emac_priv
*priv
= netdev_priv(ndev
);
2042 dev_notice(&ndev
->dev
, "DaVinci EMAC: davinci_emac_remove()\n");
2044 platform_set_drvdata(pdev
, NULL
);
2045 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2048 cpdma_chan_destroy(priv
->txchan
);
2050 cpdma_chan_destroy(priv
->rxchan
);
2051 cpdma_ctlr_destroy(priv
->dma
);
2053 release_mem_region(res
->start
, resource_size(res
));
2055 unregister_netdev(ndev
);
2056 iounmap(priv
->remap_addr
);
2059 clk_disable(emac_clk
);
2065 static int davinci_emac_suspend(struct device
*dev
)
2067 struct platform_device
*pdev
= to_platform_device(dev
);
2068 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2070 if (netif_running(ndev
))
2071 emac_dev_stop(ndev
);
2073 clk_disable(emac_clk
);
2078 static int davinci_emac_resume(struct device
*dev
)
2080 struct platform_device
*pdev
= to_platform_device(dev
);
2081 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2083 clk_enable(emac_clk
);
2085 if (netif_running(ndev
))
2086 emac_dev_open(ndev
);
2091 static const struct dev_pm_ops davinci_emac_pm_ops
= {
2092 .suspend
= davinci_emac_suspend
,
2093 .resume
= davinci_emac_resume
,
2096 static const struct of_device_id davinci_emac_of_match
[] = {
2097 {.compatible
= "ti,davinci-dm6467-emac", },
2100 MODULE_DEVICE_TABLE(of
, davinci_emac_of_match
);
2102 /* davinci_emac_driver: EMAC platform driver structure */
2103 static struct platform_driver davinci_emac_driver
= {
2105 .name
= "davinci_emac",
2106 .owner
= THIS_MODULE
,
2107 .pm
= &davinci_emac_pm_ops
,
2108 .of_match_table
= of_match_ptr(davinci_emac_of_match
),
2110 .probe
= davinci_emac_probe
,
2111 .remove
= __devexit_p(davinci_emac_remove
),
2115 * davinci_emac_init - EMAC driver module init
2117 * Called when initializing the driver. We register the driver with
2120 static int __init
davinci_emac_init(void)
2122 return platform_driver_register(&davinci_emac_driver
);
2124 late_initcall(davinci_emac_init
);
2127 * davinci_emac_exit - EMAC driver module exit
2129 * Called when exiting the driver completely. We unregister the driver with
2130 * the platform and exit
2132 static void __exit
davinci_emac_exit(void)
2134 platform_driver_unregister(&davinci_emac_driver
);
2136 module_exit(davinci_emac_exit
);
2138 MODULE_LICENSE("GPL");
2139 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2140 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2141 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");