2 * DaVinci Ethernet Medium Access Controller
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 * Copyright (C) 2009 Texas Instruments.
8 * ---------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/spinlock.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/clk.h>
54 #include <linux/platform_device.h>
55 #include <linux/semaphore.h>
56 #include <linux/phy.h>
57 #include <linux/bitops.h>
59 #include <linux/uaccess.h>
60 #include <linux/pm_runtime.h>
61 #include <linux/davinci_emac.h>
63 #include <linux/of_address.h>
64 #include <linux/of_device.h>
65 #include <linux/of_irq.h>
66 #include <linux/of_net.h>
71 #include "davinci_cpdma.h"
73 static int debug_level
;
74 module_param(debug_level
, int, 0);
75 MODULE_PARM_DESC(debug_level
, "DaVinci EMAC debug level (NETIF_MSG bits)");
77 /* Netif debug messages possible */
78 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
86 NETIF_MSG_TX_QUEUED | \
89 NETIF_MSG_RX_STATUS | \
95 #define EMAC_MAJOR_VERSION 6
96 #define EMAC_MINOR_VERSION 1
97 #define EMAC_MODULE_VERSION "6.1"
98 MODULE_VERSION(EMAC_MODULE_VERSION
);
99 static const char emac_version_string
[] = "TI DaVinci EMAC Linux v6.1";
101 /* Configuration items */
102 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
103 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
104 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
105 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
106 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
107 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
108 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
109 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
110 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
111 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
112 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
113 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
115 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
116 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
118 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
119 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
120 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
121 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
122 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
123 #define EMAC_DEF_RX_NUM_DESC (128)
124 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
125 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
126 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
128 /* Buffer descriptor parameters */
129 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
130 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
132 /* EMAC register related defines */
133 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
134 #define EMAC_NUM_MULTICAST_BITS (64)
135 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
136 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
137 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
138 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
139 #define EMAC_INT_MASK_CLEAR (0xFF)
141 /* RX MBP register bit positions */
142 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
143 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
144 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
145 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
146 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
147 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
148 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
149 #define EMAC_RXMBP_PROMCH_SHIFT (16)
150 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
151 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
152 #define EMAC_RXMBP_BROADCH_SHIFT (8)
153 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
154 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
155 #define EMAC_RXMBP_MULTICH_SHIFT (0)
156 #define EMAC_RXMBP_MULTICH_MASK (0x7)
157 #define EMAC_RXMBP_CHMASK (0x7)
159 /* EMAC register definitions/bit maps used */
160 # define EMAC_MBP_RXPROMISC (0x00200000)
161 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
162 # define EMAC_MBP_RXBCAST (0x00002000)
163 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
164 # define EMAC_MBP_RXMCAST (0x00000020)
165 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
167 /* EMAC mac_control register */
168 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
169 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
170 #define EMAC_MACCONTROL_GMIIEN BIT(5)
171 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
172 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
173 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
175 /* GIGABIT MODE related bits */
176 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
177 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
179 /* EMAC mac_status register */
180 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
181 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
182 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
183 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
184 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
185 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
186 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
187 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
189 /* EMAC RX register masks */
190 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
191 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
193 /* MAC_IN_VECTOR (0x180) register bit fields */
194 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
195 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
196 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
197 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
199 /** NOTE:: For DM646x the IN_VECTOR has changed */
200 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
201 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
202 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
203 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
205 /* CPPI bit positions */
206 #define EMAC_CPPI_SOP_BIT BIT(31)
207 #define EMAC_CPPI_EOP_BIT BIT(30)
208 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
209 #define EMAC_CPPI_EOQ_BIT BIT(28)
210 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
211 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
212 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
213 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
214 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
216 /* Max hardware defines */
217 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
218 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
220 /* EMAC Peripheral Device Register Memory Layout structure */
221 #define EMAC_MACINVECTOR 0x90
223 #define EMAC_DM646X_MACEOIVECTOR 0x94
225 #define EMAC_MACINTSTATRAW 0xB0
226 #define EMAC_MACINTSTATMASKED 0xB4
227 #define EMAC_MACINTMASKSET 0xB8
228 #define EMAC_MACINTMASKCLEAR 0xBC
230 #define EMAC_RXMBPENABLE 0x100
231 #define EMAC_RXUNICASTSET 0x104
232 #define EMAC_RXUNICASTCLEAR 0x108
233 #define EMAC_RXMAXLEN 0x10C
234 #define EMAC_RXBUFFEROFFSET 0x110
235 #define EMAC_RXFILTERLOWTHRESH 0x114
237 #define EMAC_MACCONTROL 0x160
238 #define EMAC_MACSTATUS 0x164
239 #define EMAC_EMCONTROL 0x168
240 #define EMAC_FIFOCONTROL 0x16C
241 #define EMAC_MACCONFIG 0x170
242 #define EMAC_SOFTRESET 0x174
243 #define EMAC_MACSRCADDRLO 0x1D0
244 #define EMAC_MACSRCADDRHI 0x1D4
245 #define EMAC_MACHASH1 0x1D8
246 #define EMAC_MACHASH2 0x1DC
247 #define EMAC_MACADDRLO 0x500
248 #define EMAC_MACADDRHI 0x504
249 #define EMAC_MACINDEX 0x508
251 /* EMAC statistics registers */
252 #define EMAC_RXGOODFRAMES 0x200
253 #define EMAC_RXBCASTFRAMES 0x204
254 #define EMAC_RXMCASTFRAMES 0x208
255 #define EMAC_RXPAUSEFRAMES 0x20C
256 #define EMAC_RXCRCERRORS 0x210
257 #define EMAC_RXALIGNCODEERRORS 0x214
258 #define EMAC_RXOVERSIZED 0x218
259 #define EMAC_RXJABBER 0x21C
260 #define EMAC_RXUNDERSIZED 0x220
261 #define EMAC_RXFRAGMENTS 0x224
262 #define EMAC_RXFILTERED 0x228
263 #define EMAC_RXQOSFILTERED 0x22C
264 #define EMAC_RXOCTETS 0x230
265 #define EMAC_TXGOODFRAMES 0x234
266 #define EMAC_TXBCASTFRAMES 0x238
267 #define EMAC_TXMCASTFRAMES 0x23C
268 #define EMAC_TXPAUSEFRAMES 0x240
269 #define EMAC_TXDEFERRED 0x244
270 #define EMAC_TXCOLLISION 0x248
271 #define EMAC_TXSINGLECOLL 0x24C
272 #define EMAC_TXMULTICOLL 0x250
273 #define EMAC_TXEXCESSIVECOLL 0x254
274 #define EMAC_TXLATECOLL 0x258
275 #define EMAC_TXUNDERRUN 0x25C
276 #define EMAC_TXCARRIERSENSE 0x260
277 #define EMAC_TXOCTETS 0x264
278 #define EMAC_NETOCTETS 0x280
279 #define EMAC_RXSOFOVERRUNS 0x284
280 #define EMAC_RXMOFOVERRUNS 0x288
281 #define EMAC_RXDMAOVERRUNS 0x28C
283 /* EMAC DM644x control registers */
284 #define EMAC_CTRL_EWCTL (0x4)
285 #define EMAC_CTRL_EWINTTCNT (0x8)
287 /* EMAC DM644x control module masks */
288 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
289 #define EMAC_DM644X_INTMIN_INTVL 0x1
290 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
292 /* EMAC DM646X control module registers */
293 #define EMAC_DM646X_CMINTCTRL 0x0C
294 #define EMAC_DM646X_CMRXINTEN 0x14
295 #define EMAC_DM646X_CMTXINTEN 0x18
296 #define EMAC_DM646X_CMRXINTMAX 0x70
297 #define EMAC_DM646X_CMTXINTMAX 0x74
299 /* EMAC DM646X control module masks */
300 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
301 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
302 #define EMAC_DM646X_CMINTMAX_CNT 63
303 #define EMAC_DM646X_CMINTMIN_CNT 2
304 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
305 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
308 /* EMAC EOI codes for C0 */
309 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
310 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
312 /* EMAC Stats Clear Mask */
313 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
315 /* emac_priv: EMAC private data structure
317 * EMAC adapter private data structure
321 struct net_device
*ndev
;
322 struct platform_device
*pdev
;
323 struct napi_struct napi
;
325 void __iomem
*remap_addr
;
327 void __iomem
*emac_base
;
328 void __iomem
*ctrl_base
;
329 struct cpdma_ctlr
*dma
;
330 struct cpdma_chan
*txchan
;
331 struct cpdma_chan
*rxchan
;
332 u32 link
; /* 1=link on, 0=link off */
333 u32 speed
; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
334 u32 duplex
; /* Link duplex: 0=Half, 1=Full */
343 u32 multicast_hash_cnt
[EMAC_NUM_MULTICAST_BITS
];
347 struct device_node
*phy_node
;
349 struct phy_device
*phydev
;
351 /*platform specific members*/
352 void (*int_enable
) (void);
353 void (*int_disable
) (void);
356 /* EMAC TX Host Error description strings */
357 static char *emac_txhost_errcodes
[16] = {
358 "No error", "SOP error", "Ownership bit not set in SOP buffer",
359 "Zero Next Buffer Descriptor Pointer Without EOP",
360 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
361 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
362 "Reserved", "Reserved", "Reserved", "Reserved"
365 /* EMAC RX Host Error description strings */
366 static char *emac_rxhost_errcodes
[16] = {
367 "No error", "Reserved", "Ownership bit not set in input buffer",
368 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
369 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
370 "Reserved", "Reserved", "Reserved", "Reserved"
374 #define emac_read(reg) ioread32(priv->emac_base + (reg))
375 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
377 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
378 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
381 * emac_dump_regs - Dump important EMAC registers to debug terminal
382 * @priv: The DaVinci EMAC private adapter structure
384 * Executes ethtool set cmd & sets phy mode
387 static void emac_dump_regs(struct emac_priv
*priv
)
389 struct device
*emac_dev
= &priv
->ndev
->dev
;
391 /* Print important registers in EMAC */
392 dev_info(emac_dev
, "EMAC Basic registers\n");
393 if (priv
->version
== EMAC_VERSION_1
) {
394 dev_info(emac_dev
, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
395 emac_ctrl_read(EMAC_CTRL_EWCTL
),
396 emac_ctrl_read(EMAC_CTRL_EWINTTCNT
));
398 dev_info(emac_dev
, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
399 emac_read(EMAC_EMCONTROL
), emac_read(EMAC_FIFOCONTROL
));
400 dev_info(emac_dev
, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
401 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE
),
402 emac_read(EMAC_RXUNICASTSET
), emac_read(EMAC_RXMAXLEN
));
403 dev_info(emac_dev
, "EMAC: MacControl:%08X, MacStatus: %08X, "\
404 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL
),
405 emac_read(EMAC_MACSTATUS
), emac_read(EMAC_MACCONFIG
));
406 dev_info(emac_dev
, "EMAC Statistics\n");
407 dev_info(emac_dev
, "EMAC: rx_good_frames:%d\n",
408 emac_read(EMAC_RXGOODFRAMES
));
409 dev_info(emac_dev
, "EMAC: rx_broadcast_frames:%d\n",
410 emac_read(EMAC_RXBCASTFRAMES
));
411 dev_info(emac_dev
, "EMAC: rx_multicast_frames:%d\n",
412 emac_read(EMAC_RXMCASTFRAMES
));
413 dev_info(emac_dev
, "EMAC: rx_pause_frames:%d\n",
414 emac_read(EMAC_RXPAUSEFRAMES
));
415 dev_info(emac_dev
, "EMAC: rx_crcerrors:%d\n",
416 emac_read(EMAC_RXCRCERRORS
));
417 dev_info(emac_dev
, "EMAC: rx_align_code_errors:%d\n",
418 emac_read(EMAC_RXALIGNCODEERRORS
));
419 dev_info(emac_dev
, "EMAC: rx_oversized_frames:%d\n",
420 emac_read(EMAC_RXOVERSIZED
));
421 dev_info(emac_dev
, "EMAC: rx_jabber_frames:%d\n",
422 emac_read(EMAC_RXJABBER
));
423 dev_info(emac_dev
, "EMAC: rx_undersized_frames:%d\n",
424 emac_read(EMAC_RXUNDERSIZED
));
425 dev_info(emac_dev
, "EMAC: rx_fragments:%d\n",
426 emac_read(EMAC_RXFRAGMENTS
));
427 dev_info(emac_dev
, "EMAC: rx_filtered_frames:%d\n",
428 emac_read(EMAC_RXFILTERED
));
429 dev_info(emac_dev
, "EMAC: rx_qos_filtered_frames:%d\n",
430 emac_read(EMAC_RXQOSFILTERED
));
431 dev_info(emac_dev
, "EMAC: rx_octets:%d\n",
432 emac_read(EMAC_RXOCTETS
));
433 dev_info(emac_dev
, "EMAC: tx_goodframes:%d\n",
434 emac_read(EMAC_TXGOODFRAMES
));
435 dev_info(emac_dev
, "EMAC: tx_bcastframes:%d\n",
436 emac_read(EMAC_TXBCASTFRAMES
));
437 dev_info(emac_dev
, "EMAC: tx_mcastframes:%d\n",
438 emac_read(EMAC_TXMCASTFRAMES
));
439 dev_info(emac_dev
, "EMAC: tx_pause_frames:%d\n",
440 emac_read(EMAC_TXPAUSEFRAMES
));
441 dev_info(emac_dev
, "EMAC: tx_deferred_frames:%d\n",
442 emac_read(EMAC_TXDEFERRED
));
443 dev_info(emac_dev
, "EMAC: tx_collision_frames:%d\n",
444 emac_read(EMAC_TXCOLLISION
));
445 dev_info(emac_dev
, "EMAC: tx_single_coll_frames:%d\n",
446 emac_read(EMAC_TXSINGLECOLL
));
447 dev_info(emac_dev
, "EMAC: tx_mult_coll_frames:%d\n",
448 emac_read(EMAC_TXMULTICOLL
));
449 dev_info(emac_dev
, "EMAC: tx_excessive_collisions:%d\n",
450 emac_read(EMAC_TXEXCESSIVECOLL
));
451 dev_info(emac_dev
, "EMAC: tx_late_collisions:%d\n",
452 emac_read(EMAC_TXLATECOLL
));
453 dev_info(emac_dev
, "EMAC: tx_underrun:%d\n",
454 emac_read(EMAC_TXUNDERRUN
));
455 dev_info(emac_dev
, "EMAC: tx_carrier_sense_errors:%d\n",
456 emac_read(EMAC_TXCARRIERSENSE
));
457 dev_info(emac_dev
, "EMAC: tx_octets:%d\n",
458 emac_read(EMAC_TXOCTETS
));
459 dev_info(emac_dev
, "EMAC: net_octets:%d\n",
460 emac_read(EMAC_NETOCTETS
));
461 dev_info(emac_dev
, "EMAC: rx_sof_overruns:%d\n",
462 emac_read(EMAC_RXSOFOVERRUNS
));
463 dev_info(emac_dev
, "EMAC: rx_mof_overruns:%d\n",
464 emac_read(EMAC_RXMOFOVERRUNS
));
465 dev_info(emac_dev
, "EMAC: rx_dma_overruns:%d\n",
466 emac_read(EMAC_RXDMAOVERRUNS
));
468 cpdma_ctlr_dump(priv
->dma
);
472 * emac_get_drvinfo - Get EMAC driver information
473 * @ndev: The DaVinci EMAC network adapter
474 * @info: ethtool info structure containing name and version
476 * Returns EMAC driver information (name and version)
479 static void emac_get_drvinfo(struct net_device
*ndev
,
480 struct ethtool_drvinfo
*info
)
482 strlcpy(info
->driver
, emac_version_string
, sizeof(info
->driver
));
483 strlcpy(info
->version
, EMAC_MODULE_VERSION
, sizeof(info
->version
));
487 * emac_get_settings - Get EMAC settings
488 * @ndev: The DaVinci EMAC network adapter
489 * @ecmd: ethtool command
491 * Executes ethool get command
494 static int emac_get_settings(struct net_device
*ndev
,
495 struct ethtool_cmd
*ecmd
)
497 struct emac_priv
*priv
= netdev_priv(ndev
);
499 return phy_ethtool_gset(priv
->phydev
, ecmd
);
506 * emac_set_settings - Set EMAC settings
507 * @ndev: The DaVinci EMAC network adapter
508 * @ecmd: ethtool command
510 * Executes ethool set command
513 static int emac_set_settings(struct net_device
*ndev
, struct ethtool_cmd
*ecmd
)
515 struct emac_priv
*priv
= netdev_priv(ndev
);
517 return phy_ethtool_sset(priv
->phydev
, ecmd
);
524 * emac_get_coalesce - Get interrupt coalesce settings for this device
525 * @ndev : The DaVinci EMAC network adapter
526 * @coal : ethtool coalesce settings structure
528 * Fetch the current interrupt coalesce settings
531 static int emac_get_coalesce(struct net_device
*ndev
,
532 struct ethtool_coalesce
*coal
)
534 struct emac_priv
*priv
= netdev_priv(ndev
);
536 coal
->rx_coalesce_usecs
= priv
->coal_intvl
;
542 * emac_set_coalesce - Set interrupt coalesce settings for this device
543 * @ndev : The DaVinci EMAC network adapter
544 * @coal : ethtool coalesce settings structure
546 * Set interrupt coalesce parameters
549 static int emac_set_coalesce(struct net_device
*ndev
,
550 struct ethtool_coalesce
*coal
)
552 struct emac_priv
*priv
= netdev_priv(ndev
);
553 u32 int_ctrl
, num_interrupts
= 0;
554 u32 prescale
= 0, addnl_dvdr
= 1, coal_intvl
= 0;
556 if (!coal
->rx_coalesce_usecs
)
559 coal_intvl
= coal
->rx_coalesce_usecs
;
561 switch (priv
->version
) {
563 int_ctrl
= emac_ctrl_read(EMAC_DM646X_CMINTCTRL
);
564 prescale
= priv
->bus_freq_mhz
* 4;
566 if (coal_intvl
< EMAC_DM646X_CMINTMIN_INTVL
)
567 coal_intvl
= EMAC_DM646X_CMINTMIN_INTVL
;
569 if (coal_intvl
> EMAC_DM646X_CMINTMAX_INTVL
) {
571 * Interrupt pacer works with 4us Pulse, we can
572 * throttle further by dilating the 4us pulse.
574 addnl_dvdr
= EMAC_DM646X_INTPRESCALE_MASK
/ prescale
;
576 if (addnl_dvdr
> 1) {
577 prescale
*= addnl_dvdr
;
578 if (coal_intvl
> (EMAC_DM646X_CMINTMAX_INTVL
580 coal_intvl
= (EMAC_DM646X_CMINTMAX_INTVL
584 coal_intvl
= EMAC_DM646X_CMINTMAX_INTVL
;
588 num_interrupts
= (1000 * addnl_dvdr
) / coal_intvl
;
590 int_ctrl
|= EMAC_DM646X_INTPACEEN
;
591 int_ctrl
&= (~EMAC_DM646X_INTPRESCALE_MASK
);
592 int_ctrl
|= (prescale
& EMAC_DM646X_INTPRESCALE_MASK
);
593 emac_ctrl_write(EMAC_DM646X_CMINTCTRL
, int_ctrl
);
595 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX
, num_interrupts
);
596 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX
, num_interrupts
);
600 int_ctrl
= emac_ctrl_read(EMAC_CTRL_EWINTTCNT
);
601 int_ctrl
&= (~EMAC_DM644X_EWINTCNT_MASK
);
602 prescale
= coal_intvl
* priv
->bus_freq_mhz
;
603 if (prescale
> EMAC_DM644X_EWINTCNT_MASK
) {
604 prescale
= EMAC_DM644X_EWINTCNT_MASK
;
605 coal_intvl
= prescale
/ priv
->bus_freq_mhz
;
607 emac_ctrl_write(EMAC_CTRL_EWINTTCNT
, (int_ctrl
| prescale
));
612 printk(KERN_INFO
"Set coalesce to %d usecs.\n", coal_intvl
);
613 priv
->coal_intvl
= coal_intvl
;
620 /* ethtool_ops: DaVinci EMAC Ethtool structure
622 * Ethtool support for EMAC adapter
624 static const struct ethtool_ops ethtool_ops
= {
625 .get_drvinfo
= emac_get_drvinfo
,
626 .get_settings
= emac_get_settings
,
627 .set_settings
= emac_set_settings
,
628 .get_link
= ethtool_op_get_link
,
629 .get_coalesce
= emac_get_coalesce
,
630 .set_coalesce
= emac_set_coalesce
,
631 .get_ts_info
= ethtool_op_get_ts_info
,
635 * emac_update_phystatus - Update Phy status
636 * @priv: The DaVinci EMAC private adapter structure
638 * Updates phy status and takes action for network queue if required
639 * based upon link status
642 static void emac_update_phystatus(struct emac_priv
*priv
)
647 struct net_device
*ndev
= priv
->ndev
;
649 mac_control
= emac_read(EMAC_MACCONTROL
);
650 cur_duplex
= (mac_control
& EMAC_MACCONTROL_FULLDUPLEXEN
) ?
651 DUPLEX_FULL
: DUPLEX_HALF
;
653 new_duplex
= priv
->phydev
->duplex
;
655 new_duplex
= DUPLEX_FULL
;
657 /* We get called only if link has changed (speed/duplex/status) */
658 if ((priv
->link
) && (new_duplex
!= cur_duplex
)) {
659 priv
->duplex
= new_duplex
;
660 if (DUPLEX_FULL
== priv
->duplex
)
661 mac_control
|= (EMAC_MACCONTROL_FULLDUPLEXEN
);
663 mac_control
&= ~(EMAC_MACCONTROL_FULLDUPLEXEN
);
666 if (priv
->speed
== SPEED_1000
&& (priv
->version
== EMAC_VERSION_2
)) {
667 mac_control
= emac_read(EMAC_MACCONTROL
);
668 mac_control
|= (EMAC_DM646X_MACCONTORL_GIG
|
669 EMAC_DM646X_MACCONTORL_GIGFORCE
);
671 /* Clear the GIG bit and GIGFORCE bit */
672 mac_control
&= ~(EMAC_DM646X_MACCONTORL_GIGFORCE
|
673 EMAC_DM646X_MACCONTORL_GIG
);
675 if (priv
->rmii_en
&& (priv
->speed
== SPEED_100
))
676 mac_control
|= EMAC_MACCONTROL_RMIISPEED_MASK
;
678 mac_control
&= ~EMAC_MACCONTROL_RMIISPEED_MASK
;
681 /* Update mac_control if changed */
682 emac_write(EMAC_MACCONTROL
, mac_control
);
686 if (!netif_carrier_ok(ndev
))
687 netif_carrier_on(ndev
);
688 /* reactivate the transmit queue if it is stopped */
689 if (netif_running(ndev
) && netif_queue_stopped(ndev
))
690 netif_wake_queue(ndev
);
693 if (netif_carrier_ok(ndev
))
694 netif_carrier_off(ndev
);
695 if (!netif_queue_stopped(ndev
))
696 netif_stop_queue(ndev
);
701 * hash_get - Calculate hash value from mac address
702 * @addr: mac address to delete from hash table
704 * Calculates hash value from mac address
707 static u32
hash_get(u8
*addr
)
714 for (cnt
= 0; cnt
< 2; cnt
++) {
716 hash
^= (tmpval
>> 2) ^ (tmpval
<< 4);
718 hash
^= (tmpval
>> 4) ^ (tmpval
<< 2);
720 hash
^= (tmpval
>> 6) ^ (tmpval
);
727 * hash_add - Hash function to add mac addr from hash table
728 * @priv: The DaVinci EMAC private adapter structure
729 * @mac_addr: mac address to delete from hash table
731 * Adds mac address to the internal hash table
734 static int hash_add(struct emac_priv
*priv
, u8
*mac_addr
)
736 struct device
*emac_dev
= &priv
->ndev
->dev
;
739 u32 hash_value
= hash_get(mac_addr
);
741 if (hash_value
>= EMAC_NUM_MULTICAST_BITS
) {
742 if (netif_msg_drv(priv
)) {
743 dev_err(emac_dev
, "DaVinci EMAC: hash_add(): Invalid "\
744 "Hash %08x, should not be greater than %08x",
745 hash_value
, (EMAC_NUM_MULTICAST_BITS
- 1));
750 /* set the hash bit only if not previously set */
751 if (priv
->multicast_hash_cnt
[hash_value
] == 0) {
752 rc
= 1; /* hash value changed */
753 if (hash_value
< 32) {
754 hash_bit
= BIT(hash_value
);
755 priv
->mac_hash1
|= hash_bit
;
757 hash_bit
= BIT((hash_value
- 32));
758 priv
->mac_hash2
|= hash_bit
;
762 /* incr counter for num of mcast addr's mapped to "this" hash bit */
763 ++priv
->multicast_hash_cnt
[hash_value
];
769 * hash_del - Hash function to delete mac addr from hash table
770 * @priv: The DaVinci EMAC private adapter structure
771 * @mac_addr: mac address to delete from hash table
773 * Removes mac address from the internal hash table
776 static int hash_del(struct emac_priv
*priv
, u8
*mac_addr
)
781 hash_value
= hash_get(mac_addr
);
782 if (priv
->multicast_hash_cnt
[hash_value
] > 0) {
783 /* dec cntr for num of mcast addr's mapped to this hash bit */
784 --priv
->multicast_hash_cnt
[hash_value
];
787 /* if counter still > 0, at least one multicast address refers
788 * to this hash bit. so return 0 */
789 if (priv
->multicast_hash_cnt
[hash_value
] > 0)
792 if (hash_value
< 32) {
793 hash_bit
= BIT(hash_value
);
794 priv
->mac_hash1
&= ~hash_bit
;
796 hash_bit
= BIT((hash_value
- 32));
797 priv
->mac_hash2
&= ~hash_bit
;
800 /* return 1 to indicate change in mac_hash registers reqd */
804 /* EMAC multicast operation */
805 #define EMAC_MULTICAST_ADD 0
806 #define EMAC_MULTICAST_DEL 1
807 #define EMAC_ALL_MULTI_SET 2
808 #define EMAC_ALL_MULTI_CLR 3
811 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
812 * @priv: The DaVinci EMAC private adapter structure
813 * @action: multicast operation to perform
814 * mac_addr: mac address to set
816 * Set multicast addresses in EMAC adapter - internal function
819 static void emac_add_mcast(struct emac_priv
*priv
, u32 action
, u8
*mac_addr
)
821 struct device
*emac_dev
= &priv
->ndev
->dev
;
825 case EMAC_MULTICAST_ADD
:
826 update
= hash_add(priv
, mac_addr
);
828 case EMAC_MULTICAST_DEL
:
829 update
= hash_del(priv
, mac_addr
);
831 case EMAC_ALL_MULTI_SET
:
833 priv
->mac_hash1
= EMAC_ALL_MULTI_REG_VALUE
;
834 priv
->mac_hash2
= EMAC_ALL_MULTI_REG_VALUE
;
836 case EMAC_ALL_MULTI_CLR
:
840 memset(&(priv
->multicast_hash_cnt
[0]), 0,
841 sizeof(priv
->multicast_hash_cnt
[0]) *
842 EMAC_NUM_MULTICAST_BITS
);
845 if (netif_msg_drv(priv
))
846 dev_err(emac_dev
, "DaVinci EMAC: add_mcast"\
847 ": bad operation %d", action
);
851 /* write to the hardware only if the register status chances */
853 emac_write(EMAC_MACHASH1
, priv
->mac_hash1
);
854 emac_write(EMAC_MACHASH2
, priv
->mac_hash2
);
859 * emac_dev_mcast_set - Set multicast address in the EMAC adapter
860 * @ndev: The DaVinci EMAC network adapter
862 * Set multicast addresses in EMAC adapter
865 static void emac_dev_mcast_set(struct net_device
*ndev
)
868 struct emac_priv
*priv
= netdev_priv(ndev
);
870 mbp_enable
= emac_read(EMAC_RXMBPENABLE
);
871 if (ndev
->flags
& IFF_PROMISC
) {
872 mbp_enable
&= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH
));
873 mbp_enable
|= (EMAC_MBP_RXPROMISC
);
875 mbp_enable
= (mbp_enable
& ~EMAC_MBP_RXPROMISC
);
876 if ((ndev
->flags
& IFF_ALLMULTI
) ||
877 netdev_mc_count(ndev
) > EMAC_DEF_MAX_MULTICAST_ADDRESSES
) {
878 mbp_enable
= (mbp_enable
| EMAC_MBP_RXMCAST
);
879 emac_add_mcast(priv
, EMAC_ALL_MULTI_SET
, NULL
);
880 } else if (!netdev_mc_empty(ndev
)) {
881 struct netdev_hw_addr
*ha
;
883 mbp_enable
= (mbp_enable
| EMAC_MBP_RXMCAST
);
884 emac_add_mcast(priv
, EMAC_ALL_MULTI_CLR
, NULL
);
885 /* program multicast address list into EMAC hardware */
886 netdev_for_each_mc_addr(ha
, ndev
) {
887 emac_add_mcast(priv
, EMAC_MULTICAST_ADD
,
891 mbp_enable
= (mbp_enable
& ~EMAC_MBP_RXMCAST
);
892 emac_add_mcast(priv
, EMAC_ALL_MULTI_CLR
, NULL
);
895 /* Set mbp config register */
896 emac_write(EMAC_RXMBPENABLE
, mbp_enable
);
899 /*************************************************************************
900 * EMAC Hardware manipulation
901 *************************************************************************/
904 * emac_int_disable - Disable EMAC module interrupt (from adapter)
905 * @priv: The DaVinci EMAC private adapter structure
907 * Disable EMAC interrupt on the adapter
910 static void emac_int_disable(struct emac_priv
*priv
)
912 if (priv
->version
== EMAC_VERSION_2
) {
915 local_irq_save(flags
);
917 /* Program C0_Int_En to zero to turn off
918 * interrupts to the CPU */
919 emac_ctrl_write(EMAC_DM646X_CMRXINTEN
, 0x0);
920 emac_ctrl_write(EMAC_DM646X_CMTXINTEN
, 0x0);
921 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
922 if (priv
->int_disable
)
925 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
927 /* ack rxen only then a new pulse will be generated */
928 emac_write(EMAC_DM646X_MACEOIVECTOR
,
929 EMAC_DM646X_MAC_EOI_C0_RXEN
);
931 /* ack txen- only then a new pulse will be generated */
932 emac_write(EMAC_DM646X_MACEOIVECTOR
,
933 EMAC_DM646X_MAC_EOI_C0_TXEN
);
935 local_irq_restore(flags
);
938 /* Set DM644x control registers for interrupt control */
939 emac_ctrl_write(EMAC_CTRL_EWCTL
, 0x0);
944 * emac_int_enable - Enable EMAC module interrupt (from adapter)
945 * @priv: The DaVinci EMAC private adapter structure
947 * Enable EMAC interrupt on the adapter
950 static void emac_int_enable(struct emac_priv
*priv
)
952 if (priv
->version
== EMAC_VERSION_2
) {
953 if (priv
->int_enable
)
956 emac_ctrl_write(EMAC_DM646X_CMRXINTEN
, 0xff);
957 emac_ctrl_write(EMAC_DM646X_CMTXINTEN
, 0xff);
959 /* In addition to turning on interrupt Enable, we need
960 * ack by writing appropriate values to the EOI
963 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
965 /* Set DM644x control registers for interrupt control */
966 emac_ctrl_write(EMAC_CTRL_EWCTL
, 0x1);
971 * emac_irq - EMAC interrupt handler
972 * @irq: interrupt number
973 * @dev_id: EMAC network adapter data structure ptr
975 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
976 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
978 * Returns interrupt handled condition
980 static irqreturn_t
emac_irq(int irq
, void *dev_id
)
982 struct net_device
*ndev
= (struct net_device
*)dev_id
;
983 struct emac_priv
*priv
= netdev_priv(ndev
);
986 if (likely(netif_running(priv
->ndev
))) {
987 emac_int_disable(priv
);
988 napi_schedule(&priv
->napi
);
990 /* we are closing down, so dont process anything */
995 static struct sk_buff
*emac_rx_alloc(struct emac_priv
*priv
)
997 struct sk_buff
*skb
= netdev_alloc_skb(priv
->ndev
, priv
->rx_buf_size
);
1000 skb_reserve(skb
, NET_IP_ALIGN
);
1004 static void emac_rx_handler(void *token
, int len
, int status
)
1006 struct sk_buff
*skb
= token
;
1007 struct net_device
*ndev
= skb
->dev
;
1008 struct emac_priv
*priv
= netdev_priv(ndev
);
1009 struct device
*emac_dev
= &ndev
->dev
;
1012 /* free and bail if we are shutting down */
1013 if (unlikely(!netif_running(ndev
))) {
1014 dev_kfree_skb_any(skb
);
1018 /* recycle on receive error */
1020 ndev
->stats
.rx_errors
++;
1024 /* feed received packet up the stack */
1026 skb
->protocol
= eth_type_trans(skb
, ndev
);
1027 netif_receive_skb(skb
);
1028 ndev
->stats
.rx_bytes
+= len
;
1029 ndev
->stats
.rx_packets
++;
1031 /* alloc a new packet for receive */
1032 skb
= emac_rx_alloc(priv
);
1034 if (netif_msg_rx_err(priv
) && net_ratelimit())
1035 dev_err(emac_dev
, "failed rx buffer alloc\n");
1040 ret
= cpdma_chan_submit(priv
->rxchan
, skb
, skb
->data
,
1041 skb_tailroom(skb
), 0);
1043 WARN_ON(ret
== -ENOMEM
);
1044 if (unlikely(ret
< 0))
1045 dev_kfree_skb_any(skb
);
1048 static void emac_tx_handler(void *token
, int len
, int status
)
1050 struct sk_buff
*skb
= token
;
1051 struct net_device
*ndev
= skb
->dev
;
1053 /* Check whether the queue is stopped due to stalled tx dma, if the
1054 * queue is stopped then start the queue as we have free desc for tx
1056 if (unlikely(netif_queue_stopped(ndev
)))
1057 netif_wake_queue(ndev
);
1058 ndev
->stats
.tx_packets
++;
1059 ndev
->stats
.tx_bytes
+= len
;
1060 dev_kfree_skb_any(skb
);
1064 * emac_dev_xmit - EMAC Transmit function
1066 * @ndev: The DaVinci EMAC network adapter
1068 * Called by the system to transmit a packet - we queue the packet in
1069 * EMAC hardware transmit queue
1071 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1073 static int emac_dev_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
1075 struct device
*emac_dev
= &ndev
->dev
;
1077 struct emac_priv
*priv
= netdev_priv(ndev
);
1079 /* If no link, return */
1080 if (unlikely(!priv
->link
)) {
1081 if (netif_msg_tx_err(priv
) && net_ratelimit())
1082 dev_err(emac_dev
, "DaVinci EMAC: No link to transmit");
1086 ret_code
= skb_padto(skb
, EMAC_DEF_MIN_ETHPKTSIZE
);
1087 if (unlikely(ret_code
< 0)) {
1088 if (netif_msg_tx_err(priv
) && net_ratelimit())
1089 dev_err(emac_dev
, "DaVinci EMAC: packet pad failed");
1093 skb_tx_timestamp(skb
);
1095 ret_code
= cpdma_chan_submit(priv
->txchan
, skb
, skb
->data
, skb
->len
,
1097 if (unlikely(ret_code
!= 0)) {
1098 if (netif_msg_tx_err(priv
) && net_ratelimit())
1099 dev_err(emac_dev
, "DaVinci EMAC: desc submit failed");
1103 /* If there is no more tx desc left free then we need to
1104 * tell the kernel to stop sending us tx frames.
1106 if (unlikely(!cpdma_check_free_tx_desc(priv
->txchan
)))
1107 netif_stop_queue(ndev
);
1109 return NETDEV_TX_OK
;
1112 ndev
->stats
.tx_dropped
++;
1113 netif_stop_queue(ndev
);
1114 return NETDEV_TX_BUSY
;
1118 * emac_dev_tx_timeout - EMAC Transmit timeout function
1119 * @ndev: The DaVinci EMAC network adapter
1121 * Called when system detects that a skb timeout period has expired
1122 * potentially due to a fault in the adapter in not being able to send
1123 * it out on the wire. We teardown the TX channel assuming a hardware
1124 * error and re-initialize the TX channel for hardware operation
1127 static void emac_dev_tx_timeout(struct net_device
*ndev
)
1129 struct emac_priv
*priv
= netdev_priv(ndev
);
1130 struct device
*emac_dev
= &ndev
->dev
;
1132 if (netif_msg_tx_err(priv
))
1133 dev_err(emac_dev
, "DaVinci EMAC: xmit timeout, restarting TX");
1135 emac_dump_regs(priv
);
1137 ndev
->stats
.tx_errors
++;
1138 emac_int_disable(priv
);
1139 cpdma_chan_stop(priv
->txchan
);
1140 cpdma_chan_start(priv
->txchan
);
1141 emac_int_enable(priv
);
1145 * emac_set_type0addr - Set EMAC Type0 mac address
1146 * @priv: The DaVinci EMAC private adapter structure
1147 * @ch: RX channel number
1148 * @mac_addr: MAC address to set in device
1150 * Called internally to set Type0 mac address of the adapter (Device)
1152 * Returns success (0) or appropriate error code (none as of now)
1154 static void emac_set_type0addr(struct emac_priv
*priv
, u32 ch
, char *mac_addr
)
1157 val
= ((mac_addr
[5] << 8) | (mac_addr
[4]));
1158 emac_write(EMAC_MACSRCADDRLO
, val
);
1160 val
= ((mac_addr
[3] << 24) | (mac_addr
[2] << 16) | \
1161 (mac_addr
[1] << 8) | (mac_addr
[0]));
1162 emac_write(EMAC_MACSRCADDRHI
, val
);
1163 val
= emac_read(EMAC_RXUNICASTSET
);
1165 emac_write(EMAC_RXUNICASTSET
, val
);
1166 val
= emac_read(EMAC_RXUNICASTCLEAR
);
1168 emac_write(EMAC_RXUNICASTCLEAR
, val
);
1172 * emac_set_type1addr - Set EMAC Type1 mac address
1173 * @priv: The DaVinci EMAC private adapter structure
1174 * @ch: RX channel number
1175 * @mac_addr: MAC address to set in device
1177 * Called internally to set Type1 mac address of the adapter (Device)
1179 * Returns success (0) or appropriate error code (none as of now)
1181 static void emac_set_type1addr(struct emac_priv
*priv
, u32 ch
, char *mac_addr
)
1184 emac_write(EMAC_MACINDEX
, ch
);
1185 val
= ((mac_addr
[5] << 8) | mac_addr
[4]);
1186 emac_write(EMAC_MACADDRLO
, val
);
1187 val
= ((mac_addr
[3] << 24) | (mac_addr
[2] << 16) | \
1188 (mac_addr
[1] << 8) | (mac_addr
[0]));
1189 emac_write(EMAC_MACADDRHI
, val
);
1190 emac_set_type0addr(priv
, ch
, mac_addr
);
1194 * emac_set_type2addr - Set EMAC Type2 mac address
1195 * @priv: The DaVinci EMAC private adapter structure
1196 * @ch: RX channel number
1197 * @mac_addr: MAC address to set in device
1198 * @index: index into RX address entries
1199 * @match: match parameter for RX address matching logic
1201 * Called internally to set Type2 mac address of the adapter (Device)
1203 * Returns success (0) or appropriate error code (none as of now)
1205 static void emac_set_type2addr(struct emac_priv
*priv
, u32 ch
,
1206 char *mac_addr
, int index
, int match
)
1209 emac_write(EMAC_MACINDEX
, index
);
1210 val
= ((mac_addr
[3] << 24) | (mac_addr
[2] << 16) | \
1211 (mac_addr
[1] << 8) | (mac_addr
[0]));
1212 emac_write(EMAC_MACADDRHI
, val
);
1213 val
= ((mac_addr
[5] << 8) | mac_addr
[4] | ((ch
& 0x7) << 16) | \
1214 (match
<< 19) | BIT(20));
1215 emac_write(EMAC_MACADDRLO
, val
);
1216 emac_set_type0addr(priv
, ch
, mac_addr
);
1220 * emac_setmac - Set mac address in the adapter (internal function)
1221 * @priv: The DaVinci EMAC private adapter structure
1222 * @ch: RX channel number
1223 * @mac_addr: MAC address to set in device
1225 * Called internally to set the mac address of the adapter (Device)
1227 * Returns success (0) or appropriate error code (none as of now)
1229 static void emac_setmac(struct emac_priv
*priv
, u32 ch
, char *mac_addr
)
1231 struct device
*emac_dev
= &priv
->ndev
->dev
;
1233 if (priv
->rx_addr_type
== 0) {
1234 emac_set_type0addr(priv
, ch
, mac_addr
);
1235 } else if (priv
->rx_addr_type
== 1) {
1237 for (cnt
= 0; cnt
< EMAC_MAX_TXRX_CHANNELS
; cnt
++)
1238 emac_set_type1addr(priv
, ch
, mac_addr
);
1239 } else if (priv
->rx_addr_type
== 2) {
1240 emac_set_type2addr(priv
, ch
, mac_addr
, ch
, 1);
1241 emac_set_type0addr(priv
, ch
, mac_addr
);
1243 if (netif_msg_drv(priv
))
1244 dev_err(emac_dev
, "DaVinci EMAC: Wrong addressing\n");
1249 * emac_dev_setmac_addr - Set mac address in the adapter
1250 * @ndev: The DaVinci EMAC network adapter
1251 * @addr: MAC address to set in device
1253 * Called by the system to set the mac address of the adapter (Device)
1255 * Returns success (0) or appropriate error code (none as of now)
1257 static int emac_dev_setmac_addr(struct net_device
*ndev
, void *addr
)
1259 struct emac_priv
*priv
= netdev_priv(ndev
);
1260 struct device
*emac_dev
= &priv
->ndev
->dev
;
1261 struct sockaddr
*sa
= addr
;
1263 if (!is_valid_ether_addr(sa
->sa_data
))
1264 return -EADDRNOTAVAIL
;
1266 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1267 memcpy(priv
->mac_addr
, sa
->sa_data
, ndev
->addr_len
);
1268 memcpy(ndev
->dev_addr
, sa
->sa_data
, ndev
->addr_len
);
1270 /* MAC address is configured only after the interface is enabled. */
1271 if (netif_running(ndev
)) {
1272 emac_setmac(priv
, EMAC_DEF_RX_CH
, priv
->mac_addr
);
1275 if (netif_msg_drv(priv
))
1276 dev_notice(emac_dev
, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1283 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
1284 * @priv: The DaVinci EMAC private adapter structure
1286 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1287 * for packet reception and enables device interrupts and then NAPI
1289 * Returns success (0) or appropriate error code (none right now)
1291 static int emac_hw_enable(struct emac_priv
*priv
)
1293 u32 val
, mbp_enable
, mac_control
;
1296 emac_write(EMAC_SOFTRESET
, 1);
1297 while (emac_read(EMAC_SOFTRESET
))
1300 /* Disable interrupt & Set pacing for more interrupts initially */
1301 emac_int_disable(priv
);
1303 /* Full duplex enable bit set when auto negotiation happens */
1305 (((EMAC_DEF_TXPRIO_FIXED
) ? (EMAC_MACCONTROL_TXPTYPE
) : 0x0) |
1306 ((priv
->speed
== 1000) ? EMAC_MACCONTROL_GIGABITEN
: 0x0) |
1307 ((EMAC_DEF_TXPACING_EN
) ? (EMAC_MACCONTROL_TXPACEEN
) : 0x0) |
1308 ((priv
->duplex
== DUPLEX_FULL
) ? 0x1 : 0));
1309 emac_write(EMAC_MACCONTROL
, mac_control
);
1312 (((EMAC_DEF_PASS_CRC
) ? (EMAC_RXMBP_PASSCRC_MASK
) : 0x0) |
1313 ((EMAC_DEF_QOS_EN
) ? (EMAC_RXMBP_QOSEN_MASK
) : 0x0) |
1314 ((EMAC_DEF_NO_BUFF_CHAIN
) ? (EMAC_RXMBP_NOCHAIN_MASK
) : 0x0) |
1315 ((EMAC_DEF_MACCTRL_FRAME_EN
) ? (EMAC_RXMBP_CMFEN_MASK
) : 0x0) |
1316 ((EMAC_DEF_SHORT_FRAME_EN
) ? (EMAC_RXMBP_CSFEN_MASK
) : 0x0) |
1317 ((EMAC_DEF_ERROR_FRAME_EN
) ? (EMAC_RXMBP_CEFEN_MASK
) : 0x0) |
1318 ((EMAC_DEF_PROM_EN
) ? (EMAC_RXMBP_CAFEN_MASK
) : 0x0) |
1319 ((EMAC_DEF_PROM_CH
& EMAC_RXMBP_CHMASK
) << \
1320 EMAC_RXMBP_PROMCH_SHIFT
) |
1321 ((EMAC_DEF_BCAST_EN
) ? (EMAC_RXMBP_BROADEN_MASK
) : 0x0) |
1322 ((EMAC_DEF_BCAST_CH
& EMAC_RXMBP_CHMASK
) << \
1323 EMAC_RXMBP_BROADCH_SHIFT
) |
1324 ((EMAC_DEF_MCAST_EN
) ? (EMAC_RXMBP_MULTIEN_MASK
) : 0x0) |
1325 ((EMAC_DEF_MCAST_CH
& EMAC_RXMBP_CHMASK
) << \
1326 EMAC_RXMBP_MULTICH_SHIFT
));
1327 emac_write(EMAC_RXMBPENABLE
, mbp_enable
);
1328 emac_write(EMAC_RXMAXLEN
, (EMAC_DEF_MAX_FRAME_SIZE
&
1329 EMAC_RX_MAX_LEN_MASK
));
1330 emac_write(EMAC_RXBUFFEROFFSET
, (EMAC_DEF_BUFFER_OFFSET
&
1331 EMAC_RX_BUFFER_OFFSET_MASK
));
1332 emac_write(EMAC_RXFILTERLOWTHRESH
, 0);
1333 emac_write(EMAC_RXUNICASTCLEAR
, EMAC_RX_UNICAST_CLEAR_ALL
);
1334 priv
->rx_addr_type
= (emac_read(EMAC_MACCONFIG
) >> 8) & 0xFF;
1336 emac_write(EMAC_MACINTMASKSET
, EMAC_MAC_HOST_ERR_INTMASK_VAL
);
1338 emac_setmac(priv
, EMAC_DEF_RX_CH
, priv
->mac_addr
);
1341 val
= emac_read(EMAC_MACCONTROL
);
1342 val
|= (EMAC_MACCONTROL_GMIIEN
);
1343 emac_write(EMAC_MACCONTROL
, val
);
1345 /* Enable NAPI and interrupts */
1346 napi_enable(&priv
->napi
);
1347 emac_int_enable(priv
);
1353 * emac_poll - EMAC NAPI Poll function
1354 * @ndev: The DaVinci EMAC network adapter
1355 * @budget: Number of receive packets to process (as told by NAPI layer)
1357 * NAPI Poll function implemented to process packets as per budget. We check
1358 * the type of interrupt on the device and accordingly call the TX or RX
1359 * packet processing functions. We follow the budget for RX processing and
1360 * also put a cap on number of TX pkts processed through config param. The
1361 * NAPI schedule function is called if more packets pending.
1363 * Returns number of packets received (in most cases; else TX pkts - rarely)
1365 static int emac_poll(struct napi_struct
*napi
, int budget
)
1368 struct emac_priv
*priv
= container_of(napi
, struct emac_priv
, napi
);
1369 struct net_device
*ndev
= priv
->ndev
;
1370 struct device
*emac_dev
= &ndev
->dev
;
1372 u32 num_tx_pkts
= 0, num_rx_pkts
= 0;
1374 /* Check interrupt vectors and call packet processing */
1375 status
= emac_read(EMAC_MACINVECTOR
);
1377 mask
= EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC
;
1379 if (priv
->version
== EMAC_VERSION_2
)
1380 mask
= EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC
;
1382 if (status
& mask
) {
1383 num_tx_pkts
= cpdma_chan_process(priv
->txchan
,
1384 EMAC_DEF_TX_MAX_SERVICE
);
1385 } /* TX processing */
1387 mask
= EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC
;
1389 if (priv
->version
== EMAC_VERSION_2
)
1390 mask
= EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC
;
1392 if (status
& mask
) {
1393 num_rx_pkts
= cpdma_chan_process(priv
->rxchan
, budget
);
1394 } /* RX processing */
1396 mask
= EMAC_DM644X_MAC_IN_VECTOR_HOST_INT
;
1397 if (priv
->version
== EMAC_VERSION_2
)
1398 mask
= EMAC_DM646X_MAC_IN_VECTOR_HOST_INT
;
1400 if (unlikely(status
& mask
)) {
1402 dev_err(emac_dev
, "DaVinci EMAC: Fatal Hardware Error\n");
1403 netif_stop_queue(ndev
);
1404 napi_disable(&priv
->napi
);
1406 status
= emac_read(EMAC_MACSTATUS
);
1407 cause
= ((status
& EMAC_MACSTATUS_TXERRCODE_MASK
) >>
1408 EMAC_MACSTATUS_TXERRCODE_SHIFT
);
1410 ch
= ((status
& EMAC_MACSTATUS_TXERRCH_MASK
) >>
1411 EMAC_MACSTATUS_TXERRCH_SHIFT
);
1412 if (net_ratelimit()) {
1413 dev_err(emac_dev
, "TX Host error %s on ch=%d\n",
1414 &emac_txhost_errcodes
[cause
][0], ch
);
1417 cause
= ((status
& EMAC_MACSTATUS_RXERRCODE_MASK
) >>
1418 EMAC_MACSTATUS_RXERRCODE_SHIFT
);
1420 ch
= ((status
& EMAC_MACSTATUS_RXERRCH_MASK
) >>
1421 EMAC_MACSTATUS_RXERRCH_SHIFT
);
1422 if (netif_msg_hw(priv
) && net_ratelimit())
1423 dev_err(emac_dev
, "RX Host error %s on ch=%d\n",
1424 &emac_rxhost_errcodes
[cause
][0], ch
);
1426 } else if (num_rx_pkts
< budget
) {
1427 napi_complete(napi
);
1428 emac_int_enable(priv
);
1434 #ifdef CONFIG_NET_POLL_CONTROLLER
1436 * emac_poll_controller - EMAC Poll controller function
1437 * @ndev: The DaVinci EMAC network adapter
1439 * Polled functionality used by netconsole and others in non interrupt mode
1442 static void emac_poll_controller(struct net_device
*ndev
)
1444 struct emac_priv
*priv
= netdev_priv(ndev
);
1446 emac_int_disable(priv
);
1447 emac_irq(ndev
->irq
, ndev
);
1448 emac_int_enable(priv
);
1452 static void emac_adjust_link(struct net_device
*ndev
)
1454 struct emac_priv
*priv
= netdev_priv(ndev
);
1455 struct phy_device
*phydev
= priv
->phydev
;
1456 unsigned long flags
;
1459 spin_lock_irqsave(&priv
->lock
, flags
);
1462 /* check the mode of operation - full/half duplex */
1463 if (phydev
->duplex
!= priv
->duplex
) {
1465 priv
->duplex
= phydev
->duplex
;
1467 if (phydev
->speed
!= priv
->speed
) {
1469 priv
->speed
= phydev
->speed
;
1476 } else if (priv
->link
) {
1483 emac_update_phystatus(priv
);
1484 phy_print_status(priv
->phydev
);
1487 spin_unlock_irqrestore(&priv
->lock
, flags
);
1490 /*************************************************************************
1491 * Linux Driver Model
1492 *************************************************************************/
1495 * emac_devioctl - EMAC adapter ioctl
1496 * @ndev: The DaVinci EMAC network adapter
1497 * @ifrq: request parameter
1498 * @cmd: command parameter
1500 * EMAC driver ioctl function
1502 * Returns success(0) or appropriate error code
1504 static int emac_devioctl(struct net_device
*ndev
, struct ifreq
*ifrq
, int cmd
)
1506 struct emac_priv
*priv
= netdev_priv(ndev
);
1508 if (!(netif_running(ndev
)))
1511 /* TODO: Add phy read and write and private statistics get feature */
1513 return phy_mii_ioctl(priv
->phydev
, ifrq
, cmd
);
1516 static int match_first_device(struct device
*dev
, void *data
)
1518 return !strncmp(dev_name(dev
), "davinci_mdio", 12);
1522 * emac_dev_open - EMAC device open
1523 * @ndev: The DaVinci EMAC network adapter
1525 * Called when system wants to start the interface. We init TX/RX channels
1526 * and enable the hardware for packet reception/transmission and start the
1529 * Returns 0 for a successful open, or appropriate error code
1531 static int emac_dev_open(struct net_device
*ndev
)
1533 struct device
*emac_dev
= &ndev
->dev
;
1535 struct resource
*res
;
1537 int res_num
= 0, irq_num
= 0;
1539 struct emac_priv
*priv
= netdev_priv(ndev
);
1541 ret
= pm_runtime_get_sync(&priv
->pdev
->dev
);
1543 pm_runtime_put_noidle(&priv
->pdev
->dev
);
1544 dev_err(&priv
->pdev
->dev
, "%s: failed to get_sync(%d)\n",
1549 netif_carrier_off(ndev
);
1550 for (cnt
= 0; cnt
< ETH_ALEN
; cnt
++)
1551 ndev
->dev_addr
[cnt
] = priv
->mac_addr
[cnt
];
1553 /* Configuration items */
1554 priv
->rx_buf_size
= EMAC_DEF_MAX_FRAME_SIZE
+ NET_IP_ALIGN
;
1556 priv
->mac_hash1
= 0;
1557 priv
->mac_hash2
= 0;
1558 emac_write(EMAC_MACHASH1
, 0);
1559 emac_write(EMAC_MACHASH2
, 0);
1561 for (i
= 0; i
< EMAC_DEF_RX_NUM_DESC
; i
++) {
1562 struct sk_buff
*skb
= emac_rx_alloc(priv
);
1567 ret
= cpdma_chan_submit(priv
->rxchan
, skb
, skb
->data
,
1568 skb_tailroom(skb
), 0);
1569 if (WARN_ON(ret
< 0))
1574 while ((res
= platform_get_resource(priv
->pdev
, IORESOURCE_IRQ
,
1576 for (irq_num
= res
->start
; irq_num
<= res
->end
; irq_num
++) {
1577 if (request_irq(irq_num
, emac_irq
, 0, ndev
->name
,
1580 "DaVinci EMAC: request_irq() failed\n");
1588 /* prepare counters for rollback in case of an error */
1592 /* Start/Enable EMAC hardware */
1593 emac_hw_enable(priv
);
1595 /* Enable Interrupt pacing if configured */
1596 if (priv
->coal_intvl
!= 0) {
1597 struct ethtool_coalesce coal
;
1599 coal
.rx_coalesce_usecs
= (priv
->coal_intvl
<< 4);
1600 emac_set_coalesce(ndev
, &coal
);
1603 cpdma_ctlr_start(priv
->dma
);
1605 priv
->phydev
= NULL
;
1606 /* use the first phy on the bus if pdata did not give us a phy id */
1607 if (!priv
->phy_id
) {
1610 phy
= bus_find_device(&mdio_bus_type
, NULL
, NULL
,
1611 match_first_device
);
1613 priv
->phy_id
= dev_name(phy
);
1616 if (priv
->phy_id
&& *priv
->phy_id
) {
1617 priv
->phydev
= phy_connect(ndev
, priv
->phy_id
,
1619 PHY_INTERFACE_MODE_MII
);
1621 if (IS_ERR(priv
->phydev
)) {
1622 dev_err(emac_dev
, "could not connect to phy %s\n",
1624 ret
= PTR_ERR(priv
->phydev
);
1625 priv
->phydev
= NULL
;
1633 dev_info(emac_dev
, "attached PHY driver [%s] "
1634 "(mii_bus:phy_addr=%s, id=%x)\n",
1635 priv
->phydev
->drv
->name
, dev_name(&priv
->phydev
->dev
),
1636 priv
->phydev
->phy_id
);
1638 /* No PHY , fix the link, speed and duplex settings */
1639 dev_notice(emac_dev
, "no phy, defaulting to 100/full\n");
1641 priv
->speed
= SPEED_100
;
1642 priv
->duplex
= DUPLEX_FULL
;
1643 emac_update_phystatus(priv
);
1646 if (!netif_running(ndev
)) /* debug only - to avoid compiler warning */
1647 emac_dump_regs(priv
);
1649 if (netif_msg_drv(priv
))
1650 dev_notice(emac_dev
, "DaVinci EMAC: Opened %s\n", ndev
->name
);
1653 phy_start(priv
->phydev
);
1658 emac_int_disable(priv
);
1659 napi_disable(&priv
->napi
);
1662 for (q
= res_num
; q
>= 0; q
--) {
1663 res
= platform_get_resource(priv
->pdev
, IORESOURCE_IRQ
, q
);
1664 /* at the first iteration, irq_num is already set to the
1670 for (m
= irq_num
; m
>= res
->start
; m
--)
1673 cpdma_ctlr_stop(priv
->dma
);
1674 pm_runtime_put(&priv
->pdev
->dev
);
1679 * emac_dev_stop - EMAC device stop
1680 * @ndev: The DaVinci EMAC network adapter
1682 * Called when system wants to stop or down the interface. We stop the network
1683 * queue, disable interrupts and cleanup TX/RX channels.
1685 * We return the statistics in net_device_stats structure pulled from emac
1687 static int emac_dev_stop(struct net_device
*ndev
)
1689 struct resource
*res
;
1692 struct emac_priv
*priv
= netdev_priv(ndev
);
1693 struct device
*emac_dev
= &ndev
->dev
;
1695 /* inform the upper layers. */
1696 netif_stop_queue(ndev
);
1697 napi_disable(&priv
->napi
);
1699 netif_carrier_off(ndev
);
1700 emac_int_disable(priv
);
1701 cpdma_ctlr_stop(priv
->dma
);
1702 emac_write(EMAC_SOFTRESET
, 1);
1705 phy_disconnect(priv
->phydev
);
1708 while ((res
= platform_get_resource(priv
->pdev
, IORESOURCE_IRQ
, i
))) {
1709 for (irq_num
= res
->start
; irq_num
<= res
->end
; irq_num
++)
1710 free_irq(irq_num
, priv
->ndev
);
1714 if (netif_msg_drv(priv
))
1715 dev_notice(emac_dev
, "DaVinci EMAC: %s stopped\n", ndev
->name
);
1717 pm_runtime_put(&priv
->pdev
->dev
);
1722 * emac_dev_getnetstats - EMAC get statistics function
1723 * @ndev: The DaVinci EMAC network adapter
1725 * Called when system wants to get statistics from the device.
1727 * We return the statistics in net_device_stats structure pulled from emac
1729 static struct net_device_stats
*emac_dev_getnetstats(struct net_device
*ndev
)
1731 struct emac_priv
*priv
= netdev_priv(ndev
);
1733 u32 stats_clear_mask
;
1736 err
= pm_runtime_get_sync(&priv
->pdev
->dev
);
1738 pm_runtime_put_noidle(&priv
->pdev
->dev
);
1739 dev_err(&priv
->pdev
->dev
, "%s: failed to get_sync(%d)\n",
1741 return &ndev
->stats
;
1744 /* update emac hardware stats and reset the registers*/
1746 mac_control
= emac_read(EMAC_MACCONTROL
);
1748 if (mac_control
& EMAC_MACCONTROL_GMIIEN
)
1749 stats_clear_mask
= EMAC_STATS_CLR_MASK
;
1751 stats_clear_mask
= 0;
1753 ndev
->stats
.multicast
+= emac_read(EMAC_RXMCASTFRAMES
);
1754 emac_write(EMAC_RXMCASTFRAMES
, stats_clear_mask
);
1756 ndev
->stats
.collisions
+= (emac_read(EMAC_TXCOLLISION
) +
1757 emac_read(EMAC_TXSINGLECOLL
) +
1758 emac_read(EMAC_TXMULTICOLL
));
1759 emac_write(EMAC_TXCOLLISION
, stats_clear_mask
);
1760 emac_write(EMAC_TXSINGLECOLL
, stats_clear_mask
);
1761 emac_write(EMAC_TXMULTICOLL
, stats_clear_mask
);
1763 ndev
->stats
.rx_length_errors
+= (emac_read(EMAC_RXOVERSIZED
) +
1764 emac_read(EMAC_RXJABBER
) +
1765 emac_read(EMAC_RXUNDERSIZED
));
1766 emac_write(EMAC_RXOVERSIZED
, stats_clear_mask
);
1767 emac_write(EMAC_RXJABBER
, stats_clear_mask
);
1768 emac_write(EMAC_RXUNDERSIZED
, stats_clear_mask
);
1770 ndev
->stats
.rx_over_errors
+= (emac_read(EMAC_RXSOFOVERRUNS
) +
1771 emac_read(EMAC_RXMOFOVERRUNS
));
1772 emac_write(EMAC_RXSOFOVERRUNS
, stats_clear_mask
);
1773 emac_write(EMAC_RXMOFOVERRUNS
, stats_clear_mask
);
1775 ndev
->stats
.rx_fifo_errors
+= emac_read(EMAC_RXDMAOVERRUNS
);
1776 emac_write(EMAC_RXDMAOVERRUNS
, stats_clear_mask
);
1778 ndev
->stats
.tx_carrier_errors
+=
1779 emac_read(EMAC_TXCARRIERSENSE
);
1780 emac_write(EMAC_TXCARRIERSENSE
, stats_clear_mask
);
1782 ndev
->stats
.tx_fifo_errors
+= emac_read(EMAC_TXUNDERRUN
);
1783 emac_write(EMAC_TXUNDERRUN
, stats_clear_mask
);
1785 pm_runtime_put(&priv
->pdev
->dev
);
1787 return &ndev
->stats
;
1790 static const struct net_device_ops emac_netdev_ops
= {
1791 .ndo_open
= emac_dev_open
,
1792 .ndo_stop
= emac_dev_stop
,
1793 .ndo_start_xmit
= emac_dev_xmit
,
1794 .ndo_set_rx_mode
= emac_dev_mcast_set
,
1795 .ndo_set_mac_address
= emac_dev_setmac_addr
,
1796 .ndo_do_ioctl
= emac_devioctl
,
1797 .ndo_tx_timeout
= emac_dev_tx_timeout
,
1798 .ndo_get_stats
= emac_dev_getnetstats
,
1799 #ifdef CONFIG_NET_POLL_CONTROLLER
1800 .ndo_poll_controller
= emac_poll_controller
,
1804 static const struct of_device_id davinci_emac_of_match
[];
1806 static struct emac_platform_data
*
1807 davinci_emac_of_get_pdata(struct platform_device
*pdev
, struct emac_priv
*priv
)
1809 struct device_node
*np
;
1810 const struct of_device_id
*match
;
1811 const struct emac_platform_data
*auxdata
;
1812 struct emac_platform_data
*pdata
= NULL
;
1815 if (!IS_ENABLED(CONFIG_OF
) || !pdev
->dev
.of_node
)
1816 return dev_get_platdata(&pdev
->dev
);
1818 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1822 np
= pdev
->dev
.of_node
;
1823 pdata
->version
= EMAC_VERSION_2
;
1825 if (!is_valid_ether_addr(pdata
->mac_addr
)) {
1826 mac_addr
= of_get_mac_address(np
);
1828 memcpy(pdata
->mac_addr
, mac_addr
, ETH_ALEN
);
1831 of_property_read_u32(np
, "ti,davinci-ctrl-reg-offset",
1832 &pdata
->ctrl_reg_offset
);
1834 of_property_read_u32(np
, "ti,davinci-ctrl-mod-reg-offset",
1835 &pdata
->ctrl_mod_reg_offset
);
1837 of_property_read_u32(np
, "ti,davinci-ctrl-ram-offset",
1838 &pdata
->ctrl_ram_offset
);
1840 of_property_read_u32(np
, "ti,davinci-ctrl-ram-size",
1841 &pdata
->ctrl_ram_size
);
1843 of_property_read_u8(np
, "ti,davinci-rmii-en", &pdata
->rmii_en
);
1845 pdata
->no_bd_ram
= of_property_read_bool(np
, "ti,davinci-no-bd-ram");
1847 priv
->phy_node
= of_parse_phandle(np
, "phy-handle", 0);
1848 if (!priv
->phy_node
)
1849 pdata
->phy_id
= NULL
;
1851 auxdata
= pdev
->dev
.platform_data
;
1853 pdata
->interrupt_enable
= auxdata
->interrupt_enable
;
1854 pdata
->interrupt_disable
= auxdata
->interrupt_disable
;
1857 match
= of_match_device(davinci_emac_of_match
, &pdev
->dev
);
1858 if (match
&& match
->data
) {
1859 auxdata
= match
->data
;
1860 pdata
->version
= auxdata
->version
;
1861 pdata
->hw_ram_addr
= auxdata
->hw_ram_addr
;
1864 pdev
->dev
.platform_data
= pdata
;
1870 * davinci_emac_probe - EMAC device probe
1871 * @pdev: The DaVinci EMAC device that we are removing
1873 * Called when probing for emac devicesr. We get details of instances and
1874 * resource information from platform init and register a network device
1875 * and allocate resources necessary for driver to perform
1877 static int davinci_emac_probe(struct platform_device
*pdev
)
1880 struct resource
*res
;
1881 struct net_device
*ndev
;
1882 struct emac_priv
*priv
;
1883 unsigned long hw_ram_addr
;
1884 struct emac_platform_data
*pdata
;
1885 struct cpdma_params dma_params
;
1886 struct clk
*emac_clk
;
1887 unsigned long emac_bus_frequency
;
1890 /* obtain emac clock from kernel */
1891 emac_clk
= devm_clk_get(&pdev
->dev
, NULL
);
1892 if (IS_ERR(emac_clk
)) {
1893 dev_err(&pdev
->dev
, "failed to get EMAC clock\n");
1896 emac_bus_frequency
= clk_get_rate(emac_clk
);
1897 devm_clk_put(&pdev
->dev
, emac_clk
);
1899 /* TODO: Probe PHY here if possible */
1901 ndev
= alloc_etherdev(sizeof(struct emac_priv
));
1905 platform_set_drvdata(pdev
, ndev
);
1906 priv
= netdev_priv(ndev
);
1909 priv
->msg_enable
= netif_msg_init(debug_level
, DAVINCI_EMAC_DEBUG
);
1911 spin_lock_init(&priv
->lock
);
1913 pdata
= davinci_emac_of_get_pdata(pdev
, priv
);
1915 dev_err(&pdev
->dev
, "no platform data\n");
1920 /* MAC addr and PHY mask , RMII enable info from platform_data */
1921 memcpy(priv
->mac_addr
, pdata
->mac_addr
, ETH_ALEN
);
1922 priv
->phy_id
= pdata
->phy_id
;
1923 priv
->rmii_en
= pdata
->rmii_en
;
1924 priv
->version
= pdata
->version
;
1925 priv
->int_enable
= pdata
->interrupt_enable
;
1926 priv
->int_disable
= pdata
->interrupt_disable
;
1928 priv
->coal_intvl
= 0;
1929 priv
->bus_freq_mhz
= (u32
)(emac_bus_frequency
/ 1000000);
1931 /* Get EMAC platform data */
1932 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1933 priv
->emac_base_phys
= res
->start
+ pdata
->ctrl_reg_offset
;
1934 priv
->remap_addr
= devm_ioremap_resource(&pdev
->dev
, res
);
1935 if (IS_ERR(priv
->remap_addr
)) {
1936 rc
= PTR_ERR(priv
->remap_addr
);
1939 priv
->emac_base
= priv
->remap_addr
+ pdata
->ctrl_reg_offset
;
1940 ndev
->base_addr
= (unsigned long)priv
->remap_addr
;
1942 priv
->ctrl_base
= priv
->remap_addr
+ pdata
->ctrl_mod_reg_offset
;
1944 hw_ram_addr
= pdata
->hw_ram_addr
;
1946 hw_ram_addr
= (u32 __force
)res
->start
+ pdata
->ctrl_ram_offset
;
1948 memset(&dma_params
, 0, sizeof(dma_params
));
1949 dma_params
.dev
= &pdev
->dev
;
1950 dma_params
.dmaregs
= priv
->emac_base
;
1951 dma_params
.rxthresh
= priv
->emac_base
+ 0x120;
1952 dma_params
.rxfree
= priv
->emac_base
+ 0x140;
1953 dma_params
.txhdp
= priv
->emac_base
+ 0x600;
1954 dma_params
.rxhdp
= priv
->emac_base
+ 0x620;
1955 dma_params
.txcp
= priv
->emac_base
+ 0x640;
1956 dma_params
.rxcp
= priv
->emac_base
+ 0x660;
1957 dma_params
.num_chan
= EMAC_MAX_TXRX_CHANNELS
;
1958 dma_params
.min_packet_size
= EMAC_DEF_MIN_ETHPKTSIZE
;
1959 dma_params
.desc_hw_addr
= hw_ram_addr
;
1960 dma_params
.desc_mem_size
= pdata
->ctrl_ram_size
;
1961 dma_params
.desc_align
= 16;
1963 dma_params
.desc_mem_phys
= pdata
->no_bd_ram
? 0 :
1964 (u32 __force
)res
->start
+ pdata
->ctrl_ram_offset
;
1966 priv
->dma
= cpdma_ctlr_create(&dma_params
);
1968 dev_err(&pdev
->dev
, "error initializing DMA\n");
1973 priv
->txchan
= cpdma_chan_create(priv
->dma
, tx_chan_num(EMAC_DEF_TX_CH
),
1975 priv
->rxchan
= cpdma_chan_create(priv
->dma
, rx_chan_num(EMAC_DEF_RX_CH
),
1977 if (WARN_ON(!priv
->txchan
|| !priv
->rxchan
)) {
1982 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1984 dev_err(&pdev
->dev
, "error getting irq res\n");
1988 ndev
->irq
= res
->start
;
1990 if (!is_valid_ether_addr(priv
->mac_addr
)) {
1991 /* Use random MAC if none passed */
1992 eth_hw_addr_random(ndev
);
1993 memcpy(priv
->mac_addr
, ndev
->dev_addr
, ndev
->addr_len
);
1994 dev_warn(&pdev
->dev
, "using random MAC addr: %pM\n",
1998 ndev
->netdev_ops
= &emac_netdev_ops
;
1999 ndev
->ethtool_ops
= ðtool_ops
;
2000 netif_napi_add(ndev
, &priv
->napi
, emac_poll
, EMAC_POLL_WEIGHT
);
2002 pm_runtime_enable(&pdev
->dev
);
2003 rc
= pm_runtime_get_sync(&pdev
->dev
);
2005 pm_runtime_put_noidle(&pdev
->dev
);
2006 dev_err(&pdev
->dev
, "%s: failed to get_sync(%d)\n",
2011 /* register the network device */
2012 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2013 rc
= register_netdev(ndev
);
2015 dev_err(&pdev
->dev
, "error in register_netdev\n");
2017 pm_runtime_put(&pdev
->dev
);
2022 if (netif_msg_probe(priv
)) {
2023 dev_notice(&pdev
->dev
, "DaVinci EMAC Probe found device "
2024 "(regs: %p, irq: %d)\n",
2025 (void *)priv
->emac_base_phys
, ndev
->irq
);
2027 pm_runtime_put(&pdev
->dev
);
2033 cpdma_chan_destroy(priv
->txchan
);
2035 cpdma_chan_destroy(priv
->rxchan
);
2036 cpdma_ctlr_destroy(priv
->dma
);
2043 * davinci_emac_remove - EMAC device remove
2044 * @pdev: The DaVinci EMAC device that we are removing
2046 * Called when removing the device driver. We disable clock usage and release
2047 * the resources taken up by the driver and unregister network device
2049 static int davinci_emac_remove(struct platform_device
*pdev
)
2051 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2052 struct emac_priv
*priv
= netdev_priv(ndev
);
2054 dev_notice(&ndev
->dev
, "DaVinci EMAC: davinci_emac_remove()\n");
2057 cpdma_chan_destroy(priv
->txchan
);
2059 cpdma_chan_destroy(priv
->rxchan
);
2060 cpdma_ctlr_destroy(priv
->dma
);
2062 unregister_netdev(ndev
);
2068 static int davinci_emac_suspend(struct device
*dev
)
2070 struct platform_device
*pdev
= to_platform_device(dev
);
2071 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2073 if (netif_running(ndev
))
2074 emac_dev_stop(ndev
);
2079 static int davinci_emac_resume(struct device
*dev
)
2081 struct platform_device
*pdev
= to_platform_device(dev
);
2082 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2084 if (netif_running(ndev
))
2085 emac_dev_open(ndev
);
2090 static const struct dev_pm_ops davinci_emac_pm_ops
= {
2091 .suspend
= davinci_emac_suspend
,
2092 .resume
= davinci_emac_resume
,
2095 #if IS_ENABLED(CONFIG_OF)
2096 static const struct emac_platform_data am3517_emac_data
= {
2097 .version
= EMAC_VERSION_2
,
2098 .hw_ram_addr
= 0x01e20000,
2101 static const struct of_device_id davinci_emac_of_match
[] = {
2102 {.compatible
= "ti,davinci-dm6467-emac", },
2103 {.compatible
= "ti,am3517-emac", .data
= &am3517_emac_data
, },
2106 MODULE_DEVICE_TABLE(of
, davinci_emac_of_match
);
2109 /* davinci_emac_driver: EMAC platform driver structure */
2110 static struct platform_driver davinci_emac_driver
= {
2112 .name
= "davinci_emac",
2113 .pm
= &davinci_emac_pm_ops
,
2114 .of_match_table
= of_match_ptr(davinci_emac_of_match
),
2116 .probe
= davinci_emac_probe
,
2117 .remove
= davinci_emac_remove
,
2121 * davinci_emac_init - EMAC driver module init
2123 * Called when initializing the driver. We register the driver with
2126 static int __init
davinci_emac_init(void)
2128 return platform_driver_register(&davinci_emac_driver
);
2130 late_initcall(davinci_emac_init
);
2133 * davinci_emac_exit - EMAC driver module exit
2135 * Called when exiting the driver completely. We unregister the driver with
2136 * the platform and exit
2138 static void __exit
davinci_emac_exit(void)
2140 platform_driver_unregister(&davinci_emac_driver
);
2142 module_exit(davinci_emac_exit
);
2144 MODULE_LICENSE("GPL");
2145 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2146 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2147 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");