2 * Ethernet driver for the WIZnet W5100 chip.
4 * Copyright (C) 2006-2008 WIZnet Co.,Ltd.
5 * Copyright (C) 2012 Mike Sinkovsky <msink@permonline.ru>
7 * Licensed under the GPL-2 or later.
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/kconfig.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/platform_device.h>
16 #include <linux/platform_data/wiznet.h>
17 #include <linux/ethtool.h>
18 #include <linux/skbuff.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
25 #include <linux/ioport.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/gpio.h>
32 #define DRV_NAME "w5100"
33 #define DRV_VERSION "2012-04-04"
35 MODULE_DESCRIPTION("WIZnet W5100 Ethernet driver v"DRV_VERSION
);
36 MODULE_AUTHOR("Mike Sinkovsky <msink@permonline.ru>");
37 MODULE_ALIAS("platform:"DRV_NAME
);
38 MODULE_LICENSE("GPL");
41 * W5100/W5200/W5500 common registers
43 #define W5100_COMMON_REGS 0x0000
44 #define W5100_MR 0x0000 /* Mode Register */
45 #define MR_RST 0x80 /* S/W reset */
46 #define MR_PB 0x10 /* Ping block */
47 #define MR_AI 0x02 /* Address Auto-Increment */
48 #define MR_IND 0x01 /* Indirect mode */
49 #define W5100_SHAR 0x0009 /* Source MAC address */
50 #define W5100_IR 0x0015 /* Interrupt Register */
51 #define W5100_COMMON_REGS_LEN 0x0040
53 #define W5100_Sn_MR 0x0000 /* Sn Mode Register */
54 #define W5100_Sn_CR 0x0001 /* Sn Command Register */
55 #define W5100_Sn_IR 0x0002 /* Sn Interrupt Register */
56 #define W5100_Sn_SR 0x0003 /* Sn Status Register */
57 #define W5100_Sn_TX_FSR 0x0020 /* Sn Transmit free memory size */
58 #define W5100_Sn_TX_RD 0x0022 /* Sn Transmit memory read pointer */
59 #define W5100_Sn_TX_WR 0x0024 /* Sn Transmit memory write pointer */
60 #define W5100_Sn_RX_RSR 0x0026 /* Sn Receive free memory size */
61 #define W5100_Sn_RX_RD 0x0028 /* Sn Receive memory read pointer */
63 #define S0_REGS(priv) ((priv)->s0_regs)
65 #define W5100_S0_MR(priv) (S0_REGS(priv) + W5100_Sn_MR)
66 #define S0_MR_MACRAW 0x04 /* MAC RAW mode (promiscuous) */
67 #define S0_MR_MACRAW_MF 0x44 /* MAC RAW mode (filtered) */
68 #define W5100_S0_CR(priv) (S0_REGS(priv) + W5100_Sn_CR)
69 #define S0_CR_OPEN 0x01 /* OPEN command */
70 #define S0_CR_CLOSE 0x10 /* CLOSE command */
71 #define S0_CR_SEND 0x20 /* SEND command */
72 #define S0_CR_RECV 0x40 /* RECV command */
73 #define W5100_S0_IR(priv) (S0_REGS(priv) + W5100_Sn_IR)
74 #define S0_IR_SENDOK 0x10 /* complete sending */
75 #define S0_IR_RECV 0x04 /* receiving data */
76 #define W5100_S0_SR(priv) (S0_REGS(priv) + W5100_Sn_SR)
77 #define S0_SR_MACRAW 0x42 /* mac raw mode */
78 #define W5100_S0_TX_FSR(priv) (S0_REGS(priv) + W5100_Sn_TX_FSR)
79 #define W5100_S0_TX_RD(priv) (S0_REGS(priv) + W5100_Sn_TX_RD)
80 #define W5100_S0_TX_WR(priv) (S0_REGS(priv) + W5100_Sn_TX_WR)
81 #define W5100_S0_RX_RSR(priv) (S0_REGS(priv) + W5100_Sn_RX_RSR)
82 #define W5100_S0_RX_RD(priv) (S0_REGS(priv) + W5100_Sn_RX_RD)
84 #define W5100_S0_REGS_LEN 0x0040
87 * W5100 and W5200 common registers
89 #define W5100_IMR 0x0016 /* Interrupt Mask Register */
90 #define IR_S0 0x01 /* S0 interrupt */
91 #define W5100_RTR 0x0017 /* Retry Time-value Register */
92 #define RTR_DEFAULT 2000 /* =0x07d0 (2000) */
95 * W5100 specific register and memory
97 #define W5100_RMSR 0x001a /* Receive Memory Size */
98 #define W5100_TMSR 0x001b /* Transmit Memory Size */
100 #define W5100_S0_REGS 0x0400
102 #define W5100_TX_MEM_START 0x4000
103 #define W5100_TX_MEM_SIZE 0x2000
104 #define W5100_RX_MEM_START 0x6000
105 #define W5100_RX_MEM_SIZE 0x2000
108 * W5200 specific register and memory
110 #define W5200_S0_REGS 0x4000
112 #define W5200_Sn_RXMEM_SIZE(n) (0x401e + (n) * 0x0100) /* Sn RX Memory Size */
113 #define W5200_Sn_TXMEM_SIZE(n) (0x401f + (n) * 0x0100) /* Sn TX Memory Size */
115 #define W5200_TX_MEM_START 0x8000
116 #define W5200_TX_MEM_SIZE 0x4000
117 #define W5200_RX_MEM_START 0xc000
118 #define W5200_RX_MEM_SIZE 0x4000
121 * W5500 specific register and memory
123 * W5500 register and memory are organized by multiple blocks. Each one is
124 * selected by 16bits offset address and 5bits block select bits. So we
125 * encode it into 32bits address. (lower 16bits is offset address and
126 * upper 16bits is block select bits)
128 #define W5500_SIMR 0x0018 /* Socket Interrupt Mask Register */
129 #define W5500_RTR 0x0019 /* Retry Time-value Register */
131 #define W5500_S0_REGS 0x10000
133 #define W5500_Sn_RXMEM_SIZE(n) \
134 (0x1001e + (n) * 0x40000) /* Sn RX Memory Size */
135 #define W5500_Sn_TXMEM_SIZE(n) \
136 (0x1001f + (n) * 0x40000) /* Sn TX Memory Size */
138 #define W5500_TX_MEM_START 0x20000
139 #define W5500_TX_MEM_SIZE 0x04000
140 #define W5500_RX_MEM_START 0x30000
141 #define W5500_RX_MEM_SIZE 0x04000
144 * Device driver private data structure
148 const struct w5100_ops
*ops
;
150 /* Socket 0 register offset address */
152 /* Socket 0 TX buffer offset address and size */
155 /* Socket 0 RX buffer offset address and size */
163 struct napi_struct napi
;
164 struct net_device
*ndev
;
168 struct workqueue_struct
*xfer_wq
;
169 struct work_struct rx_work
;
170 struct sk_buff
*tx_skb
;
171 struct work_struct tx_work
;
172 struct work_struct setrx_work
;
173 struct work_struct restart_work
;
176 static inline bool is_w5200(struct w5100_priv
*priv
)
178 return priv
->ops
->chip_id
== W5200
;
181 /************************************************************************
183 * Lowlevel I/O functions
185 ***********************************************************************/
187 struct w5100_mmio_priv
{
189 /* Serialize access in indirect address mode */
193 static inline struct w5100_mmio_priv
*w5100_mmio_priv(struct net_device
*dev
)
195 return w5100_ops_priv(dev
);
198 static inline void __iomem
*w5100_mmio(struct net_device
*ndev
)
200 struct w5100_mmio_priv
*mmio_priv
= w5100_mmio_priv(ndev
);
202 return mmio_priv
->base
;
206 * In direct address mode host system can directly access W5100 registers
207 * after mapping to Memory-Mapped I/O space.
209 * 0x8000 bytes are required for memory space.
211 static inline int w5100_read_direct(struct net_device
*ndev
, u32 addr
)
213 return ioread8(w5100_mmio(ndev
) + (addr
<< CONFIG_WIZNET_BUS_SHIFT
));
216 static inline int __w5100_write_direct(struct net_device
*ndev
, u32 addr
,
219 iowrite8(data
, w5100_mmio(ndev
) + (addr
<< CONFIG_WIZNET_BUS_SHIFT
));
224 static inline int w5100_write_direct(struct net_device
*ndev
, u32 addr
, u8 data
)
226 __w5100_write_direct(ndev
, addr
, data
);
232 static int w5100_read16_direct(struct net_device
*ndev
, u32 addr
)
235 data
= w5100_read_direct(ndev
, addr
) << 8;
236 data
|= w5100_read_direct(ndev
, addr
+ 1);
240 static int w5100_write16_direct(struct net_device
*ndev
, u32 addr
, u16 data
)
242 __w5100_write_direct(ndev
, addr
, data
>> 8);
243 __w5100_write_direct(ndev
, addr
+ 1, data
);
249 static int w5100_readbulk_direct(struct net_device
*ndev
, u32 addr
, u8
*buf
,
254 for (i
= 0; i
< len
; i
++, addr
++)
255 *buf
++ = w5100_read_direct(ndev
, addr
);
260 static int w5100_writebulk_direct(struct net_device
*ndev
, u32 addr
,
261 const u8
*buf
, int len
)
265 for (i
= 0; i
< len
; i
++, addr
++)
266 __w5100_write_direct(ndev
, addr
, *buf
++);
273 static int w5100_mmio_init(struct net_device
*ndev
)
275 struct platform_device
*pdev
= to_platform_device(ndev
->dev
.parent
);
276 struct w5100_priv
*priv
= netdev_priv(ndev
);
277 struct w5100_mmio_priv
*mmio_priv
= w5100_mmio_priv(ndev
);
278 struct resource
*mem
;
280 spin_lock_init(&mmio_priv
->reg_lock
);
282 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
283 mmio_priv
->base
= devm_ioremap_resource(&pdev
->dev
, mem
);
284 if (IS_ERR(mmio_priv
->base
))
285 return PTR_ERR(mmio_priv
->base
);
287 netdev_info(ndev
, "at 0x%llx irq %d\n", (u64
)mem
->start
, priv
->irq
);
292 static const struct w5100_ops w5100_mmio_direct_ops
= {
294 .read
= w5100_read_direct
,
295 .write
= w5100_write_direct
,
296 .read16
= w5100_read16_direct
,
297 .write16
= w5100_write16_direct
,
298 .readbulk
= w5100_readbulk_direct
,
299 .writebulk
= w5100_writebulk_direct
,
300 .init
= w5100_mmio_init
,
304 * In indirect address mode host system indirectly accesses registers by
305 * using Indirect Mode Address Register (IDM_AR) and Indirect Mode Data
306 * Register (IDM_DR), which are directly mapped to Memory-Mapped I/O space.
307 * Mode Register (MR) is directly accessible.
309 * Only 0x04 bytes are required for memory space.
311 #define W5100_IDM_AR 0x01 /* Indirect Mode Address Register */
312 #define W5100_IDM_DR 0x03 /* Indirect Mode Data Register */
314 static int w5100_read_indirect(struct net_device
*ndev
, u32 addr
)
316 struct w5100_mmio_priv
*mmio_priv
= w5100_mmio_priv(ndev
);
320 spin_lock_irqsave(&mmio_priv
->reg_lock
, flags
);
321 w5100_write16_direct(ndev
, W5100_IDM_AR
, addr
);
322 data
= w5100_read_direct(ndev
, W5100_IDM_DR
);
323 spin_unlock_irqrestore(&mmio_priv
->reg_lock
, flags
);
328 static int w5100_write_indirect(struct net_device
*ndev
, u32 addr
, u8 data
)
330 struct w5100_mmio_priv
*mmio_priv
= w5100_mmio_priv(ndev
);
333 spin_lock_irqsave(&mmio_priv
->reg_lock
, flags
);
334 w5100_write16_direct(ndev
, W5100_IDM_AR
, addr
);
335 w5100_write_direct(ndev
, W5100_IDM_DR
, data
);
336 spin_unlock_irqrestore(&mmio_priv
->reg_lock
, flags
);
341 static int w5100_read16_indirect(struct net_device
*ndev
, u32 addr
)
343 struct w5100_mmio_priv
*mmio_priv
= w5100_mmio_priv(ndev
);
347 spin_lock_irqsave(&mmio_priv
->reg_lock
, flags
);
348 w5100_write16_direct(ndev
, W5100_IDM_AR
, addr
);
349 data
= w5100_read_direct(ndev
, W5100_IDM_DR
) << 8;
350 data
|= w5100_read_direct(ndev
, W5100_IDM_DR
);
351 spin_unlock_irqrestore(&mmio_priv
->reg_lock
, flags
);
356 static int w5100_write16_indirect(struct net_device
*ndev
, u32 addr
, u16 data
)
358 struct w5100_mmio_priv
*mmio_priv
= w5100_mmio_priv(ndev
);
361 spin_lock_irqsave(&mmio_priv
->reg_lock
, flags
);
362 w5100_write16_direct(ndev
, W5100_IDM_AR
, addr
);
363 __w5100_write_direct(ndev
, W5100_IDM_DR
, data
>> 8);
364 w5100_write_direct(ndev
, W5100_IDM_DR
, data
);
365 spin_unlock_irqrestore(&mmio_priv
->reg_lock
, flags
);
370 static int w5100_readbulk_indirect(struct net_device
*ndev
, u32 addr
, u8
*buf
,
373 struct w5100_mmio_priv
*mmio_priv
= w5100_mmio_priv(ndev
);
377 spin_lock_irqsave(&mmio_priv
->reg_lock
, flags
);
378 w5100_write16_direct(ndev
, W5100_IDM_AR
, addr
);
380 for (i
= 0; i
< len
; i
++)
381 *buf
++ = w5100_read_direct(ndev
, W5100_IDM_DR
);
384 spin_unlock_irqrestore(&mmio_priv
->reg_lock
, flags
);
389 static int w5100_writebulk_indirect(struct net_device
*ndev
, u32 addr
,
390 const u8
*buf
, int len
)
392 struct w5100_mmio_priv
*mmio_priv
= w5100_mmio_priv(ndev
);
396 spin_lock_irqsave(&mmio_priv
->reg_lock
, flags
);
397 w5100_write16_direct(ndev
, W5100_IDM_AR
, addr
);
399 for (i
= 0; i
< len
; i
++)
400 __w5100_write_direct(ndev
, W5100_IDM_DR
, *buf
++);
403 spin_unlock_irqrestore(&mmio_priv
->reg_lock
, flags
);
408 static int w5100_reset_indirect(struct net_device
*ndev
)
410 w5100_write_direct(ndev
, W5100_MR
, MR_RST
);
412 w5100_write_direct(ndev
, W5100_MR
, MR_PB
| MR_AI
| MR_IND
);
417 static const struct w5100_ops w5100_mmio_indirect_ops
= {
419 .read
= w5100_read_indirect
,
420 .write
= w5100_write_indirect
,
421 .read16
= w5100_read16_indirect
,
422 .write16
= w5100_write16_indirect
,
423 .readbulk
= w5100_readbulk_indirect
,
424 .writebulk
= w5100_writebulk_indirect
,
425 .init
= w5100_mmio_init
,
426 .reset
= w5100_reset_indirect
,
429 #if defined(CONFIG_WIZNET_BUS_DIRECT)
431 static int w5100_read(struct w5100_priv
*priv
, u32 addr
)
433 return w5100_read_direct(priv
->ndev
, addr
);
436 static int w5100_write(struct w5100_priv
*priv
, u32 addr
, u8 data
)
438 return w5100_write_direct(priv
->ndev
, addr
, data
);
441 static int w5100_read16(struct w5100_priv
*priv
, u32 addr
)
443 return w5100_read16_direct(priv
->ndev
, addr
);
446 static int w5100_write16(struct w5100_priv
*priv
, u32 addr
, u16 data
)
448 return w5100_write16_direct(priv
->ndev
, addr
, data
);
451 static int w5100_readbulk(struct w5100_priv
*priv
, u32 addr
, u8
*buf
, int len
)
453 return w5100_readbulk_direct(priv
->ndev
, addr
, buf
, len
);
456 static int w5100_writebulk(struct w5100_priv
*priv
, u32 addr
, const u8
*buf
,
459 return w5100_writebulk_direct(priv
->ndev
, addr
, buf
, len
);
462 #elif defined(CONFIG_WIZNET_BUS_INDIRECT)
464 static int w5100_read(struct w5100_priv
*priv
, u32 addr
)
466 return w5100_read_indirect(priv
->ndev
, addr
);
469 static int w5100_write(struct w5100_priv
*priv
, u32 addr
, u8 data
)
471 return w5100_write_indirect(priv
->ndev
, addr
, data
);
474 static int w5100_read16(struct w5100_priv
*priv
, u32 addr
)
476 return w5100_read16_indirect(priv
->ndev
, addr
);
479 static int w5100_write16(struct w5100_priv
*priv
, u32 addr
, u16 data
)
481 return w5100_write16_indirect(priv
->ndev
, addr
, data
);
484 static int w5100_readbulk(struct w5100_priv
*priv
, u32 addr
, u8
*buf
, int len
)
486 return w5100_readbulk_indirect(priv
->ndev
, addr
, buf
, len
);
489 static int w5100_writebulk(struct w5100_priv
*priv
, u32 addr
, const u8
*buf
,
492 return w5100_writebulk_indirect(priv
->ndev
, addr
, buf
, len
);
495 #else /* CONFIG_WIZNET_BUS_ANY */
497 static int w5100_read(struct w5100_priv
*priv
, u32 addr
)
499 return priv
->ops
->read(priv
->ndev
, addr
);
502 static int w5100_write(struct w5100_priv
*priv
, u32 addr
, u8 data
)
504 return priv
->ops
->write(priv
->ndev
, addr
, data
);
507 static int w5100_read16(struct w5100_priv
*priv
, u32 addr
)
509 return priv
->ops
->read16(priv
->ndev
, addr
);
512 static int w5100_write16(struct w5100_priv
*priv
, u32 addr
, u16 data
)
514 return priv
->ops
->write16(priv
->ndev
, addr
, data
);
517 static int w5100_readbulk(struct w5100_priv
*priv
, u32 addr
, u8
*buf
, int len
)
519 return priv
->ops
->readbulk(priv
->ndev
, addr
, buf
, len
);
522 static int w5100_writebulk(struct w5100_priv
*priv
, u32 addr
, const u8
*buf
,
525 return priv
->ops
->writebulk(priv
->ndev
, addr
, buf
, len
);
530 static int w5100_readbuf(struct w5100_priv
*priv
, u16 offset
, u8
*buf
, int len
)
535 const u32 mem_start
= priv
->s0_rx_buf
;
536 const u16 mem_size
= priv
->s0_rx_buf_size
;
539 addr
= mem_start
+ offset
;
541 if (offset
+ len
> mem_size
) {
542 remain
= (offset
+ len
) % mem_size
;
543 len
= mem_size
- offset
;
546 ret
= w5100_readbulk(priv
, addr
, buf
, len
);
550 return w5100_readbulk(priv
, mem_start
, buf
+ len
, remain
);
553 static int w5100_writebuf(struct w5100_priv
*priv
, u16 offset
, const u8
*buf
,
559 const u32 mem_start
= priv
->s0_tx_buf
;
560 const u16 mem_size
= priv
->s0_tx_buf_size
;
563 addr
= mem_start
+ offset
;
565 if (offset
+ len
> mem_size
) {
566 remain
= (offset
+ len
) % mem_size
;
567 len
= mem_size
- offset
;
570 ret
= w5100_writebulk(priv
, addr
, buf
, len
);
574 return w5100_writebulk(priv
, mem_start
, buf
+ len
, remain
);
577 static int w5100_reset(struct w5100_priv
*priv
)
579 if (priv
->ops
->reset
)
580 return priv
->ops
->reset(priv
->ndev
);
582 w5100_write(priv
, W5100_MR
, MR_RST
);
584 w5100_write(priv
, W5100_MR
, MR_PB
);
589 static int w5100_command(struct w5100_priv
*priv
, u16 cmd
)
591 unsigned long timeout
;
593 w5100_write(priv
, W5100_S0_CR(priv
), cmd
);
595 timeout
= jiffies
+ msecs_to_jiffies(100);
597 while (w5100_read(priv
, W5100_S0_CR(priv
)) != 0) {
598 if (time_after(jiffies
, timeout
))
606 static void w5100_write_macaddr(struct w5100_priv
*priv
)
608 struct net_device
*ndev
= priv
->ndev
;
610 w5100_writebulk(priv
, W5100_SHAR
, ndev
->dev_addr
, ETH_ALEN
);
613 static void w5100_socket_intr_mask(struct w5100_priv
*priv
, u8 mask
)
617 if (priv
->ops
->chip_id
== W5500
)
622 w5100_write(priv
, imr
, mask
);
625 static void w5100_enable_intr(struct w5100_priv
*priv
)
627 w5100_socket_intr_mask(priv
, IR_S0
);
630 static void w5100_disable_intr(struct w5100_priv
*priv
)
632 w5100_socket_intr_mask(priv
, 0);
635 static void w5100_memory_configure(struct w5100_priv
*priv
)
637 /* Configure 16K of internal memory
638 * as 8K RX buffer and 8K TX buffer
640 w5100_write(priv
, W5100_RMSR
, 0x03);
641 w5100_write(priv
, W5100_TMSR
, 0x03);
644 static void w5200_memory_configure(struct w5100_priv
*priv
)
648 /* Configure internal RX memory as 16K RX buffer and
649 * internal TX memory as 16K TX buffer
651 w5100_write(priv
, W5200_Sn_RXMEM_SIZE(0), 0x10);
652 w5100_write(priv
, W5200_Sn_TXMEM_SIZE(0), 0x10);
654 for (i
= 1; i
< 8; i
++) {
655 w5100_write(priv
, W5200_Sn_RXMEM_SIZE(i
), 0);
656 w5100_write(priv
, W5200_Sn_TXMEM_SIZE(i
), 0);
660 static void w5500_memory_configure(struct w5100_priv
*priv
)
664 /* Configure internal RX memory as 16K RX buffer and
665 * internal TX memory as 16K TX buffer
667 w5100_write(priv
, W5500_Sn_RXMEM_SIZE(0), 0x10);
668 w5100_write(priv
, W5500_Sn_TXMEM_SIZE(0), 0x10);
670 for (i
= 1; i
< 8; i
++) {
671 w5100_write(priv
, W5500_Sn_RXMEM_SIZE(i
), 0);
672 w5100_write(priv
, W5500_Sn_TXMEM_SIZE(i
), 0);
676 static int w5100_hw_reset(struct w5100_priv
*priv
)
682 w5100_disable_intr(priv
);
683 w5100_write_macaddr(priv
);
685 switch (priv
->ops
->chip_id
) {
687 w5100_memory_configure(priv
);
691 w5200_memory_configure(priv
);
695 w5500_memory_configure(priv
);
702 if (w5100_read16(priv
, rtr
) != RTR_DEFAULT
)
708 static void w5100_hw_start(struct w5100_priv
*priv
)
710 w5100_write(priv
, W5100_S0_MR(priv
), priv
->promisc
?
711 S0_MR_MACRAW
: S0_MR_MACRAW_MF
);
712 w5100_command(priv
, S0_CR_OPEN
);
713 w5100_enable_intr(priv
);
716 static void w5100_hw_close(struct w5100_priv
*priv
)
718 w5100_disable_intr(priv
);
719 w5100_command(priv
, S0_CR_CLOSE
);
722 /***********************************************************************
724 * Device driver functions / callbacks
726 ***********************************************************************/
728 static void w5100_get_drvinfo(struct net_device
*ndev
,
729 struct ethtool_drvinfo
*info
)
731 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
732 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
733 strlcpy(info
->bus_info
, dev_name(ndev
->dev
.parent
),
734 sizeof(info
->bus_info
));
737 static u32
w5100_get_link(struct net_device
*ndev
)
739 struct w5100_priv
*priv
= netdev_priv(ndev
);
741 if (gpio_is_valid(priv
->link_gpio
))
742 return !!gpio_get_value(priv
->link_gpio
);
747 static u32
w5100_get_msglevel(struct net_device
*ndev
)
749 struct w5100_priv
*priv
= netdev_priv(ndev
);
751 return priv
->msg_enable
;
754 static void w5100_set_msglevel(struct net_device
*ndev
, u32 value
)
756 struct w5100_priv
*priv
= netdev_priv(ndev
);
758 priv
->msg_enable
= value
;
761 static int w5100_get_regs_len(struct net_device
*ndev
)
763 return W5100_COMMON_REGS_LEN
+ W5100_S0_REGS_LEN
;
766 static void w5100_get_regs(struct net_device
*ndev
,
767 struct ethtool_regs
*regs
, void *buf
)
769 struct w5100_priv
*priv
= netdev_priv(ndev
);
772 w5100_readbulk(priv
, W5100_COMMON_REGS
, buf
, W5100_COMMON_REGS_LEN
);
773 buf
+= W5100_COMMON_REGS_LEN
;
774 w5100_readbulk(priv
, S0_REGS(priv
), buf
, W5100_S0_REGS_LEN
);
777 static void w5100_restart(struct net_device
*ndev
)
779 struct w5100_priv
*priv
= netdev_priv(ndev
);
781 netif_stop_queue(ndev
);
782 w5100_hw_reset(priv
);
783 w5100_hw_start(priv
);
784 ndev
->stats
.tx_errors
++;
785 ndev
->trans_start
= jiffies
;
786 netif_wake_queue(ndev
);
789 static void w5100_restart_work(struct work_struct
*work
)
791 struct w5100_priv
*priv
= container_of(work
, struct w5100_priv
,
794 w5100_restart(priv
->ndev
);
797 static void w5100_tx_timeout(struct net_device
*ndev
)
799 struct w5100_priv
*priv
= netdev_priv(ndev
);
801 if (priv
->ops
->may_sleep
)
802 schedule_work(&priv
->restart_work
);
807 static void w5100_tx_skb(struct net_device
*ndev
, struct sk_buff
*skb
)
809 struct w5100_priv
*priv
= netdev_priv(ndev
);
812 offset
= w5100_read16(priv
, W5100_S0_TX_WR(priv
));
813 w5100_writebuf(priv
, offset
, skb
->data
, skb
->len
);
814 w5100_write16(priv
, W5100_S0_TX_WR(priv
), offset
+ skb
->len
);
815 ndev
->stats
.tx_bytes
+= skb
->len
;
816 ndev
->stats
.tx_packets
++;
819 w5100_command(priv
, S0_CR_SEND
);
822 static void w5100_tx_work(struct work_struct
*work
)
824 struct w5100_priv
*priv
= container_of(work
, struct w5100_priv
,
826 struct sk_buff
*skb
= priv
->tx_skb
;
832 w5100_tx_skb(priv
->ndev
, skb
);
835 static int w5100_start_tx(struct sk_buff
*skb
, struct net_device
*ndev
)
837 struct w5100_priv
*priv
= netdev_priv(ndev
);
839 netif_stop_queue(ndev
);
841 if (priv
->ops
->may_sleep
) {
842 WARN_ON(priv
->tx_skb
);
844 queue_work(priv
->xfer_wq
, &priv
->tx_work
);
846 w5100_tx_skb(ndev
, skb
);
852 static struct sk_buff
*w5100_rx_skb(struct net_device
*ndev
)
854 struct w5100_priv
*priv
= netdev_priv(ndev
);
859 u16 rx_buf_len
= w5100_read16(priv
, W5100_S0_RX_RSR(priv
));
864 offset
= w5100_read16(priv
, W5100_S0_RX_RD(priv
));
865 w5100_readbuf(priv
, offset
, header
, 2);
866 rx_len
= get_unaligned_be16(header
) - 2;
868 skb
= netdev_alloc_skb_ip_align(ndev
, rx_len
);
869 if (unlikely(!skb
)) {
870 w5100_write16(priv
, W5100_S0_RX_RD(priv
), offset
+ rx_buf_len
);
871 w5100_command(priv
, S0_CR_RECV
);
872 ndev
->stats
.rx_dropped
++;
876 skb_put(skb
, rx_len
);
877 w5100_readbuf(priv
, offset
+ 2, skb
->data
, rx_len
);
878 w5100_write16(priv
, W5100_S0_RX_RD(priv
), offset
+ 2 + rx_len
);
879 w5100_command(priv
, S0_CR_RECV
);
880 skb
->protocol
= eth_type_trans(skb
, ndev
);
882 ndev
->stats
.rx_packets
++;
883 ndev
->stats
.rx_bytes
+= rx_len
;
888 static void w5100_rx_work(struct work_struct
*work
)
890 struct w5100_priv
*priv
= container_of(work
, struct w5100_priv
,
894 while ((skb
= w5100_rx_skb(priv
->ndev
)))
897 w5100_enable_intr(priv
);
900 static int w5100_napi_poll(struct napi_struct
*napi
, int budget
)
902 struct w5100_priv
*priv
= container_of(napi
, struct w5100_priv
, napi
);
905 for (rx_count
= 0; rx_count
< budget
; rx_count
++) {
906 struct sk_buff
*skb
= w5100_rx_skb(priv
->ndev
);
909 netif_receive_skb(skb
);
914 if (rx_count
< budget
) {
916 w5100_enable_intr(priv
);
922 static irqreturn_t
w5100_interrupt(int irq
, void *ndev_instance
)
924 struct net_device
*ndev
= ndev_instance
;
925 struct w5100_priv
*priv
= netdev_priv(ndev
);
927 int ir
= w5100_read(priv
, W5100_S0_IR(priv
));
930 w5100_write(priv
, W5100_S0_IR(priv
), ir
);
932 if (ir
& S0_IR_SENDOK
) {
933 netif_dbg(priv
, tx_done
, ndev
, "tx done\n");
934 netif_wake_queue(ndev
);
937 if (ir
& S0_IR_RECV
) {
938 w5100_disable_intr(priv
);
940 if (priv
->ops
->may_sleep
)
941 queue_work(priv
->xfer_wq
, &priv
->rx_work
);
942 else if (napi_schedule_prep(&priv
->napi
))
943 __napi_schedule(&priv
->napi
);
949 static irqreturn_t
w5100_detect_link(int irq
, void *ndev_instance
)
951 struct net_device
*ndev
= ndev_instance
;
952 struct w5100_priv
*priv
= netdev_priv(ndev
);
954 if (netif_running(ndev
)) {
955 if (gpio_get_value(priv
->link_gpio
) != 0) {
956 netif_info(priv
, link
, ndev
, "link is up\n");
957 netif_carrier_on(ndev
);
959 netif_info(priv
, link
, ndev
, "link is down\n");
960 netif_carrier_off(ndev
);
967 static void w5100_setrx_work(struct work_struct
*work
)
969 struct w5100_priv
*priv
= container_of(work
, struct w5100_priv
,
972 w5100_hw_start(priv
);
975 static void w5100_set_rx_mode(struct net_device
*ndev
)
977 struct w5100_priv
*priv
= netdev_priv(ndev
);
978 bool set_promisc
= (ndev
->flags
& IFF_PROMISC
) != 0;
980 if (priv
->promisc
!= set_promisc
) {
981 priv
->promisc
= set_promisc
;
983 if (priv
->ops
->may_sleep
)
984 schedule_work(&priv
->setrx_work
);
986 w5100_hw_start(priv
);
990 static int w5100_set_macaddr(struct net_device
*ndev
, void *addr
)
992 struct w5100_priv
*priv
= netdev_priv(ndev
);
993 struct sockaddr
*sock_addr
= addr
;
995 if (!is_valid_ether_addr(sock_addr
->sa_data
))
996 return -EADDRNOTAVAIL
;
997 memcpy(ndev
->dev_addr
, sock_addr
->sa_data
, ETH_ALEN
);
998 w5100_write_macaddr(priv
);
1002 static int w5100_open(struct net_device
*ndev
)
1004 struct w5100_priv
*priv
= netdev_priv(ndev
);
1006 netif_info(priv
, ifup
, ndev
, "enabling\n");
1007 w5100_hw_start(priv
);
1008 napi_enable(&priv
->napi
);
1009 netif_start_queue(ndev
);
1010 if (!gpio_is_valid(priv
->link_gpio
) ||
1011 gpio_get_value(priv
->link_gpio
) != 0)
1012 netif_carrier_on(ndev
);
1016 static int w5100_stop(struct net_device
*ndev
)
1018 struct w5100_priv
*priv
= netdev_priv(ndev
);
1020 netif_info(priv
, ifdown
, ndev
, "shutting down\n");
1021 w5100_hw_close(priv
);
1022 netif_carrier_off(ndev
);
1023 netif_stop_queue(ndev
);
1024 napi_disable(&priv
->napi
);
1028 static const struct ethtool_ops w5100_ethtool_ops
= {
1029 .get_drvinfo
= w5100_get_drvinfo
,
1030 .get_msglevel
= w5100_get_msglevel
,
1031 .set_msglevel
= w5100_set_msglevel
,
1032 .get_link
= w5100_get_link
,
1033 .get_regs_len
= w5100_get_regs_len
,
1034 .get_regs
= w5100_get_regs
,
1037 static const struct net_device_ops w5100_netdev_ops
= {
1038 .ndo_open
= w5100_open
,
1039 .ndo_stop
= w5100_stop
,
1040 .ndo_start_xmit
= w5100_start_tx
,
1041 .ndo_tx_timeout
= w5100_tx_timeout
,
1042 .ndo_set_rx_mode
= w5100_set_rx_mode
,
1043 .ndo_set_mac_address
= w5100_set_macaddr
,
1044 .ndo_validate_addr
= eth_validate_addr
,
1045 .ndo_change_mtu
= eth_change_mtu
,
1048 static int w5100_mmio_probe(struct platform_device
*pdev
)
1050 struct wiznet_platform_data
*data
= dev_get_platdata(&pdev
->dev
);
1051 u8
*mac_addr
= NULL
;
1052 struct resource
*mem
;
1053 const struct w5100_ops
*ops
;
1056 if (data
&& is_valid_ether_addr(data
->mac_addr
))
1057 mac_addr
= data
->mac_addr
;
1059 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1060 if (resource_size(mem
) < W5100_BUS_DIRECT_SIZE
)
1061 ops
= &w5100_mmio_indirect_ops
;
1063 ops
= &w5100_mmio_direct_ops
;
1065 irq
= platform_get_irq(pdev
, 0);
1069 return w5100_probe(&pdev
->dev
, ops
, sizeof(struct w5100_mmio_priv
),
1070 mac_addr
, irq
, data
? data
->link_gpio
: -EINVAL
);
1073 static int w5100_mmio_remove(struct platform_device
*pdev
)
1075 return w5100_remove(&pdev
->dev
);
1078 void *w5100_ops_priv(const struct net_device
*ndev
)
1080 return netdev_priv(ndev
) +
1081 ALIGN(sizeof(struct w5100_priv
), NETDEV_ALIGN
);
1083 EXPORT_SYMBOL_GPL(w5100_ops_priv
);
1085 int w5100_probe(struct device
*dev
, const struct w5100_ops
*ops
,
1086 int sizeof_ops_priv
, u8
*mac_addr
, int irq
, int link_gpio
)
1088 struct w5100_priv
*priv
;
1089 struct net_device
*ndev
;
1093 alloc_size
= sizeof(*priv
);
1094 if (sizeof_ops_priv
) {
1095 alloc_size
= ALIGN(alloc_size
, NETDEV_ALIGN
);
1096 alloc_size
+= sizeof_ops_priv
;
1098 alloc_size
+= NETDEV_ALIGN
- 1;
1100 ndev
= alloc_etherdev(alloc_size
);
1103 SET_NETDEV_DEV(ndev
, dev
);
1104 dev_set_drvdata(dev
, ndev
);
1105 priv
= netdev_priv(ndev
);
1107 switch (ops
->chip_id
) {
1109 priv
->s0_regs
= W5100_S0_REGS
;
1110 priv
->s0_tx_buf
= W5100_TX_MEM_START
;
1111 priv
->s0_tx_buf_size
= W5100_TX_MEM_SIZE
;
1112 priv
->s0_rx_buf
= W5100_RX_MEM_START
;
1113 priv
->s0_rx_buf_size
= W5100_RX_MEM_SIZE
;
1116 priv
->s0_regs
= W5200_S0_REGS
;
1117 priv
->s0_tx_buf
= W5200_TX_MEM_START
;
1118 priv
->s0_tx_buf_size
= W5200_TX_MEM_SIZE
;
1119 priv
->s0_rx_buf
= W5200_RX_MEM_START
;
1120 priv
->s0_rx_buf_size
= W5200_RX_MEM_SIZE
;
1123 priv
->s0_regs
= W5500_S0_REGS
;
1124 priv
->s0_tx_buf
= W5500_TX_MEM_START
;
1125 priv
->s0_tx_buf_size
= W5500_TX_MEM_SIZE
;
1126 priv
->s0_rx_buf
= W5500_RX_MEM_START
;
1127 priv
->s0_rx_buf_size
= W5500_RX_MEM_SIZE
;
1137 priv
->link_gpio
= link_gpio
;
1139 ndev
->netdev_ops
= &w5100_netdev_ops
;
1140 ndev
->ethtool_ops
= &w5100_ethtool_ops
;
1141 ndev
->watchdog_timeo
= HZ
;
1142 netif_napi_add(ndev
, &priv
->napi
, w5100_napi_poll
, 16);
1144 /* This chip doesn't support VLAN packets with normal MTU,
1145 * so disable VLAN for this device.
1147 ndev
->features
|= NETIF_F_VLAN_CHALLENGED
;
1149 err
= register_netdev(ndev
);
1153 priv
->xfer_wq
= create_workqueue(netdev_name(ndev
));
1154 if (!priv
->xfer_wq
) {
1159 INIT_WORK(&priv
->rx_work
, w5100_rx_work
);
1160 INIT_WORK(&priv
->tx_work
, w5100_tx_work
);
1161 INIT_WORK(&priv
->setrx_work
, w5100_setrx_work
);
1162 INIT_WORK(&priv
->restart_work
, w5100_restart_work
);
1165 memcpy(ndev
->dev_addr
, mac_addr
, ETH_ALEN
);
1167 eth_hw_addr_random(ndev
);
1169 if (priv
->ops
->init
) {
1170 err
= priv
->ops
->init(priv
->ndev
);
1175 err
= w5100_hw_reset(priv
);
1179 if (ops
->may_sleep
) {
1180 err
= request_threaded_irq(priv
->irq
, NULL
, w5100_interrupt
,
1181 IRQF_TRIGGER_LOW
| IRQF_ONESHOT
,
1182 netdev_name(ndev
), ndev
);
1184 err
= request_irq(priv
->irq
, w5100_interrupt
,
1185 IRQF_TRIGGER_LOW
, netdev_name(ndev
), ndev
);
1190 if (gpio_is_valid(priv
->link_gpio
)) {
1191 char *link_name
= devm_kzalloc(dev
, 16, GFP_KERNEL
);
1197 snprintf(link_name
, 16, "%s-link", netdev_name(ndev
));
1198 priv
->link_irq
= gpio_to_irq(priv
->link_gpio
);
1199 if (request_any_context_irq(priv
->link_irq
, w5100_detect_link
,
1200 IRQF_TRIGGER_RISING
|
1201 IRQF_TRIGGER_FALLING
,
1202 link_name
, priv
->ndev
) < 0)
1203 priv
->link_gpio
= -EINVAL
;
1209 free_irq(priv
->irq
, ndev
);
1211 destroy_workqueue(priv
->xfer_wq
);
1213 unregister_netdev(ndev
);
1218 EXPORT_SYMBOL_GPL(w5100_probe
);
1220 int w5100_remove(struct device
*dev
)
1222 struct net_device
*ndev
= dev_get_drvdata(dev
);
1223 struct w5100_priv
*priv
= netdev_priv(ndev
);
1225 w5100_hw_reset(priv
);
1226 free_irq(priv
->irq
, ndev
);
1227 if (gpio_is_valid(priv
->link_gpio
))
1228 free_irq(priv
->link_irq
, ndev
);
1230 flush_work(&priv
->setrx_work
);
1231 flush_work(&priv
->restart_work
);
1232 flush_workqueue(priv
->xfer_wq
);
1233 destroy_workqueue(priv
->xfer_wq
);
1235 unregister_netdev(ndev
);
1239 EXPORT_SYMBOL_GPL(w5100_remove
);
1241 #ifdef CONFIG_PM_SLEEP
1242 static int w5100_suspend(struct device
*dev
)
1244 struct net_device
*ndev
= dev_get_drvdata(dev
);
1245 struct w5100_priv
*priv
= netdev_priv(ndev
);
1247 if (netif_running(ndev
)) {
1248 netif_carrier_off(ndev
);
1249 netif_device_detach(ndev
);
1251 w5100_hw_close(priv
);
1256 static int w5100_resume(struct device
*dev
)
1258 struct net_device
*ndev
= dev_get_drvdata(dev
);
1259 struct w5100_priv
*priv
= netdev_priv(ndev
);
1261 if (netif_running(ndev
)) {
1262 w5100_hw_reset(priv
);
1263 w5100_hw_start(priv
);
1265 netif_device_attach(ndev
);
1266 if (!gpio_is_valid(priv
->link_gpio
) ||
1267 gpio_get_value(priv
->link_gpio
) != 0)
1268 netif_carrier_on(ndev
);
1272 #endif /* CONFIG_PM_SLEEP */
1274 SIMPLE_DEV_PM_OPS(w5100_pm_ops
, w5100_suspend
, w5100_resume
);
1275 EXPORT_SYMBOL_GPL(w5100_pm_ops
);
1277 static struct platform_driver w5100_mmio_driver
= {
1280 .pm
= &w5100_pm_ops
,
1282 .probe
= w5100_mmio_probe
,
1283 .remove
= w5100_mmio_remove
,
1285 module_platform_driver(w5100_mmio_driver
);