1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xilinx Axi Ethernet device driver
5 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
6 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
7 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
9 * Copyright (c) 2010 - 2011 PetaLogix
10 * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
11 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
13 * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
17 * - Add Axi Fifo support.
18 * - Factor out Axi DMA code into separate driver.
19 * - Test and fix basic multicast filtering.
20 * - Add support for extended multicast filtering.
21 * - Test basic VLAN support.
22 * - Add support for extended VLAN support.
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/etherdevice.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
33 #include <linux/of_irq.h>
34 #include <linux/of_address.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/phy.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
41 #include "xilinx_axienet.h"
43 /* Descriptors defines for Tx and Rx DMA */
44 #define TX_BD_NUM_DEFAULT 64
45 #define RX_BD_NUM_DEFAULT 1024
46 #define TX_BD_NUM_MAX 4096
47 #define RX_BD_NUM_MAX 4096
49 /* Must be shorter than length of ethtool_drvinfo.driver field to fit */
50 #define DRIVER_NAME "xaxienet"
51 #define DRIVER_DESCRIPTION "Xilinx Axi Ethernet driver"
52 #define DRIVER_VERSION "1.00a"
54 #define AXIENET_REGS_N 40
56 /* Match table for of_platform binding */
57 static const struct of_device_id axienet_of_match
[] = {
58 { .compatible
= "xlnx,axi-ethernet-1.00.a", },
59 { .compatible
= "xlnx,axi-ethernet-1.01.a", },
60 { .compatible
= "xlnx,axi-ethernet-2.01.a", },
64 MODULE_DEVICE_TABLE(of
, axienet_of_match
);
66 /* Option table for setting up Axi Ethernet hardware options */
67 static struct axienet_option axienet_options
[] = {
68 /* Turn on jumbo packet support for both Rx and Tx */
70 .opt
= XAE_OPTION_JUMBO
,
72 .m_or
= XAE_TC_JUM_MASK
,
74 .opt
= XAE_OPTION_JUMBO
,
75 .reg
= XAE_RCW1_OFFSET
,
76 .m_or
= XAE_RCW1_JUM_MASK
,
77 }, { /* Turn on VLAN packet support for both Rx and Tx */
78 .opt
= XAE_OPTION_VLAN
,
80 .m_or
= XAE_TC_VLAN_MASK
,
82 .opt
= XAE_OPTION_VLAN
,
83 .reg
= XAE_RCW1_OFFSET
,
84 .m_or
= XAE_RCW1_VLAN_MASK
,
85 }, { /* Turn on FCS stripping on receive packets */
86 .opt
= XAE_OPTION_FCS_STRIP
,
87 .reg
= XAE_RCW1_OFFSET
,
88 .m_or
= XAE_RCW1_FCS_MASK
,
89 }, { /* Turn on FCS insertion on transmit packets */
90 .opt
= XAE_OPTION_FCS_INSERT
,
92 .m_or
= XAE_TC_FCS_MASK
,
93 }, { /* Turn off length/type field checking on receive packets */
94 .opt
= XAE_OPTION_LENTYPE_ERR
,
95 .reg
= XAE_RCW1_OFFSET
,
96 .m_or
= XAE_RCW1_LT_DIS_MASK
,
97 }, { /* Turn on Rx flow control */
98 .opt
= XAE_OPTION_FLOW_CONTROL
,
99 .reg
= XAE_FCC_OFFSET
,
100 .m_or
= XAE_FCC_FCRX_MASK
,
101 }, { /* Turn on Tx flow control */
102 .opt
= XAE_OPTION_FLOW_CONTROL
,
103 .reg
= XAE_FCC_OFFSET
,
104 .m_or
= XAE_FCC_FCTX_MASK
,
105 }, { /* Turn on promiscuous frame filtering */
106 .opt
= XAE_OPTION_PROMISC
,
107 .reg
= XAE_FMI_OFFSET
,
108 .m_or
= XAE_FMI_PM_MASK
,
109 }, { /* Enable transmitter */
110 .opt
= XAE_OPTION_TXEN
,
111 .reg
= XAE_TC_OFFSET
,
112 .m_or
= XAE_TC_TX_MASK
,
113 }, { /* Enable receiver */
114 .opt
= XAE_OPTION_RXEN
,
115 .reg
= XAE_RCW1_OFFSET
,
116 .m_or
= XAE_RCW1_RX_MASK
,
122 * axienet_dma_in32 - Memory mapped Axi DMA register read
123 * @lp: Pointer to axienet local structure
124 * @reg: Address offset from the base address of the Axi DMA core
126 * Return: The contents of the Axi DMA register
128 * This function returns the contents of the corresponding Axi DMA register.
130 static inline u32
axienet_dma_in32(struct axienet_local
*lp
, off_t reg
)
132 return ioread32(lp
->dma_regs
+ reg
);
136 * axienet_dma_out32 - Memory mapped Axi DMA register write.
137 * @lp: Pointer to axienet local structure
138 * @reg: Address offset from the base address of the Axi DMA core
139 * @value: Value to be written into the Axi DMA register
141 * This function writes the desired value into the corresponding Axi DMA
144 static inline void axienet_dma_out32(struct axienet_local
*lp
,
145 off_t reg
, u32 value
)
147 iowrite32(value
, lp
->dma_regs
+ reg
);
150 static void axienet_dma_out_addr(struct axienet_local
*lp
, off_t reg
,
153 axienet_dma_out32(lp
, reg
, lower_32_bits(addr
));
156 static void desc_set_phys_addr(struct axienet_local
*lp
, dma_addr_t addr
,
157 struct axidma_bd
*desc
)
159 desc
->phys
= lower_32_bits(addr
);
160 if (lp
->features
& XAE_FEATURE_DMA_64BIT
)
161 desc
->phys_msb
= upper_32_bits(addr
);
164 static dma_addr_t
desc_get_phys_addr(struct axienet_local
*lp
,
165 struct axidma_bd
*desc
)
167 dma_addr_t ret
= desc
->phys
;
169 if (lp
->features
& XAE_FEATURE_DMA_64BIT
)
170 ret
|= ((dma_addr_t
)desc
->phys_msb
<< 16) << 16;
176 * axienet_dma_bd_release - Release buffer descriptor rings
177 * @ndev: Pointer to the net_device structure
179 * This function is used to release the descriptors allocated in
180 * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet
181 * driver stop api is called.
183 static void axienet_dma_bd_release(struct net_device
*ndev
)
186 struct axienet_local
*lp
= netdev_priv(ndev
);
188 /* If we end up here, tx_bd_v must have been DMA allocated. */
189 dma_free_coherent(ndev
->dev
.parent
,
190 sizeof(*lp
->tx_bd_v
) * lp
->tx_bd_num
,
197 for (i
= 0; i
< lp
->rx_bd_num
; i
++) {
200 /* A NULL skb means this descriptor has not been initialised
203 if (!lp
->rx_bd_v
[i
].skb
)
206 dev_kfree_skb(lp
->rx_bd_v
[i
].skb
);
208 /* For each descriptor, we programmed cntrl with the (non-zero)
209 * descriptor size, after it had been successfully allocated.
210 * So a non-zero value in there means we need to unmap it.
212 if (lp
->rx_bd_v
[i
].cntrl
) {
213 phys
= desc_get_phys_addr(lp
, &lp
->rx_bd_v
[i
]);
214 dma_unmap_single(ndev
->dev
.parent
, phys
,
215 lp
->max_frm_size
, DMA_FROM_DEVICE
);
219 dma_free_coherent(ndev
->dev
.parent
,
220 sizeof(*lp
->rx_bd_v
) * lp
->rx_bd_num
,
226 * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA
227 * @ndev: Pointer to the net_device structure
229 * Return: 0, on success -ENOMEM, on failure
231 * This function is called to initialize the Rx and Tx DMA descriptor
232 * rings. This initializes the descriptors with required default values
233 * and is called when Axi Ethernet driver reset is called.
235 static int axienet_dma_bd_init(struct net_device
*ndev
)
240 struct axienet_local
*lp
= netdev_priv(ndev
);
242 /* Reset the indexes which are used for accessing the BDs */
247 /* Allocate the Tx and Rx buffer descriptors. */
248 lp
->tx_bd_v
= dma_alloc_coherent(ndev
->dev
.parent
,
249 sizeof(*lp
->tx_bd_v
) * lp
->tx_bd_num
,
250 &lp
->tx_bd_p
, GFP_KERNEL
);
254 lp
->rx_bd_v
= dma_alloc_coherent(ndev
->dev
.parent
,
255 sizeof(*lp
->rx_bd_v
) * lp
->rx_bd_num
,
256 &lp
->rx_bd_p
, GFP_KERNEL
);
260 for (i
= 0; i
< lp
->tx_bd_num
; i
++) {
261 dma_addr_t addr
= lp
->tx_bd_p
+
262 sizeof(*lp
->tx_bd_v
) *
263 ((i
+ 1) % lp
->tx_bd_num
);
265 lp
->tx_bd_v
[i
].next
= lower_32_bits(addr
);
266 if (lp
->features
& XAE_FEATURE_DMA_64BIT
)
267 lp
->tx_bd_v
[i
].next_msb
= upper_32_bits(addr
);
270 for (i
= 0; i
< lp
->rx_bd_num
; i
++) {
273 addr
= lp
->rx_bd_p
+ sizeof(*lp
->rx_bd_v
) *
274 ((i
+ 1) % lp
->rx_bd_num
);
275 lp
->rx_bd_v
[i
].next
= lower_32_bits(addr
);
276 if (lp
->features
& XAE_FEATURE_DMA_64BIT
)
277 lp
->rx_bd_v
[i
].next_msb
= upper_32_bits(addr
);
279 skb
= netdev_alloc_skb_ip_align(ndev
, lp
->max_frm_size
);
283 lp
->rx_bd_v
[i
].skb
= skb
;
284 addr
= dma_map_single(ndev
->dev
.parent
, skb
->data
,
285 lp
->max_frm_size
, DMA_FROM_DEVICE
);
286 if (dma_mapping_error(ndev
->dev
.parent
, addr
)) {
287 netdev_err(ndev
, "DMA mapping error\n");
290 desc_set_phys_addr(lp
, addr
, &lp
->rx_bd_v
[i
]);
292 lp
->rx_bd_v
[i
].cntrl
= lp
->max_frm_size
;
295 /* Start updating the Rx channel control register */
296 cr
= axienet_dma_in32(lp
, XAXIDMA_RX_CR_OFFSET
);
297 /* Update the interrupt coalesce count */
298 cr
= ((cr
& ~XAXIDMA_COALESCE_MASK
) |
299 ((lp
->coalesce_count_rx
) << XAXIDMA_COALESCE_SHIFT
));
300 /* Update the delay timer count */
301 cr
= ((cr
& ~XAXIDMA_DELAY_MASK
) |
302 (XAXIDMA_DFT_RX_WAITBOUND
<< XAXIDMA_DELAY_SHIFT
));
303 /* Enable coalesce, delay timer and error interrupts */
304 cr
|= XAXIDMA_IRQ_ALL_MASK
;
305 /* Write to the Rx channel control register */
306 axienet_dma_out32(lp
, XAXIDMA_RX_CR_OFFSET
, cr
);
308 /* Start updating the Tx channel control register */
309 cr
= axienet_dma_in32(lp
, XAXIDMA_TX_CR_OFFSET
);
310 /* Update the interrupt coalesce count */
311 cr
= (((cr
& ~XAXIDMA_COALESCE_MASK
)) |
312 ((lp
->coalesce_count_tx
) << XAXIDMA_COALESCE_SHIFT
));
313 /* Update the delay timer count */
314 cr
= (((cr
& ~XAXIDMA_DELAY_MASK
)) |
315 (XAXIDMA_DFT_TX_WAITBOUND
<< XAXIDMA_DELAY_SHIFT
));
316 /* Enable coalesce, delay timer and error interrupts */
317 cr
|= XAXIDMA_IRQ_ALL_MASK
;
318 /* Write to the Tx channel control register */
319 axienet_dma_out32(lp
, XAXIDMA_TX_CR_OFFSET
, cr
);
321 /* Populate the tail pointer and bring the Rx Axi DMA engine out of
322 * halted state. This will make the Rx side ready for reception.
324 axienet_dma_out_addr(lp
, XAXIDMA_RX_CDESC_OFFSET
, lp
->rx_bd_p
);
325 cr
= axienet_dma_in32(lp
, XAXIDMA_RX_CR_OFFSET
);
326 axienet_dma_out32(lp
, XAXIDMA_RX_CR_OFFSET
,
327 cr
| XAXIDMA_CR_RUNSTOP_MASK
);
328 axienet_dma_out_addr(lp
, XAXIDMA_RX_TDESC_OFFSET
, lp
->rx_bd_p
+
329 (sizeof(*lp
->rx_bd_v
) * (lp
->rx_bd_num
- 1)));
331 /* Write to the RS (Run-stop) bit in the Tx channel control register.
332 * Tx channel is now ready to run. But only after we write to the
333 * tail pointer register that the Tx channel will start transmitting.
335 axienet_dma_out_addr(lp
, XAXIDMA_TX_CDESC_OFFSET
, lp
->tx_bd_p
);
336 cr
= axienet_dma_in32(lp
, XAXIDMA_TX_CR_OFFSET
);
337 axienet_dma_out32(lp
, XAXIDMA_TX_CR_OFFSET
,
338 cr
| XAXIDMA_CR_RUNSTOP_MASK
);
342 axienet_dma_bd_release(ndev
);
347 * axienet_set_mac_address - Write the MAC address
348 * @ndev: Pointer to the net_device structure
349 * @address: 6 byte Address to be written as MAC address
351 * This function is called to initialize the MAC address of the Axi Ethernet
352 * core. It writes to the UAW0 and UAW1 registers of the core.
354 static void axienet_set_mac_address(struct net_device
*ndev
,
357 struct axienet_local
*lp
= netdev_priv(ndev
);
360 memcpy(ndev
->dev_addr
, address
, ETH_ALEN
);
361 if (!is_valid_ether_addr(ndev
->dev_addr
))
362 eth_hw_addr_random(ndev
);
364 /* Set up unicast MAC address filter set its mac address */
365 axienet_iow(lp
, XAE_UAW0_OFFSET
,
366 (ndev
->dev_addr
[0]) |
367 (ndev
->dev_addr
[1] << 8) |
368 (ndev
->dev_addr
[2] << 16) |
369 (ndev
->dev_addr
[3] << 24));
370 axienet_iow(lp
, XAE_UAW1_OFFSET
,
371 (((axienet_ior(lp
, XAE_UAW1_OFFSET
)) &
372 ~XAE_UAW1_UNICASTADDR_MASK
) |
374 (ndev
->dev_addr
[5] << 8))));
378 * netdev_set_mac_address - Write the MAC address (from outside the driver)
379 * @ndev: Pointer to the net_device structure
380 * @p: 6 byte Address to be written as MAC address
382 * Return: 0 for all conditions. Presently, there is no failure case.
384 * This function is called to initialize the MAC address of the Axi Ethernet
385 * core. It calls the core specific axienet_set_mac_address. This is the
386 * function that goes into net_device_ops structure entry ndo_set_mac_address.
388 static int netdev_set_mac_address(struct net_device
*ndev
, void *p
)
390 struct sockaddr
*addr
= p
;
391 axienet_set_mac_address(ndev
, addr
->sa_data
);
396 * axienet_set_multicast_list - Prepare the multicast table
397 * @ndev: Pointer to the net_device structure
399 * This function is called to initialize the multicast table during
400 * initialization. The Axi Ethernet basic multicast support has a four-entry
401 * multicast table which is initialized here. Additionally this function
402 * goes into the net_device_ops structure entry ndo_set_multicast_list. This
403 * means whenever the multicast table entries need to be updated this
404 * function gets called.
406 static void axienet_set_multicast_list(struct net_device
*ndev
)
409 u32 reg
, af0reg
, af1reg
;
410 struct axienet_local
*lp
= netdev_priv(ndev
);
412 if (ndev
->flags
& (IFF_ALLMULTI
| IFF_PROMISC
) ||
413 netdev_mc_count(ndev
) > XAE_MULTICAST_CAM_TABLE_NUM
) {
414 /* We must make the kernel realize we had to move into
415 * promiscuous mode. If it was a promiscuous mode request
416 * the flag is already set. If not we set it.
418 ndev
->flags
|= IFF_PROMISC
;
419 reg
= axienet_ior(lp
, XAE_FMI_OFFSET
);
420 reg
|= XAE_FMI_PM_MASK
;
421 axienet_iow(lp
, XAE_FMI_OFFSET
, reg
);
422 dev_info(&ndev
->dev
, "Promiscuous mode enabled.\n");
423 } else if (!netdev_mc_empty(ndev
)) {
424 struct netdev_hw_addr
*ha
;
427 netdev_for_each_mc_addr(ha
, ndev
) {
428 if (i
>= XAE_MULTICAST_CAM_TABLE_NUM
)
431 af0reg
= (ha
->addr
[0]);
432 af0reg
|= (ha
->addr
[1] << 8);
433 af0reg
|= (ha
->addr
[2] << 16);
434 af0reg
|= (ha
->addr
[3] << 24);
436 af1reg
= (ha
->addr
[4]);
437 af1reg
|= (ha
->addr
[5] << 8);
439 reg
= axienet_ior(lp
, XAE_FMI_OFFSET
) & 0xFFFFFF00;
442 axienet_iow(lp
, XAE_FMI_OFFSET
, reg
);
443 axienet_iow(lp
, XAE_AF0_OFFSET
, af0reg
);
444 axienet_iow(lp
, XAE_AF1_OFFSET
, af1reg
);
448 reg
= axienet_ior(lp
, XAE_FMI_OFFSET
);
449 reg
&= ~XAE_FMI_PM_MASK
;
451 axienet_iow(lp
, XAE_FMI_OFFSET
, reg
);
453 for (i
= 0; i
< XAE_MULTICAST_CAM_TABLE_NUM
; i
++) {
454 reg
= axienet_ior(lp
, XAE_FMI_OFFSET
) & 0xFFFFFF00;
457 axienet_iow(lp
, XAE_FMI_OFFSET
, reg
);
458 axienet_iow(lp
, XAE_AF0_OFFSET
, 0);
459 axienet_iow(lp
, XAE_AF1_OFFSET
, 0);
462 dev_info(&ndev
->dev
, "Promiscuous mode disabled.\n");
467 * axienet_setoptions - Set an Axi Ethernet option
468 * @ndev: Pointer to the net_device structure
469 * @options: Option to be enabled/disabled
471 * The Axi Ethernet core has multiple features which can be selectively turned
472 * on or off. The typical options could be jumbo frame option, basic VLAN
473 * option, promiscuous mode option etc. This function is used to set or clear
474 * these options in the Axi Ethernet hardware. This is done through
475 * axienet_option structure .
477 static void axienet_setoptions(struct net_device
*ndev
, u32 options
)
480 struct axienet_local
*lp
= netdev_priv(ndev
);
481 struct axienet_option
*tp
= &axienet_options
[0];
484 reg
= ((axienet_ior(lp
, tp
->reg
)) & ~(tp
->m_or
));
485 if (options
& tp
->opt
)
487 axienet_iow(lp
, tp
->reg
, reg
);
491 lp
->options
|= options
;
494 static int __axienet_device_reset(struct axienet_local
*lp
)
498 /* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
499 * process of Axi DMA takes a while to complete as all pending
500 * commands/transfers will be flushed or completed during this
502 * Note that even though both TX and RX have their own reset register,
503 * they both reset the entire DMA core, so only one needs to be used.
505 axienet_dma_out32(lp
, XAXIDMA_TX_CR_OFFSET
, XAXIDMA_CR_RESET_MASK
);
506 timeout
= DELAY_OF_ONE_MILLISEC
;
507 while (axienet_dma_in32(lp
, XAXIDMA_TX_CR_OFFSET
) &
508 XAXIDMA_CR_RESET_MASK
) {
510 if (--timeout
== 0) {
511 netdev_err(lp
->ndev
, "%s: DMA reset timeout!\n",
521 * axienet_device_reset - Reset and initialize the Axi Ethernet hardware.
522 * @ndev: Pointer to the net_device structure
524 * This function is called to reset and initialize the Axi Ethernet core. This
525 * is typically called during initialization. It does a reset of the Axi DMA
526 * Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines
527 * areconnected to Axi Ethernet reset lines, this in turn resets the Axi
528 * Ethernet core. No separate hardware reset is done for the Axi Ethernet
530 * Returns 0 on success or a negative error number otherwise.
532 static int axienet_device_reset(struct net_device
*ndev
)
535 struct axienet_local
*lp
= netdev_priv(ndev
);
538 ret
= __axienet_device_reset(lp
);
542 lp
->max_frm_size
= XAE_MAX_VLAN_FRAME_SIZE
;
543 lp
->options
|= XAE_OPTION_VLAN
;
544 lp
->options
&= (~XAE_OPTION_JUMBO
);
546 if ((ndev
->mtu
> XAE_MTU
) &&
547 (ndev
->mtu
<= XAE_JUMBO_MTU
)) {
548 lp
->max_frm_size
= ndev
->mtu
+ VLAN_ETH_HLEN
+
551 if (lp
->max_frm_size
<= lp
->rxmem
)
552 lp
->options
|= XAE_OPTION_JUMBO
;
555 ret
= axienet_dma_bd_init(ndev
);
557 netdev_err(ndev
, "%s: descriptor allocation failed\n",
562 axienet_status
= axienet_ior(lp
, XAE_RCW1_OFFSET
);
563 axienet_status
&= ~XAE_RCW1_RX_MASK
;
564 axienet_iow(lp
, XAE_RCW1_OFFSET
, axienet_status
);
566 axienet_status
= axienet_ior(lp
, XAE_IP_OFFSET
);
567 if (axienet_status
& XAE_INT_RXRJECT_MASK
)
568 axienet_iow(lp
, XAE_IS_OFFSET
, XAE_INT_RXRJECT_MASK
);
569 axienet_iow(lp
, XAE_IE_OFFSET
, lp
->eth_irq
> 0 ?
570 XAE_INT_RECV_ERROR_MASK
: 0);
572 axienet_iow(lp
, XAE_FCC_OFFSET
, XAE_FCC_FCRX_MASK
);
574 /* Sync default options with HW but leave receiver and
575 * transmitter disabled.
577 axienet_setoptions(ndev
, lp
->options
&
578 ~(XAE_OPTION_TXEN
| XAE_OPTION_RXEN
));
579 axienet_set_mac_address(ndev
, NULL
);
580 axienet_set_multicast_list(ndev
);
581 axienet_setoptions(ndev
, lp
->options
);
583 netif_trans_update(ndev
);
589 * axienet_free_tx_chain - Clean up a series of linked TX descriptors.
590 * @ndev: Pointer to the net_device structure
591 * @first_bd: Index of first descriptor to clean up
592 * @nr_bds: Number of descriptors to clean up, can be -1 if unknown.
593 * @sizep: Pointer to a u32 filled with the total sum of all bytes
594 * in all cleaned-up descriptors. Ignored if NULL.
596 * Would either be called after a successful transmit operation, or after
597 * there was an error when setting up the chain.
598 * Returns the number of descriptors handled.
600 static int axienet_free_tx_chain(struct net_device
*ndev
, u32 first_bd
,
601 int nr_bds
, u32
*sizep
)
603 struct axienet_local
*lp
= netdev_priv(ndev
);
604 struct axidma_bd
*cur_p
;
605 int max_bds
= nr_bds
;
611 max_bds
= lp
->tx_bd_num
;
613 for (i
= 0; i
< max_bds
; i
++) {
614 cur_p
= &lp
->tx_bd_v
[(first_bd
+ i
) % lp
->tx_bd_num
];
615 status
= cur_p
->status
;
617 /* If no number is given, clean up *all* descriptors that have
618 * been completed by the MAC.
620 if (nr_bds
== -1 && !(status
& XAXIDMA_BD_STS_COMPLETE_MASK
))
623 phys
= desc_get_phys_addr(lp
, cur_p
);
624 dma_unmap_single(ndev
->dev
.parent
, phys
,
625 (cur_p
->cntrl
& XAXIDMA_BD_CTRL_LENGTH_MASK
),
628 if (cur_p
->skb
&& (status
& XAXIDMA_BD_STS_COMPLETE_MASK
))
629 dev_consume_skb_irq(cur_p
->skb
);
640 *sizep
+= status
& XAXIDMA_BD_STS_ACTUAL_LEN_MASK
;
647 * axienet_start_xmit_done - Invoked once a transmit is completed by the
648 * Axi DMA Tx channel.
649 * @ndev: Pointer to the net_device structure
651 * This function is invoked from the Axi DMA Tx isr to notify the completion
652 * of transmit operation. It clears fields in the corresponding Tx BDs and
653 * unmaps the corresponding buffer so that CPU can regain ownership of the
654 * buffer. It finally invokes "netif_wake_queue" to restart transmission if
657 static void axienet_start_xmit_done(struct net_device
*ndev
)
659 struct axienet_local
*lp
= netdev_priv(ndev
);
663 packets
= axienet_free_tx_chain(ndev
, lp
->tx_bd_ci
, -1, &size
);
665 lp
->tx_bd_ci
+= packets
;
666 if (lp
->tx_bd_ci
>= lp
->tx_bd_num
)
667 lp
->tx_bd_ci
-= lp
->tx_bd_num
;
669 ndev
->stats
.tx_packets
+= packets
;
670 ndev
->stats
.tx_bytes
+= size
;
672 /* Matches barrier in axienet_start_xmit */
675 netif_wake_queue(ndev
);
679 * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
680 * @lp: Pointer to the axienet_local structure
681 * @num_frag: The number of BDs to check for
683 * Return: 0, on success
684 * NETDEV_TX_BUSY, if any of the descriptors are not free
686 * This function is invoked before BDs are allocated and transmission starts.
687 * This function returns 0 if a BD or group of BDs can be allocated for
688 * transmission. If the BD or any of the BDs are not free the function
689 * returns a busy status. This is invoked from axienet_start_xmit.
691 static inline int axienet_check_tx_bd_space(struct axienet_local
*lp
,
694 struct axidma_bd
*cur_p
;
695 cur_p
= &lp
->tx_bd_v
[(lp
->tx_bd_tail
+ num_frag
) % lp
->tx_bd_num
];
696 if (cur_p
->status
& XAXIDMA_BD_STS_ALL_MASK
)
697 return NETDEV_TX_BUSY
;
702 * axienet_start_xmit - Starts the transmission.
703 * @skb: sk_buff pointer that contains data to be Txed.
704 * @ndev: Pointer to net_device structure.
706 * Return: NETDEV_TX_OK, on success
707 * NETDEV_TX_BUSY, if any of the descriptors are not free
709 * This function is invoked from upper layers to initiate transmission. The
710 * function uses the next available free BDs and populates their fields to
711 * start the transmission. Additionally if checksum offloading is supported,
712 * it populates AXI Stream Control fields with appropriate values.
715 axienet_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
722 dma_addr_t tail_p
, phys
;
723 struct axienet_local
*lp
= netdev_priv(ndev
);
724 struct axidma_bd
*cur_p
;
725 u32 orig_tail_ptr
= lp
->tx_bd_tail
;
727 num_frag
= skb_shinfo(skb
)->nr_frags
;
728 cur_p
= &lp
->tx_bd_v
[lp
->tx_bd_tail
];
730 if (axienet_check_tx_bd_space(lp
, num_frag
)) {
731 if (netif_queue_stopped(ndev
))
732 return NETDEV_TX_BUSY
;
734 netif_stop_queue(ndev
);
736 /* Matches barrier in axienet_start_xmit_done */
739 /* Space might have just been freed - check again */
740 if (axienet_check_tx_bd_space(lp
, num_frag
))
741 return NETDEV_TX_BUSY
;
743 netif_wake_queue(ndev
);
746 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
747 if (lp
->features
& XAE_FEATURE_FULL_TX_CSUM
) {
748 /* Tx Full Checksum Offload Enabled */
750 } else if (lp
->features
& XAE_FEATURE_PARTIAL_RX_CSUM
) {
751 csum_start_off
= skb_transport_offset(skb
);
752 csum_index_off
= csum_start_off
+ skb
->csum_offset
;
753 /* Tx Partial Checksum Offload Enabled */
755 cur_p
->app1
= (csum_start_off
<< 16) | csum_index_off
;
757 } else if (skb
->ip_summed
== CHECKSUM_UNNECESSARY
) {
758 cur_p
->app0
|= 2; /* Tx Full Checksum Offload Enabled */
761 phys
= dma_map_single(ndev
->dev
.parent
, skb
->data
,
762 skb_headlen(skb
), DMA_TO_DEVICE
);
763 if (unlikely(dma_mapping_error(ndev
->dev
.parent
, phys
))) {
765 netdev_err(ndev
, "TX DMA mapping error\n");
766 ndev
->stats
.tx_dropped
++;
769 desc_set_phys_addr(lp
, phys
, cur_p
);
770 cur_p
->cntrl
= skb_headlen(skb
) | XAXIDMA_BD_CTRL_TXSOF_MASK
;
772 for (ii
= 0; ii
< num_frag
; ii
++) {
773 if (++lp
->tx_bd_tail
>= lp
->tx_bd_num
)
775 cur_p
= &lp
->tx_bd_v
[lp
->tx_bd_tail
];
776 frag
= &skb_shinfo(skb
)->frags
[ii
];
777 phys
= dma_map_single(ndev
->dev
.parent
,
778 skb_frag_address(frag
),
781 if (unlikely(dma_mapping_error(ndev
->dev
.parent
, phys
))) {
783 netdev_err(ndev
, "TX DMA mapping error\n");
784 ndev
->stats
.tx_dropped
++;
785 axienet_free_tx_chain(ndev
, orig_tail_ptr
, ii
+ 1,
787 lp
->tx_bd_tail
= orig_tail_ptr
;
791 desc_set_phys_addr(lp
, phys
, cur_p
);
792 cur_p
->cntrl
= skb_frag_size(frag
);
795 cur_p
->cntrl
|= XAXIDMA_BD_CTRL_TXEOF_MASK
;
798 tail_p
= lp
->tx_bd_p
+ sizeof(*lp
->tx_bd_v
) * lp
->tx_bd_tail
;
799 /* Start the transfer */
800 axienet_dma_out_addr(lp
, XAXIDMA_TX_TDESC_OFFSET
, tail_p
);
801 if (++lp
->tx_bd_tail
>= lp
->tx_bd_num
)
808 * axienet_recv - Is called from Axi DMA Rx Isr to complete the received
810 * @ndev: Pointer to net_device structure.
812 * This function is invoked from the Axi DMA Rx isr to process the Rx BDs. It
813 * does minimal processing and invokes "netif_rx" to complete further
816 static void axienet_recv(struct net_device
*ndev
)
822 dma_addr_t tail_p
= 0;
823 struct axienet_local
*lp
= netdev_priv(ndev
);
824 struct sk_buff
*skb
, *new_skb
;
825 struct axidma_bd
*cur_p
;
827 cur_p
= &lp
->rx_bd_v
[lp
->rx_bd_ci
];
829 while ((cur_p
->status
& XAXIDMA_BD_STS_COMPLETE_MASK
)) {
832 tail_p
= lp
->rx_bd_p
+ sizeof(*lp
->rx_bd_v
) * lp
->rx_bd_ci
;
834 phys
= desc_get_phys_addr(lp
, cur_p
);
835 dma_unmap_single(ndev
->dev
.parent
, phys
, lp
->max_frm_size
,
840 length
= cur_p
->app4
& 0x0000FFFF;
842 skb_put(skb
, length
);
843 skb
->protocol
= eth_type_trans(skb
, ndev
);
844 /*skb_checksum_none_assert(skb);*/
845 skb
->ip_summed
= CHECKSUM_NONE
;
847 /* if we're doing Rx csum offload, set it up */
848 if (lp
->features
& XAE_FEATURE_FULL_RX_CSUM
) {
849 csumstatus
= (cur_p
->app2
&
850 XAE_FULL_CSUM_STATUS_MASK
) >> 3;
851 if ((csumstatus
== XAE_IP_TCP_CSUM_VALIDATED
) ||
852 (csumstatus
== XAE_IP_UDP_CSUM_VALIDATED
)) {
853 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
855 } else if ((lp
->features
& XAE_FEATURE_PARTIAL_RX_CSUM
) != 0 &&
856 skb
->protocol
== htons(ETH_P_IP
) &&
858 skb
->csum
= be32_to_cpu(cur_p
->app3
& 0xFFFF);
859 skb
->ip_summed
= CHECKSUM_COMPLETE
;
867 new_skb
= netdev_alloc_skb_ip_align(ndev
, lp
->max_frm_size
);
871 phys
= dma_map_single(ndev
->dev
.parent
, new_skb
->data
,
874 if (unlikely(dma_mapping_error(ndev
->dev
.parent
, phys
))) {
876 netdev_err(ndev
, "RX DMA mapping error\n");
877 dev_kfree_skb(new_skb
);
880 desc_set_phys_addr(lp
, phys
, cur_p
);
882 cur_p
->cntrl
= lp
->max_frm_size
;
884 cur_p
->skb
= new_skb
;
886 if (++lp
->rx_bd_ci
>= lp
->rx_bd_num
)
888 cur_p
= &lp
->rx_bd_v
[lp
->rx_bd_ci
];
891 ndev
->stats
.rx_packets
+= packets
;
892 ndev
->stats
.rx_bytes
+= size
;
895 axienet_dma_out_addr(lp
, XAXIDMA_RX_TDESC_OFFSET
, tail_p
);
899 * axienet_tx_irq - Tx Done Isr.
901 * @_ndev: net_device pointer
903 * Return: IRQ_HANDLED if device generated a TX interrupt, IRQ_NONE otherwise.
905 * This is the Axi DMA Tx done Isr. It invokes "axienet_start_xmit_done"
906 * to complete the BD processing.
908 static irqreturn_t
axienet_tx_irq(int irq
, void *_ndev
)
912 struct net_device
*ndev
= _ndev
;
913 struct axienet_local
*lp
= netdev_priv(ndev
);
915 status
= axienet_dma_in32(lp
, XAXIDMA_TX_SR_OFFSET
);
916 if (status
& (XAXIDMA_IRQ_IOC_MASK
| XAXIDMA_IRQ_DELAY_MASK
)) {
917 axienet_dma_out32(lp
, XAXIDMA_TX_SR_OFFSET
, status
);
918 axienet_start_xmit_done(lp
->ndev
);
921 if (!(status
& XAXIDMA_IRQ_ALL_MASK
))
923 if (status
& XAXIDMA_IRQ_ERROR_MASK
) {
924 dev_err(&ndev
->dev
, "DMA Tx error 0x%x\n", status
);
925 dev_err(&ndev
->dev
, "Current BD is at: 0x%x%08x\n",
926 (lp
->tx_bd_v
[lp
->tx_bd_ci
]).phys_msb
,
927 (lp
->tx_bd_v
[lp
->tx_bd_ci
]).phys
);
929 cr
= axienet_dma_in32(lp
, XAXIDMA_TX_CR_OFFSET
);
930 /* Disable coalesce, delay timer and error interrupts */
931 cr
&= (~XAXIDMA_IRQ_ALL_MASK
);
932 /* Write to the Tx channel control register */
933 axienet_dma_out32(lp
, XAXIDMA_TX_CR_OFFSET
, cr
);
935 cr
= axienet_dma_in32(lp
, XAXIDMA_RX_CR_OFFSET
);
936 /* Disable coalesce, delay timer and error interrupts */
937 cr
&= (~XAXIDMA_IRQ_ALL_MASK
);
938 /* Write to the Rx channel control register */
939 axienet_dma_out32(lp
, XAXIDMA_RX_CR_OFFSET
, cr
);
941 schedule_work(&lp
->dma_err_task
);
942 axienet_dma_out32(lp
, XAXIDMA_TX_SR_OFFSET
, status
);
949 * axienet_rx_irq - Rx Isr.
951 * @_ndev: net_device pointer
953 * Return: IRQ_HANDLED if device generated a RX interrupt, IRQ_NONE otherwise.
955 * This is the Axi DMA Rx Isr. It invokes "axienet_recv" to complete the BD
958 static irqreturn_t
axienet_rx_irq(int irq
, void *_ndev
)
962 struct net_device
*ndev
= _ndev
;
963 struct axienet_local
*lp
= netdev_priv(ndev
);
965 status
= axienet_dma_in32(lp
, XAXIDMA_RX_SR_OFFSET
);
966 if (status
& (XAXIDMA_IRQ_IOC_MASK
| XAXIDMA_IRQ_DELAY_MASK
)) {
967 axienet_dma_out32(lp
, XAXIDMA_RX_SR_OFFSET
, status
);
968 axienet_recv(lp
->ndev
);
971 if (!(status
& XAXIDMA_IRQ_ALL_MASK
))
973 if (status
& XAXIDMA_IRQ_ERROR_MASK
) {
974 dev_err(&ndev
->dev
, "DMA Rx error 0x%x\n", status
);
975 dev_err(&ndev
->dev
, "Current BD is at: 0x%x%08x\n",
976 (lp
->rx_bd_v
[lp
->rx_bd_ci
]).phys_msb
,
977 (lp
->rx_bd_v
[lp
->rx_bd_ci
]).phys
);
979 cr
= axienet_dma_in32(lp
, XAXIDMA_TX_CR_OFFSET
);
980 /* Disable coalesce, delay timer and error interrupts */
981 cr
&= (~XAXIDMA_IRQ_ALL_MASK
);
982 /* Finally write to the Tx channel control register */
983 axienet_dma_out32(lp
, XAXIDMA_TX_CR_OFFSET
, cr
);
985 cr
= axienet_dma_in32(lp
, XAXIDMA_RX_CR_OFFSET
);
986 /* Disable coalesce, delay timer and error interrupts */
987 cr
&= (~XAXIDMA_IRQ_ALL_MASK
);
988 /* write to the Rx channel control register */
989 axienet_dma_out32(lp
, XAXIDMA_RX_CR_OFFSET
, cr
);
991 schedule_work(&lp
->dma_err_task
);
992 axienet_dma_out32(lp
, XAXIDMA_RX_SR_OFFSET
, status
);
999 * axienet_eth_irq - Ethernet core Isr.
1001 * @_ndev: net_device pointer
1003 * Return: IRQ_HANDLED if device generated a core interrupt, IRQ_NONE otherwise.
1005 * Handle miscellaneous conditions indicated by Ethernet core IRQ.
1007 static irqreturn_t
axienet_eth_irq(int irq
, void *_ndev
)
1009 struct net_device
*ndev
= _ndev
;
1010 struct axienet_local
*lp
= netdev_priv(ndev
);
1011 unsigned int pending
;
1013 pending
= axienet_ior(lp
, XAE_IP_OFFSET
);
1017 if (pending
& XAE_INT_RXFIFOOVR_MASK
)
1018 ndev
->stats
.rx_missed_errors
++;
1020 if (pending
& XAE_INT_RXRJECT_MASK
)
1021 ndev
->stats
.rx_frame_errors
++;
1023 axienet_iow(lp
, XAE_IS_OFFSET
, pending
);
1027 static void axienet_dma_err_handler(struct work_struct
*work
);
1030 * axienet_open - Driver open routine.
1031 * @ndev: Pointer to net_device structure
1033 * Return: 0, on success.
1034 * non-zero error value on failure
1036 * This is the driver open routine. It calls phylink_start to start the
1038 * It also allocates interrupt service routines, enables the interrupt lines
1039 * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer
1040 * descriptors are initialized.
1042 static int axienet_open(struct net_device
*ndev
)
1045 struct axienet_local
*lp
= netdev_priv(ndev
);
1047 dev_dbg(&ndev
->dev
, "axienet_open()\n");
1049 /* Disable the MDIO interface till Axi Ethernet Reset is completed.
1050 * When we do an Axi Ethernet reset, it resets the complete core
1051 * including the MDIO. MDIO must be disabled before resetting
1052 * and re-enabled afterwards.
1053 * Hold MDIO bus lock to avoid MDIO accesses during the reset.
1055 mutex_lock(&lp
->mii_bus
->mdio_lock
);
1056 axienet_mdio_disable(lp
);
1057 ret
= axienet_device_reset(ndev
);
1059 ret
= axienet_mdio_enable(lp
);
1060 mutex_unlock(&lp
->mii_bus
->mdio_lock
);
1064 ret
= phylink_of_phy_connect(lp
->phylink
, lp
->dev
->of_node
, 0);
1066 dev_err(lp
->dev
, "phylink_of_phy_connect() failed: %d\n", ret
);
1070 phylink_start(lp
->phylink
);
1072 /* Enable worker thread for Axi DMA error handling */
1073 INIT_WORK(&lp
->dma_err_task
, axienet_dma_err_handler
);
1075 /* Enable interrupts for Axi DMA Tx */
1076 ret
= request_irq(lp
->tx_irq
, axienet_tx_irq
, IRQF_SHARED
,
1080 /* Enable interrupts for Axi DMA Rx */
1081 ret
= request_irq(lp
->rx_irq
, axienet_rx_irq
, IRQF_SHARED
,
1085 /* Enable interrupts for Axi Ethernet core (if defined) */
1086 if (lp
->eth_irq
> 0) {
1087 ret
= request_irq(lp
->eth_irq
, axienet_eth_irq
, IRQF_SHARED
,
1096 free_irq(lp
->rx_irq
, ndev
);
1098 free_irq(lp
->tx_irq
, ndev
);
1100 phylink_stop(lp
->phylink
);
1101 phylink_disconnect_phy(lp
->phylink
);
1102 cancel_work_sync(&lp
->dma_err_task
);
1103 dev_err(lp
->dev
, "request_irq() failed\n");
1108 * axienet_stop - Driver stop routine.
1109 * @ndev: Pointer to net_device structure
1111 * Return: 0, on success.
1113 * This is the driver stop routine. It calls phylink_disconnect to stop the PHY
1114 * device. It also removes the interrupt handlers and disables the interrupts.
1115 * The Axi DMA Tx/Rx BDs are released.
1117 static int axienet_stop(struct net_device
*ndev
)
1121 struct axienet_local
*lp
= netdev_priv(ndev
);
1123 dev_dbg(&ndev
->dev
, "axienet_close()\n");
1125 phylink_stop(lp
->phylink
);
1126 phylink_disconnect_phy(lp
->phylink
);
1128 axienet_setoptions(ndev
, lp
->options
&
1129 ~(XAE_OPTION_TXEN
| XAE_OPTION_RXEN
));
1131 cr
= axienet_dma_in32(lp
, XAXIDMA_RX_CR_OFFSET
);
1132 cr
&= ~(XAXIDMA_CR_RUNSTOP_MASK
| XAXIDMA_IRQ_ALL_MASK
);
1133 axienet_dma_out32(lp
, XAXIDMA_RX_CR_OFFSET
, cr
);
1135 cr
= axienet_dma_in32(lp
, XAXIDMA_TX_CR_OFFSET
);
1136 cr
&= ~(XAXIDMA_CR_RUNSTOP_MASK
| XAXIDMA_IRQ_ALL_MASK
);
1137 axienet_dma_out32(lp
, XAXIDMA_TX_CR_OFFSET
, cr
);
1139 axienet_iow(lp
, XAE_IE_OFFSET
, 0);
1141 /* Give DMAs a chance to halt gracefully */
1142 sr
= axienet_dma_in32(lp
, XAXIDMA_RX_SR_OFFSET
);
1143 for (count
= 0; !(sr
& XAXIDMA_SR_HALT_MASK
) && count
< 5; ++count
) {
1145 sr
= axienet_dma_in32(lp
, XAXIDMA_RX_SR_OFFSET
);
1148 sr
= axienet_dma_in32(lp
, XAXIDMA_TX_SR_OFFSET
);
1149 for (count
= 0; !(sr
& XAXIDMA_SR_HALT_MASK
) && count
< 5; ++count
) {
1151 sr
= axienet_dma_in32(lp
, XAXIDMA_TX_SR_OFFSET
);
1154 /* Do a reset to ensure DMA is really stopped */
1155 mutex_lock(&lp
->mii_bus
->mdio_lock
);
1156 axienet_mdio_disable(lp
);
1157 __axienet_device_reset(lp
);
1158 axienet_mdio_enable(lp
);
1159 mutex_unlock(&lp
->mii_bus
->mdio_lock
);
1161 cancel_work_sync(&lp
->dma_err_task
);
1163 if (lp
->eth_irq
> 0)
1164 free_irq(lp
->eth_irq
, ndev
);
1165 free_irq(lp
->tx_irq
, ndev
);
1166 free_irq(lp
->rx_irq
, ndev
);
1168 axienet_dma_bd_release(ndev
);
1173 * axienet_change_mtu - Driver change mtu routine.
1174 * @ndev: Pointer to net_device structure
1175 * @new_mtu: New mtu value to be applied
1177 * Return: Always returns 0 (success).
1179 * This is the change mtu driver routine. It checks if the Axi Ethernet
1180 * hardware supports jumbo frames before changing the mtu. This can be
1181 * called only when the device is not up.
1183 static int axienet_change_mtu(struct net_device
*ndev
, int new_mtu
)
1185 struct axienet_local
*lp
= netdev_priv(ndev
);
1187 if (netif_running(ndev
))
1190 if ((new_mtu
+ VLAN_ETH_HLEN
+
1191 XAE_TRL_SIZE
) > lp
->rxmem
)
1194 ndev
->mtu
= new_mtu
;
1199 #ifdef CONFIG_NET_POLL_CONTROLLER
1201 * axienet_poll_controller - Axi Ethernet poll mechanism.
1202 * @ndev: Pointer to net_device structure
1204 * This implements Rx/Tx ISR poll mechanisms. The interrupts are disabled prior
1205 * to polling the ISRs and are enabled back after the polling is done.
1207 static void axienet_poll_controller(struct net_device
*ndev
)
1209 struct axienet_local
*lp
= netdev_priv(ndev
);
1210 disable_irq(lp
->tx_irq
);
1211 disable_irq(lp
->rx_irq
);
1212 axienet_rx_irq(lp
->tx_irq
, ndev
);
1213 axienet_tx_irq(lp
->rx_irq
, ndev
);
1214 enable_irq(lp
->tx_irq
);
1215 enable_irq(lp
->rx_irq
);
1219 static int axienet_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
1221 struct axienet_local
*lp
= netdev_priv(dev
);
1223 if (!netif_running(dev
))
1226 return phylink_mii_ioctl(lp
->phylink
, rq
, cmd
);
1229 static const struct net_device_ops axienet_netdev_ops
= {
1230 .ndo_open
= axienet_open
,
1231 .ndo_stop
= axienet_stop
,
1232 .ndo_start_xmit
= axienet_start_xmit
,
1233 .ndo_change_mtu
= axienet_change_mtu
,
1234 .ndo_set_mac_address
= netdev_set_mac_address
,
1235 .ndo_validate_addr
= eth_validate_addr
,
1236 .ndo_do_ioctl
= axienet_ioctl
,
1237 .ndo_set_rx_mode
= axienet_set_multicast_list
,
1238 #ifdef CONFIG_NET_POLL_CONTROLLER
1239 .ndo_poll_controller
= axienet_poll_controller
,
1244 * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information.
1245 * @ndev: Pointer to net_device structure
1246 * @ed: Pointer to ethtool_drvinfo structure
1248 * This implements ethtool command for getting the driver information.
1249 * Issue "ethtool -i ethX" under linux prompt to execute this function.
1251 static void axienet_ethtools_get_drvinfo(struct net_device
*ndev
,
1252 struct ethtool_drvinfo
*ed
)
1254 strlcpy(ed
->driver
, DRIVER_NAME
, sizeof(ed
->driver
));
1255 strlcpy(ed
->version
, DRIVER_VERSION
, sizeof(ed
->version
));
1259 * axienet_ethtools_get_regs_len - Get the total regs length present in the
1261 * @ndev: Pointer to net_device structure
1263 * This implements ethtool command for getting the total register length
1266 * Return: the total regs length
1268 static int axienet_ethtools_get_regs_len(struct net_device
*ndev
)
1270 return sizeof(u32
) * AXIENET_REGS_N
;
1274 * axienet_ethtools_get_regs - Dump the contents of all registers present
1275 * in AxiEthernet core.
1276 * @ndev: Pointer to net_device structure
1277 * @regs: Pointer to ethtool_regs structure
1278 * @ret: Void pointer used to return the contents of the registers.
1280 * This implements ethtool command for getting the Axi Ethernet register dump.
1281 * Issue "ethtool -d ethX" to execute this function.
1283 static void axienet_ethtools_get_regs(struct net_device
*ndev
,
1284 struct ethtool_regs
*regs
, void *ret
)
1286 u32
*data
= (u32
*) ret
;
1287 size_t len
= sizeof(u32
) * AXIENET_REGS_N
;
1288 struct axienet_local
*lp
= netdev_priv(ndev
);
1293 memset(data
, 0, len
);
1294 data
[0] = axienet_ior(lp
, XAE_RAF_OFFSET
);
1295 data
[1] = axienet_ior(lp
, XAE_TPF_OFFSET
);
1296 data
[2] = axienet_ior(lp
, XAE_IFGP_OFFSET
);
1297 data
[3] = axienet_ior(lp
, XAE_IS_OFFSET
);
1298 data
[4] = axienet_ior(lp
, XAE_IP_OFFSET
);
1299 data
[5] = axienet_ior(lp
, XAE_IE_OFFSET
);
1300 data
[6] = axienet_ior(lp
, XAE_TTAG_OFFSET
);
1301 data
[7] = axienet_ior(lp
, XAE_RTAG_OFFSET
);
1302 data
[8] = axienet_ior(lp
, XAE_UAWL_OFFSET
);
1303 data
[9] = axienet_ior(lp
, XAE_UAWU_OFFSET
);
1304 data
[10] = axienet_ior(lp
, XAE_TPID0_OFFSET
);
1305 data
[11] = axienet_ior(lp
, XAE_TPID1_OFFSET
);
1306 data
[12] = axienet_ior(lp
, XAE_PPST_OFFSET
);
1307 data
[13] = axienet_ior(lp
, XAE_RCW0_OFFSET
);
1308 data
[14] = axienet_ior(lp
, XAE_RCW1_OFFSET
);
1309 data
[15] = axienet_ior(lp
, XAE_TC_OFFSET
);
1310 data
[16] = axienet_ior(lp
, XAE_FCC_OFFSET
);
1311 data
[17] = axienet_ior(lp
, XAE_EMMC_OFFSET
);
1312 data
[18] = axienet_ior(lp
, XAE_PHYC_OFFSET
);
1313 data
[19] = axienet_ior(lp
, XAE_MDIO_MC_OFFSET
);
1314 data
[20] = axienet_ior(lp
, XAE_MDIO_MCR_OFFSET
);
1315 data
[21] = axienet_ior(lp
, XAE_MDIO_MWD_OFFSET
);
1316 data
[22] = axienet_ior(lp
, XAE_MDIO_MRD_OFFSET
);
1317 data
[27] = axienet_ior(lp
, XAE_UAW0_OFFSET
);
1318 data
[28] = axienet_ior(lp
, XAE_UAW1_OFFSET
);
1319 data
[29] = axienet_ior(lp
, XAE_FMI_OFFSET
);
1320 data
[30] = axienet_ior(lp
, XAE_AF0_OFFSET
);
1321 data
[31] = axienet_ior(lp
, XAE_AF1_OFFSET
);
1322 data
[32] = axienet_dma_in32(lp
, XAXIDMA_TX_CR_OFFSET
);
1323 data
[33] = axienet_dma_in32(lp
, XAXIDMA_TX_SR_OFFSET
);
1324 data
[34] = axienet_dma_in32(lp
, XAXIDMA_TX_CDESC_OFFSET
);
1325 data
[35] = axienet_dma_in32(lp
, XAXIDMA_TX_TDESC_OFFSET
);
1326 data
[36] = axienet_dma_in32(lp
, XAXIDMA_RX_CR_OFFSET
);
1327 data
[37] = axienet_dma_in32(lp
, XAXIDMA_RX_SR_OFFSET
);
1328 data
[38] = axienet_dma_in32(lp
, XAXIDMA_RX_CDESC_OFFSET
);
1329 data
[39] = axienet_dma_in32(lp
, XAXIDMA_RX_TDESC_OFFSET
);
1332 static void axienet_ethtools_get_ringparam(struct net_device
*ndev
,
1333 struct ethtool_ringparam
*ering
)
1335 struct axienet_local
*lp
= netdev_priv(ndev
);
1337 ering
->rx_max_pending
= RX_BD_NUM_MAX
;
1338 ering
->rx_mini_max_pending
= 0;
1339 ering
->rx_jumbo_max_pending
= 0;
1340 ering
->tx_max_pending
= TX_BD_NUM_MAX
;
1341 ering
->rx_pending
= lp
->rx_bd_num
;
1342 ering
->rx_mini_pending
= 0;
1343 ering
->rx_jumbo_pending
= 0;
1344 ering
->tx_pending
= lp
->tx_bd_num
;
1347 static int axienet_ethtools_set_ringparam(struct net_device
*ndev
,
1348 struct ethtool_ringparam
*ering
)
1350 struct axienet_local
*lp
= netdev_priv(ndev
);
1352 if (ering
->rx_pending
> RX_BD_NUM_MAX
||
1353 ering
->rx_mini_pending
||
1354 ering
->rx_jumbo_pending
||
1355 ering
->rx_pending
> TX_BD_NUM_MAX
)
1358 if (netif_running(ndev
))
1361 lp
->rx_bd_num
= ering
->rx_pending
;
1362 lp
->tx_bd_num
= ering
->tx_pending
;
1367 * axienet_ethtools_get_pauseparam - Get the pause parameter setting for
1369 * @ndev: Pointer to net_device structure
1370 * @epauseparm: Pointer to ethtool_pauseparam structure.
1372 * This implements ethtool command for getting axi ethernet pause frame
1373 * setting. Issue "ethtool -a ethX" to execute this function.
1376 axienet_ethtools_get_pauseparam(struct net_device
*ndev
,
1377 struct ethtool_pauseparam
*epauseparm
)
1379 struct axienet_local
*lp
= netdev_priv(ndev
);
1381 phylink_ethtool_get_pauseparam(lp
->phylink
, epauseparm
);
1385 * axienet_ethtools_set_pauseparam - Set device pause parameter(flow control)
1387 * @ndev: Pointer to net_device structure
1388 * @epauseparm:Pointer to ethtool_pauseparam structure
1390 * This implements ethtool command for enabling flow control on Rx and Tx
1391 * paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this
1394 * Return: 0 on success, -EFAULT if device is running
1397 axienet_ethtools_set_pauseparam(struct net_device
*ndev
,
1398 struct ethtool_pauseparam
*epauseparm
)
1400 struct axienet_local
*lp
= netdev_priv(ndev
);
1402 return phylink_ethtool_set_pauseparam(lp
->phylink
, epauseparm
);
1406 * axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count.
1407 * @ndev: Pointer to net_device structure
1408 * @ecoalesce: Pointer to ethtool_coalesce structure
1410 * This implements ethtool command for getting the DMA interrupt coalescing
1411 * count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to
1412 * execute this function.
1416 static int axienet_ethtools_get_coalesce(struct net_device
*ndev
,
1417 struct ethtool_coalesce
*ecoalesce
)
1420 struct axienet_local
*lp
= netdev_priv(ndev
);
1421 regval
= axienet_dma_in32(lp
, XAXIDMA_RX_CR_OFFSET
);
1422 ecoalesce
->rx_max_coalesced_frames
= (regval
& XAXIDMA_COALESCE_MASK
)
1423 >> XAXIDMA_COALESCE_SHIFT
;
1424 regval
= axienet_dma_in32(lp
, XAXIDMA_TX_CR_OFFSET
);
1425 ecoalesce
->tx_max_coalesced_frames
= (regval
& XAXIDMA_COALESCE_MASK
)
1426 >> XAXIDMA_COALESCE_SHIFT
;
1431 * axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count.
1432 * @ndev: Pointer to net_device structure
1433 * @ecoalesce: Pointer to ethtool_coalesce structure
1435 * This implements ethtool command for setting the DMA interrupt coalescing
1436 * count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux
1437 * prompt to execute this function.
1439 * Return: 0, on success, Non-zero error value on failure.
1441 static int axienet_ethtools_set_coalesce(struct net_device
*ndev
,
1442 struct ethtool_coalesce
*ecoalesce
)
1444 struct axienet_local
*lp
= netdev_priv(ndev
);
1446 if (netif_running(ndev
)) {
1448 "Please stop netif before applying configuration\n");
1452 if (ecoalesce
->rx_max_coalesced_frames
)
1453 lp
->coalesce_count_rx
= ecoalesce
->rx_max_coalesced_frames
;
1454 if (ecoalesce
->tx_max_coalesced_frames
)
1455 lp
->coalesce_count_tx
= ecoalesce
->tx_max_coalesced_frames
;
1461 axienet_ethtools_get_link_ksettings(struct net_device
*ndev
,
1462 struct ethtool_link_ksettings
*cmd
)
1464 struct axienet_local
*lp
= netdev_priv(ndev
);
1466 return phylink_ethtool_ksettings_get(lp
->phylink
, cmd
);
1470 axienet_ethtools_set_link_ksettings(struct net_device
*ndev
,
1471 const struct ethtool_link_ksettings
*cmd
)
1473 struct axienet_local
*lp
= netdev_priv(ndev
);
1475 return phylink_ethtool_ksettings_set(lp
->phylink
, cmd
);
1478 static const struct ethtool_ops axienet_ethtool_ops
= {
1479 .supported_coalesce_params
= ETHTOOL_COALESCE_MAX_FRAMES
,
1480 .get_drvinfo
= axienet_ethtools_get_drvinfo
,
1481 .get_regs_len
= axienet_ethtools_get_regs_len
,
1482 .get_regs
= axienet_ethtools_get_regs
,
1483 .get_link
= ethtool_op_get_link
,
1484 .get_ringparam
= axienet_ethtools_get_ringparam
,
1485 .set_ringparam
= axienet_ethtools_set_ringparam
,
1486 .get_pauseparam
= axienet_ethtools_get_pauseparam
,
1487 .set_pauseparam
= axienet_ethtools_set_pauseparam
,
1488 .get_coalesce
= axienet_ethtools_get_coalesce
,
1489 .set_coalesce
= axienet_ethtools_set_coalesce
,
1490 .get_link_ksettings
= axienet_ethtools_get_link_ksettings
,
1491 .set_link_ksettings
= axienet_ethtools_set_link_ksettings
,
1494 static void axienet_validate(struct phylink_config
*config
,
1495 unsigned long *supported
,
1496 struct phylink_link_state
*state
)
1498 struct net_device
*ndev
= to_net_dev(config
->dev
);
1499 struct axienet_local
*lp
= netdev_priv(ndev
);
1500 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
1502 /* Only support the mode we are configured for */
1503 if (state
->interface
!= PHY_INTERFACE_MODE_NA
&&
1504 state
->interface
!= lp
->phy_mode
) {
1505 netdev_warn(ndev
, "Cannot use PHY mode %s, supported: %s\n",
1506 phy_modes(state
->interface
),
1507 phy_modes(lp
->phy_mode
));
1508 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
1512 phylink_set(mask
, Autoneg
);
1513 phylink_set_port_modes(mask
);
1515 phylink_set(mask
, Asym_Pause
);
1516 phylink_set(mask
, Pause
);
1517 phylink_set(mask
, 1000baseX_Full
);
1518 phylink_set(mask
, 10baseT_Full
);
1519 phylink_set(mask
, 100baseT_Full
);
1520 phylink_set(mask
, 1000baseT_Full
);
1522 bitmap_and(supported
, supported
, mask
,
1523 __ETHTOOL_LINK_MODE_MASK_NBITS
);
1524 bitmap_and(state
->advertising
, state
->advertising
, mask
,
1525 __ETHTOOL_LINK_MODE_MASK_NBITS
);
1528 static void axienet_mac_pcs_get_state(struct phylink_config
*config
,
1529 struct phylink_link_state
*state
)
1531 struct net_device
*ndev
= to_net_dev(config
->dev
);
1532 struct axienet_local
*lp
= netdev_priv(ndev
);
1533 u32 emmc_reg
, fcc_reg
;
1535 state
->interface
= lp
->phy_mode
;
1537 emmc_reg
= axienet_ior(lp
, XAE_EMMC_OFFSET
);
1538 if (emmc_reg
& XAE_EMMC_LINKSPD_1000
)
1539 state
->speed
= SPEED_1000
;
1540 else if (emmc_reg
& XAE_EMMC_LINKSPD_100
)
1541 state
->speed
= SPEED_100
;
1543 state
->speed
= SPEED_10
;
1546 fcc_reg
= axienet_ior(lp
, XAE_FCC_OFFSET
);
1547 if (fcc_reg
& XAE_FCC_FCTX_MASK
)
1548 state
->pause
|= MLO_PAUSE_TX
;
1549 if (fcc_reg
& XAE_FCC_FCRX_MASK
)
1550 state
->pause
|= MLO_PAUSE_RX
;
1552 state
->an_complete
= 0;
1556 static void axienet_mac_an_restart(struct phylink_config
*config
)
1558 /* Unsupported, do nothing */
1561 static void axienet_mac_config(struct phylink_config
*config
, unsigned int mode
,
1562 const struct phylink_link_state
*state
)
1564 /* nothing meaningful to do */
1567 static void axienet_mac_link_down(struct phylink_config
*config
,
1569 phy_interface_t interface
)
1571 /* nothing meaningful to do */
1574 static void axienet_mac_link_up(struct phylink_config
*config
,
1575 struct phy_device
*phy
,
1576 unsigned int mode
, phy_interface_t interface
,
1577 int speed
, int duplex
,
1578 bool tx_pause
, bool rx_pause
)
1580 struct net_device
*ndev
= to_net_dev(config
->dev
);
1581 struct axienet_local
*lp
= netdev_priv(ndev
);
1582 u32 emmc_reg
, fcc_reg
;
1584 emmc_reg
= axienet_ior(lp
, XAE_EMMC_OFFSET
);
1585 emmc_reg
&= ~XAE_EMMC_LINKSPEED_MASK
;
1589 emmc_reg
|= XAE_EMMC_LINKSPD_1000
;
1592 emmc_reg
|= XAE_EMMC_LINKSPD_100
;
1595 emmc_reg
|= XAE_EMMC_LINKSPD_10
;
1599 "Speed other than 10, 100 or 1Gbps is not supported\n");
1603 axienet_iow(lp
, XAE_EMMC_OFFSET
, emmc_reg
);
1605 fcc_reg
= axienet_ior(lp
, XAE_FCC_OFFSET
);
1607 fcc_reg
|= XAE_FCC_FCTX_MASK
;
1609 fcc_reg
&= ~XAE_FCC_FCTX_MASK
;
1611 fcc_reg
|= XAE_FCC_FCRX_MASK
;
1613 fcc_reg
&= ~XAE_FCC_FCRX_MASK
;
1614 axienet_iow(lp
, XAE_FCC_OFFSET
, fcc_reg
);
1617 static const struct phylink_mac_ops axienet_phylink_ops
= {
1618 .validate
= axienet_validate
,
1619 .mac_pcs_get_state
= axienet_mac_pcs_get_state
,
1620 .mac_an_restart
= axienet_mac_an_restart
,
1621 .mac_config
= axienet_mac_config
,
1622 .mac_link_down
= axienet_mac_link_down
,
1623 .mac_link_up
= axienet_mac_link_up
,
1627 * axienet_dma_err_handler - Work queue task for Axi DMA Error
1628 * @work: pointer to work_struct
1630 * Resets the Axi DMA and Axi Ethernet devices, and reconfigures the
1633 static void axienet_dma_err_handler(struct work_struct
*work
)
1637 struct axienet_local
*lp
= container_of(work
, struct axienet_local
,
1639 struct net_device
*ndev
= lp
->ndev
;
1640 struct axidma_bd
*cur_p
;
1642 axienet_setoptions(ndev
, lp
->options
&
1643 ~(XAE_OPTION_TXEN
| XAE_OPTION_RXEN
));
1644 /* Disable the MDIO interface till Axi Ethernet Reset is completed.
1645 * When we do an Axi Ethernet reset, it resets the complete core
1646 * including the MDIO. MDIO must be disabled before resetting
1647 * and re-enabled afterwards.
1648 * Hold MDIO bus lock to avoid MDIO accesses during the reset.
1650 mutex_lock(&lp
->mii_bus
->mdio_lock
);
1651 axienet_mdio_disable(lp
);
1652 __axienet_device_reset(lp
);
1653 axienet_mdio_enable(lp
);
1654 mutex_unlock(&lp
->mii_bus
->mdio_lock
);
1656 for (i
= 0; i
< lp
->tx_bd_num
; i
++) {
1657 cur_p
= &lp
->tx_bd_v
[i
];
1659 dma_addr_t addr
= desc_get_phys_addr(lp
, cur_p
);
1661 dma_unmap_single(ndev
->dev
.parent
, addr
,
1663 XAXIDMA_BD_CTRL_LENGTH_MASK
),
1667 dev_kfree_skb_irq(cur_p
->skb
);
1669 cur_p
->phys_msb
= 0;
1680 for (i
= 0; i
< lp
->rx_bd_num
; i
++) {
1681 cur_p
= &lp
->rx_bd_v
[i
];
1694 /* Start updating the Rx channel control register */
1695 cr
= axienet_dma_in32(lp
, XAXIDMA_RX_CR_OFFSET
);
1696 /* Update the interrupt coalesce count */
1697 cr
= ((cr
& ~XAXIDMA_COALESCE_MASK
) |
1698 (XAXIDMA_DFT_RX_THRESHOLD
<< XAXIDMA_COALESCE_SHIFT
));
1699 /* Update the delay timer count */
1700 cr
= ((cr
& ~XAXIDMA_DELAY_MASK
) |
1701 (XAXIDMA_DFT_RX_WAITBOUND
<< XAXIDMA_DELAY_SHIFT
));
1702 /* Enable coalesce, delay timer and error interrupts */
1703 cr
|= XAXIDMA_IRQ_ALL_MASK
;
1704 /* Finally write to the Rx channel control register */
1705 axienet_dma_out32(lp
, XAXIDMA_RX_CR_OFFSET
, cr
);
1707 /* Start updating the Tx channel control register */
1708 cr
= axienet_dma_in32(lp
, XAXIDMA_TX_CR_OFFSET
);
1709 /* Update the interrupt coalesce count */
1710 cr
= (((cr
& ~XAXIDMA_COALESCE_MASK
)) |
1711 (XAXIDMA_DFT_TX_THRESHOLD
<< XAXIDMA_COALESCE_SHIFT
));
1712 /* Update the delay timer count */
1713 cr
= (((cr
& ~XAXIDMA_DELAY_MASK
)) |
1714 (XAXIDMA_DFT_TX_WAITBOUND
<< XAXIDMA_DELAY_SHIFT
));
1715 /* Enable coalesce, delay timer and error interrupts */
1716 cr
|= XAXIDMA_IRQ_ALL_MASK
;
1717 /* Finally write to the Tx channel control register */
1718 axienet_dma_out32(lp
, XAXIDMA_TX_CR_OFFSET
, cr
);
1720 /* Populate the tail pointer and bring the Rx Axi DMA engine out of
1721 * halted state. This will make the Rx side ready for reception.
1723 axienet_dma_out_addr(lp
, XAXIDMA_RX_CDESC_OFFSET
, lp
->rx_bd_p
);
1724 cr
= axienet_dma_in32(lp
, XAXIDMA_RX_CR_OFFSET
);
1725 axienet_dma_out32(lp
, XAXIDMA_RX_CR_OFFSET
,
1726 cr
| XAXIDMA_CR_RUNSTOP_MASK
);
1727 axienet_dma_out_addr(lp
, XAXIDMA_RX_TDESC_OFFSET
, lp
->rx_bd_p
+
1728 (sizeof(*lp
->rx_bd_v
) * (lp
->rx_bd_num
- 1)));
1730 /* Write to the RS (Run-stop) bit in the Tx channel control register.
1731 * Tx channel is now ready to run. But only after we write to the
1732 * tail pointer register that the Tx channel will start transmitting
1734 axienet_dma_out_addr(lp
, XAXIDMA_TX_CDESC_OFFSET
, lp
->tx_bd_p
);
1735 cr
= axienet_dma_in32(lp
, XAXIDMA_TX_CR_OFFSET
);
1736 axienet_dma_out32(lp
, XAXIDMA_TX_CR_OFFSET
,
1737 cr
| XAXIDMA_CR_RUNSTOP_MASK
);
1739 axienet_status
= axienet_ior(lp
, XAE_RCW1_OFFSET
);
1740 axienet_status
&= ~XAE_RCW1_RX_MASK
;
1741 axienet_iow(lp
, XAE_RCW1_OFFSET
, axienet_status
);
1743 axienet_status
= axienet_ior(lp
, XAE_IP_OFFSET
);
1744 if (axienet_status
& XAE_INT_RXRJECT_MASK
)
1745 axienet_iow(lp
, XAE_IS_OFFSET
, XAE_INT_RXRJECT_MASK
);
1746 axienet_iow(lp
, XAE_IE_OFFSET
, lp
->eth_irq
> 0 ?
1747 XAE_INT_RECV_ERROR_MASK
: 0);
1748 axienet_iow(lp
, XAE_FCC_OFFSET
, XAE_FCC_FCRX_MASK
);
1750 /* Sync default options with HW but leave receiver and
1751 * transmitter disabled.
1753 axienet_setoptions(ndev
, lp
->options
&
1754 ~(XAE_OPTION_TXEN
| XAE_OPTION_RXEN
));
1755 axienet_set_mac_address(ndev
, NULL
);
1756 axienet_set_multicast_list(ndev
);
1757 axienet_setoptions(ndev
, lp
->options
);
1761 * axienet_probe - Axi Ethernet probe function.
1762 * @pdev: Pointer to platform device structure.
1764 * Return: 0, on success
1765 * Non-zero error value on failure.
1767 * This is the probe routine for Axi Ethernet driver. This is called before
1768 * any other driver routines are invoked. It allocates and sets up the Ethernet
1769 * device. Parses through device tree and populates fields of
1770 * axienet_local. It registers the Ethernet device.
1772 static int axienet_probe(struct platform_device
*pdev
)
1775 struct device_node
*np
;
1776 struct axienet_local
*lp
;
1777 struct net_device
*ndev
;
1778 const void *mac_addr
;
1779 struct resource
*ethres
;
1782 ndev
= alloc_etherdev(sizeof(*lp
));
1786 platform_set_drvdata(pdev
, ndev
);
1788 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1789 ndev
->flags
&= ~IFF_MULTICAST
; /* clear multicast */
1790 ndev
->features
= NETIF_F_SG
;
1791 ndev
->netdev_ops
= &axienet_netdev_ops
;
1792 ndev
->ethtool_ops
= &axienet_ethtool_ops
;
1794 /* MTU range: 64 - 9000 */
1796 ndev
->max_mtu
= XAE_JUMBO_MTU
;
1798 lp
= netdev_priv(ndev
);
1800 lp
->dev
= &pdev
->dev
;
1801 lp
->options
= XAE_OPTION_DEFAULTS
;
1802 lp
->rx_bd_num
= RX_BD_NUM_DEFAULT
;
1803 lp
->tx_bd_num
= TX_BD_NUM_DEFAULT
;
1804 /* Map device registers */
1805 ethres
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1806 lp
->regs
= devm_ioremap_resource(&pdev
->dev
, ethres
);
1807 if (IS_ERR(lp
->regs
)) {
1808 dev_err(&pdev
->dev
, "could not map Axi Ethernet regs.\n");
1809 ret
= PTR_ERR(lp
->regs
);
1812 lp
->regs_start
= ethres
->start
;
1814 /* Setup checksum offload, but default to off if not specified */
1817 ret
= of_property_read_u32(pdev
->dev
.of_node
, "xlnx,txcsum", &value
);
1821 lp
->csum_offload_on_tx_path
=
1822 XAE_FEATURE_PARTIAL_TX_CSUM
;
1823 lp
->features
|= XAE_FEATURE_PARTIAL_TX_CSUM
;
1824 /* Can checksum TCP/UDP over IPv4. */
1825 ndev
->features
|= NETIF_F_IP_CSUM
;
1828 lp
->csum_offload_on_tx_path
=
1829 XAE_FEATURE_FULL_TX_CSUM
;
1830 lp
->features
|= XAE_FEATURE_FULL_TX_CSUM
;
1831 /* Can checksum TCP/UDP over IPv4. */
1832 ndev
->features
|= NETIF_F_IP_CSUM
;
1835 lp
->csum_offload_on_tx_path
= XAE_NO_CSUM_OFFLOAD
;
1838 ret
= of_property_read_u32(pdev
->dev
.of_node
, "xlnx,rxcsum", &value
);
1842 lp
->csum_offload_on_rx_path
=
1843 XAE_FEATURE_PARTIAL_RX_CSUM
;
1844 lp
->features
|= XAE_FEATURE_PARTIAL_RX_CSUM
;
1847 lp
->csum_offload_on_rx_path
=
1848 XAE_FEATURE_FULL_RX_CSUM
;
1849 lp
->features
|= XAE_FEATURE_FULL_RX_CSUM
;
1852 lp
->csum_offload_on_rx_path
= XAE_NO_CSUM_OFFLOAD
;
1855 /* For supporting jumbo frames, the Axi Ethernet hardware must have
1856 * a larger Rx/Tx Memory. Typically, the size must be large so that
1857 * we can enable jumbo option and start supporting jumbo frames.
1858 * Here we check for memory allocated for Rx/Tx in the hardware from
1859 * the device-tree and accordingly set flags.
1861 of_property_read_u32(pdev
->dev
.of_node
, "xlnx,rxmem", &lp
->rxmem
);
1863 /* Start with the proprietary, and broken phy_type */
1864 ret
= of_property_read_u32(pdev
->dev
.of_node
, "xlnx,phy-type", &value
);
1866 netdev_warn(ndev
, "Please upgrade your device tree binary blob to use phy-mode");
1868 case XAE_PHY_TYPE_MII
:
1869 lp
->phy_mode
= PHY_INTERFACE_MODE_MII
;
1871 case XAE_PHY_TYPE_GMII
:
1872 lp
->phy_mode
= PHY_INTERFACE_MODE_GMII
;
1874 case XAE_PHY_TYPE_RGMII_2_0
:
1875 lp
->phy_mode
= PHY_INTERFACE_MODE_RGMII_ID
;
1877 case XAE_PHY_TYPE_SGMII
:
1878 lp
->phy_mode
= PHY_INTERFACE_MODE_SGMII
;
1880 case XAE_PHY_TYPE_1000BASE_X
:
1881 lp
->phy_mode
= PHY_INTERFACE_MODE_1000BASEX
;
1888 ret
= of_get_phy_mode(pdev
->dev
.of_node
, &lp
->phy_mode
);
1893 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1894 np
= of_parse_phandle(pdev
->dev
.of_node
, "axistream-connected", 0);
1896 struct resource dmares
;
1898 ret
= of_address_to_resource(np
, 0, &dmares
);
1901 "unable to get DMA resource\n");
1905 lp
->dma_regs
= devm_ioremap_resource(&pdev
->dev
,
1907 lp
->rx_irq
= irq_of_parse_and_map(np
, 1);
1908 lp
->tx_irq
= irq_of_parse_and_map(np
, 0);
1910 lp
->eth_irq
= platform_get_irq_optional(pdev
, 0);
1912 /* Check for these resources directly on the Ethernet node. */
1913 struct resource
*res
= platform_get_resource(pdev
,
1915 lp
->dma_regs
= devm_ioremap_resource(&pdev
->dev
, res
);
1916 lp
->rx_irq
= platform_get_irq(pdev
, 1);
1917 lp
->tx_irq
= platform_get_irq(pdev
, 0);
1918 lp
->eth_irq
= platform_get_irq_optional(pdev
, 2);
1920 if (IS_ERR(lp
->dma_regs
)) {
1921 dev_err(&pdev
->dev
, "could not map DMA regs\n");
1922 ret
= PTR_ERR(lp
->dma_regs
);
1925 if ((lp
->rx_irq
<= 0) || (lp
->tx_irq
<= 0)) {
1926 dev_err(&pdev
->dev
, "could not determine irqs\n");
1931 /* Check for Ethernet core IRQ (optional) */
1932 if (lp
->eth_irq
<= 0)
1933 dev_info(&pdev
->dev
, "Ethernet core IRQ not defined\n");
1935 /* Retrieve the MAC address */
1936 mac_addr
= of_get_mac_address(pdev
->dev
.of_node
);
1937 if (IS_ERR(mac_addr
)) {
1938 dev_warn(&pdev
->dev
, "could not find MAC address property: %ld\n",
1942 axienet_set_mac_address(ndev
, mac_addr
);
1944 lp
->coalesce_count_rx
= XAXIDMA_DFT_RX_THRESHOLD
;
1945 lp
->coalesce_count_tx
= XAXIDMA_DFT_TX_THRESHOLD
;
1947 lp
->phy_node
= of_parse_phandle(pdev
->dev
.of_node
, "phy-handle", 0);
1949 lp
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1950 if (IS_ERR(lp
->clk
)) {
1951 dev_warn(&pdev
->dev
, "Failed to get clock: %ld\n",
1955 ret
= clk_prepare_enable(lp
->clk
);
1957 dev_err(&pdev
->dev
, "Unable to enable clock: %d\n",
1963 ret
= axienet_mdio_setup(lp
);
1965 dev_warn(&pdev
->dev
,
1966 "error registering MDIO bus: %d\n", ret
);
1969 lp
->phylink_config
.dev
= &ndev
->dev
;
1970 lp
->phylink_config
.type
= PHYLINK_NETDEV
;
1972 lp
->phylink
= phylink_create(&lp
->phylink_config
, pdev
->dev
.fwnode
,
1974 &axienet_phylink_ops
);
1975 if (IS_ERR(lp
->phylink
)) {
1976 ret
= PTR_ERR(lp
->phylink
);
1977 dev_err(&pdev
->dev
, "phylink_create error (%i)\n", ret
);
1981 ret
= register_netdev(lp
->ndev
);
1983 dev_err(lp
->dev
, "register_netdev() error (%i)\n", ret
);
1995 static int axienet_remove(struct platform_device
*pdev
)
1997 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1998 struct axienet_local
*lp
= netdev_priv(ndev
);
2000 unregister_netdev(ndev
);
2003 phylink_destroy(lp
->phylink
);
2005 axienet_mdio_teardown(lp
);
2008 clk_disable_unprepare(lp
->clk
);
2010 of_node_put(lp
->phy_node
);
2011 lp
->phy_node
= NULL
;
2018 static void axienet_shutdown(struct platform_device
*pdev
)
2020 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2023 netif_device_detach(ndev
);
2025 if (netif_running(ndev
))
2031 static struct platform_driver axienet_driver
= {
2032 .probe
= axienet_probe
,
2033 .remove
= axienet_remove
,
2034 .shutdown
= axienet_shutdown
,
2036 .name
= "xilinx_axienet",
2037 .of_match_table
= axienet_of_match
,
2041 module_platform_driver(axienet_driver
);
2043 MODULE_DESCRIPTION("Xilinx Axi Ethernet driver");
2044 MODULE_AUTHOR("Xilinx");
2045 MODULE_LICENSE("GPL");