2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/workqueue.h>
38 #include <linux/bitops.h>
40 #include <linux/irq.h>
41 #include <linux/clk.h>
42 #include <linux/platform_device.h>
43 #include <linux/phy.h>
45 #include <asm/cacheflush.h>
47 #ifndef CONFIG_ARCH_MXC
48 #include <asm/coldfire.h>
49 #include <asm/mcfsim.h>
54 #ifdef CONFIG_ARCH_MXC
55 #include <mach/hardware.h>
56 #define FEC_ALIGNMENT 0xf
58 #define FEC_ALIGNMENT 0x3
62 * Define the fixed address of the FEC hardware.
64 #if defined(CONFIG_M5272)
66 static unsigned char fec_mac_default
[] = {
67 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
71 * Some hardware gets it MAC address out of local flash memory.
72 * if this is non-zero then assume it is the address to get MAC from.
74 #if defined(CONFIG_NETtel)
75 #define FEC_FLASHMAC 0xf0006006
76 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
77 #define FEC_FLASHMAC 0xf0006000
78 #elif defined(CONFIG_CANCam)
79 #define FEC_FLASHMAC 0xf0020000
80 #elif defined (CONFIG_M5272C3)
81 #define FEC_FLASHMAC (0xffe04000 + 4)
82 #elif defined(CONFIG_MOD5272)
83 #define FEC_FLASHMAC 0xffc0406b
85 #define FEC_FLASHMAC 0
87 #endif /* CONFIG_M5272 */
89 /* The number of Tx and Rx buffers. These are allocated from the page
90 * pool. The code may assume these are power of two, so it it best
91 * to keep them that size.
92 * We don't need to allocate pages for the transmitter. We just use
93 * the skbuffer directly.
95 #define FEC_ENET_RX_PAGES 8
96 #define FEC_ENET_RX_FRSIZE 2048
97 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
98 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
99 #define FEC_ENET_TX_FRSIZE 2048
100 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
101 #define TX_RING_SIZE 16 /* Must be power of two */
102 #define TX_RING_MOD_MASK 15 /* for this to work */
104 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
105 #error "FEC: descriptor ring size constants too large"
108 /* Interrupt events/masks. */
109 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
110 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
111 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
112 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
113 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
114 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
115 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
116 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
117 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
118 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
120 /* The FEC stores dest/src/type, data, and checksum for receive packets.
122 #define PKT_MAXBUF_SIZE 1518
123 #define PKT_MINBUF_SIZE 64
124 #define PKT_MAXBLR_SIZE 1520
128 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
129 * size bits. Other FEC hardware does not, so we need to take that into
130 * account when setting it.
132 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
133 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
134 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
136 #define OPT_FRAME_SIZE 0
139 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
140 * tx_bd_base always point to the base of the buffer descriptors. The
141 * cur_rx and cur_tx point to the currently available buffer.
142 * The dirty_tx tracks the current buffer that is being sent by the
143 * controller. The cur_tx and dirty_tx are equal under both completely
144 * empty and completely full conditions. The empty/ready indicator in
145 * the buffer descriptor determines the actual condition.
147 struct fec_enet_private
{
148 /* Hardware registers of the FEC device */
151 struct net_device
*netdev
;
155 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
156 unsigned char *tx_bounce
[TX_RING_SIZE
];
157 struct sk_buff
* tx_skbuff
[TX_RING_SIZE
];
158 struct sk_buff
* rx_skbuff
[RX_RING_SIZE
];
162 /* CPM dual port RAM relative addresses */
164 /* Address of Rx and Tx buffers */
165 struct bufdesc
*rx_bd_base
;
166 struct bufdesc
*tx_bd_base
;
167 /* The next free ring entry */
168 struct bufdesc
*cur_rx
, *cur_tx
;
169 /* The ring entries to be free()ed */
170 struct bufdesc
*dirty_tx
;
173 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
176 struct platform_device
*pdev
;
180 /* Phylib and MDIO interface */
181 struct mii_bus
*mii_bus
;
182 struct phy_device
*phy_dev
;
190 static irqreturn_t
fec_enet_interrupt(int irq
, void * dev_id
);
191 static void fec_enet_tx(struct net_device
*dev
);
192 static void fec_enet_rx(struct net_device
*dev
);
193 static int fec_enet_close(struct net_device
*dev
);
194 static void fec_restart(struct net_device
*dev
, int duplex
);
195 static void fec_stop(struct net_device
*dev
);
197 /* FEC MII MMFR bits definition */
198 #define FEC_MMFR_ST (1 << 30)
199 #define FEC_MMFR_OP_READ (2 << 28)
200 #define FEC_MMFR_OP_WRITE (1 << 28)
201 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
202 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
203 #define FEC_MMFR_TA (2 << 16)
204 #define FEC_MMFR_DATA(v) (v & 0xffff)
206 #define FEC_MII_TIMEOUT 10000
208 /* Transmitter timeout */
209 #define TX_TIMEOUT (2 * HZ)
212 fec_enet_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
214 struct fec_enet_private
*fep
= netdev_priv(dev
);
217 unsigned short status
;
221 /* Link is down or autonegotiation is in progress. */
222 return NETDEV_TX_BUSY
;
225 spin_lock_irqsave(&fep
->hw_lock
, flags
);
226 /* Fill in a Tx ring entry */
229 status
= bdp
->cbd_sc
;
231 if (status
& BD_ENET_TX_READY
) {
232 /* Ooops. All transmit buffers are full. Bail out.
233 * This should not happen, since dev->tbusy should be set.
235 printk("%s: tx queue full!.\n", dev
->name
);
236 spin_unlock_irqrestore(&fep
->hw_lock
, flags
);
237 return NETDEV_TX_BUSY
;
240 /* Clear all of the status flags */
241 status
&= ~BD_ENET_TX_STATS
;
243 /* Set buffer length and buffer pointer */
245 bdp
->cbd_datlen
= skb
->len
;
248 * On some FEC implementations data must be aligned on
249 * 4-byte boundaries. Use bounce buffers to copy data
250 * and get it aligned. Ugh.
252 if (((unsigned long) bufaddr
) & FEC_ALIGNMENT
) {
254 index
= bdp
- fep
->tx_bd_base
;
255 memcpy(fep
->tx_bounce
[index
], (void *)skb
->data
, skb
->len
);
256 bufaddr
= fep
->tx_bounce
[index
];
259 /* Save skb pointer */
260 fep
->tx_skbuff
[fep
->skb_cur
] = skb
;
262 dev
->stats
.tx_bytes
+= skb
->len
;
263 fep
->skb_cur
= (fep
->skb_cur
+1) & TX_RING_MOD_MASK
;
265 /* Push the data cache so the CPM does not get stale memory
268 bdp
->cbd_bufaddr
= dma_map_single(&dev
->dev
, bufaddr
,
269 FEC_ENET_TX_FRSIZE
, DMA_TO_DEVICE
);
271 /* Send it on its way. Tell FEC it's ready, interrupt when done,
272 * it's the last BD of the frame, and to put the CRC on the end.
274 status
|= (BD_ENET_TX_READY
| BD_ENET_TX_INTR
275 | BD_ENET_TX_LAST
| BD_ENET_TX_TC
);
276 bdp
->cbd_sc
= status
;
278 /* Trigger transmission start */
279 writel(0, fep
->hwp
+ FEC_X_DES_ACTIVE
);
281 /* If this was the last BD in the ring, start at the beginning again. */
282 if (status
& BD_ENET_TX_WRAP
)
283 bdp
= fep
->tx_bd_base
;
287 if (bdp
== fep
->dirty_tx
) {
289 netif_stop_queue(dev
);
294 spin_unlock_irqrestore(&fep
->hw_lock
, flags
);
300 fec_timeout(struct net_device
*dev
)
302 struct fec_enet_private
*fep
= netdev_priv(dev
);
304 dev
->stats
.tx_errors
++;
306 fec_restart(dev
, fep
->full_duplex
);
307 netif_wake_queue(dev
);
311 fec_enet_interrupt(int irq
, void * dev_id
)
313 struct net_device
*dev
= dev_id
;
314 struct fec_enet_private
*fep
= netdev_priv(dev
);
316 irqreturn_t ret
= IRQ_NONE
;
319 int_events
= readl(fep
->hwp
+ FEC_IEVENT
);
320 writel(int_events
, fep
->hwp
+ FEC_IEVENT
);
322 if (int_events
& FEC_ENET_RXF
) {
327 /* Transmit OK, or non-fatal error. Update the buffer
328 * descriptors. FEC handles all errors, we just discover
329 * them as part of the transmit process.
331 if (int_events
& FEC_ENET_TXF
) {
335 } while (int_events
);
342 fec_enet_tx(struct net_device
*dev
)
344 struct fec_enet_private
*fep
;
346 unsigned short status
;
349 fep
= netdev_priv(dev
);
350 spin_lock(&fep
->hw_lock
);
353 while (((status
= bdp
->cbd_sc
) & BD_ENET_TX_READY
) == 0) {
354 if (bdp
== fep
->cur_tx
&& fep
->tx_full
== 0)
357 dma_unmap_single(&dev
->dev
, bdp
->cbd_bufaddr
, FEC_ENET_TX_FRSIZE
, DMA_TO_DEVICE
);
358 bdp
->cbd_bufaddr
= 0;
360 skb
= fep
->tx_skbuff
[fep
->skb_dirty
];
361 /* Check for errors. */
362 if (status
& (BD_ENET_TX_HB
| BD_ENET_TX_LC
|
363 BD_ENET_TX_RL
| BD_ENET_TX_UN
|
365 dev
->stats
.tx_errors
++;
366 if (status
& BD_ENET_TX_HB
) /* No heartbeat */
367 dev
->stats
.tx_heartbeat_errors
++;
368 if (status
& BD_ENET_TX_LC
) /* Late collision */
369 dev
->stats
.tx_window_errors
++;
370 if (status
& BD_ENET_TX_RL
) /* Retrans limit */
371 dev
->stats
.tx_aborted_errors
++;
372 if (status
& BD_ENET_TX_UN
) /* Underrun */
373 dev
->stats
.tx_fifo_errors
++;
374 if (status
& BD_ENET_TX_CSL
) /* Carrier lost */
375 dev
->stats
.tx_carrier_errors
++;
377 dev
->stats
.tx_packets
++;
380 if (status
& BD_ENET_TX_READY
)
381 printk("HEY! Enet xmit interrupt and TX_READY.\n");
383 /* Deferred means some collisions occurred during transmit,
384 * but we eventually sent the packet OK.
386 if (status
& BD_ENET_TX_DEF
)
387 dev
->stats
.collisions
++;
389 /* Free the sk buffer associated with this last transmit */
390 dev_kfree_skb_any(skb
);
391 fep
->tx_skbuff
[fep
->skb_dirty
] = NULL
;
392 fep
->skb_dirty
= (fep
->skb_dirty
+ 1) & TX_RING_MOD_MASK
;
394 /* Update pointer to next buffer descriptor to be transmitted */
395 if (status
& BD_ENET_TX_WRAP
)
396 bdp
= fep
->tx_bd_base
;
400 /* Since we have freed up a buffer, the ring is no longer full
404 if (netif_queue_stopped(dev
))
405 netif_wake_queue(dev
);
409 spin_unlock(&fep
->hw_lock
);
413 /* During a receive, the cur_rx points to the current incoming buffer.
414 * When we update through the ring, if the next incoming buffer has
415 * not been given to the system, we just set the empty indicator,
416 * effectively tossing the packet.
419 fec_enet_rx(struct net_device
*dev
)
421 struct fec_enet_private
*fep
= netdev_priv(dev
);
423 unsigned short status
;
432 spin_lock(&fep
->hw_lock
);
434 /* First, grab all of the stats for the incoming packet.
435 * These get messed up if we get called due to a busy condition.
439 while (!((status
= bdp
->cbd_sc
) & BD_ENET_RX_EMPTY
)) {
441 /* Since we have allocated space to hold a complete frame,
442 * the last indicator should be set.
444 if ((status
& BD_ENET_RX_LAST
) == 0)
445 printk("FEC ENET: rcv is not +last\n");
448 goto rx_processing_done
;
450 /* Check for errors. */
451 if (status
& (BD_ENET_RX_LG
| BD_ENET_RX_SH
| BD_ENET_RX_NO
|
452 BD_ENET_RX_CR
| BD_ENET_RX_OV
)) {
453 dev
->stats
.rx_errors
++;
454 if (status
& (BD_ENET_RX_LG
| BD_ENET_RX_SH
)) {
455 /* Frame too long or too short. */
456 dev
->stats
.rx_length_errors
++;
458 if (status
& BD_ENET_RX_NO
) /* Frame alignment */
459 dev
->stats
.rx_frame_errors
++;
460 if (status
& BD_ENET_RX_CR
) /* CRC Error */
461 dev
->stats
.rx_crc_errors
++;
462 if (status
& BD_ENET_RX_OV
) /* FIFO overrun */
463 dev
->stats
.rx_fifo_errors
++;
466 /* Report late collisions as a frame error.
467 * On this error, the BD is closed, but we don't know what we
468 * have in the buffer. So, just drop this frame on the floor.
470 if (status
& BD_ENET_RX_CL
) {
471 dev
->stats
.rx_errors
++;
472 dev
->stats
.rx_frame_errors
++;
473 goto rx_processing_done
;
476 /* Process the incoming frame. */
477 dev
->stats
.rx_packets
++;
478 pkt_len
= bdp
->cbd_datlen
;
479 dev
->stats
.rx_bytes
+= pkt_len
;
480 data
= (__u8
*)__va(bdp
->cbd_bufaddr
);
482 dma_unmap_single(NULL
, bdp
->cbd_bufaddr
, bdp
->cbd_datlen
,
485 /* This does 16 byte alignment, exactly what we need.
486 * The packet length includes FCS, but we don't want to
487 * include that when passing upstream as it messes up
488 * bridging applications.
490 skb
= dev_alloc_skb(pkt_len
- 4 + NET_IP_ALIGN
);
492 if (unlikely(!skb
)) {
493 printk("%s: Memory squeeze, dropping packet.\n",
495 dev
->stats
.rx_dropped
++;
497 skb_reserve(skb
, NET_IP_ALIGN
);
498 skb_put(skb
, pkt_len
- 4); /* Make room */
499 skb_copy_to_linear_data(skb
, data
, pkt_len
- 4);
500 skb
->protocol
= eth_type_trans(skb
, dev
);
504 bdp
->cbd_bufaddr
= dma_map_single(NULL
, data
, bdp
->cbd_datlen
,
507 /* Clear the status flags for this buffer */
508 status
&= ~BD_ENET_RX_STATS
;
510 /* Mark the buffer empty */
511 status
|= BD_ENET_RX_EMPTY
;
512 bdp
->cbd_sc
= status
;
514 /* Update BD pointer to next entry */
515 if (status
& BD_ENET_RX_WRAP
)
516 bdp
= fep
->rx_bd_base
;
519 /* Doing this here will keep the FEC running while we process
520 * incoming frames. On a heavily loaded network, we should be
521 * able to keep up at the expense of system resources.
523 writel(0, fep
->hwp
+ FEC_R_DES_ACTIVE
);
527 spin_unlock(&fep
->hw_lock
);
530 /* ------------------------------------------------------------------------- */
532 static void __inline__
fec_get_mac(struct net_device
*dev
)
534 struct fec_enet_private
*fep
= netdev_priv(dev
);
535 unsigned char *iap
, tmpaddr
[ETH_ALEN
];
539 * Get MAC address from FLASH.
540 * If it is all 1's or 0's, use the default.
542 iap
= (unsigned char *)FEC_FLASHMAC
;
543 if ((iap
[0] == 0) && (iap
[1] == 0) && (iap
[2] == 0) &&
544 (iap
[3] == 0) && (iap
[4] == 0) && (iap
[5] == 0))
545 iap
= fec_mac_default
;
546 if ((iap
[0] == 0xff) && (iap
[1] == 0xff) && (iap
[2] == 0xff) &&
547 (iap
[3] == 0xff) && (iap
[4] == 0xff) && (iap
[5] == 0xff))
548 iap
= fec_mac_default
;
550 *((unsigned long *) &tmpaddr
[0]) = readl(fep
->hwp
+ FEC_ADDR_LOW
);
551 *((unsigned short *) &tmpaddr
[4]) = (readl(fep
->hwp
+ FEC_ADDR_HIGH
) >> 16);
555 memcpy(dev
->dev_addr
, iap
, ETH_ALEN
);
557 /* Adjust MAC if using default MAC address */
558 if (iap
== fec_mac_default
)
559 dev
->dev_addr
[ETH_ALEN
-1] = fec_mac_default
[ETH_ALEN
-1] + fep
->index
;
563 /* ------------------------------------------------------------------------- */
568 static void fec_enet_adjust_link(struct net_device
*dev
)
570 struct fec_enet_private
*fep
= netdev_priv(dev
);
571 struct phy_device
*phy_dev
= fep
->phy_dev
;
574 int status_change
= 0;
576 spin_lock_irqsave(&fep
->hw_lock
, flags
);
578 /* Prevent a state halted on mii error */
579 if (fep
->mii_timeout
&& phy_dev
->state
== PHY_HALTED
) {
580 phy_dev
->state
= PHY_RESUMING
;
584 /* Duplex link change */
586 if (fep
->full_duplex
!= phy_dev
->duplex
) {
587 fec_restart(dev
, phy_dev
->duplex
);
592 /* Link on or off change */
593 if (phy_dev
->link
!= fep
->link
) {
594 fep
->link
= phy_dev
->link
;
596 fec_restart(dev
, phy_dev
->duplex
);
603 spin_unlock_irqrestore(&fep
->hw_lock
, flags
);
606 phy_print_status(phy_dev
);
610 * NOTE: a MII transaction is during around 25 us, so polling it...
612 static int fec_enet_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
614 struct fec_enet_private
*fep
= bus
->priv
;
615 int timeout
= FEC_MII_TIMEOUT
;
617 fep
->mii_timeout
= 0;
619 /* clear MII end of transfer bit*/
620 writel(FEC_ENET_MII
, fep
->hwp
+ FEC_IEVENT
);
622 /* start a read op */
623 writel(FEC_MMFR_ST
| FEC_MMFR_OP_READ
|
624 FEC_MMFR_PA(mii_id
) | FEC_MMFR_RA(regnum
) |
625 FEC_MMFR_TA
, fep
->hwp
+ FEC_MII_DATA
);
627 /* wait for end of transfer */
628 while (!(readl(fep
->hwp
+ FEC_IEVENT
) & FEC_ENET_MII
)) {
631 fep
->mii_timeout
= 1;
632 printk(KERN_ERR
"FEC: MDIO read timeout\n");
638 return FEC_MMFR_DATA(readl(fep
->hwp
+ FEC_MII_DATA
));
641 static int fec_enet_mdio_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
644 struct fec_enet_private
*fep
= bus
->priv
;
645 int timeout
= FEC_MII_TIMEOUT
;
647 fep
->mii_timeout
= 0;
649 /* clear MII end of transfer bit*/
650 writel(FEC_ENET_MII
, fep
->hwp
+ FEC_IEVENT
);
652 /* start a read op */
653 writel(FEC_MMFR_ST
| FEC_MMFR_OP_READ
|
654 FEC_MMFR_PA(mii_id
) | FEC_MMFR_RA(regnum
) |
655 FEC_MMFR_TA
| FEC_MMFR_DATA(value
),
656 fep
->hwp
+ FEC_MII_DATA
);
658 /* wait for end of transfer */
659 while (!(readl(fep
->hwp
+ FEC_IEVENT
) & FEC_ENET_MII
)) {
662 fep
->mii_timeout
= 1;
663 printk(KERN_ERR
"FEC: MDIO write timeout\n");
671 static int fec_enet_mdio_reset(struct mii_bus
*bus
)
676 static int fec_enet_mii_probe(struct net_device
*dev
)
678 struct fec_enet_private
*fep
= netdev_priv(dev
);
679 struct phy_device
*phy_dev
= NULL
;
682 /* find the first phy */
683 for (phy_addr
= 0; phy_addr
< PHY_MAX_ADDR
; phy_addr
++) {
684 if (fep
->mii_bus
->phy_map
[phy_addr
]) {
685 phy_dev
= fep
->mii_bus
->phy_map
[phy_addr
];
691 printk(KERN_ERR
"%s: no PHY found\n", dev
->name
);
695 /* attach the mac to the phy */
696 phy_dev
= phy_connect(dev
, dev_name(&phy_dev
->dev
),
697 &fec_enet_adjust_link
, 0,
698 PHY_INTERFACE_MODE_MII
);
699 if (IS_ERR(phy_dev
)) {
700 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
701 return PTR_ERR(phy_dev
);
704 /* mask with MAC supported features */
705 phy_dev
->supported
&= PHY_BASIC_FEATURES
;
706 phy_dev
->advertising
= phy_dev
->supported
;
708 fep
->phy_dev
= phy_dev
;
710 fep
->full_duplex
= 0;
715 static int fec_enet_mii_init(struct platform_device
*pdev
)
717 struct net_device
*dev
= platform_get_drvdata(pdev
);
718 struct fec_enet_private
*fep
= netdev_priv(dev
);
721 fep
->mii_timeout
= 0;
724 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
726 fep
->phy_speed
= DIV_ROUND_UP(clk_get_rate(fep
->clk
), 5000000) << 1;
727 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
729 fep
->mii_bus
= mdiobus_alloc();
730 if (fep
->mii_bus
== NULL
) {
735 fep
->mii_bus
->name
= "fec_enet_mii_bus";
736 fep
->mii_bus
->read
= fec_enet_mdio_read
;
737 fep
->mii_bus
->write
= fec_enet_mdio_write
;
738 fep
->mii_bus
->reset
= fec_enet_mdio_reset
;
739 snprintf(fep
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%x", pdev
->id
);
740 fep
->mii_bus
->priv
= fep
;
741 fep
->mii_bus
->parent
= &pdev
->dev
;
743 fep
->mii_bus
->irq
= kmalloc(sizeof(int) * PHY_MAX_ADDR
, GFP_KERNEL
);
744 if (!fep
->mii_bus
->irq
) {
746 goto err_out_free_mdiobus
;
749 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
750 fep
->mii_bus
->irq
[i
] = PHY_POLL
;
752 platform_set_drvdata(dev
, fep
->mii_bus
);
754 if (mdiobus_register(fep
->mii_bus
))
755 goto err_out_free_mdio_irq
;
757 if (fec_enet_mii_probe(dev
) != 0)
758 goto err_out_unregister_bus
;
762 err_out_unregister_bus
:
763 mdiobus_unregister(fep
->mii_bus
);
764 err_out_free_mdio_irq
:
765 kfree(fep
->mii_bus
->irq
);
766 err_out_free_mdiobus
:
767 mdiobus_free(fep
->mii_bus
);
772 static void fec_enet_mii_remove(struct fec_enet_private
*fep
)
775 phy_disconnect(fep
->phy_dev
);
776 mdiobus_unregister(fep
->mii_bus
);
777 kfree(fep
->mii_bus
->irq
);
778 mdiobus_free(fep
->mii_bus
);
781 static int fec_enet_get_settings(struct net_device
*dev
,
782 struct ethtool_cmd
*cmd
)
784 struct fec_enet_private
*fep
= netdev_priv(dev
);
785 struct phy_device
*phydev
= fep
->phy_dev
;
790 return phy_ethtool_gset(phydev
, cmd
);
793 static int fec_enet_set_settings(struct net_device
*dev
,
794 struct ethtool_cmd
*cmd
)
796 struct fec_enet_private
*fep
= netdev_priv(dev
);
797 struct phy_device
*phydev
= fep
->phy_dev
;
802 return phy_ethtool_sset(phydev
, cmd
);
805 static void fec_enet_get_drvinfo(struct net_device
*dev
,
806 struct ethtool_drvinfo
*info
)
808 struct fec_enet_private
*fep
= netdev_priv(dev
);
810 strcpy(info
->driver
, fep
->pdev
->dev
.driver
->name
);
811 strcpy(info
->version
, "Revision: 1.0");
812 strcpy(info
->bus_info
, dev_name(&dev
->dev
));
815 static struct ethtool_ops fec_enet_ethtool_ops
= {
816 .get_settings
= fec_enet_get_settings
,
817 .set_settings
= fec_enet_set_settings
,
818 .get_drvinfo
= fec_enet_get_drvinfo
,
819 .get_link
= ethtool_op_get_link
,
822 static int fec_enet_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
824 struct fec_enet_private
*fep
= netdev_priv(dev
);
825 struct phy_device
*phydev
= fep
->phy_dev
;
827 if (!netif_running(dev
))
833 return phy_mii_ioctl(phydev
, if_mii(rq
), cmd
);
836 static void fec_enet_free_buffers(struct net_device
*dev
)
838 struct fec_enet_private
*fep
= netdev_priv(dev
);
843 bdp
= fep
->rx_bd_base
;
844 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
845 skb
= fep
->rx_skbuff
[i
];
847 if (bdp
->cbd_bufaddr
)
848 dma_unmap_single(&dev
->dev
, bdp
->cbd_bufaddr
,
849 FEC_ENET_RX_FRSIZE
, DMA_FROM_DEVICE
);
855 bdp
= fep
->tx_bd_base
;
856 for (i
= 0; i
< TX_RING_SIZE
; i
++)
857 kfree(fep
->tx_bounce
[i
]);
860 static int fec_enet_alloc_buffers(struct net_device
*dev
)
862 struct fec_enet_private
*fep
= netdev_priv(dev
);
867 bdp
= fep
->rx_bd_base
;
868 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
869 skb
= dev_alloc_skb(FEC_ENET_RX_FRSIZE
);
871 fec_enet_free_buffers(dev
);
874 fep
->rx_skbuff
[i
] = skb
;
876 bdp
->cbd_bufaddr
= dma_map_single(&dev
->dev
, skb
->data
,
877 FEC_ENET_RX_FRSIZE
, DMA_FROM_DEVICE
);
878 bdp
->cbd_sc
= BD_ENET_RX_EMPTY
;
882 /* Set the last buffer to wrap. */
884 bdp
->cbd_sc
|= BD_SC_WRAP
;
886 bdp
= fep
->tx_bd_base
;
887 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
888 fep
->tx_bounce
[i
] = kmalloc(FEC_ENET_TX_FRSIZE
, GFP_KERNEL
);
891 bdp
->cbd_bufaddr
= 0;
895 /* Set the last buffer to wrap. */
897 bdp
->cbd_sc
|= BD_SC_WRAP
;
903 fec_enet_open(struct net_device
*dev
)
905 struct fec_enet_private
*fep
= netdev_priv(dev
);
908 /* I should reset the ring buffers here, but I don't yet know
909 * a simple way to do that.
912 ret
= fec_enet_alloc_buffers(dev
);
916 /* schedule a link state check */
917 phy_start(fep
->phy_dev
);
918 netif_start_queue(dev
);
924 fec_enet_close(struct net_device
*dev
)
926 struct fec_enet_private
*fep
= netdev_priv(dev
);
928 /* Don't know what to do yet. */
930 phy_stop(fep
->phy_dev
);
931 netif_stop_queue(dev
);
934 fec_enet_free_buffers(dev
);
939 /* Set or clear the multicast filter for this adaptor.
940 * Skeleton taken from sunlance driver.
941 * The CPM Ethernet implementation allows Multicast as well as individual
942 * MAC address filtering. Some of the drivers check to make sure it is
943 * a group multicast address, and discard those that are not. I guess I
944 * will do the same for now, but just remove the test if you want
945 * individual filtering as well (do the upper net layers want or support
946 * this kind of feature?).
949 #define HASH_BITS 6 /* #bits in hash */
950 #define CRC32_POLY 0xEDB88320
952 static void set_multicast_list(struct net_device
*dev
)
954 struct fec_enet_private
*fep
= netdev_priv(dev
);
955 struct netdev_hw_addr
*ha
;
956 unsigned int i
, bit
, data
, crc
, tmp
;
959 if (dev
->flags
& IFF_PROMISC
) {
960 tmp
= readl(fep
->hwp
+ FEC_R_CNTRL
);
962 writel(tmp
, fep
->hwp
+ FEC_R_CNTRL
);
966 tmp
= readl(fep
->hwp
+ FEC_R_CNTRL
);
968 writel(tmp
, fep
->hwp
+ FEC_R_CNTRL
);
970 if (dev
->flags
& IFF_ALLMULTI
) {
971 /* Catch all multicast addresses, so set the
974 writel(0xffffffff, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
975 writel(0xffffffff, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
980 /* Clear filter and add the addresses in hash register
982 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
983 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
985 netdev_for_each_mc_addr(ha
, dev
) {
986 /* Only support group multicast for now */
987 if (!(ha
->addr
[0] & 1))
990 /* calculate crc32 value of mac address */
993 for (i
= 0; i
< dev
->addr_len
; i
++) {
995 for (bit
= 0; bit
< 8; bit
++, data
>>= 1) {
997 (((crc
^ data
) & 1) ? CRC32_POLY
: 0);
1001 /* only upper 6 bits (HASH_BITS) are used
1002 * which point to specific bit in he hash registers
1004 hash
= (crc
>> (32 - HASH_BITS
)) & 0x3f;
1007 tmp
= readl(fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1008 tmp
|= 1 << (hash
- 32);
1009 writel(tmp
, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1011 tmp
= readl(fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1013 writel(tmp
, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1018 /* Set a MAC change in hardware. */
1020 fec_set_mac_address(struct net_device
*dev
, void *p
)
1022 struct fec_enet_private
*fep
= netdev_priv(dev
);
1023 struct sockaddr
*addr
= p
;
1025 if (!is_valid_ether_addr(addr
->sa_data
))
1026 return -EADDRNOTAVAIL
;
1028 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1030 writel(dev
->dev_addr
[3] | (dev
->dev_addr
[2] << 8) |
1031 (dev
->dev_addr
[1] << 16) | (dev
->dev_addr
[0] << 24),
1032 fep
->hwp
+ FEC_ADDR_LOW
);
1033 writel((dev
->dev_addr
[5] << 16) | (dev
->dev_addr
[4] << 24),
1034 fep
+ FEC_ADDR_HIGH
);
1038 static const struct net_device_ops fec_netdev_ops
= {
1039 .ndo_open
= fec_enet_open
,
1040 .ndo_stop
= fec_enet_close
,
1041 .ndo_start_xmit
= fec_enet_start_xmit
,
1042 .ndo_set_multicast_list
= set_multicast_list
,
1043 .ndo_change_mtu
= eth_change_mtu
,
1044 .ndo_validate_addr
= eth_validate_addr
,
1045 .ndo_tx_timeout
= fec_timeout
,
1046 .ndo_set_mac_address
= fec_set_mac_address
,
1047 .ndo_do_ioctl
= fec_enet_ioctl
,
1051 * XXX: We need to clean up on failure exits here.
1053 * index is only used in legacy code
1055 static int fec_enet_init(struct net_device
*dev
, int index
)
1057 struct fec_enet_private
*fep
= netdev_priv(dev
);
1058 struct bufdesc
*cbd_base
;
1059 struct bufdesc
*bdp
;
1062 /* Allocate memory for buffer descriptors. */
1063 cbd_base
= dma_alloc_coherent(NULL
, PAGE_SIZE
, &fep
->bd_dma
,
1066 printk("FEC: allocate descriptor memory failed?\n");
1070 spin_lock_init(&fep
->hw_lock
);
1073 fep
->hwp
= (void __iomem
*)dev
->base_addr
;
1076 /* Set the Ethernet address */
1082 l
= readl(fep
->hwp
+ FEC_ADDR_LOW
);
1083 dev
->dev_addr
[0] = (unsigned char)((l
& 0xFF000000) >> 24);
1084 dev
->dev_addr
[1] = (unsigned char)((l
& 0x00FF0000) >> 16);
1085 dev
->dev_addr
[2] = (unsigned char)((l
& 0x0000FF00) >> 8);
1086 dev
->dev_addr
[3] = (unsigned char)((l
& 0x000000FF) >> 0);
1087 l
= readl(fep
->hwp
+ FEC_ADDR_HIGH
);
1088 dev
->dev_addr
[4] = (unsigned char)((l
& 0xFF000000) >> 24);
1089 dev
->dev_addr
[5] = (unsigned char)((l
& 0x00FF0000) >> 16);
1093 /* Set receive and transmit descriptor base. */
1094 fep
->rx_bd_base
= cbd_base
;
1095 fep
->tx_bd_base
= cbd_base
+ RX_RING_SIZE
;
1097 /* The FEC Ethernet specific entries in the device structure */
1098 dev
->watchdog_timeo
= TX_TIMEOUT
;
1099 dev
->netdev_ops
= &fec_netdev_ops
;
1100 dev
->ethtool_ops
= &fec_enet_ethtool_ops
;
1102 /* Initialize the receive buffer descriptors. */
1103 bdp
= fep
->rx_bd_base
;
1104 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1106 /* Initialize the BD for every fragment in the page. */
1111 /* Set the last buffer to wrap */
1113 bdp
->cbd_sc
|= BD_SC_WRAP
;
1115 /* ...and the same for transmit */
1116 bdp
= fep
->tx_bd_base
;
1117 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1119 /* Initialize the BD for every fragment in the page. */
1121 bdp
->cbd_bufaddr
= 0;
1125 /* Set the last buffer to wrap */
1127 bdp
->cbd_sc
|= BD_SC_WRAP
;
1129 fec_restart(dev
, 0);
1134 /* This function is called to start or restart the FEC during a link
1135 * change. This only happens when switching between half and full
1139 fec_restart(struct net_device
*dev
, int duplex
)
1141 struct fec_enet_private
*fep
= netdev_priv(dev
);
1144 /* Whack a reset. We should wait for this. */
1145 writel(1, fep
->hwp
+ FEC_ECNTRL
);
1148 /* Clear any outstanding interrupt. */
1149 writel(0xffc00000, fep
->hwp
+ FEC_IEVENT
);
1151 /* Reset all multicast. */
1152 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1153 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1154 #ifndef CONFIG_M5272
1155 writel(0, fep
->hwp
+ FEC_HASH_TABLE_HIGH
);
1156 writel(0, fep
->hwp
+ FEC_HASH_TABLE_LOW
);
1159 /* Set maximum receive buffer size. */
1160 writel(PKT_MAXBLR_SIZE
, fep
->hwp
+ FEC_R_BUFF_SIZE
);
1162 /* Set receive and transmit descriptor base. */
1163 writel(fep
->bd_dma
, fep
->hwp
+ FEC_R_DES_START
);
1164 writel((unsigned long)fep
->bd_dma
+ sizeof(struct bufdesc
) * RX_RING_SIZE
,
1165 fep
->hwp
+ FEC_X_DES_START
);
1167 fep
->dirty_tx
= fep
->cur_tx
= fep
->tx_bd_base
;
1168 fep
->cur_rx
= fep
->rx_bd_base
;
1170 /* Reset SKB transmit buffers. */
1171 fep
->skb_cur
= fep
->skb_dirty
= 0;
1172 for (i
= 0; i
<= TX_RING_MOD_MASK
; i
++) {
1173 if (fep
->tx_skbuff
[i
]) {
1174 dev_kfree_skb_any(fep
->tx_skbuff
[i
]);
1175 fep
->tx_skbuff
[i
] = NULL
;
1179 /* Enable MII mode */
1181 /* MII enable / FD enable */
1182 writel(OPT_FRAME_SIZE
| 0x04, fep
->hwp
+ FEC_R_CNTRL
);
1183 writel(0x04, fep
->hwp
+ FEC_X_CNTRL
);
1185 /* MII enable / No Rcv on Xmit */
1186 writel(OPT_FRAME_SIZE
| 0x06, fep
->hwp
+ FEC_R_CNTRL
);
1187 writel(0x0, fep
->hwp
+ FEC_X_CNTRL
);
1189 fep
->full_duplex
= duplex
;
1192 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
1194 /* And last, enable the transmit and receive processing */
1195 writel(2, fep
->hwp
+ FEC_ECNTRL
);
1196 writel(0, fep
->hwp
+ FEC_R_DES_ACTIVE
);
1198 /* Enable interrupts we wish to service */
1199 writel(FEC_ENET_TXF
| FEC_ENET_RXF
, fep
->hwp
+ FEC_IMASK
);
1203 fec_stop(struct net_device
*dev
)
1205 struct fec_enet_private
*fep
= netdev_priv(dev
);
1207 /* We cannot expect a graceful transmit stop without link !!! */
1209 writel(1, fep
->hwp
+ FEC_X_CNTRL
); /* Graceful transmit stop */
1211 if (!(readl(fep
->hwp
+ FEC_IEVENT
) & FEC_ENET_GRA
))
1212 printk("fec_stop : Graceful transmit stop did not complete !\n");
1215 /* Whack a reset. We should wait for this. */
1216 writel(1, fep
->hwp
+ FEC_ECNTRL
);
1219 /* Clear outstanding MII command interrupts. */
1220 writel(FEC_ENET_MII
, fep
->hwp
+ FEC_IEVENT
);
1222 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
1225 static int __devinit
1226 fec_probe(struct platform_device
*pdev
)
1228 struct fec_enet_private
*fep
;
1229 struct net_device
*ndev
;
1230 int i
, irq
, ret
= 0;
1233 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1237 r
= request_mem_region(r
->start
, resource_size(r
), pdev
->name
);
1241 /* Init network device */
1242 ndev
= alloc_etherdev(sizeof(struct fec_enet_private
));
1246 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1248 /* setup board info structure */
1249 fep
= netdev_priv(ndev
);
1250 memset(fep
, 0, sizeof(*fep
));
1252 ndev
->base_addr
= (unsigned long)ioremap(r
->start
, resource_size(r
));
1255 if (!ndev
->base_addr
) {
1257 goto failed_ioremap
;
1260 platform_set_drvdata(pdev
, ndev
);
1262 /* This device has up to three irqs on some platforms */
1263 for (i
= 0; i
< 3; i
++) {
1264 irq
= platform_get_irq(pdev
, i
);
1267 ret
= request_irq(irq
, fec_enet_interrupt
, IRQF_DISABLED
, pdev
->name
, ndev
);
1270 irq
= platform_get_irq(pdev
, i
);
1271 free_irq(irq
, ndev
);
1278 fep
->clk
= clk_get(&pdev
->dev
, "fec_clk");
1279 if (IS_ERR(fep
->clk
)) {
1280 ret
= PTR_ERR(fep
->clk
);
1283 clk_enable(fep
->clk
);
1285 ret
= fec_enet_init(ndev
, 0);
1289 ret
= fec_enet_mii_init(pdev
);
1291 goto failed_mii_init
;
1293 ret
= register_netdev(ndev
);
1295 goto failed_register
;
1297 printk(KERN_INFO
"%s: Freescale FEC PHY driver [%s] "
1298 "(mii_bus:phy_addr=%s, irq=%d)\n", ndev
->name
,
1299 fep
->phy_dev
->drv
->name
, dev_name(&fep
->phy_dev
->dev
),
1305 fec_enet_mii_remove(fep
);
1308 clk_disable(fep
->clk
);
1311 for (i
= 0; i
< 3; i
++) {
1312 irq
= platform_get_irq(pdev
, i
);
1314 free_irq(irq
, ndev
);
1317 iounmap((void __iomem
*)ndev
->base_addr
);
1324 static int __devexit
1325 fec_drv_remove(struct platform_device
*pdev
)
1327 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1328 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1330 platform_set_drvdata(pdev
, NULL
);
1333 fec_enet_mii_remove(fep
);
1334 clk_disable(fep
->clk
);
1336 iounmap((void __iomem
*)ndev
->base_addr
);
1337 unregister_netdev(ndev
);
1343 fec_suspend(struct platform_device
*dev
, pm_message_t state
)
1345 struct net_device
*ndev
= platform_get_drvdata(dev
);
1346 struct fec_enet_private
*fep
;
1349 fep
= netdev_priv(ndev
);
1350 if (netif_running(ndev
)) {
1351 netif_device_detach(ndev
);
1359 fec_resume(struct platform_device
*dev
)
1361 struct net_device
*ndev
= platform_get_drvdata(dev
);
1364 if (netif_running(ndev
)) {
1365 fec_enet_init(ndev
, 0);
1366 netif_device_attach(ndev
);
1372 static struct platform_driver fec_driver
= {
1375 .owner
= THIS_MODULE
,
1378 .remove
= __devexit_p(fec_drv_remove
),
1379 .suspend
= fec_suspend
,
1380 .resume
= fec_resume
,
1384 fec_enet_module_init(void)
1386 printk(KERN_INFO
"FEC Ethernet Driver\n");
1388 return platform_driver_register(&fec_driver
);
1392 fec_enet_cleanup(void)
1394 platform_driver_unregister(&fec_driver
);
1397 module_exit(fec_enet_cleanup
);
1398 module_init(fec_enet_module_init
);
1400 MODULE_LICENSE("GPL");