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Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[mirror_ubuntu-eoan-kernel.git] / drivers / net / fec.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * This version of the driver is specific to the FADS implementation,
6 * since the board contains control registers external to the processor
7 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
8 * describes connections using the internal parallel port I/O, which
9 * is basically all of Port D.
10 *
11 * Right now, I am very wasteful with the buffers. I allocate memory
12 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will easily handle lots of
16 * small packets.
17 *
18 * Much better multiple PHY support by Magnus Damm.
19 * Copyright (c) 2000 Ericsson Radio Systems AB.
20 *
21 * Support for FEC controller of ColdFire processors.
22 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
23 *
24 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
25 * Copyright (c) 2004-2006 Macq Electronique SA.
26 */
27
28 #include <linux/config.h>
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/string.h>
32 #include <linux/ptrace.h>
33 #include <linux/errno.h>
34 #include <linux/ioport.h>
35 #include <linux/slab.h>
36 #include <linux/interrupt.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/skbuff.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
46
47 #include <asm/irq.h>
48 #include <asm/uaccess.h>
49 #include <asm/io.h>
50 #include <asm/pgtable.h>
51
52 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
53 defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
54 defined(CONFIG_M520x) || defined(CONFIG_M532x)
55 #include <asm/coldfire.h>
56 #include <asm/mcfsim.h>
57 #include "fec.h"
58 #else
59 #include <asm/8xx_immap.h>
60 #include <asm/mpc8xx.h>
61 #include "commproc.h"
62 #endif
63
64 #if defined(CONFIG_FEC2)
65 #define FEC_MAX_PORTS 2
66 #else
67 #define FEC_MAX_PORTS 1
68 #endif
69
70 /*
71 * Define the fixed address of the FEC hardware.
72 */
73 static unsigned int fec_hw[] = {
74 #if defined(CONFIG_M5272)
75 (MCF_MBAR + 0x840),
76 #elif defined(CONFIG_M527x)
77 (MCF_MBAR + 0x1000),
78 (MCF_MBAR + 0x1800),
79 #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
80 (MCF_MBAR + 0x1000),
81 #elif defined(CONFIG_M520x)
82 (MCF_MBAR+0x30000),
83 #elif defined(CONFIG_M532x)
84 (MCF_MBAR+0xfc030000),
85 #else
86 &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
87 #endif
88 };
89
90 static unsigned char fec_mac_default[] = {
91 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
92 };
93
94 /*
95 * Some hardware gets it MAC address out of local flash memory.
96 * if this is non-zero then assume it is the address to get MAC from.
97 */
98 #if defined(CONFIG_NETtel)
99 #define FEC_FLASHMAC 0xf0006006
100 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
101 #define FEC_FLASHMAC 0xf0006000
102 #elif defined (CONFIG_MTD_KeyTechnology)
103 #define FEC_FLASHMAC 0xffe04000
104 #elif defined(CONFIG_CANCam)
105 #define FEC_FLASHMAC 0xf0020000
106 #elif defined (CONFIG_M5272C3)
107 #define FEC_FLASHMAC (0xffe04000 + 4)
108 #elif defined(CONFIG_MOD5272)
109 #define FEC_FLASHMAC 0xffc0406b
110 #else
111 #define FEC_FLASHMAC 0
112 #endif
113
114 /* Forward declarations of some structures to support different PHYs
115 */
116
117 typedef struct {
118 uint mii_data;
119 void (*funct)(uint mii_reg, struct net_device *dev);
120 } phy_cmd_t;
121
122 typedef struct {
123 uint id;
124 char *name;
125
126 const phy_cmd_t *config;
127 const phy_cmd_t *startup;
128 const phy_cmd_t *ack_int;
129 const phy_cmd_t *shutdown;
130 } phy_info_t;
131
132 /* The number of Tx and Rx buffers. These are allocated from the page
133 * pool. The code may assume these are power of two, so it it best
134 * to keep them that size.
135 * We don't need to allocate pages for the transmitter. We just use
136 * the skbuffer directly.
137 */
138 #define FEC_ENET_RX_PAGES 8
139 #define FEC_ENET_RX_FRSIZE 2048
140 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
141 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
142 #define FEC_ENET_TX_FRSIZE 2048
143 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
144 #define TX_RING_SIZE 16 /* Must be power of two */
145 #define TX_RING_MOD_MASK 15 /* for this to work */
146
147 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
148 #error "FEC: descriptor ring size constants too large"
149 #endif
150
151 /* Interrupt events/masks.
152 */
153 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
154 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
155 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
156 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
157 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
158 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
159 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
160 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
161 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
162 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
163
164 /* The FEC stores dest/src/type, data, and checksum for receive packets.
165 */
166 #define PKT_MAXBUF_SIZE 1518
167 #define PKT_MINBUF_SIZE 64
168 #define PKT_MAXBLR_SIZE 1520
169
170
171 /*
172 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
173 * size bits. Other FEC hardware does not, so we need to take that into
174 * account when setting it.
175 */
176 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
177 defined(CONFIG_M520x) || defined(CONFIG_M532x)
178 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
179 #else
180 #define OPT_FRAME_SIZE 0
181 #endif
182
183 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
184 * tx_bd_base always point to the base of the buffer descriptors. The
185 * cur_rx and cur_tx point to the currently available buffer.
186 * The dirty_tx tracks the current buffer that is being sent by the
187 * controller. The cur_tx and dirty_tx are equal under both completely
188 * empty and completely full conditions. The empty/ready indicator in
189 * the buffer descriptor determines the actual condition.
190 */
191 struct fec_enet_private {
192 /* Hardware registers of the FEC device */
193 volatile fec_t *hwp;
194
195 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
196 unsigned char *tx_bounce[TX_RING_SIZE];
197 struct sk_buff* tx_skbuff[TX_RING_SIZE];
198 ushort skb_cur;
199 ushort skb_dirty;
200
201 /* CPM dual port RAM relative addresses.
202 */
203 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
204 cbd_t *tx_bd_base;
205 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
206 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
207 struct net_device_stats stats;
208 uint tx_full;
209 spinlock_t lock;
210
211 uint phy_id;
212 uint phy_id_done;
213 uint phy_status;
214 uint phy_speed;
215 phy_info_t const *phy;
216 struct work_struct phy_task;
217
218 uint sequence_done;
219 uint mii_phy_task_queued;
220
221 uint phy_addr;
222
223 int index;
224 int opened;
225 int link;
226 int old_link;
227 int full_duplex;
228 };
229
230 static int fec_enet_open(struct net_device *dev);
231 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
232 static void fec_enet_mii(struct net_device *dev);
233 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs);
234 static void fec_enet_tx(struct net_device *dev);
235 static void fec_enet_rx(struct net_device *dev);
236 static int fec_enet_close(struct net_device *dev);
237 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
238 static void set_multicast_list(struct net_device *dev);
239 static void fec_restart(struct net_device *dev, int duplex);
240 static void fec_stop(struct net_device *dev);
241 static void fec_set_mac_address(struct net_device *dev);
242
243
244 /* MII processing. We keep this as simple as possible. Requests are
245 * placed on the list (if there is room). When the request is finished
246 * by the MII, an optional function may be called.
247 */
248 typedef struct mii_list {
249 uint mii_regval;
250 void (*mii_func)(uint val, struct net_device *dev);
251 struct mii_list *mii_next;
252 } mii_list_t;
253
254 #define NMII 20
255 static mii_list_t mii_cmds[NMII];
256 static mii_list_t *mii_free;
257 static mii_list_t *mii_head;
258 static mii_list_t *mii_tail;
259
260 static int mii_queue(struct net_device *dev, int request,
261 void (*func)(uint, struct net_device *));
262
263 /* Make MII read/write commands for the FEC.
264 */
265 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
266 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
267 (VAL & 0xffff))
268 #define mk_mii_end 0
269
270 /* Transmitter timeout.
271 */
272 #define TX_TIMEOUT (2*HZ)
273
274 /* Register definitions for the PHY.
275 */
276
277 #define MII_REG_CR 0 /* Control Register */
278 #define MII_REG_SR 1 /* Status Register */
279 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
280 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
281 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
282 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
283 #define MII_REG_ANER 6 /* A-N Expansion Register */
284 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
285 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
286
287 /* values for phy_status */
288
289 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
290 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
291 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
292 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
293 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
294 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
295 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
296
297 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
298 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
299 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
300 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
301 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
302 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
303 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
304 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
305
306
307 static int
308 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
309 {
310 struct fec_enet_private *fep;
311 volatile fec_t *fecp;
312 volatile cbd_t *bdp;
313 unsigned short status;
314
315 fep = netdev_priv(dev);
316 fecp = (volatile fec_t*)dev->base_addr;
317
318 if (!fep->link) {
319 /* Link is down or autonegotiation is in progress. */
320 return 1;
321 }
322
323 /* Fill in a Tx ring entry */
324 bdp = fep->cur_tx;
325
326 status = bdp->cbd_sc;
327 #ifndef final_version
328 if (status & BD_ENET_TX_READY) {
329 /* Ooops. All transmit buffers are full. Bail out.
330 * This should not happen, since dev->tbusy should be set.
331 */
332 printk("%s: tx queue full!.\n", dev->name);
333 return 1;
334 }
335 #endif
336
337 /* Clear all of the status flags.
338 */
339 status &= ~BD_ENET_TX_STATS;
340
341 /* Set buffer length and buffer pointer.
342 */
343 bdp->cbd_bufaddr = __pa(skb->data);
344 bdp->cbd_datlen = skb->len;
345
346 /*
347 * On some FEC implementations data must be aligned on
348 * 4-byte boundaries. Use bounce buffers to copy data
349 * and get it aligned. Ugh.
350 */
351 if (bdp->cbd_bufaddr & 0x3) {
352 unsigned int index;
353 index = bdp - fep->tx_bd_base;
354 memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
355 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
356 }
357
358 /* Save skb pointer.
359 */
360 fep->tx_skbuff[fep->skb_cur] = skb;
361
362 fep->stats.tx_bytes += skb->len;
363 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
364
365 /* Push the data cache so the CPM does not get stale memory
366 * data.
367 */
368 flush_dcache_range((unsigned long)skb->data,
369 (unsigned long)skb->data + skb->len);
370
371 spin_lock_irq(&fep->lock);
372
373 /* Send it on its way. Tell FEC it's ready, interrupt when done,
374 * it's the last BD of the frame, and to put the CRC on the end.
375 */
376
377 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
378 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
379 bdp->cbd_sc = status;
380
381 dev->trans_start = jiffies;
382
383 /* Trigger transmission start */
384 fecp->fec_x_des_active = 0;
385
386 /* If this was the last BD in the ring, start at the beginning again.
387 */
388 if (status & BD_ENET_TX_WRAP) {
389 bdp = fep->tx_bd_base;
390 } else {
391 bdp++;
392 }
393
394 if (bdp == fep->dirty_tx) {
395 fep->tx_full = 1;
396 netif_stop_queue(dev);
397 }
398
399 fep->cur_tx = (cbd_t *)bdp;
400
401 spin_unlock_irq(&fep->lock);
402
403 return 0;
404 }
405
406 static void
407 fec_timeout(struct net_device *dev)
408 {
409 struct fec_enet_private *fep = netdev_priv(dev);
410
411 printk("%s: transmit timed out.\n", dev->name);
412 fep->stats.tx_errors++;
413 #ifndef final_version
414 {
415 int i;
416 cbd_t *bdp;
417
418 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
419 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
420 (unsigned long)fep->dirty_tx,
421 (unsigned long)fep->cur_rx);
422
423 bdp = fep->tx_bd_base;
424 printk(" tx: %u buffers\n", TX_RING_SIZE);
425 for (i = 0 ; i < TX_RING_SIZE; i++) {
426 printk(" %08x: %04x %04x %08x\n",
427 (uint) bdp,
428 bdp->cbd_sc,
429 bdp->cbd_datlen,
430 (int) bdp->cbd_bufaddr);
431 bdp++;
432 }
433
434 bdp = fep->rx_bd_base;
435 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
436 for (i = 0 ; i < RX_RING_SIZE; i++) {
437 printk(" %08x: %04x %04x %08x\n",
438 (uint) bdp,
439 bdp->cbd_sc,
440 bdp->cbd_datlen,
441 (int) bdp->cbd_bufaddr);
442 bdp++;
443 }
444 }
445 #endif
446 fec_restart(dev, fep->full_duplex);
447 netif_wake_queue(dev);
448 }
449
450 /* The interrupt handler.
451 * This is called from the MPC core interrupt.
452 */
453 static irqreturn_t
454 fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
455 {
456 struct net_device *dev = dev_id;
457 volatile fec_t *fecp;
458 uint int_events;
459 int handled = 0;
460
461 fecp = (volatile fec_t*)dev->base_addr;
462
463 /* Get the interrupt events that caused us to be here.
464 */
465 while ((int_events = fecp->fec_ievent) != 0) {
466 fecp->fec_ievent = int_events;
467
468 /* Handle receive event in its own function.
469 */
470 if (int_events & FEC_ENET_RXF) {
471 handled = 1;
472 fec_enet_rx(dev);
473 }
474
475 /* Transmit OK, or non-fatal error. Update the buffer
476 descriptors. FEC handles all errors, we just discover
477 them as part of the transmit process.
478 */
479 if (int_events & FEC_ENET_TXF) {
480 handled = 1;
481 fec_enet_tx(dev);
482 }
483
484 if (int_events & FEC_ENET_MII) {
485 handled = 1;
486 fec_enet_mii(dev);
487 }
488
489 }
490 return IRQ_RETVAL(handled);
491 }
492
493
494 static void
495 fec_enet_tx(struct net_device *dev)
496 {
497 struct fec_enet_private *fep;
498 volatile cbd_t *bdp;
499 unsigned short status;
500 struct sk_buff *skb;
501
502 fep = netdev_priv(dev);
503 spin_lock(&fep->lock);
504 bdp = fep->dirty_tx;
505
506 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
507 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
508
509 skb = fep->tx_skbuff[fep->skb_dirty];
510 /* Check for errors. */
511 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
512 BD_ENET_TX_RL | BD_ENET_TX_UN |
513 BD_ENET_TX_CSL)) {
514 fep->stats.tx_errors++;
515 if (status & BD_ENET_TX_HB) /* No heartbeat */
516 fep->stats.tx_heartbeat_errors++;
517 if (status & BD_ENET_TX_LC) /* Late collision */
518 fep->stats.tx_window_errors++;
519 if (status & BD_ENET_TX_RL) /* Retrans limit */
520 fep->stats.tx_aborted_errors++;
521 if (status & BD_ENET_TX_UN) /* Underrun */
522 fep->stats.tx_fifo_errors++;
523 if (status & BD_ENET_TX_CSL) /* Carrier lost */
524 fep->stats.tx_carrier_errors++;
525 } else {
526 fep->stats.tx_packets++;
527 }
528
529 #ifndef final_version
530 if (status & BD_ENET_TX_READY)
531 printk("HEY! Enet xmit interrupt and TX_READY.\n");
532 #endif
533 /* Deferred means some collisions occurred during transmit,
534 * but we eventually sent the packet OK.
535 */
536 if (status & BD_ENET_TX_DEF)
537 fep->stats.collisions++;
538
539 /* Free the sk buffer associated with this last transmit.
540 */
541 dev_kfree_skb_any(skb);
542 fep->tx_skbuff[fep->skb_dirty] = NULL;
543 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
544
545 /* Update pointer to next buffer descriptor to be transmitted.
546 */
547 if (status & BD_ENET_TX_WRAP)
548 bdp = fep->tx_bd_base;
549 else
550 bdp++;
551
552 /* Since we have freed up a buffer, the ring is no longer
553 * full.
554 */
555 if (fep->tx_full) {
556 fep->tx_full = 0;
557 if (netif_queue_stopped(dev))
558 netif_wake_queue(dev);
559 }
560 }
561 fep->dirty_tx = (cbd_t *)bdp;
562 spin_unlock(&fep->lock);
563 }
564
565
566 /* During a receive, the cur_rx points to the current incoming buffer.
567 * When we update through the ring, if the next incoming buffer has
568 * not been given to the system, we just set the empty indicator,
569 * effectively tossing the packet.
570 */
571 static void
572 fec_enet_rx(struct net_device *dev)
573 {
574 struct fec_enet_private *fep;
575 volatile fec_t *fecp;
576 volatile cbd_t *bdp;
577 unsigned short status;
578 struct sk_buff *skb;
579 ushort pkt_len;
580 __u8 *data;
581
582 #ifdef CONFIG_M532x
583 flush_cache_all();
584 #endif
585
586 fep = netdev_priv(dev);
587 fecp = (volatile fec_t*)dev->base_addr;
588
589 /* First, grab all of the stats for the incoming packet.
590 * These get messed up if we get called due to a busy condition.
591 */
592 bdp = fep->cur_rx;
593
594 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
595
596 #ifndef final_version
597 /* Since we have allocated space to hold a complete frame,
598 * the last indicator should be set.
599 */
600 if ((status & BD_ENET_RX_LAST) == 0)
601 printk("FEC ENET: rcv is not +last\n");
602 #endif
603
604 if (!fep->opened)
605 goto rx_processing_done;
606
607 /* Check for errors. */
608 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
609 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
610 fep->stats.rx_errors++;
611 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
612 /* Frame too long or too short. */
613 fep->stats.rx_length_errors++;
614 }
615 if (status & BD_ENET_RX_NO) /* Frame alignment */
616 fep->stats.rx_frame_errors++;
617 if (status & BD_ENET_RX_CR) /* CRC Error */
618 fep->stats.rx_crc_errors++;
619 if (status & BD_ENET_RX_OV) /* FIFO overrun */
620 fep->stats.rx_fifo_errors++;
621 }
622
623 /* Report late collisions as a frame error.
624 * On this error, the BD is closed, but we don't know what we
625 * have in the buffer. So, just drop this frame on the floor.
626 */
627 if (status & BD_ENET_RX_CL) {
628 fep->stats.rx_errors++;
629 fep->stats.rx_frame_errors++;
630 goto rx_processing_done;
631 }
632
633 /* Process the incoming frame.
634 */
635 fep->stats.rx_packets++;
636 pkt_len = bdp->cbd_datlen;
637 fep->stats.rx_bytes += pkt_len;
638 data = (__u8*)__va(bdp->cbd_bufaddr);
639
640 /* This does 16 byte alignment, exactly what we need.
641 * The packet length includes FCS, but we don't want to
642 * include that when passing upstream as it messes up
643 * bridging applications.
644 */
645 skb = dev_alloc_skb(pkt_len-4);
646
647 if (skb == NULL) {
648 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
649 fep->stats.rx_dropped++;
650 } else {
651 skb->dev = dev;
652 skb_put(skb,pkt_len-4); /* Make room */
653 eth_copy_and_sum(skb, data, pkt_len-4, 0);
654 skb->protocol=eth_type_trans(skb,dev);
655 netif_rx(skb);
656 }
657 rx_processing_done:
658
659 /* Clear the status flags for this buffer.
660 */
661 status &= ~BD_ENET_RX_STATS;
662
663 /* Mark the buffer empty.
664 */
665 status |= BD_ENET_RX_EMPTY;
666 bdp->cbd_sc = status;
667
668 /* Update BD pointer to next entry.
669 */
670 if (status & BD_ENET_RX_WRAP)
671 bdp = fep->rx_bd_base;
672 else
673 bdp++;
674
675 #if 1
676 /* Doing this here will keep the FEC running while we process
677 * incoming frames. On a heavily loaded network, we should be
678 * able to keep up at the expense of system resources.
679 */
680 fecp->fec_r_des_active = 0;
681 #endif
682 } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
683 fep->cur_rx = (cbd_t *)bdp;
684
685 #if 0
686 /* Doing this here will allow us to process all frames in the
687 * ring before the FEC is allowed to put more there. On a heavily
688 * loaded network, some frames may be lost. Unfortunately, this
689 * increases the interrupt overhead since we can potentially work
690 * our way back to the interrupt return only to come right back
691 * here.
692 */
693 fecp->fec_r_des_active = 0;
694 #endif
695 }
696
697
698 /* called from interrupt context */
699 static void
700 fec_enet_mii(struct net_device *dev)
701 {
702 struct fec_enet_private *fep;
703 volatile fec_t *ep;
704 mii_list_t *mip;
705 uint mii_reg;
706
707 fep = netdev_priv(dev);
708 ep = fep->hwp;
709 mii_reg = ep->fec_mii_data;
710
711 spin_lock(&fep->lock);
712
713 if ((mip = mii_head) == NULL) {
714 printk("MII and no head!\n");
715 goto unlock;
716 }
717
718 if (mip->mii_func != NULL)
719 (*(mip->mii_func))(mii_reg, dev);
720
721 mii_head = mip->mii_next;
722 mip->mii_next = mii_free;
723 mii_free = mip;
724
725 if ((mip = mii_head) != NULL)
726 ep->fec_mii_data = mip->mii_regval;
727
728 unlock:
729 spin_unlock(&fep->lock);
730 }
731
732 static int
733 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
734 {
735 struct fec_enet_private *fep;
736 unsigned long flags;
737 mii_list_t *mip;
738 int retval;
739
740 /* Add PHY address to register command.
741 */
742 fep = netdev_priv(dev);
743 regval |= fep->phy_addr << 23;
744
745 retval = 0;
746
747 spin_lock_irqsave(&fep->lock,flags);
748
749 if ((mip = mii_free) != NULL) {
750 mii_free = mip->mii_next;
751 mip->mii_regval = regval;
752 mip->mii_func = func;
753 mip->mii_next = NULL;
754 if (mii_head) {
755 mii_tail->mii_next = mip;
756 mii_tail = mip;
757 }
758 else {
759 mii_head = mii_tail = mip;
760 fep->hwp->fec_mii_data = regval;
761 }
762 }
763 else {
764 retval = 1;
765 }
766
767 spin_unlock_irqrestore(&fep->lock,flags);
768
769 return(retval);
770 }
771
772 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
773 {
774 int k;
775
776 if(!c)
777 return;
778
779 for(k = 0; (c+k)->mii_data != mk_mii_end; k++) {
780 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
781 }
782 }
783
784 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
785 {
786 struct fec_enet_private *fep = netdev_priv(dev);
787 volatile uint *s = &(fep->phy_status);
788 uint status;
789
790 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
791
792 if (mii_reg & 0x0004)
793 status |= PHY_STAT_LINK;
794 if (mii_reg & 0x0010)
795 status |= PHY_STAT_FAULT;
796 if (mii_reg & 0x0020)
797 status |= PHY_STAT_ANC;
798
799 *s = status;
800 }
801
802 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
803 {
804 struct fec_enet_private *fep = netdev_priv(dev);
805 volatile uint *s = &(fep->phy_status);
806 uint status;
807
808 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
809
810 if (mii_reg & 0x1000)
811 status |= PHY_CONF_ANE;
812 if (mii_reg & 0x4000)
813 status |= PHY_CONF_LOOP;
814 *s = status;
815 }
816
817 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
818 {
819 struct fec_enet_private *fep = netdev_priv(dev);
820 volatile uint *s = &(fep->phy_status);
821 uint status;
822
823 status = *s & ~(PHY_CONF_SPMASK);
824
825 if (mii_reg & 0x0020)
826 status |= PHY_CONF_10HDX;
827 if (mii_reg & 0x0040)
828 status |= PHY_CONF_10FDX;
829 if (mii_reg & 0x0080)
830 status |= PHY_CONF_100HDX;
831 if (mii_reg & 0x00100)
832 status |= PHY_CONF_100FDX;
833 *s = status;
834 }
835
836 /* ------------------------------------------------------------------------- */
837 /* The Level one LXT970 is used by many boards */
838
839 #define MII_LXT970_MIRROR 16 /* Mirror register */
840 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
841 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
842 #define MII_LXT970_CONFIG 19 /* Configuration Register */
843 #define MII_LXT970_CSR 20 /* Chip Status Register */
844
845 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
846 {
847 struct fec_enet_private *fep = netdev_priv(dev);
848 volatile uint *s = &(fep->phy_status);
849 uint status;
850
851 status = *s & ~(PHY_STAT_SPMASK);
852 if (mii_reg & 0x0800) {
853 if (mii_reg & 0x1000)
854 status |= PHY_STAT_100FDX;
855 else
856 status |= PHY_STAT_100HDX;
857 } else {
858 if (mii_reg & 0x1000)
859 status |= PHY_STAT_10FDX;
860 else
861 status |= PHY_STAT_10HDX;
862 }
863 *s = status;
864 }
865
866 static phy_cmd_t const phy_cmd_lxt970_config[] = {
867 { mk_mii_read(MII_REG_CR), mii_parse_cr },
868 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
869 { mk_mii_end, }
870 };
871 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
872 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
873 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
874 { mk_mii_end, }
875 };
876 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
877 /* read SR and ISR to acknowledge */
878 { mk_mii_read(MII_REG_SR), mii_parse_sr },
879 { mk_mii_read(MII_LXT970_ISR), NULL },
880
881 /* find out the current status */
882 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
883 { mk_mii_end, }
884 };
885 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
886 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
887 { mk_mii_end, }
888 };
889 static phy_info_t const phy_info_lxt970 = {
890 .id = 0x07810000,
891 .name = "LXT970",
892 .config = phy_cmd_lxt970_config,
893 .startup = phy_cmd_lxt970_startup,
894 .ack_int = phy_cmd_lxt970_ack_int,
895 .shutdown = phy_cmd_lxt970_shutdown
896 };
897
898 /* ------------------------------------------------------------------------- */
899 /* The Level one LXT971 is used on some of my custom boards */
900
901 /* register definitions for the 971 */
902
903 #define MII_LXT971_PCR 16 /* Port Control Register */
904 #define MII_LXT971_SR2 17 /* Status Register 2 */
905 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
906 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
907 #define MII_LXT971_LCR 20 /* LED Control Register */
908 #define MII_LXT971_TCR 30 /* Transmit Control Register */
909
910 /*
911 * I had some nice ideas of running the MDIO faster...
912 * The 971 should support 8MHz and I tried it, but things acted really
913 * weird, so 2.5 MHz ought to be enough for anyone...
914 */
915
916 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
917 {
918 struct fec_enet_private *fep = netdev_priv(dev);
919 volatile uint *s = &(fep->phy_status);
920 uint status;
921
922 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
923
924 if (mii_reg & 0x0400) {
925 fep->link = 1;
926 status |= PHY_STAT_LINK;
927 } else {
928 fep->link = 0;
929 }
930 if (mii_reg & 0x0080)
931 status |= PHY_STAT_ANC;
932 if (mii_reg & 0x4000) {
933 if (mii_reg & 0x0200)
934 status |= PHY_STAT_100FDX;
935 else
936 status |= PHY_STAT_100HDX;
937 } else {
938 if (mii_reg & 0x0200)
939 status |= PHY_STAT_10FDX;
940 else
941 status |= PHY_STAT_10HDX;
942 }
943 if (mii_reg & 0x0008)
944 status |= PHY_STAT_FAULT;
945
946 *s = status;
947 }
948
949 static phy_cmd_t const phy_cmd_lxt971_config[] = {
950 /* limit to 10MBit because my prototype board
951 * doesn't work with 100. */
952 { mk_mii_read(MII_REG_CR), mii_parse_cr },
953 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
954 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
955 { mk_mii_end, }
956 };
957 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
958 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
959 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
960 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
961 /* Somehow does the 971 tell me that the link is down
962 * the first read after power-up.
963 * read here to get a valid value in ack_int */
964 { mk_mii_read(MII_REG_SR), mii_parse_sr },
965 { mk_mii_end, }
966 };
967 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
968 /* acknowledge the int before reading status ! */
969 { mk_mii_read(MII_LXT971_ISR), NULL },
970 /* find out the current status */
971 { mk_mii_read(MII_REG_SR), mii_parse_sr },
972 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
973 { mk_mii_end, }
974 };
975 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
976 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
977 { mk_mii_end, }
978 };
979 static phy_info_t const phy_info_lxt971 = {
980 .id = 0x0001378e,
981 .name = "LXT971",
982 .config = phy_cmd_lxt971_config,
983 .startup = phy_cmd_lxt971_startup,
984 .ack_int = phy_cmd_lxt971_ack_int,
985 .shutdown = phy_cmd_lxt971_shutdown
986 };
987
988 /* ------------------------------------------------------------------------- */
989 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
990
991 /* register definitions */
992
993 #define MII_QS6612_MCR 17 /* Mode Control Register */
994 #define MII_QS6612_FTR 27 /* Factory Test Register */
995 #define MII_QS6612_MCO 28 /* Misc. Control Register */
996 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
997 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
998 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
999
1000 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
1001 {
1002 struct fec_enet_private *fep = netdev_priv(dev);
1003 volatile uint *s = &(fep->phy_status);
1004 uint status;
1005
1006 status = *s & ~(PHY_STAT_SPMASK);
1007
1008 switch((mii_reg >> 2) & 7) {
1009 case 1: status |= PHY_STAT_10HDX; break;
1010 case 2: status |= PHY_STAT_100HDX; break;
1011 case 5: status |= PHY_STAT_10FDX; break;
1012 case 6: status |= PHY_STAT_100FDX; break;
1013 }
1014
1015 *s = status;
1016 }
1017
1018 static phy_cmd_t const phy_cmd_qs6612_config[] = {
1019 /* The PHY powers up isolated on the RPX,
1020 * so send a command to allow operation.
1021 */
1022 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1023
1024 /* parse cr and anar to get some info */
1025 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1026 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1027 { mk_mii_end, }
1028 };
1029 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
1030 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1031 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1032 { mk_mii_end, }
1033 };
1034 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
1035 /* we need to read ISR, SR and ANER to acknowledge */
1036 { mk_mii_read(MII_QS6612_ISR), NULL },
1037 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1038 { mk_mii_read(MII_REG_ANER), NULL },
1039
1040 /* read pcr to get info */
1041 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1042 { mk_mii_end, }
1043 };
1044 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
1045 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1046 { mk_mii_end, }
1047 };
1048 static phy_info_t const phy_info_qs6612 = {
1049 .id = 0x00181440,
1050 .name = "QS6612",
1051 .config = phy_cmd_qs6612_config,
1052 .startup = phy_cmd_qs6612_startup,
1053 .ack_int = phy_cmd_qs6612_ack_int,
1054 .shutdown = phy_cmd_qs6612_shutdown
1055 };
1056
1057 /* ------------------------------------------------------------------------- */
1058 /* AMD AM79C874 phy */
1059
1060 /* register definitions for the 874 */
1061
1062 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1063 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1064 #define MII_AM79C874_DR 18 /* Diagnostic Register */
1065 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1066 #define MII_AM79C874_MCR 21 /* ModeControl Register */
1067 #define MII_AM79C874_DC 23 /* Disconnect Counter */
1068 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
1069
1070 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1071 {
1072 struct fec_enet_private *fep = netdev_priv(dev);
1073 volatile uint *s = &(fep->phy_status);
1074 uint status;
1075
1076 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1077
1078 if (mii_reg & 0x0080)
1079 status |= PHY_STAT_ANC;
1080 if (mii_reg & 0x0400)
1081 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1082 else
1083 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1084
1085 *s = status;
1086 }
1087
1088 static phy_cmd_t const phy_cmd_am79c874_config[] = {
1089 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1090 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1091 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1092 { mk_mii_end, }
1093 };
1094 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1095 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1096 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1097 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1098 { mk_mii_end, }
1099 };
1100 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1101 /* find out the current status */
1102 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1103 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1104 /* we only need to read ISR to acknowledge */
1105 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1106 { mk_mii_end, }
1107 };
1108 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1109 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1110 { mk_mii_end, }
1111 };
1112 static phy_info_t const phy_info_am79c874 = {
1113 .id = 0x00022561,
1114 .name = "AM79C874",
1115 .config = phy_cmd_am79c874_config,
1116 .startup = phy_cmd_am79c874_startup,
1117 .ack_int = phy_cmd_am79c874_ack_int,
1118 .shutdown = phy_cmd_am79c874_shutdown
1119 };
1120
1121
1122 /* ------------------------------------------------------------------------- */
1123 /* Kendin KS8721BL phy */
1124
1125 /* register definitions for the 8721 */
1126
1127 #define MII_KS8721BL_RXERCR 21
1128 #define MII_KS8721BL_ICSR 22
1129 #define MII_KS8721BL_PHYCR 31
1130
1131 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1132 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1133 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1134 { mk_mii_end, }
1135 };
1136 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1137 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1138 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1139 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1140 { mk_mii_end, }
1141 };
1142 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1143 /* find out the current status */
1144 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1145 /* we only need to read ISR to acknowledge */
1146 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1147 { mk_mii_end, }
1148 };
1149 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1150 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1151 { mk_mii_end, }
1152 };
1153 static phy_info_t const phy_info_ks8721bl = {
1154 .id = 0x00022161,
1155 .name = "KS8721BL",
1156 .config = phy_cmd_ks8721bl_config,
1157 .startup = phy_cmd_ks8721bl_startup,
1158 .ack_int = phy_cmd_ks8721bl_ack_int,
1159 .shutdown = phy_cmd_ks8721bl_shutdown
1160 };
1161
1162 /* ------------------------------------------------------------------------- */
1163 /* register definitions for the DP83848 */
1164
1165 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1166
1167 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1168 {
1169 struct fec_enet_private *fep = dev->priv;
1170 volatile uint *s = &(fep->phy_status);
1171
1172 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1173
1174 /* Link up */
1175 if (mii_reg & 0x0001) {
1176 fep->link = 1;
1177 *s |= PHY_STAT_LINK;
1178 } else
1179 fep->link = 0;
1180 /* Status of link */
1181 if (mii_reg & 0x0010) /* Autonegotioation complete */
1182 *s |= PHY_STAT_ANC;
1183 if (mii_reg & 0x0002) { /* 10MBps? */
1184 if (mii_reg & 0x0004) /* Full Duplex? */
1185 *s |= PHY_STAT_10FDX;
1186 else
1187 *s |= PHY_STAT_10HDX;
1188 } else { /* 100 Mbps? */
1189 if (mii_reg & 0x0004) /* Full Duplex? */
1190 *s |= PHY_STAT_100FDX;
1191 else
1192 *s |= PHY_STAT_100HDX;
1193 }
1194 if (mii_reg & 0x0008)
1195 *s |= PHY_STAT_FAULT;
1196 }
1197
1198 static phy_info_t phy_info_dp83848= {
1199 0x020005c9,
1200 "DP83848",
1201
1202 (const phy_cmd_t []) { /* config */
1203 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1204 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1205 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1206 { mk_mii_end, }
1207 },
1208 (const phy_cmd_t []) { /* startup - enable interrupts */
1209 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1210 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1211 { mk_mii_end, }
1212 },
1213 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1214 { mk_mii_end, }
1215 },
1216 (const phy_cmd_t []) { /* shutdown */
1217 { mk_mii_end, }
1218 },
1219 };
1220
1221 /* ------------------------------------------------------------------------- */
1222
1223 static phy_info_t const * const phy_info[] = {
1224 &phy_info_lxt970,
1225 &phy_info_lxt971,
1226 &phy_info_qs6612,
1227 &phy_info_am79c874,
1228 &phy_info_ks8721bl,
1229 &phy_info_dp83848,
1230 NULL
1231 };
1232
1233 /* ------------------------------------------------------------------------- */
1234 #if !defined(CONFIG_M532x)
1235 #ifdef CONFIG_RPXCLASSIC
1236 static void
1237 mii_link_interrupt(void *dev_id);
1238 #else
1239 static irqreturn_t
1240 mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs);
1241 #endif
1242 #endif
1243
1244 #if defined(CONFIG_M5272)
1245
1246 /*
1247 * Code specific to Coldfire 5272 setup.
1248 */
1249 static void __inline__ fec_request_intrs(struct net_device *dev)
1250 {
1251 volatile unsigned long *icrp;
1252 static const struct idesc {
1253 char *name;
1254 unsigned short irq;
1255 irqreturn_t (*handler)(int, void *, struct pt_regs *);
1256 } *idp, id[] = {
1257 { "fec(RX)", 86, fec_enet_interrupt },
1258 { "fec(TX)", 87, fec_enet_interrupt },
1259 { "fec(OTHER)", 88, fec_enet_interrupt },
1260 { "fec(MII)", 66, mii_link_interrupt },
1261 { NULL },
1262 };
1263
1264 /* Setup interrupt handlers. */
1265 for (idp = id; idp->name; idp++) {
1266 if (request_irq(idp->irq, idp->handler, 0, idp->name, dev) != 0)
1267 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1268 }
1269
1270 /* Unmask interrupt at ColdFire 5272 SIM */
1271 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1272 *icrp = 0x00000ddd;
1273 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1274 *icrp = (*icrp & 0x70777777) | 0x0d000000;
1275 }
1276
1277 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1278 {
1279 volatile fec_t *fecp;
1280
1281 fecp = fep->hwp;
1282 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1283 fecp->fec_x_cntrl = 0x00;
1284
1285 /*
1286 * Set MII speed to 2.5 MHz
1287 * See 5272 manual section 11.5.8: MSCR
1288 */
1289 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1290 fecp->fec_mii_speed = fep->phy_speed;
1291
1292 fec_restart(dev, 0);
1293 }
1294
1295 static void __inline__ fec_get_mac(struct net_device *dev)
1296 {
1297 struct fec_enet_private *fep = netdev_priv(dev);
1298 volatile fec_t *fecp;
1299 unsigned char *iap, tmpaddr[ETH_ALEN];
1300
1301 fecp = fep->hwp;
1302
1303 if (FEC_FLASHMAC) {
1304 /*
1305 * Get MAC address from FLASH.
1306 * If it is all 1's or 0's, use the default.
1307 */
1308 iap = (unsigned char *)FEC_FLASHMAC;
1309 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1310 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1311 iap = fec_mac_default;
1312 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1313 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1314 iap = fec_mac_default;
1315 } else {
1316 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1317 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1318 iap = &tmpaddr[0];
1319 }
1320
1321 memcpy(dev->dev_addr, iap, ETH_ALEN);
1322
1323 /* Adjust MAC if using default MAC address */
1324 if (iap == fec_mac_default)
1325 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1326 }
1327
1328 static void __inline__ fec_enable_phy_intr(void)
1329 {
1330 }
1331
1332 static void __inline__ fec_disable_phy_intr(void)
1333 {
1334 volatile unsigned long *icrp;
1335 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1336 *icrp = (*icrp & 0x70777777) | 0x08000000;
1337 }
1338
1339 static void __inline__ fec_phy_ack_intr(void)
1340 {
1341 volatile unsigned long *icrp;
1342 /* Acknowledge the interrupt */
1343 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1344 *icrp = (*icrp & 0x77777777) | 0x08000000;
1345 }
1346
1347 static void __inline__ fec_localhw_setup(void)
1348 {
1349 }
1350
1351 /*
1352 * Do not need to make region uncached on 5272.
1353 */
1354 static void __inline__ fec_uncache(unsigned long addr)
1355 {
1356 }
1357
1358 /* ------------------------------------------------------------------------- */
1359
1360 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
1361
1362 /*
1363 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1364 * the 5270/5271/5274/5275 and 5280/5282 setups.
1365 */
1366 static void __inline__ fec_request_intrs(struct net_device *dev)
1367 {
1368 struct fec_enet_private *fep;
1369 int b;
1370 static const struct idesc {
1371 char *name;
1372 unsigned short irq;
1373 } *idp, id[] = {
1374 { "fec(TXF)", 23 },
1375 { "fec(TXB)", 24 },
1376 { "fec(TXFIFO)", 25 },
1377 { "fec(TXCR)", 26 },
1378 { "fec(RXF)", 27 },
1379 { "fec(RXB)", 28 },
1380 { "fec(MII)", 29 },
1381 { "fec(LC)", 30 },
1382 { "fec(HBERR)", 31 },
1383 { "fec(GRA)", 32 },
1384 { "fec(EBERR)", 33 },
1385 { "fec(BABT)", 34 },
1386 { "fec(BABR)", 35 },
1387 { NULL },
1388 };
1389
1390 fep = netdev_priv(dev);
1391 b = (fep->index) ? 128 : 64;
1392
1393 /* Setup interrupt handlers. */
1394 for (idp = id; idp->name; idp++) {
1395 if (request_irq(b+idp->irq, fec_enet_interrupt, 0, idp->name, dev) != 0)
1396 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1397 }
1398
1399 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1400 {
1401 volatile unsigned char *icrp;
1402 volatile unsigned long *imrp;
1403 int i, ilip;
1404
1405 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1406 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1407 MCFINTC_ICR0);
1408 for (i = 23, ilip = 0x28; (i < 36); i++)
1409 icrp[i] = ilip--;
1410
1411 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1412 MCFINTC_IMRH);
1413 *imrp &= ~0x0000000f;
1414 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1415 MCFINTC_IMRL);
1416 *imrp &= ~0xff800001;
1417 }
1418
1419 #if defined(CONFIG_M528x)
1420 /* Set up gpio outputs for MII lines */
1421 {
1422 volatile u16 *gpio_paspar;
1423 volatile u8 *gpio_pehlpar;
1424
1425 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1426 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1427 *gpio_paspar |= 0x0f00;
1428 *gpio_pehlpar = 0xc0;
1429 }
1430 #endif
1431 }
1432
1433 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1434 {
1435 volatile fec_t *fecp;
1436
1437 fecp = fep->hwp;
1438 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1439 fecp->fec_x_cntrl = 0x00;
1440
1441 /*
1442 * Set MII speed to 2.5 MHz
1443 * See 5282 manual section 17.5.4.7: MSCR
1444 */
1445 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1446 fecp->fec_mii_speed = fep->phy_speed;
1447
1448 fec_restart(dev, 0);
1449 }
1450
1451 static void __inline__ fec_get_mac(struct net_device *dev)
1452 {
1453 struct fec_enet_private *fep = netdev_priv(dev);
1454 volatile fec_t *fecp;
1455 unsigned char *iap, tmpaddr[ETH_ALEN];
1456
1457 fecp = fep->hwp;
1458
1459 if (FEC_FLASHMAC) {
1460 /*
1461 * Get MAC address from FLASH.
1462 * If it is all 1's or 0's, use the default.
1463 */
1464 iap = FEC_FLASHMAC;
1465 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1466 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1467 iap = fec_mac_default;
1468 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1469 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1470 iap = fec_mac_default;
1471 } else {
1472 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1473 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1474 iap = &tmpaddr[0];
1475 }
1476
1477 memcpy(dev->dev_addr, iap, ETH_ALEN);
1478
1479 /* Adjust MAC if using default MAC address */
1480 if (iap == fec_mac_default)
1481 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1482 }
1483
1484 static void __inline__ fec_enable_phy_intr(void)
1485 {
1486 }
1487
1488 static void __inline__ fec_disable_phy_intr(void)
1489 {
1490 }
1491
1492 static void __inline__ fec_phy_ack_intr(void)
1493 {
1494 }
1495
1496 static void __inline__ fec_localhw_setup(void)
1497 {
1498 }
1499
1500 /*
1501 * Do not need to make region uncached on 5272.
1502 */
1503 static void __inline__ fec_uncache(unsigned long addr)
1504 {
1505 }
1506
1507 /* ------------------------------------------------------------------------- */
1508
1509 #elif defined(CONFIG_M520x)
1510
1511 /*
1512 * Code specific to Coldfire 520x
1513 */
1514 static void __inline__ fec_request_intrs(struct net_device *dev)
1515 {
1516 struct fec_enet_private *fep;
1517 int b;
1518 static const struct idesc {
1519 char *name;
1520 unsigned short irq;
1521 } *idp, id[] = {
1522 { "fec(TXF)", 23 },
1523 { "fec(TXB)", 24 },
1524 { "fec(TXFIFO)", 25 },
1525 { "fec(TXCR)", 26 },
1526 { "fec(RXF)", 27 },
1527 { "fec(RXB)", 28 },
1528 { "fec(MII)", 29 },
1529 { "fec(LC)", 30 },
1530 { "fec(HBERR)", 31 },
1531 { "fec(GRA)", 32 },
1532 { "fec(EBERR)", 33 },
1533 { "fec(BABT)", 34 },
1534 { "fec(BABR)", 35 },
1535 { NULL },
1536 };
1537
1538 fep = netdev_priv(dev);
1539 b = 64 + 13;
1540
1541 /* Setup interrupt handlers. */
1542 for (idp = id; idp->name; idp++) {
1543 if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
1544 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1545 }
1546
1547 /* Unmask interrupts at ColdFire interrupt controller */
1548 {
1549 volatile unsigned char *icrp;
1550 volatile unsigned long *imrp;
1551
1552 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1553 MCFINTC_ICR0);
1554 for (b = 36; (b < 49); b++)
1555 icrp[b] = 0x04;
1556 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1557 MCFINTC_IMRH);
1558 *imrp &= ~0x0001FFF0;
1559 }
1560 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1561 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1562 }
1563
1564 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1565 {
1566 volatile fec_t *fecp;
1567
1568 fecp = fep->hwp;
1569 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1570 fecp->fec_x_cntrl = 0x00;
1571
1572 /*
1573 * Set MII speed to 2.5 MHz
1574 * See 5282 manual section 17.5.4.7: MSCR
1575 */
1576 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1577 fecp->fec_mii_speed = fep->phy_speed;
1578
1579 fec_restart(dev, 0);
1580 }
1581
1582 static void __inline__ fec_get_mac(struct net_device *dev)
1583 {
1584 struct fec_enet_private *fep = netdev_priv(dev);
1585 volatile fec_t *fecp;
1586 unsigned char *iap, tmpaddr[ETH_ALEN];
1587
1588 fecp = fep->hwp;
1589
1590 if (FEC_FLASHMAC) {
1591 /*
1592 * Get MAC address from FLASH.
1593 * If it is all 1's or 0's, use the default.
1594 */
1595 iap = FEC_FLASHMAC;
1596 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1597 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1598 iap = fec_mac_default;
1599 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1600 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1601 iap = fec_mac_default;
1602 } else {
1603 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1604 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1605 iap = &tmpaddr[0];
1606 }
1607
1608 memcpy(dev->dev_addr, iap, ETH_ALEN);
1609
1610 /* Adjust MAC if using default MAC address */
1611 if (iap == fec_mac_default)
1612 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1613 }
1614
1615 static void __inline__ fec_enable_phy_intr(void)
1616 {
1617 }
1618
1619 static void __inline__ fec_disable_phy_intr(void)
1620 {
1621 }
1622
1623 static void __inline__ fec_phy_ack_intr(void)
1624 {
1625 }
1626
1627 static void __inline__ fec_localhw_setup(void)
1628 {
1629 }
1630
1631 static void __inline__ fec_uncache(unsigned long addr)
1632 {
1633 }
1634
1635 /* ------------------------------------------------------------------------- */
1636
1637 #elif defined(CONFIG_M532x)
1638 /*
1639 * Code specific for M532x
1640 */
1641 static void __inline__ fec_request_intrs(struct net_device *dev)
1642 {
1643 struct fec_enet_private *fep;
1644 int b;
1645 static const struct idesc {
1646 char *name;
1647 unsigned short irq;
1648 } *idp, id[] = {
1649 { "fec(TXF)", 36 },
1650 { "fec(TXB)", 37 },
1651 { "fec(TXFIFO)", 38 },
1652 { "fec(TXCR)", 39 },
1653 { "fec(RXF)", 40 },
1654 { "fec(RXB)", 41 },
1655 { "fec(MII)", 42 },
1656 { "fec(LC)", 43 },
1657 { "fec(HBERR)", 44 },
1658 { "fec(GRA)", 45 },
1659 { "fec(EBERR)", 46 },
1660 { "fec(BABT)", 47 },
1661 { "fec(BABR)", 48 },
1662 { NULL },
1663 };
1664
1665 fep = netdev_priv(dev);
1666 b = (fep->index) ? 128 : 64;
1667
1668 /* Setup interrupt handlers. */
1669 for (idp = id; idp->name; idp++) {
1670 if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
1671 printk("FEC: Could not allocate %s IRQ(%d)!\n",
1672 idp->name, b+idp->irq);
1673 }
1674
1675 /* Unmask interrupts */
1676 MCF_INTC0_ICR36 = 0x2;
1677 MCF_INTC0_ICR37 = 0x2;
1678 MCF_INTC0_ICR38 = 0x2;
1679 MCF_INTC0_ICR39 = 0x2;
1680 MCF_INTC0_ICR40 = 0x2;
1681 MCF_INTC0_ICR41 = 0x2;
1682 MCF_INTC0_ICR42 = 0x2;
1683 MCF_INTC0_ICR43 = 0x2;
1684 MCF_INTC0_ICR44 = 0x2;
1685 MCF_INTC0_ICR45 = 0x2;
1686 MCF_INTC0_ICR46 = 0x2;
1687 MCF_INTC0_ICR47 = 0x2;
1688 MCF_INTC0_ICR48 = 0x2;
1689
1690 MCF_INTC0_IMRH &= ~(
1691 MCF_INTC_IMRH_INT_MASK36 |
1692 MCF_INTC_IMRH_INT_MASK37 |
1693 MCF_INTC_IMRH_INT_MASK38 |
1694 MCF_INTC_IMRH_INT_MASK39 |
1695 MCF_INTC_IMRH_INT_MASK40 |
1696 MCF_INTC_IMRH_INT_MASK41 |
1697 MCF_INTC_IMRH_INT_MASK42 |
1698 MCF_INTC_IMRH_INT_MASK43 |
1699 MCF_INTC_IMRH_INT_MASK44 |
1700 MCF_INTC_IMRH_INT_MASK45 |
1701 MCF_INTC_IMRH_INT_MASK46 |
1702 MCF_INTC_IMRH_INT_MASK47 |
1703 MCF_INTC_IMRH_INT_MASK48 );
1704
1705 /* Set up gpio outputs for MII lines */
1706 MCF_GPIO_PAR_FECI2C |= (0 |
1707 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
1708 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
1709 MCF_GPIO_PAR_FEC = (0 |
1710 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
1711 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
1712 }
1713
1714 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1715 {
1716 volatile fec_t *fecp;
1717
1718 fecp = fep->hwp;
1719 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1720 fecp->fec_x_cntrl = 0x00;
1721
1722 /*
1723 * Set MII speed to 2.5 MHz
1724 */
1725 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1726 fecp->fec_mii_speed = fep->phy_speed;
1727
1728 fec_restart(dev, 0);
1729 }
1730
1731 static void __inline__ fec_get_mac(struct net_device *dev)
1732 {
1733 struct fec_enet_private *fep = netdev_priv(dev);
1734 volatile fec_t *fecp;
1735 unsigned char *iap, tmpaddr[ETH_ALEN];
1736
1737 fecp = fep->hwp;
1738
1739 if (FEC_FLASHMAC) {
1740 /*
1741 * Get MAC address from FLASH.
1742 * If it is all 1's or 0's, use the default.
1743 */
1744 iap = FEC_FLASHMAC;
1745 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1746 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1747 iap = fec_mac_default;
1748 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1749 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1750 iap = fec_mac_default;
1751 } else {
1752 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1753 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1754 iap = &tmpaddr[0];
1755 }
1756
1757 memcpy(dev->dev_addr, iap, ETH_ALEN);
1758
1759 /* Adjust MAC if using default MAC address */
1760 if (iap == fec_mac_default)
1761 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1762 }
1763
1764 static void __inline__ fec_enable_phy_intr(void)
1765 {
1766 }
1767
1768 static void __inline__ fec_disable_phy_intr(void)
1769 {
1770 }
1771
1772 static void __inline__ fec_phy_ack_intr(void)
1773 {
1774 }
1775
1776 static void __inline__ fec_localhw_setup(void)
1777 {
1778 }
1779
1780 /*
1781 * Do not need to make region uncached on 532x.
1782 */
1783 static void __inline__ fec_uncache(unsigned long addr)
1784 {
1785 }
1786
1787 /* ------------------------------------------------------------------------- */
1788
1789
1790 #else
1791
1792 /*
1793 * Code specific to the MPC860T setup.
1794 */
1795 static void __inline__ fec_request_intrs(struct net_device *dev)
1796 {
1797 volatile immap_t *immap;
1798
1799 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1800
1801 if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1802 panic("Could not allocate FEC IRQ!");
1803
1804 #ifdef CONFIG_RPXCLASSIC
1805 /* Make Port C, bit 15 an input that causes interrupts.
1806 */
1807 immap->im_ioport.iop_pcpar &= ~0x0001;
1808 immap->im_ioport.iop_pcdir &= ~0x0001;
1809 immap->im_ioport.iop_pcso &= ~0x0001;
1810 immap->im_ioport.iop_pcint |= 0x0001;
1811 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1812
1813 /* Make LEDS reflect Link status.
1814 */
1815 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1816 #endif
1817 #ifdef CONFIG_FADS
1818 if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0)
1819 panic("Could not allocate MII IRQ!");
1820 #endif
1821 }
1822
1823 static void __inline__ fec_get_mac(struct net_device *dev)
1824 {
1825 bd_t *bd;
1826
1827 bd = (bd_t *)__res;
1828 memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN);
1829
1830 #ifdef CONFIG_RPXCLASSIC
1831 /* The Embedded Planet boards have only one MAC address in
1832 * the EEPROM, but can have two Ethernet ports. For the
1833 * FEC port, we create another address by setting one of
1834 * the address bits above something that would have (up to
1835 * now) been allocated.
1836 */
1837 dev->dev_adrd[3] |= 0x80;
1838 #endif
1839 }
1840
1841 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1842 {
1843 extern uint _get_IMMR(void);
1844 volatile immap_t *immap;
1845 volatile fec_t *fecp;
1846
1847 fecp = fep->hwp;
1848 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1849
1850 /* Configure all of port D for MII.
1851 */
1852 immap->im_ioport.iop_pdpar = 0x1fff;
1853
1854 /* Bits moved from Rev. D onward.
1855 */
1856 if ((_get_IMMR() & 0xffff) < 0x0501)
1857 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1858 else
1859 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1860
1861 /* Set MII speed to 2.5 MHz
1862 */
1863 fecp->fec_mii_speed = fep->phy_speed =
1864 ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e;
1865 }
1866
1867 static void __inline__ fec_enable_phy_intr(void)
1868 {
1869 volatile fec_t *fecp;
1870
1871 fecp = fep->hwp;
1872
1873 /* Enable MII command finished interrupt
1874 */
1875 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1876 }
1877
1878 static void __inline__ fec_disable_phy_intr(void)
1879 {
1880 }
1881
1882 static void __inline__ fec_phy_ack_intr(void)
1883 {
1884 }
1885
1886 static void __inline__ fec_localhw_setup(void)
1887 {
1888 volatile fec_t *fecp;
1889
1890 fecp = fep->hwp;
1891 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1892 /* Enable big endian and don't care about SDMA FC.
1893 */
1894 fecp->fec_fun_code = 0x78000000;
1895 }
1896
1897 static void __inline__ fec_uncache(unsigned long addr)
1898 {
1899 pte_t *pte;
1900 pte = va_to_pte(mem_addr);
1901 pte_val(*pte) |= _PAGE_NO_CACHE;
1902 flush_tlb_page(init_mm.mmap, mem_addr);
1903 }
1904
1905 #endif
1906
1907 /* ------------------------------------------------------------------------- */
1908
1909 static void mii_display_status(struct net_device *dev)
1910 {
1911 struct fec_enet_private *fep = netdev_priv(dev);
1912 volatile uint *s = &(fep->phy_status);
1913
1914 if (!fep->link && !fep->old_link) {
1915 /* Link is still down - don't print anything */
1916 return;
1917 }
1918
1919 printk("%s: status: ", dev->name);
1920
1921 if (!fep->link) {
1922 printk("link down");
1923 } else {
1924 printk("link up");
1925
1926 switch(*s & PHY_STAT_SPMASK) {
1927 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1928 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1929 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1930 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1931 default:
1932 printk(", Unknown speed/duplex");
1933 }
1934
1935 if (*s & PHY_STAT_ANC)
1936 printk(", auto-negotiation complete");
1937 }
1938
1939 if (*s & PHY_STAT_FAULT)
1940 printk(", remote fault");
1941
1942 printk(".\n");
1943 }
1944
1945 static void mii_display_config(struct net_device *dev)
1946 {
1947 struct fec_enet_private *fep = netdev_priv(dev);
1948 uint status = fep->phy_status;
1949
1950 /*
1951 ** When we get here, phy_task is already removed from
1952 ** the workqueue. It is thus safe to allow to reuse it.
1953 */
1954 fep->mii_phy_task_queued = 0;
1955 printk("%s: config: auto-negotiation ", dev->name);
1956
1957 if (status & PHY_CONF_ANE)
1958 printk("on");
1959 else
1960 printk("off");
1961
1962 if (status & PHY_CONF_100FDX)
1963 printk(", 100FDX");
1964 if (status & PHY_CONF_100HDX)
1965 printk(", 100HDX");
1966 if (status & PHY_CONF_10FDX)
1967 printk(", 10FDX");
1968 if (status & PHY_CONF_10HDX)
1969 printk(", 10HDX");
1970 if (!(status & PHY_CONF_SPMASK))
1971 printk(", No speed/duplex selected?");
1972
1973 if (status & PHY_CONF_LOOP)
1974 printk(", loopback enabled");
1975
1976 printk(".\n");
1977
1978 fep->sequence_done = 1;
1979 }
1980
1981 static void mii_relink(struct net_device *dev)
1982 {
1983 struct fec_enet_private *fep = netdev_priv(dev);
1984 int duplex;
1985
1986 /*
1987 ** When we get here, phy_task is already removed from
1988 ** the workqueue. It is thus safe to allow to reuse it.
1989 */
1990 fep->mii_phy_task_queued = 0;
1991 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1992 mii_display_status(dev);
1993 fep->old_link = fep->link;
1994
1995 if (fep->link) {
1996 duplex = 0;
1997 if (fep->phy_status
1998 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1999 duplex = 1;
2000 fec_restart(dev, duplex);
2001 }
2002 else
2003 fec_stop(dev);
2004
2005 #if 0
2006 enable_irq(fep->mii_irq);
2007 #endif
2008
2009 }
2010
2011 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
2012 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
2013 {
2014 struct fec_enet_private *fep = netdev_priv(dev);
2015
2016 /*
2017 ** We cannot queue phy_task twice in the workqueue. It
2018 ** would cause an endless loop in the workqueue.
2019 ** Fortunately, if the last mii_relink entry has not yet been
2020 ** executed now, it will do the job for the current interrupt,
2021 ** which is just what we want.
2022 */
2023 if (fep->mii_phy_task_queued)
2024 return;
2025
2026 fep->mii_phy_task_queued = 1;
2027 INIT_WORK(&fep->phy_task, (void*)mii_relink, dev);
2028 schedule_work(&fep->phy_task);
2029 }
2030
2031 /* mii_queue_config is called in interrupt context from fec_enet_mii */
2032 static void mii_queue_config(uint mii_reg, struct net_device *dev)
2033 {
2034 struct fec_enet_private *fep = netdev_priv(dev);
2035
2036 if (fep->mii_phy_task_queued)
2037 return;
2038
2039 fep->mii_phy_task_queued = 1;
2040 INIT_WORK(&fep->phy_task, (void*)mii_display_config, dev);
2041 schedule_work(&fep->phy_task);
2042 }
2043
2044 phy_cmd_t const phy_cmd_relink[] = {
2045 { mk_mii_read(MII_REG_CR), mii_queue_relink },
2046 { mk_mii_end, }
2047 };
2048 phy_cmd_t const phy_cmd_config[] = {
2049 { mk_mii_read(MII_REG_CR), mii_queue_config },
2050 { mk_mii_end, }
2051 };
2052
2053 /* Read remainder of PHY ID.
2054 */
2055 static void
2056 mii_discover_phy3(uint mii_reg, struct net_device *dev)
2057 {
2058 struct fec_enet_private *fep;
2059 int i;
2060
2061 fep = netdev_priv(dev);
2062 fep->phy_id |= (mii_reg & 0xffff);
2063 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
2064
2065 for(i = 0; phy_info[i]; i++) {
2066 if(phy_info[i]->id == (fep->phy_id >> 4))
2067 break;
2068 }
2069
2070 if (phy_info[i])
2071 printk(" -- %s\n", phy_info[i]->name);
2072 else
2073 printk(" -- unknown PHY!\n");
2074
2075 fep->phy = phy_info[i];
2076 fep->phy_id_done = 1;
2077 }
2078
2079 /* Scan all of the MII PHY addresses looking for someone to respond
2080 * with a valid ID. This usually happens quickly.
2081 */
2082 static void
2083 mii_discover_phy(uint mii_reg, struct net_device *dev)
2084 {
2085 struct fec_enet_private *fep;
2086 volatile fec_t *fecp;
2087 uint phytype;
2088
2089 fep = netdev_priv(dev);
2090 fecp = fep->hwp;
2091
2092 if (fep->phy_addr < 32) {
2093 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
2094
2095 /* Got first part of ID, now get remainder.
2096 */
2097 fep->phy_id = phytype << 16;
2098 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
2099 mii_discover_phy3);
2100 }
2101 else {
2102 fep->phy_addr++;
2103 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
2104 mii_discover_phy);
2105 }
2106 } else {
2107 printk("FEC: No PHY device found.\n");
2108 /* Disable external MII interface */
2109 fecp->fec_mii_speed = fep->phy_speed = 0;
2110 fec_disable_phy_intr();
2111 }
2112 }
2113
2114 /* This interrupt occurs when the PHY detects a link change.
2115 */
2116 #ifdef CONFIG_RPXCLASSIC
2117 static void
2118 mii_link_interrupt(void *dev_id)
2119 #else
2120 static irqreturn_t
2121 mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
2122 #endif
2123 {
2124 struct net_device *dev = dev_id;
2125 struct fec_enet_private *fep = netdev_priv(dev);
2126
2127 fec_phy_ack_intr();
2128
2129 #if 0
2130 disable_irq(fep->mii_irq); /* disable now, enable later */
2131 #endif
2132
2133 mii_do_cmd(dev, fep->phy->ack_int);
2134 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
2135
2136 return IRQ_HANDLED;
2137 }
2138
2139 static int
2140 fec_enet_open(struct net_device *dev)
2141 {
2142 struct fec_enet_private *fep = netdev_priv(dev);
2143
2144 /* I should reset the ring buffers here, but I don't yet know
2145 * a simple way to do that.
2146 */
2147 fec_set_mac_address(dev);
2148
2149 fep->sequence_done = 0;
2150 fep->link = 0;
2151
2152 if (fep->phy) {
2153 mii_do_cmd(dev, fep->phy->ack_int);
2154 mii_do_cmd(dev, fep->phy->config);
2155 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
2156
2157 /* Poll until the PHY tells us its configuration
2158 * (not link state).
2159 * Request is initiated by mii_do_cmd above, but answer
2160 * comes by interrupt.
2161 * This should take about 25 usec per register at 2.5 MHz,
2162 * and we read approximately 5 registers.
2163 */
2164 while(!fep->sequence_done)
2165 schedule();
2166
2167 mii_do_cmd(dev, fep->phy->startup);
2168
2169 /* Set the initial link state to true. A lot of hardware
2170 * based on this device does not implement a PHY interrupt,
2171 * so we are never notified of link change.
2172 */
2173 fep->link = 1;
2174 } else {
2175 fep->link = 1; /* lets just try it and see */
2176 /* no phy, go full duplex, it's most likely a hub chip */
2177 fec_restart(dev, 1);
2178 }
2179
2180 netif_start_queue(dev);
2181 fep->opened = 1;
2182 return 0; /* Success */
2183 }
2184
2185 static int
2186 fec_enet_close(struct net_device *dev)
2187 {
2188 struct fec_enet_private *fep = netdev_priv(dev);
2189
2190 /* Don't know what to do yet.
2191 */
2192 fep->opened = 0;
2193 netif_stop_queue(dev);
2194 fec_stop(dev);
2195
2196 return 0;
2197 }
2198
2199 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev)
2200 {
2201 struct fec_enet_private *fep = netdev_priv(dev);
2202
2203 return &fep->stats;
2204 }
2205
2206 /* Set or clear the multicast filter for this adaptor.
2207 * Skeleton taken from sunlance driver.
2208 * The CPM Ethernet implementation allows Multicast as well as individual
2209 * MAC address filtering. Some of the drivers check to make sure it is
2210 * a group multicast address, and discard those that are not. I guess I
2211 * will do the same for now, but just remove the test if you want
2212 * individual filtering as well (do the upper net layers want or support
2213 * this kind of feature?).
2214 */
2215
2216 #define HASH_BITS 6 /* #bits in hash */
2217 #define CRC32_POLY 0xEDB88320
2218
2219 static void set_multicast_list(struct net_device *dev)
2220 {
2221 struct fec_enet_private *fep;
2222 volatile fec_t *ep;
2223 struct dev_mc_list *dmi;
2224 unsigned int i, j, bit, data, crc;
2225 unsigned char hash;
2226
2227 fep = netdev_priv(dev);
2228 ep = fep->hwp;
2229
2230 if (dev->flags&IFF_PROMISC) {
2231 /* Log any net taps. */
2232 printk("%s: Promiscuous mode enabled.\n", dev->name);
2233 ep->fec_r_cntrl |= 0x0008;
2234 } else {
2235
2236 ep->fec_r_cntrl &= ~0x0008;
2237
2238 if (dev->flags & IFF_ALLMULTI) {
2239 /* Catch all multicast addresses, so set the
2240 * filter to all 1's.
2241 */
2242 ep->fec_hash_table_high = 0xffffffff;
2243 ep->fec_hash_table_low = 0xffffffff;
2244 } else {
2245 /* Clear filter and add the addresses in hash register.
2246 */
2247 ep->fec_hash_table_high = 0;
2248 ep->fec_hash_table_low = 0;
2249
2250 dmi = dev->mc_list;
2251
2252 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2253 {
2254 /* Only support group multicast for now.
2255 */
2256 if (!(dmi->dmi_addr[0] & 1))
2257 continue;
2258
2259 /* calculate crc32 value of mac address
2260 */
2261 crc = 0xffffffff;
2262
2263 for (i = 0; i < dmi->dmi_addrlen; i++)
2264 {
2265 data = dmi->dmi_addr[i];
2266 for (bit = 0; bit < 8; bit++, data >>= 1)
2267 {
2268 crc = (crc >> 1) ^
2269 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2270 }
2271 }
2272
2273 /* only upper 6 bits (HASH_BITS) are used
2274 which point to specific bit in he hash registers
2275 */
2276 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2277
2278 if (hash > 31)
2279 ep->fec_hash_table_high |= 1 << (hash - 32);
2280 else
2281 ep->fec_hash_table_low |= 1 << hash;
2282 }
2283 }
2284 }
2285 }
2286
2287 /* Set a MAC change in hardware.
2288 */
2289 static void
2290 fec_set_mac_address(struct net_device *dev)
2291 {
2292 volatile fec_t *fecp;
2293
2294 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
2295
2296 /* Set station address. */
2297 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2298 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2299 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2300 (dev->dev_addr[4] << 24);
2301
2302 }
2303
2304 /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2305 */
2306 /*
2307 * XXX: We need to clean up on failure exits here.
2308 */
2309 int __init fec_enet_init(struct net_device *dev)
2310 {
2311 struct fec_enet_private *fep = netdev_priv(dev);
2312 unsigned long mem_addr;
2313 volatile cbd_t *bdp;
2314 cbd_t *cbd_base;
2315 volatile fec_t *fecp;
2316 int i, j;
2317 static int index = 0;
2318
2319 /* Only allow us to be probed once. */
2320 if (index >= FEC_MAX_PORTS)
2321 return -ENXIO;
2322
2323 /* Allocate memory for buffer descriptors.
2324 */
2325 mem_addr = __get_free_page(GFP_KERNEL);
2326 if (mem_addr == 0) {
2327 printk("FEC: allocate descriptor memory failed?\n");
2328 return -ENOMEM;
2329 }
2330
2331 /* Create an Ethernet device instance.
2332 */
2333 fecp = (volatile fec_t *) fec_hw[index];
2334
2335 fep->index = index;
2336 fep->hwp = fecp;
2337
2338 /* Whack a reset. We should wait for this.
2339 */
2340 fecp->fec_ecntrl = 1;
2341 udelay(10);
2342
2343 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2344 * this needs some work to get unique addresses.
2345 *
2346 * This is our default MAC address unless the user changes
2347 * it via eth_mac_addr (our dev->set_mac_addr handler).
2348 */
2349 fec_get_mac(dev);
2350
2351 cbd_base = (cbd_t *)mem_addr;
2352 /* XXX: missing check for allocation failure */
2353
2354 fec_uncache(mem_addr);
2355
2356 /* Set receive and transmit descriptor base.
2357 */
2358 fep->rx_bd_base = cbd_base;
2359 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2360
2361 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2362 fep->cur_rx = fep->rx_bd_base;
2363
2364 fep->skb_cur = fep->skb_dirty = 0;
2365
2366 /* Initialize the receive buffer descriptors.
2367 */
2368 bdp = fep->rx_bd_base;
2369 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2370
2371 /* Allocate a page.
2372 */
2373 mem_addr = __get_free_page(GFP_KERNEL);
2374 /* XXX: missing check for allocation failure */
2375
2376 fec_uncache(mem_addr);
2377
2378 /* Initialize the BD for every fragment in the page.
2379 */
2380 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2381 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2382 bdp->cbd_bufaddr = __pa(mem_addr);
2383 mem_addr += FEC_ENET_RX_FRSIZE;
2384 bdp++;
2385 }
2386 }
2387
2388 /* Set the last buffer to wrap.
2389 */
2390 bdp--;
2391 bdp->cbd_sc |= BD_SC_WRAP;
2392
2393 /* ...and the same for transmmit.
2394 */
2395 bdp = fep->tx_bd_base;
2396 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2397 if (j >= FEC_ENET_TX_FRPPG) {
2398 mem_addr = __get_free_page(GFP_KERNEL);
2399 j = 1;
2400 } else {
2401 mem_addr += FEC_ENET_TX_FRSIZE;
2402 j++;
2403 }
2404 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2405
2406 /* Initialize the BD for every fragment in the page.
2407 */
2408 bdp->cbd_sc = 0;
2409 bdp->cbd_bufaddr = 0;
2410 bdp++;
2411 }
2412
2413 /* Set the last buffer to wrap.
2414 */
2415 bdp--;
2416 bdp->cbd_sc |= BD_SC_WRAP;
2417
2418 /* Set receive and transmit descriptor base.
2419 */
2420 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2421 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2422
2423 /* Install our interrupt handlers. This varies depending on
2424 * the architecture.
2425 */
2426 fec_request_intrs(dev);
2427
2428 fecp->fec_hash_table_high = 0;
2429 fecp->fec_hash_table_low = 0;
2430 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2431 fecp->fec_ecntrl = 2;
2432 fecp->fec_r_des_active = 0;
2433
2434 dev->base_addr = (unsigned long)fecp;
2435
2436 /* The FEC Ethernet specific entries in the device structure. */
2437 dev->open = fec_enet_open;
2438 dev->hard_start_xmit = fec_enet_start_xmit;
2439 dev->tx_timeout = fec_timeout;
2440 dev->watchdog_timeo = TX_TIMEOUT;
2441 dev->stop = fec_enet_close;
2442 dev->get_stats = fec_enet_get_stats;
2443 dev->set_multicast_list = set_multicast_list;
2444
2445 for (i=0; i<NMII-1; i++)
2446 mii_cmds[i].mii_next = &mii_cmds[i+1];
2447 mii_free = mii_cmds;
2448
2449 /* setup MII interface */
2450 fec_set_mii(dev, fep);
2451
2452 /* Clear and enable interrupts */
2453 fecp->fec_ievent = 0xffc00000;
2454 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2455 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2456
2457 /* Queue up command to detect the PHY and initialize the
2458 * remainder of the interface.
2459 */
2460 fep->phy_id_done = 0;
2461 fep->phy_addr = 0;
2462 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2463
2464 index++;
2465 return 0;
2466 }
2467
2468 /* This function is called to start or restart the FEC during a link
2469 * change. This only happens when switching between half and full
2470 * duplex.
2471 */
2472 static void
2473 fec_restart(struct net_device *dev, int duplex)
2474 {
2475 struct fec_enet_private *fep;
2476 volatile cbd_t *bdp;
2477 volatile fec_t *fecp;
2478 int i;
2479
2480 fep = netdev_priv(dev);
2481 fecp = fep->hwp;
2482
2483 /* Whack a reset. We should wait for this.
2484 */
2485 fecp->fec_ecntrl = 1;
2486 udelay(10);
2487
2488 /* Clear any outstanding interrupt.
2489 */
2490 fecp->fec_ievent = 0xffc00000;
2491 fec_enable_phy_intr();
2492
2493 /* Set station address.
2494 */
2495 fec_set_mac_address(dev);
2496
2497 /* Reset all multicast.
2498 */
2499 fecp->fec_hash_table_high = 0;
2500 fecp->fec_hash_table_low = 0;
2501
2502 /* Set maximum receive buffer size.
2503 */
2504 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2505
2506 fec_localhw_setup();
2507
2508 /* Set receive and transmit descriptor base.
2509 */
2510 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2511 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2512
2513 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2514 fep->cur_rx = fep->rx_bd_base;
2515
2516 /* Reset SKB transmit buffers.
2517 */
2518 fep->skb_cur = fep->skb_dirty = 0;
2519 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2520 if (fep->tx_skbuff[i] != NULL) {
2521 dev_kfree_skb_any(fep->tx_skbuff[i]);
2522 fep->tx_skbuff[i] = NULL;
2523 }
2524 }
2525
2526 /* Initialize the receive buffer descriptors.
2527 */
2528 bdp = fep->rx_bd_base;
2529 for (i=0; i<RX_RING_SIZE; i++) {
2530
2531 /* Initialize the BD for every fragment in the page.
2532 */
2533 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2534 bdp++;
2535 }
2536
2537 /* Set the last buffer to wrap.
2538 */
2539 bdp--;
2540 bdp->cbd_sc |= BD_SC_WRAP;
2541
2542 /* ...and the same for transmmit.
2543 */
2544 bdp = fep->tx_bd_base;
2545 for (i=0; i<TX_RING_SIZE; i++) {
2546
2547 /* Initialize the BD for every fragment in the page.
2548 */
2549 bdp->cbd_sc = 0;
2550 bdp->cbd_bufaddr = 0;
2551 bdp++;
2552 }
2553
2554 /* Set the last buffer to wrap.
2555 */
2556 bdp--;
2557 bdp->cbd_sc |= BD_SC_WRAP;
2558
2559 /* Enable MII mode.
2560 */
2561 if (duplex) {
2562 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2563 fecp->fec_x_cntrl = 0x04; /* FD enable */
2564 }
2565 else {
2566 /* MII enable|No Rcv on Xmit */
2567 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2568 fecp->fec_x_cntrl = 0x00;
2569 }
2570 fep->full_duplex = duplex;
2571
2572 /* Set MII speed.
2573 */
2574 fecp->fec_mii_speed = fep->phy_speed;
2575
2576 /* And last, enable the transmit and receive processing.
2577 */
2578 fecp->fec_ecntrl = 2;
2579 fecp->fec_r_des_active = 0;
2580
2581 /* Enable interrupts we wish to service.
2582 */
2583 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2584 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2585 }
2586
2587 static void
2588 fec_stop(struct net_device *dev)
2589 {
2590 volatile fec_t *fecp;
2591 struct fec_enet_private *fep;
2592
2593 fep = netdev_priv(dev);
2594 fecp = fep->hwp;
2595
2596 /*
2597 ** We cannot expect a graceful transmit stop without link !!!
2598 */
2599 if (fep->link)
2600 {
2601 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2602 udelay(10);
2603 if (!(fecp->fec_ievent & FEC_ENET_GRA))
2604 printk("fec_stop : Graceful transmit stop did not complete !\n");
2605 }
2606
2607 /* Whack a reset. We should wait for this.
2608 */
2609 fecp->fec_ecntrl = 1;
2610 udelay(10);
2611
2612 /* Clear outstanding MII command interrupts.
2613 */
2614 fecp->fec_ievent = FEC_ENET_MII;
2615 fec_enable_phy_intr();
2616
2617 fecp->fec_imask = FEC_ENET_MII;
2618 fecp->fec_mii_speed = fep->phy_speed;
2619 }
2620
2621 static int __init fec_enet_module_init(void)
2622 {
2623 struct net_device *dev;
2624 int i, j, err;
2625
2626 printk("FEC ENET Version 0.2\n");
2627
2628 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2629 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2630 if (!dev)
2631 return -ENOMEM;
2632 err = fec_enet_init(dev);
2633 if (err) {
2634 free_netdev(dev);
2635 continue;
2636 }
2637 if (register_netdev(dev) != 0) {
2638 /* XXX: missing cleanup here */
2639 free_netdev(dev);
2640 return -EIO;
2641 }
2642
2643 printk("%s: ethernet ", dev->name);
2644 for (j = 0; (j < 5); j++)
2645 printk("%02x:", dev->dev_addr[j]);
2646 printk("%02x\n", dev->dev_addr[5]);
2647 }
2648 return 0;
2649 }
2650
2651 module_init(fec_enet_module_init);
2652
2653 MODULE_LICENSE("GPL");
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