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[mirror_ubuntu-zesty-kernel.git] / drivers / net / forcedeth.c
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,5,6 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Changelog:
33 * 0.01: 05 Oct 2003: First release that compiles without warnings.
34 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
35 * Check all PCI BARs for the register window.
36 * udelay added to mii_rw.
37 * 0.03: 06 Oct 2003: Initialize dev->irq.
38 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
39 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
40 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
41 * irq mask updated
42 * 0.07: 14 Oct 2003: Further irq mask updates.
43 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
44 * added into irq handler, NULL check for drain_ring.
45 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
46 * requested interrupt sources.
47 * 0.10: 20 Oct 2003: First cleanup for release.
48 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
49 * MAC Address init fix, set_multicast cleanup.
50 * 0.12: 23 Oct 2003: Cleanups for release.
51 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
52 * Set link speed correctly. start rx before starting
53 * tx (nv_start_rx sets the link speed).
54 * 0.14: 25 Oct 2003: Nic dependant irq mask.
55 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
56 * open.
57 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
58 * increased to 1628 bytes.
59 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
60 * the tx length.
61 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
62 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
63 * addresses, really stop rx if already running
64 * in nv_start_rx, clean up a bit.
65 * 0.20: 07 Dec 2003: alloc fixes
66 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
67 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
68 * on close.
69 * 0.23: 26 Jan 2004: various small cleanups
70 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71 * 0.25: 09 Mar 2004: wol support
72 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
73 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
74 * added CK804/MCP04 device IDs, code fixes
75 * for registers, link status and other minor fixes.
76 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
77 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
78 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
79 * into nv_close, otherwise reenabling for wol can
80 * cause DMA to kfree'd memory.
81 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
82 * capabilities.
83 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
84 * 0.33: 16 May 2005: Support for MCP51 added.
85 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
86 * 0.35: 26 Jun 2005: Support for MCP55 added.
87 * 0.36: 28 Jun 2005: Add jumbo frame support.
88 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
89 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
90 * per-packet flags.
91 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
92 * 0.40: 19 Jul 2005: Add support for mac address change.
93 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
94 * of nv_remove
95 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
96 * in the second (and later) nv_open call
97 * 0.43: 10 Aug 2005: Add support for tx checksum.
98 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
99 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
100 * 0.46: 20 Oct 2005: Add irq optimization modes.
101 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
102 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
103 * 0.49: 10 Dec 2005: Fix tso for large buffers.
104 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
105 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
106 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
107 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
108 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
109 * 0.55: 22 Mar 2006: Add flow control (pause frame).
110 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
111 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
112 * 0.58: 30 Oct 2006: Added support for sideband management unit.
113 * 0.59: 30 Oct 2006: Added support for recoverable error.
114 * 0.60: 20 Jan 2007: Code optimizations for rings, rx & tx data paths, and stats.
115 *
116 * Known bugs:
117 * We suspect that on some hardware no TX done interrupts are generated.
118 * This means recovery from netif_stop_queue only happens if the hw timer
119 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
120 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
121 * If your hardware reliably generates tx done interrupts, then you can remove
122 * DEV_NEED_TIMERIRQ from the driver_data flags.
123 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
124 * superfluous timer interrupts from the nic.
125 */
126 #ifdef CONFIG_FORCEDETH_NAPI
127 #define DRIVERNAPI "-NAPI"
128 #else
129 #define DRIVERNAPI
130 #endif
131 #define FORCEDETH_VERSION "0.60"
132 #define DRV_NAME "forcedeth"
133
134 #include <linux/module.h>
135 #include <linux/types.h>
136 #include <linux/pci.h>
137 #include <linux/interrupt.h>
138 #include <linux/netdevice.h>
139 #include <linux/etherdevice.h>
140 #include <linux/delay.h>
141 #include <linux/spinlock.h>
142 #include <linux/ethtool.h>
143 #include <linux/timer.h>
144 #include <linux/skbuff.h>
145 #include <linux/mii.h>
146 #include <linux/random.h>
147 #include <linux/init.h>
148 #include <linux/if_vlan.h>
149 #include <linux/dma-mapping.h>
150
151 #include <asm/irq.h>
152 #include <asm/io.h>
153 #include <asm/uaccess.h>
154 #include <asm/system.h>
155
156 #if 0
157 #define dprintk printk
158 #else
159 #define dprintk(x...) do { } while (0)
160 #endif
161
162
163 /*
164 * Hardware access:
165 */
166
167 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
168 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
169 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
170 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
171 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
172 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
173 #define DEV_HAS_MSI 0x0040 /* device supports MSI */
174 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
175 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
176 #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
177 #define DEV_HAS_STATISTICS_V1 0x0400 /* device supports hw statistics version 1 */
178 #define DEV_HAS_STATISTICS_V2 0x0800 /* device supports hw statistics version 2 */
179 #define DEV_HAS_TEST_EXTENDED 0x1000 /* device supports extended diagnostic test */
180 #define DEV_HAS_MGMT_UNIT 0x2000 /* device supports management unit */
181
182 enum {
183 NvRegIrqStatus = 0x000,
184 #define NVREG_IRQSTAT_MIIEVENT 0x040
185 #define NVREG_IRQSTAT_MASK 0x81ff
186 NvRegIrqMask = 0x004,
187 #define NVREG_IRQ_RX_ERROR 0x0001
188 #define NVREG_IRQ_RX 0x0002
189 #define NVREG_IRQ_RX_NOBUF 0x0004
190 #define NVREG_IRQ_TX_ERR 0x0008
191 #define NVREG_IRQ_TX_OK 0x0010
192 #define NVREG_IRQ_TIMER 0x0020
193 #define NVREG_IRQ_LINK 0x0040
194 #define NVREG_IRQ_RX_FORCED 0x0080
195 #define NVREG_IRQ_TX_FORCED 0x0100
196 #define NVREG_IRQ_RECOVER_ERROR 0x8000
197 #define NVREG_IRQMASK_THROUGHPUT 0x00df
198 #define NVREG_IRQMASK_CPU 0x0040
199 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
200 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
201 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
202
203 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
204 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
205 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
206
207 NvRegUnknownSetupReg6 = 0x008,
208 #define NVREG_UNKSETUP6_VAL 3
209
210 /*
211 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
212 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
213 */
214 NvRegPollingInterval = 0x00c,
215 #define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */
216 #define NVREG_POLL_DEFAULT_CPU 13
217 NvRegMSIMap0 = 0x020,
218 NvRegMSIMap1 = 0x024,
219 NvRegMSIIrqMask = 0x030,
220 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
221 NvRegMisc1 = 0x080,
222 #define NVREG_MISC1_PAUSE_TX 0x01
223 #define NVREG_MISC1_HD 0x02
224 #define NVREG_MISC1_FORCE 0x3b0f3c
225
226 NvRegMacReset = 0x3c,
227 #define NVREG_MAC_RESET_ASSERT 0x0F3
228 NvRegTransmitterControl = 0x084,
229 #define NVREG_XMITCTL_START 0x01
230 #define NVREG_XMITCTL_MGMT_ST 0x40000000
231 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
232 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
233 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
234 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
235 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
236 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
237 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
238 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
239 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
240 NvRegTransmitterStatus = 0x088,
241 #define NVREG_XMITSTAT_BUSY 0x01
242
243 NvRegPacketFilterFlags = 0x8c,
244 #define NVREG_PFF_PAUSE_RX 0x08
245 #define NVREG_PFF_ALWAYS 0x7F0000
246 #define NVREG_PFF_PROMISC 0x80
247 #define NVREG_PFF_MYADDR 0x20
248 #define NVREG_PFF_LOOPBACK 0x10
249
250 NvRegOffloadConfig = 0x90,
251 #define NVREG_OFFLOAD_HOMEPHY 0x601
252 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
253 NvRegReceiverControl = 0x094,
254 #define NVREG_RCVCTL_START 0x01
255 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
256 NvRegReceiverStatus = 0x98,
257 #define NVREG_RCVSTAT_BUSY 0x01
258
259 NvRegRandomSeed = 0x9c,
260 #define NVREG_RNDSEED_MASK 0x00ff
261 #define NVREG_RNDSEED_FORCE 0x7f00
262 #define NVREG_RNDSEED_FORCE2 0x2d00
263 #define NVREG_RNDSEED_FORCE3 0x7400
264
265 NvRegTxDeferral = 0xA0,
266 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
267 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
268 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
269 NvRegRxDeferral = 0xA4,
270 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
271 NvRegMacAddrA = 0xA8,
272 NvRegMacAddrB = 0xAC,
273 NvRegMulticastAddrA = 0xB0,
274 #define NVREG_MCASTADDRA_FORCE 0x01
275 NvRegMulticastAddrB = 0xB4,
276 NvRegMulticastMaskA = 0xB8,
277 NvRegMulticastMaskB = 0xBC,
278
279 NvRegPhyInterface = 0xC0,
280 #define PHY_RGMII 0x10000000
281
282 NvRegTxRingPhysAddr = 0x100,
283 NvRegRxRingPhysAddr = 0x104,
284 NvRegRingSizes = 0x108,
285 #define NVREG_RINGSZ_TXSHIFT 0
286 #define NVREG_RINGSZ_RXSHIFT 16
287 NvRegTransmitPoll = 0x10c,
288 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
289 NvRegLinkSpeed = 0x110,
290 #define NVREG_LINKSPEED_FORCE 0x10000
291 #define NVREG_LINKSPEED_10 1000
292 #define NVREG_LINKSPEED_100 100
293 #define NVREG_LINKSPEED_1000 50
294 #define NVREG_LINKSPEED_MASK (0xFFF)
295 NvRegUnknownSetupReg5 = 0x130,
296 #define NVREG_UNKSETUP5_BIT31 (1<<31)
297 NvRegTxWatermark = 0x13c,
298 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
299 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
300 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
301 NvRegTxRxControl = 0x144,
302 #define NVREG_TXRXCTL_KICK 0x0001
303 #define NVREG_TXRXCTL_BIT1 0x0002
304 #define NVREG_TXRXCTL_BIT2 0x0004
305 #define NVREG_TXRXCTL_IDLE 0x0008
306 #define NVREG_TXRXCTL_RESET 0x0010
307 #define NVREG_TXRXCTL_RXCHECK 0x0400
308 #define NVREG_TXRXCTL_DESC_1 0
309 #define NVREG_TXRXCTL_DESC_2 0x002100
310 #define NVREG_TXRXCTL_DESC_3 0xc02200
311 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
312 #define NVREG_TXRXCTL_VLANINS 0x00080
313 NvRegTxRingPhysAddrHigh = 0x148,
314 NvRegRxRingPhysAddrHigh = 0x14C,
315 NvRegTxPauseFrame = 0x170,
316 #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080
317 #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030
318 NvRegMIIStatus = 0x180,
319 #define NVREG_MIISTAT_ERROR 0x0001
320 #define NVREG_MIISTAT_LINKCHANGE 0x0008
321 #define NVREG_MIISTAT_MASK 0x000f
322 #define NVREG_MIISTAT_MASK2 0x000f
323 NvRegMIIMask = 0x184,
324 #define NVREG_MII_LINKCHANGE 0x0008
325
326 NvRegAdapterControl = 0x188,
327 #define NVREG_ADAPTCTL_START 0x02
328 #define NVREG_ADAPTCTL_LINKUP 0x04
329 #define NVREG_ADAPTCTL_PHYVALID 0x40000
330 #define NVREG_ADAPTCTL_RUNNING 0x100000
331 #define NVREG_ADAPTCTL_PHYSHIFT 24
332 NvRegMIISpeed = 0x18c,
333 #define NVREG_MIISPEED_BIT8 (1<<8)
334 #define NVREG_MIIDELAY 5
335 NvRegMIIControl = 0x190,
336 #define NVREG_MIICTL_INUSE 0x08000
337 #define NVREG_MIICTL_WRITE 0x00400
338 #define NVREG_MIICTL_ADDRSHIFT 5
339 NvRegMIIData = 0x194,
340 NvRegWakeUpFlags = 0x200,
341 #define NVREG_WAKEUPFLAGS_VAL 0x7770
342 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
343 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
344 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
345 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
346 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
347 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
348 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
349 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
350 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
351 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
352
353 NvRegPatternCRC = 0x204,
354 NvRegPatternMask = 0x208,
355 NvRegPowerCap = 0x268,
356 #define NVREG_POWERCAP_D3SUPP (1<<30)
357 #define NVREG_POWERCAP_D2SUPP (1<<26)
358 #define NVREG_POWERCAP_D1SUPP (1<<25)
359 NvRegPowerState = 0x26c,
360 #define NVREG_POWERSTATE_POWEREDUP 0x8000
361 #define NVREG_POWERSTATE_VALID 0x0100
362 #define NVREG_POWERSTATE_MASK 0x0003
363 #define NVREG_POWERSTATE_D0 0x0000
364 #define NVREG_POWERSTATE_D1 0x0001
365 #define NVREG_POWERSTATE_D2 0x0002
366 #define NVREG_POWERSTATE_D3 0x0003
367 NvRegTxCnt = 0x280,
368 NvRegTxZeroReXmt = 0x284,
369 NvRegTxOneReXmt = 0x288,
370 NvRegTxManyReXmt = 0x28c,
371 NvRegTxLateCol = 0x290,
372 NvRegTxUnderflow = 0x294,
373 NvRegTxLossCarrier = 0x298,
374 NvRegTxExcessDef = 0x29c,
375 NvRegTxRetryErr = 0x2a0,
376 NvRegRxFrameErr = 0x2a4,
377 NvRegRxExtraByte = 0x2a8,
378 NvRegRxLateCol = 0x2ac,
379 NvRegRxRunt = 0x2b0,
380 NvRegRxFrameTooLong = 0x2b4,
381 NvRegRxOverflow = 0x2b8,
382 NvRegRxFCSErr = 0x2bc,
383 NvRegRxFrameAlignErr = 0x2c0,
384 NvRegRxLenErr = 0x2c4,
385 NvRegRxUnicast = 0x2c8,
386 NvRegRxMulticast = 0x2cc,
387 NvRegRxBroadcast = 0x2d0,
388 NvRegTxDef = 0x2d4,
389 NvRegTxFrame = 0x2d8,
390 NvRegRxCnt = 0x2dc,
391 NvRegTxPause = 0x2e0,
392 NvRegRxPause = 0x2e4,
393 NvRegRxDropFrame = 0x2e8,
394 NvRegVlanControl = 0x300,
395 #define NVREG_VLANCONTROL_ENABLE 0x2000
396 NvRegMSIXMap0 = 0x3e0,
397 NvRegMSIXMap1 = 0x3e4,
398 NvRegMSIXIrqStatus = 0x3f0,
399
400 NvRegPowerState2 = 0x600,
401 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
402 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
403 };
404
405 /* Big endian: should work, but is untested */
406 struct ring_desc {
407 __le32 buf;
408 __le32 flaglen;
409 };
410
411 struct ring_desc_ex {
412 __le32 bufhigh;
413 __le32 buflow;
414 __le32 txvlan;
415 __le32 flaglen;
416 };
417
418 union ring_type {
419 struct ring_desc* orig;
420 struct ring_desc_ex* ex;
421 };
422
423 #define FLAG_MASK_V1 0xffff0000
424 #define FLAG_MASK_V2 0xffffc000
425 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
426 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
427
428 #define NV_TX_LASTPACKET (1<<16)
429 #define NV_TX_RETRYERROR (1<<19)
430 #define NV_TX_FORCED_INTERRUPT (1<<24)
431 #define NV_TX_DEFERRED (1<<26)
432 #define NV_TX_CARRIERLOST (1<<27)
433 #define NV_TX_LATECOLLISION (1<<28)
434 #define NV_TX_UNDERFLOW (1<<29)
435 #define NV_TX_ERROR (1<<30)
436 #define NV_TX_VALID (1<<31)
437
438 #define NV_TX2_LASTPACKET (1<<29)
439 #define NV_TX2_RETRYERROR (1<<18)
440 #define NV_TX2_FORCED_INTERRUPT (1<<30)
441 #define NV_TX2_DEFERRED (1<<25)
442 #define NV_TX2_CARRIERLOST (1<<26)
443 #define NV_TX2_LATECOLLISION (1<<27)
444 #define NV_TX2_UNDERFLOW (1<<28)
445 /* error and valid are the same for both */
446 #define NV_TX2_ERROR (1<<30)
447 #define NV_TX2_VALID (1<<31)
448 #define NV_TX2_TSO (1<<28)
449 #define NV_TX2_TSO_SHIFT 14
450 #define NV_TX2_TSO_MAX_SHIFT 14
451 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
452 #define NV_TX2_CHECKSUM_L3 (1<<27)
453 #define NV_TX2_CHECKSUM_L4 (1<<26)
454
455 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
456
457 #define NV_RX_DESCRIPTORVALID (1<<16)
458 #define NV_RX_MISSEDFRAME (1<<17)
459 #define NV_RX_SUBSTRACT1 (1<<18)
460 #define NV_RX_ERROR1 (1<<23)
461 #define NV_RX_ERROR2 (1<<24)
462 #define NV_RX_ERROR3 (1<<25)
463 #define NV_RX_ERROR4 (1<<26)
464 #define NV_RX_CRCERR (1<<27)
465 #define NV_RX_OVERFLOW (1<<28)
466 #define NV_RX_FRAMINGERR (1<<29)
467 #define NV_RX_ERROR (1<<30)
468 #define NV_RX_AVAIL (1<<31)
469
470 #define NV_RX2_CHECKSUMMASK (0x1C000000)
471 #define NV_RX2_CHECKSUMOK1 (0x10000000)
472 #define NV_RX2_CHECKSUMOK2 (0x14000000)
473 #define NV_RX2_CHECKSUMOK3 (0x18000000)
474 #define NV_RX2_DESCRIPTORVALID (1<<29)
475 #define NV_RX2_SUBSTRACT1 (1<<25)
476 #define NV_RX2_ERROR1 (1<<18)
477 #define NV_RX2_ERROR2 (1<<19)
478 #define NV_RX2_ERROR3 (1<<20)
479 #define NV_RX2_ERROR4 (1<<21)
480 #define NV_RX2_CRCERR (1<<22)
481 #define NV_RX2_OVERFLOW (1<<23)
482 #define NV_RX2_FRAMINGERR (1<<24)
483 /* error and avail are the same for both */
484 #define NV_RX2_ERROR (1<<30)
485 #define NV_RX2_AVAIL (1<<31)
486
487 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
488 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
489
490 /* Miscelaneous hardware related defines: */
491 #define NV_PCI_REGSZ_VER1 0x270
492 #define NV_PCI_REGSZ_VER2 0x2d4
493 #define NV_PCI_REGSZ_VER3 0x604
494
495 /* various timeout delays: all in usec */
496 #define NV_TXRX_RESET_DELAY 4
497 #define NV_TXSTOP_DELAY1 10
498 #define NV_TXSTOP_DELAY1MAX 500000
499 #define NV_TXSTOP_DELAY2 100
500 #define NV_RXSTOP_DELAY1 10
501 #define NV_RXSTOP_DELAY1MAX 500000
502 #define NV_RXSTOP_DELAY2 100
503 #define NV_SETUP5_DELAY 5
504 #define NV_SETUP5_DELAYMAX 50000
505 #define NV_POWERUP_DELAY 5
506 #define NV_POWERUP_DELAYMAX 5000
507 #define NV_MIIBUSY_DELAY 50
508 #define NV_MIIPHY_DELAY 10
509 #define NV_MIIPHY_DELAYMAX 10000
510 #define NV_MAC_RESET_DELAY 64
511
512 #define NV_WAKEUPPATTERNS 5
513 #define NV_WAKEUPMASKENTRIES 4
514
515 /* General driver defaults */
516 #define NV_WATCHDOG_TIMEO (5*HZ)
517
518 #define RX_RING_DEFAULT 128
519 #define TX_RING_DEFAULT 256
520 #define RX_RING_MIN 128
521 #define TX_RING_MIN 64
522 #define RING_MAX_DESC_VER_1 1024
523 #define RING_MAX_DESC_VER_2_3 16384
524
525 /* rx/tx mac addr + type + vlan + align + slack*/
526 #define NV_RX_HEADERS (64)
527 /* even more slack. */
528 #define NV_RX_ALLOC_PAD (64)
529
530 /* maximum mtu size */
531 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
532 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
533
534 #define OOM_REFILL (1+HZ/20)
535 #define POLL_WAIT (1+HZ/100)
536 #define LINK_TIMEOUT (3*HZ)
537 #define STATS_INTERVAL (10*HZ)
538
539 /*
540 * desc_ver values:
541 * The nic supports three different descriptor types:
542 * - DESC_VER_1: Original
543 * - DESC_VER_2: support for jumbo frames.
544 * - DESC_VER_3: 64-bit format.
545 */
546 #define DESC_VER_1 1
547 #define DESC_VER_2 2
548 #define DESC_VER_3 3
549
550 /* PHY defines */
551 #define PHY_OUI_MARVELL 0x5043
552 #define PHY_OUI_CICADA 0x03f1
553 #define PHYID1_OUI_MASK 0x03ff
554 #define PHYID1_OUI_SHFT 6
555 #define PHYID2_OUI_MASK 0xfc00
556 #define PHYID2_OUI_SHFT 10
557 #define PHYID2_MODEL_MASK 0x03f0
558 #define PHY_MODEL_MARVELL_E3016 0x220
559 #define PHY_MARVELL_E3016_INITMASK 0x0300
560 #define PHY_INIT1 0x0f000
561 #define PHY_INIT2 0x0e00
562 #define PHY_INIT3 0x01000
563 #define PHY_INIT4 0x0200
564 #define PHY_INIT5 0x0004
565 #define PHY_INIT6 0x02000
566 #define PHY_GIGABIT 0x0100
567
568 #define PHY_TIMEOUT 0x1
569 #define PHY_ERROR 0x2
570
571 #define PHY_100 0x1
572 #define PHY_1000 0x2
573 #define PHY_HALF 0x100
574
575 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
576 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
577 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
578 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
579 #define NV_PAUSEFRAME_RX_REQ 0x0010
580 #define NV_PAUSEFRAME_TX_REQ 0x0020
581 #define NV_PAUSEFRAME_AUTONEG 0x0040
582
583 /* MSI/MSI-X defines */
584 #define NV_MSI_X_MAX_VECTORS 8
585 #define NV_MSI_X_VECTORS_MASK 0x000f
586 #define NV_MSI_CAPABLE 0x0010
587 #define NV_MSI_X_CAPABLE 0x0020
588 #define NV_MSI_ENABLED 0x0040
589 #define NV_MSI_X_ENABLED 0x0080
590
591 #define NV_MSI_X_VECTOR_ALL 0x0
592 #define NV_MSI_X_VECTOR_RX 0x0
593 #define NV_MSI_X_VECTOR_TX 0x1
594 #define NV_MSI_X_VECTOR_OTHER 0x2
595
596 /* statistics */
597 struct nv_ethtool_str {
598 char name[ETH_GSTRING_LEN];
599 };
600
601 static const struct nv_ethtool_str nv_estats_str[] = {
602 { "tx_bytes" },
603 { "tx_zero_rexmt" },
604 { "tx_one_rexmt" },
605 { "tx_many_rexmt" },
606 { "tx_late_collision" },
607 { "tx_fifo_errors" },
608 { "tx_carrier_errors" },
609 { "tx_excess_deferral" },
610 { "tx_retry_error" },
611 { "rx_frame_error" },
612 { "rx_extra_byte" },
613 { "rx_late_collision" },
614 { "rx_runt" },
615 { "rx_frame_too_long" },
616 { "rx_over_errors" },
617 { "rx_crc_errors" },
618 { "rx_frame_align_error" },
619 { "rx_length_error" },
620 { "rx_unicast" },
621 { "rx_multicast" },
622 { "rx_broadcast" },
623 { "rx_packets" },
624 { "rx_errors_total" },
625 { "tx_errors_total" },
626
627 /* version 2 stats */
628 { "tx_deferral" },
629 { "tx_packets" },
630 { "rx_bytes" },
631 { "tx_pause" },
632 { "rx_pause" },
633 { "rx_drop_frame" }
634 };
635
636 struct nv_ethtool_stats {
637 u64 tx_bytes;
638 u64 tx_zero_rexmt;
639 u64 tx_one_rexmt;
640 u64 tx_many_rexmt;
641 u64 tx_late_collision;
642 u64 tx_fifo_errors;
643 u64 tx_carrier_errors;
644 u64 tx_excess_deferral;
645 u64 tx_retry_error;
646 u64 rx_frame_error;
647 u64 rx_extra_byte;
648 u64 rx_late_collision;
649 u64 rx_runt;
650 u64 rx_frame_too_long;
651 u64 rx_over_errors;
652 u64 rx_crc_errors;
653 u64 rx_frame_align_error;
654 u64 rx_length_error;
655 u64 rx_unicast;
656 u64 rx_multicast;
657 u64 rx_broadcast;
658 u64 rx_packets;
659 u64 rx_errors_total;
660 u64 tx_errors_total;
661
662 /* version 2 stats */
663 u64 tx_deferral;
664 u64 tx_packets;
665 u64 rx_bytes;
666 u64 tx_pause;
667 u64 rx_pause;
668 u64 rx_drop_frame;
669 };
670
671 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
672 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
673
674 /* diagnostics */
675 #define NV_TEST_COUNT_BASE 3
676 #define NV_TEST_COUNT_EXTENDED 4
677
678 static const struct nv_ethtool_str nv_etests_str[] = {
679 { "link (online/offline)" },
680 { "register (offline) " },
681 { "interrupt (offline) " },
682 { "loopback (offline) " }
683 };
684
685 struct register_test {
686 __le32 reg;
687 __le32 mask;
688 };
689
690 static const struct register_test nv_registers_test[] = {
691 { NvRegUnknownSetupReg6, 0x01 },
692 { NvRegMisc1, 0x03c },
693 { NvRegOffloadConfig, 0x03ff },
694 { NvRegMulticastAddrA, 0xffffffff },
695 { NvRegTxWatermark, 0x0ff },
696 { NvRegWakeUpFlags, 0x07777 },
697 { 0,0 }
698 };
699
700 struct nv_skb_map {
701 struct sk_buff *skb;
702 dma_addr_t dma;
703 unsigned int dma_len;
704 };
705
706 /*
707 * SMP locking:
708 * All hardware access under dev->priv->lock, except the performance
709 * critical parts:
710 * - rx is (pseudo-) lockless: it relies on the single-threading provided
711 * by the arch code for interrupts.
712 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
713 * needs dev->priv->lock :-(
714 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
715 */
716
717 /* in dev: base, irq */
718 struct fe_priv {
719 spinlock_t lock;
720
721 /* General data:
722 * Locking: spin_lock(&np->lock); */
723 struct net_device_stats stats;
724 struct nv_ethtool_stats estats;
725 int in_shutdown;
726 u32 linkspeed;
727 int duplex;
728 int autoneg;
729 int fixed_mode;
730 int phyaddr;
731 int wolenabled;
732 unsigned int phy_oui;
733 unsigned int phy_model;
734 u16 gigabit;
735 int intr_test;
736 int recover_error;
737
738 /* General data: RO fields */
739 dma_addr_t ring_addr;
740 struct pci_dev *pci_dev;
741 u32 orig_mac[2];
742 u32 irqmask;
743 u32 desc_ver;
744 u32 txrxctl_bits;
745 u32 vlanctl_bits;
746 u32 driver_data;
747 u32 register_size;
748 int rx_csum;
749 u32 mac_in_use;
750
751 void __iomem *base;
752
753 /* rx specific fields.
754 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
755 */
756 union ring_type get_rx, put_rx, first_rx, last_rx;
757 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
758 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
759 struct nv_skb_map *rx_skb;
760
761 union ring_type rx_ring;
762 unsigned int rx_buf_sz;
763 unsigned int pkt_limit;
764 struct timer_list oom_kick;
765 struct timer_list nic_poll;
766 struct timer_list stats_poll;
767 u32 nic_poll_irq;
768 int rx_ring_size;
769
770 /* media detection workaround.
771 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
772 */
773 int need_linktimer;
774 unsigned long link_timeout;
775 /*
776 * tx specific fields.
777 */
778 union ring_type get_tx, put_tx, first_tx, last_tx;
779 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
780 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
781 struct nv_skb_map *tx_skb;
782
783 union ring_type tx_ring;
784 u32 tx_flags;
785 int tx_ring_size;
786 int tx_stop;
787
788 /* vlan fields */
789 struct vlan_group *vlangrp;
790
791 /* msi/msi-x fields */
792 u32 msi_flags;
793 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
794
795 /* flow control */
796 u32 pause_flags;
797 };
798
799 /*
800 * Maximum number of loops until we assume that a bit in the irq mask
801 * is stuck. Overridable with module param.
802 */
803 static int max_interrupt_work = 5;
804
805 /*
806 * Optimization can be either throuput mode or cpu mode
807 *
808 * Throughput Mode: Every tx and rx packet will generate an interrupt.
809 * CPU Mode: Interrupts are controlled by a timer.
810 */
811 enum {
812 NV_OPTIMIZATION_MODE_THROUGHPUT,
813 NV_OPTIMIZATION_MODE_CPU
814 };
815 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
816
817 /*
818 * Poll interval for timer irq
819 *
820 * This interval determines how frequent an interrupt is generated.
821 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
822 * Min = 0, and Max = 65535
823 */
824 static int poll_interval = -1;
825
826 /*
827 * MSI interrupts
828 */
829 enum {
830 NV_MSI_INT_DISABLED,
831 NV_MSI_INT_ENABLED
832 };
833 static int msi = NV_MSI_INT_ENABLED;
834
835 /*
836 * MSIX interrupts
837 */
838 enum {
839 NV_MSIX_INT_DISABLED,
840 NV_MSIX_INT_ENABLED
841 };
842 static int msix = NV_MSIX_INT_DISABLED;
843
844 /*
845 * DMA 64bit
846 */
847 enum {
848 NV_DMA_64BIT_DISABLED,
849 NV_DMA_64BIT_ENABLED
850 };
851 static int dma_64bit = NV_DMA_64BIT_ENABLED;
852
853 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
854 {
855 return netdev_priv(dev);
856 }
857
858 static inline u8 __iomem *get_hwbase(struct net_device *dev)
859 {
860 return ((struct fe_priv *)netdev_priv(dev))->base;
861 }
862
863 static inline void pci_push(u8 __iomem *base)
864 {
865 /* force out pending posted writes */
866 readl(base);
867 }
868
869 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
870 {
871 return le32_to_cpu(prd->flaglen)
872 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
873 }
874
875 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
876 {
877 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
878 }
879
880 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
881 int delay, int delaymax, const char *msg)
882 {
883 u8 __iomem *base = get_hwbase(dev);
884
885 pci_push(base);
886 do {
887 udelay(delay);
888 delaymax -= delay;
889 if (delaymax < 0) {
890 if (msg)
891 printk(msg);
892 return 1;
893 }
894 } while ((readl(base + offset) & mask) != target);
895 return 0;
896 }
897
898 #define NV_SETUP_RX_RING 0x01
899 #define NV_SETUP_TX_RING 0x02
900
901 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
902 {
903 struct fe_priv *np = get_nvpriv(dev);
904 u8 __iomem *base = get_hwbase(dev);
905
906 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
907 if (rxtx_flags & NV_SETUP_RX_RING) {
908 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
909 }
910 if (rxtx_flags & NV_SETUP_TX_RING) {
911 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
912 }
913 } else {
914 if (rxtx_flags & NV_SETUP_RX_RING) {
915 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
916 writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
917 }
918 if (rxtx_flags & NV_SETUP_TX_RING) {
919 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
920 writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
921 }
922 }
923 }
924
925 static void free_rings(struct net_device *dev)
926 {
927 struct fe_priv *np = get_nvpriv(dev);
928
929 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
930 if (np->rx_ring.orig)
931 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
932 np->rx_ring.orig, np->ring_addr);
933 } else {
934 if (np->rx_ring.ex)
935 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
936 np->rx_ring.ex, np->ring_addr);
937 }
938 if (np->rx_skb)
939 kfree(np->rx_skb);
940 if (np->tx_skb)
941 kfree(np->tx_skb);
942 }
943
944 static int using_multi_irqs(struct net_device *dev)
945 {
946 struct fe_priv *np = get_nvpriv(dev);
947
948 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
949 ((np->msi_flags & NV_MSI_X_ENABLED) &&
950 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
951 return 0;
952 else
953 return 1;
954 }
955
956 static void nv_enable_irq(struct net_device *dev)
957 {
958 struct fe_priv *np = get_nvpriv(dev);
959
960 if (!using_multi_irqs(dev)) {
961 if (np->msi_flags & NV_MSI_X_ENABLED)
962 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
963 else
964 enable_irq(dev->irq);
965 } else {
966 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
967 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
968 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
969 }
970 }
971
972 static void nv_disable_irq(struct net_device *dev)
973 {
974 struct fe_priv *np = get_nvpriv(dev);
975
976 if (!using_multi_irqs(dev)) {
977 if (np->msi_flags & NV_MSI_X_ENABLED)
978 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
979 else
980 disable_irq(dev->irq);
981 } else {
982 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
983 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
984 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
985 }
986 }
987
988 /* In MSIX mode, a write to irqmask behaves as XOR */
989 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
990 {
991 u8 __iomem *base = get_hwbase(dev);
992
993 writel(mask, base + NvRegIrqMask);
994 }
995
996 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
997 {
998 struct fe_priv *np = get_nvpriv(dev);
999 u8 __iomem *base = get_hwbase(dev);
1000
1001 if (np->msi_flags & NV_MSI_X_ENABLED) {
1002 writel(mask, base + NvRegIrqMask);
1003 } else {
1004 if (np->msi_flags & NV_MSI_ENABLED)
1005 writel(0, base + NvRegMSIIrqMask);
1006 writel(0, base + NvRegIrqMask);
1007 }
1008 }
1009
1010 #define MII_READ (-1)
1011 /* mii_rw: read/write a register on the PHY.
1012 *
1013 * Caller must guarantee serialization
1014 */
1015 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1016 {
1017 u8 __iomem *base = get_hwbase(dev);
1018 u32 reg;
1019 int retval;
1020
1021 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1022
1023 reg = readl(base + NvRegMIIControl);
1024 if (reg & NVREG_MIICTL_INUSE) {
1025 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1026 udelay(NV_MIIBUSY_DELAY);
1027 }
1028
1029 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1030 if (value != MII_READ) {
1031 writel(value, base + NvRegMIIData);
1032 reg |= NVREG_MIICTL_WRITE;
1033 }
1034 writel(reg, base + NvRegMIIControl);
1035
1036 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1037 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1038 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1039 dev->name, miireg, addr);
1040 retval = -1;
1041 } else if (value != MII_READ) {
1042 /* it was a write operation - fewer failures are detectable */
1043 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1044 dev->name, value, miireg, addr);
1045 retval = 0;
1046 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1047 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1048 dev->name, miireg, addr);
1049 retval = -1;
1050 } else {
1051 retval = readl(base + NvRegMIIData);
1052 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1053 dev->name, miireg, addr, retval);
1054 }
1055
1056 return retval;
1057 }
1058
1059 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1060 {
1061 struct fe_priv *np = netdev_priv(dev);
1062 u32 miicontrol;
1063 unsigned int tries = 0;
1064
1065 miicontrol = BMCR_RESET | bmcr_setup;
1066 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1067 return -1;
1068 }
1069
1070 /* wait for 500ms */
1071 msleep(500);
1072
1073 /* must wait till reset is deasserted */
1074 while (miicontrol & BMCR_RESET) {
1075 msleep(10);
1076 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1077 /* FIXME: 100 tries seem excessive */
1078 if (tries++ > 100)
1079 return -1;
1080 }
1081 return 0;
1082 }
1083
1084 static int phy_init(struct net_device *dev)
1085 {
1086 struct fe_priv *np = get_nvpriv(dev);
1087 u8 __iomem *base = get_hwbase(dev);
1088 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1089
1090 /* phy errata for E3016 phy */
1091 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1092 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1093 reg &= ~PHY_MARVELL_E3016_INITMASK;
1094 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1095 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1096 return PHY_ERROR;
1097 }
1098 }
1099
1100 /* set advertise register */
1101 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1102 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1103 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1104 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1105 return PHY_ERROR;
1106 }
1107
1108 /* get phy interface type */
1109 phyinterface = readl(base + NvRegPhyInterface);
1110
1111 /* see if gigabit phy */
1112 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1113 if (mii_status & PHY_GIGABIT) {
1114 np->gigabit = PHY_GIGABIT;
1115 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1116 mii_control_1000 &= ~ADVERTISE_1000HALF;
1117 if (phyinterface & PHY_RGMII)
1118 mii_control_1000 |= ADVERTISE_1000FULL;
1119 else
1120 mii_control_1000 &= ~ADVERTISE_1000FULL;
1121
1122 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1123 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1124 return PHY_ERROR;
1125 }
1126 }
1127 else
1128 np->gigabit = 0;
1129
1130 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1131 mii_control |= BMCR_ANENABLE;
1132
1133 /* reset the phy
1134 * (certain phys need bmcr to be setup with reset)
1135 */
1136 if (phy_reset(dev, mii_control)) {
1137 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1138 return PHY_ERROR;
1139 }
1140
1141 /* phy vendor specific configuration */
1142 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1143 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1144 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1145 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1146 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1147 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1148 return PHY_ERROR;
1149 }
1150 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1151 phy_reserved |= PHY_INIT5;
1152 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1153 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1154 return PHY_ERROR;
1155 }
1156 }
1157 if (np->phy_oui == PHY_OUI_CICADA) {
1158 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1159 phy_reserved |= PHY_INIT6;
1160 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1161 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1162 return PHY_ERROR;
1163 }
1164 }
1165 /* some phys clear out pause advertisment on reset, set it back */
1166 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1167
1168 /* restart auto negotiation */
1169 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1170 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1171 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1172 return PHY_ERROR;
1173 }
1174
1175 return 0;
1176 }
1177
1178 static void nv_start_rx(struct net_device *dev)
1179 {
1180 struct fe_priv *np = netdev_priv(dev);
1181 u8 __iomem *base = get_hwbase(dev);
1182 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1183
1184 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1185 /* Already running? Stop it. */
1186 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1187 rx_ctrl &= ~NVREG_RCVCTL_START;
1188 writel(rx_ctrl, base + NvRegReceiverControl);
1189 pci_push(base);
1190 }
1191 writel(np->linkspeed, base + NvRegLinkSpeed);
1192 pci_push(base);
1193 rx_ctrl |= NVREG_RCVCTL_START;
1194 if (np->mac_in_use)
1195 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1196 writel(rx_ctrl, base + NvRegReceiverControl);
1197 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1198 dev->name, np->duplex, np->linkspeed);
1199 pci_push(base);
1200 }
1201
1202 static void nv_stop_rx(struct net_device *dev)
1203 {
1204 struct fe_priv *np = netdev_priv(dev);
1205 u8 __iomem *base = get_hwbase(dev);
1206 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1207
1208 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1209 if (!np->mac_in_use)
1210 rx_ctrl &= ~NVREG_RCVCTL_START;
1211 else
1212 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1213 writel(rx_ctrl, base + NvRegReceiverControl);
1214 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1215 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1216 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1217
1218 udelay(NV_RXSTOP_DELAY2);
1219 if (!np->mac_in_use)
1220 writel(0, base + NvRegLinkSpeed);
1221 }
1222
1223 static void nv_start_tx(struct net_device *dev)
1224 {
1225 struct fe_priv *np = netdev_priv(dev);
1226 u8 __iomem *base = get_hwbase(dev);
1227 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1228
1229 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1230 tx_ctrl |= NVREG_XMITCTL_START;
1231 if (np->mac_in_use)
1232 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1233 writel(tx_ctrl, base + NvRegTransmitterControl);
1234 pci_push(base);
1235 }
1236
1237 static void nv_stop_tx(struct net_device *dev)
1238 {
1239 struct fe_priv *np = netdev_priv(dev);
1240 u8 __iomem *base = get_hwbase(dev);
1241 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1242
1243 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1244 if (!np->mac_in_use)
1245 tx_ctrl &= ~NVREG_XMITCTL_START;
1246 else
1247 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1248 writel(tx_ctrl, base + NvRegTransmitterControl);
1249 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1250 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1251 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1252
1253 udelay(NV_TXSTOP_DELAY2);
1254 if (!np->mac_in_use)
1255 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1256 base + NvRegTransmitPoll);
1257 }
1258
1259 static void nv_txrx_reset(struct net_device *dev)
1260 {
1261 struct fe_priv *np = netdev_priv(dev);
1262 u8 __iomem *base = get_hwbase(dev);
1263
1264 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1265 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1266 pci_push(base);
1267 udelay(NV_TXRX_RESET_DELAY);
1268 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1269 pci_push(base);
1270 }
1271
1272 static void nv_mac_reset(struct net_device *dev)
1273 {
1274 struct fe_priv *np = netdev_priv(dev);
1275 u8 __iomem *base = get_hwbase(dev);
1276
1277 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1278 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1279 pci_push(base);
1280 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1281 pci_push(base);
1282 udelay(NV_MAC_RESET_DELAY);
1283 writel(0, base + NvRegMacReset);
1284 pci_push(base);
1285 udelay(NV_MAC_RESET_DELAY);
1286 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1287 pci_push(base);
1288 }
1289
1290 static void nv_get_hw_stats(struct net_device *dev)
1291 {
1292 struct fe_priv *np = netdev_priv(dev);
1293 u8 __iomem *base = get_hwbase(dev);
1294
1295 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1296 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1297 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1298 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1299 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1300 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1301 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1302 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1303 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1304 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1305 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1306 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1307 np->estats.rx_runt += readl(base + NvRegRxRunt);
1308 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1309 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1310 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1311 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1312 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1313 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1314 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1315 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1316 np->estats.rx_packets =
1317 np->estats.rx_unicast +
1318 np->estats.rx_multicast +
1319 np->estats.rx_broadcast;
1320 np->estats.rx_errors_total =
1321 np->estats.rx_crc_errors +
1322 np->estats.rx_over_errors +
1323 np->estats.rx_frame_error +
1324 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1325 np->estats.rx_late_collision +
1326 np->estats.rx_runt +
1327 np->estats.rx_frame_too_long;
1328 np->estats.tx_errors_total =
1329 np->estats.tx_late_collision +
1330 np->estats.tx_fifo_errors +
1331 np->estats.tx_carrier_errors +
1332 np->estats.tx_excess_deferral +
1333 np->estats.tx_retry_error;
1334
1335 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1336 np->estats.tx_deferral += readl(base + NvRegTxDef);
1337 np->estats.tx_packets += readl(base + NvRegTxFrame);
1338 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1339 np->estats.tx_pause += readl(base + NvRegTxPause);
1340 np->estats.rx_pause += readl(base + NvRegRxPause);
1341 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1342 }
1343 }
1344
1345 /*
1346 * nv_get_stats: dev->get_stats function
1347 * Get latest stats value from the nic.
1348 * Called with read_lock(&dev_base_lock) held for read -
1349 * only synchronized against unregister_netdevice.
1350 */
1351 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1352 {
1353 struct fe_priv *np = netdev_priv(dev);
1354
1355 /* If the nic supports hw counters then retrieve latest values */
1356 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1357 nv_get_hw_stats(dev);
1358
1359 /* copy to net_device stats */
1360 np->stats.tx_bytes = np->estats.tx_bytes;
1361 np->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1362 np->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1363 np->stats.rx_crc_errors = np->estats.rx_crc_errors;
1364 np->stats.rx_over_errors = np->estats.rx_over_errors;
1365 np->stats.rx_errors = np->estats.rx_errors_total;
1366 np->stats.tx_errors = np->estats.tx_errors_total;
1367 }
1368 return &np->stats;
1369 }
1370
1371 /*
1372 * nv_alloc_rx: fill rx ring entries.
1373 * Return 1 if the allocations for the skbs failed and the
1374 * rx engine is without Available descriptors
1375 */
1376 static int nv_alloc_rx(struct net_device *dev)
1377 {
1378 struct fe_priv *np = netdev_priv(dev);
1379 struct ring_desc* less_rx;
1380
1381 less_rx = np->get_rx.orig;
1382 if (less_rx-- == np->first_rx.orig)
1383 less_rx = np->last_rx.orig;
1384
1385 while (np->put_rx.orig != less_rx) {
1386 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1387 if (skb) {
1388 np->put_rx_ctx->skb = skb;
1389 np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1390 skb->end-skb->data, PCI_DMA_FROMDEVICE);
1391 np->put_rx_ctx->dma_len = skb->end-skb->data;
1392 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1393 wmb();
1394 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1395 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1396 np->put_rx.orig = np->first_rx.orig;
1397 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1398 np->put_rx_ctx = np->first_rx_ctx;
1399 } else {
1400 return 1;
1401 }
1402 }
1403 return 0;
1404 }
1405
1406 static int nv_alloc_rx_optimized(struct net_device *dev)
1407 {
1408 struct fe_priv *np = netdev_priv(dev);
1409 struct ring_desc_ex* less_rx;
1410
1411 less_rx = np->get_rx.ex;
1412 if (less_rx-- == np->first_rx.ex)
1413 less_rx = np->last_rx.ex;
1414
1415 while (np->put_rx.ex != less_rx) {
1416 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1417 if (skb) {
1418 np->put_rx_ctx->skb = skb;
1419 np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1420 skb->end-skb->data, PCI_DMA_FROMDEVICE);
1421 np->put_rx_ctx->dma_len = skb->end-skb->data;
1422 np->put_rx.ex->bufhigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32;
1423 np->put_rx.ex->buflow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF;
1424 wmb();
1425 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1426 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1427 np->put_rx.ex = np->first_rx.ex;
1428 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1429 np->put_rx_ctx = np->first_rx_ctx;
1430 } else {
1431 return 1;
1432 }
1433 }
1434 return 0;
1435 }
1436
1437 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1438 #ifdef CONFIG_FORCEDETH_NAPI
1439 static void nv_do_rx_refill(unsigned long data)
1440 {
1441 struct net_device *dev = (struct net_device *) data;
1442
1443 /* Just reschedule NAPI rx processing */
1444 netif_rx_schedule(dev);
1445 }
1446 #else
1447 static void nv_do_rx_refill(unsigned long data)
1448 {
1449 struct net_device *dev = (struct net_device *) data;
1450 struct fe_priv *np = netdev_priv(dev);
1451 int retcode;
1452
1453 if (!using_multi_irqs(dev)) {
1454 if (np->msi_flags & NV_MSI_X_ENABLED)
1455 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1456 else
1457 disable_irq(dev->irq);
1458 } else {
1459 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1460 }
1461 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1462 retcode = nv_alloc_rx(dev);
1463 else
1464 retcode = nv_alloc_rx_optimized(dev);
1465 if (retcode) {
1466 spin_lock_irq(&np->lock);
1467 if (!np->in_shutdown)
1468 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1469 spin_unlock_irq(&np->lock);
1470 }
1471 if (!using_multi_irqs(dev)) {
1472 if (np->msi_flags & NV_MSI_X_ENABLED)
1473 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1474 else
1475 enable_irq(dev->irq);
1476 } else {
1477 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1478 }
1479 }
1480 #endif
1481
1482 static void nv_init_rx(struct net_device *dev)
1483 {
1484 struct fe_priv *np = netdev_priv(dev);
1485 int i;
1486 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1487 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1488 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1489 else
1490 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1491 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1492 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1493
1494 for (i = 0; i < np->rx_ring_size; i++) {
1495 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1496 np->rx_ring.orig[i].flaglen = 0;
1497 np->rx_ring.orig[i].buf = 0;
1498 } else {
1499 np->rx_ring.ex[i].flaglen = 0;
1500 np->rx_ring.ex[i].txvlan = 0;
1501 np->rx_ring.ex[i].bufhigh = 0;
1502 np->rx_ring.ex[i].buflow = 0;
1503 }
1504 np->rx_skb[i].skb = NULL;
1505 np->rx_skb[i].dma = 0;
1506 }
1507 }
1508
1509 static void nv_init_tx(struct net_device *dev)
1510 {
1511 struct fe_priv *np = netdev_priv(dev);
1512 int i;
1513 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1514 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1515 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1516 else
1517 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1518 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1519 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1520
1521 for (i = 0; i < np->tx_ring_size; i++) {
1522 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1523 np->tx_ring.orig[i].flaglen = 0;
1524 np->tx_ring.orig[i].buf = 0;
1525 } else {
1526 np->tx_ring.ex[i].flaglen = 0;
1527 np->tx_ring.ex[i].txvlan = 0;
1528 np->tx_ring.ex[i].bufhigh = 0;
1529 np->tx_ring.ex[i].buflow = 0;
1530 }
1531 np->tx_skb[i].skb = NULL;
1532 np->tx_skb[i].dma = 0;
1533 }
1534 }
1535
1536 static int nv_init_ring(struct net_device *dev)
1537 {
1538 struct fe_priv *np = netdev_priv(dev);
1539
1540 nv_init_tx(dev);
1541 nv_init_rx(dev);
1542 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1543 return nv_alloc_rx(dev);
1544 else
1545 return nv_alloc_rx_optimized(dev);
1546 }
1547
1548 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1549 {
1550 struct fe_priv *np = netdev_priv(dev);
1551
1552 if (tx_skb->dma) {
1553 pci_unmap_page(np->pci_dev, tx_skb->dma,
1554 tx_skb->dma_len,
1555 PCI_DMA_TODEVICE);
1556 tx_skb->dma = 0;
1557 }
1558 if (tx_skb->skb) {
1559 dev_kfree_skb_any(tx_skb->skb);
1560 tx_skb->skb = NULL;
1561 return 1;
1562 } else {
1563 return 0;
1564 }
1565 }
1566
1567 static void nv_drain_tx(struct net_device *dev)
1568 {
1569 struct fe_priv *np = netdev_priv(dev);
1570 unsigned int i;
1571
1572 for (i = 0; i < np->tx_ring_size; i++) {
1573 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1574 np->tx_ring.orig[i].flaglen = 0;
1575 np->tx_ring.orig[i].buf = 0;
1576 } else {
1577 np->tx_ring.ex[i].flaglen = 0;
1578 np->tx_ring.ex[i].txvlan = 0;
1579 np->tx_ring.ex[i].bufhigh = 0;
1580 np->tx_ring.ex[i].buflow = 0;
1581 }
1582 if (nv_release_txskb(dev, &np->tx_skb[i]))
1583 np->stats.tx_dropped++;
1584 }
1585 }
1586
1587 static void nv_drain_rx(struct net_device *dev)
1588 {
1589 struct fe_priv *np = netdev_priv(dev);
1590 int i;
1591
1592 for (i = 0; i < np->rx_ring_size; i++) {
1593 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1594 np->rx_ring.orig[i].flaglen = 0;
1595 np->rx_ring.orig[i].buf = 0;
1596 } else {
1597 np->rx_ring.ex[i].flaglen = 0;
1598 np->rx_ring.ex[i].txvlan = 0;
1599 np->rx_ring.ex[i].bufhigh = 0;
1600 np->rx_ring.ex[i].buflow = 0;
1601 }
1602 wmb();
1603 if (np->rx_skb[i].skb) {
1604 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1605 np->rx_skb[i].skb->end-np->rx_skb[i].skb->data,
1606 PCI_DMA_FROMDEVICE);
1607 dev_kfree_skb(np->rx_skb[i].skb);
1608 np->rx_skb[i].skb = NULL;
1609 }
1610 }
1611 }
1612
1613 static void drain_ring(struct net_device *dev)
1614 {
1615 nv_drain_tx(dev);
1616 nv_drain_rx(dev);
1617 }
1618
1619 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1620 {
1621 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1622 }
1623
1624 /*
1625 * nv_start_xmit: dev->hard_start_xmit function
1626 * Called with netif_tx_lock held.
1627 */
1628 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1629 {
1630 struct fe_priv *np = netdev_priv(dev);
1631 u32 tx_flags = 0;
1632 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1633 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1634 unsigned int i;
1635 u32 offset = 0;
1636 u32 bcnt;
1637 u32 size = skb->len-skb->data_len;
1638 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1639 u32 empty_slots;
1640 struct ring_desc* put_tx;
1641 struct ring_desc* start_tx;
1642 struct ring_desc* prev_tx;
1643 struct nv_skb_map* prev_tx_ctx;
1644
1645 /* add fragments to entries count */
1646 for (i = 0; i < fragments; i++) {
1647 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1648 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1649 }
1650
1651 empty_slots = nv_get_empty_tx_slots(np);
1652 if (unlikely(empty_slots <= entries)) {
1653 spin_lock_irq(&np->lock);
1654 netif_stop_queue(dev);
1655 np->tx_stop = 1;
1656 spin_unlock_irq(&np->lock);
1657 return NETDEV_TX_BUSY;
1658 }
1659
1660 start_tx = put_tx = np->put_tx.orig;
1661
1662 /* setup the header buffer */
1663 do {
1664 prev_tx = put_tx;
1665 prev_tx_ctx = np->put_tx_ctx;
1666 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1667 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1668 PCI_DMA_TODEVICE);
1669 np->put_tx_ctx->dma_len = bcnt;
1670 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1671 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1672
1673 tx_flags = np->tx_flags;
1674 offset += bcnt;
1675 size -= bcnt;
1676 if (unlikely(put_tx++ == np->last_tx.orig))
1677 put_tx = np->first_tx.orig;
1678 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1679 np->put_tx_ctx = np->first_tx_ctx;
1680 } while (size);
1681
1682 /* setup the fragments */
1683 for (i = 0; i < fragments; i++) {
1684 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1685 u32 size = frag->size;
1686 offset = 0;
1687
1688 do {
1689 prev_tx = put_tx;
1690 prev_tx_ctx = np->put_tx_ctx;
1691 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1692 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1693 PCI_DMA_TODEVICE);
1694 np->put_tx_ctx->dma_len = bcnt;
1695 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1696 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1697
1698 offset += bcnt;
1699 size -= bcnt;
1700 if (unlikely(put_tx++ == np->last_tx.orig))
1701 put_tx = np->first_tx.orig;
1702 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1703 np->put_tx_ctx = np->first_tx_ctx;
1704 } while (size);
1705 }
1706
1707 /* set last fragment flag */
1708 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
1709
1710 /* save skb in this slot's context area */
1711 prev_tx_ctx->skb = skb;
1712
1713 if (skb_is_gso(skb))
1714 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1715 else
1716 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1717 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1718
1719 spin_lock_irq(&np->lock);
1720
1721 /* set tx flags */
1722 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1723 np->put_tx.orig = put_tx;
1724
1725 spin_unlock_irq(&np->lock);
1726
1727 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1728 dev->name, entries, tx_flags_extra);
1729 {
1730 int j;
1731 for (j=0; j<64; j++) {
1732 if ((j%16) == 0)
1733 dprintk("\n%03x:", j);
1734 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1735 }
1736 dprintk("\n");
1737 }
1738
1739 dev->trans_start = jiffies;
1740 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1741 return NETDEV_TX_OK;
1742 }
1743
1744 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1745 {
1746 struct fe_priv *np = netdev_priv(dev);
1747 u32 tx_flags = 0;
1748 u32 tx_flags_extra;
1749 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1750 unsigned int i;
1751 u32 offset = 0;
1752 u32 bcnt;
1753 u32 size = skb->len-skb->data_len;
1754 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1755 u32 empty_slots;
1756 struct ring_desc_ex* put_tx;
1757 struct ring_desc_ex* start_tx;
1758 struct ring_desc_ex* prev_tx;
1759 struct nv_skb_map* prev_tx_ctx;
1760
1761 /* add fragments to entries count */
1762 for (i = 0; i < fragments; i++) {
1763 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1764 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1765 }
1766
1767 empty_slots = nv_get_empty_tx_slots(np);
1768 if (unlikely(empty_slots <= entries)) {
1769 spin_lock_irq(&np->lock);
1770 netif_stop_queue(dev);
1771 np->tx_stop = 1;
1772 spin_unlock_irq(&np->lock);
1773 return NETDEV_TX_BUSY;
1774 }
1775
1776 start_tx = put_tx = np->put_tx.ex;
1777
1778 /* setup the header buffer */
1779 do {
1780 prev_tx = put_tx;
1781 prev_tx_ctx = np->put_tx_ctx;
1782 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1783 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1784 PCI_DMA_TODEVICE);
1785 np->put_tx_ctx->dma_len = bcnt;
1786 put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1787 put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1788 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1789
1790 tx_flags = NV_TX2_VALID;
1791 offset += bcnt;
1792 size -= bcnt;
1793 if (unlikely(put_tx++ == np->last_tx.ex))
1794 put_tx = np->first_tx.ex;
1795 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1796 np->put_tx_ctx = np->first_tx_ctx;
1797 } while (size);
1798
1799 /* setup the fragments */
1800 for (i = 0; i < fragments; i++) {
1801 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1802 u32 size = frag->size;
1803 offset = 0;
1804
1805 do {
1806 prev_tx = put_tx;
1807 prev_tx_ctx = np->put_tx_ctx;
1808 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1809 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1810 PCI_DMA_TODEVICE);
1811 np->put_tx_ctx->dma_len = bcnt;
1812 put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1813 put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1814 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1815
1816 offset += bcnt;
1817 size -= bcnt;
1818 if (unlikely(put_tx++ == np->last_tx.ex))
1819 put_tx = np->first_tx.ex;
1820 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1821 np->put_tx_ctx = np->first_tx_ctx;
1822 } while (size);
1823 }
1824
1825 /* set last fragment flag */
1826 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
1827
1828 /* save skb in this slot's context area */
1829 prev_tx_ctx->skb = skb;
1830
1831 if (skb_is_gso(skb))
1832 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1833 else
1834 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1835 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1836
1837 /* vlan tag */
1838 if (likely(!np->vlangrp)) {
1839 start_tx->txvlan = 0;
1840 } else {
1841 if (vlan_tx_tag_present(skb))
1842 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
1843 else
1844 start_tx->txvlan = 0;
1845 }
1846
1847 spin_lock_irq(&np->lock);
1848
1849 /* set tx flags */
1850 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1851 np->put_tx.ex = put_tx;
1852
1853 spin_unlock_irq(&np->lock);
1854
1855 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
1856 dev->name, entries, tx_flags_extra);
1857 {
1858 int j;
1859 for (j=0; j<64; j++) {
1860 if ((j%16) == 0)
1861 dprintk("\n%03x:", j);
1862 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1863 }
1864 dprintk("\n");
1865 }
1866
1867 dev->trans_start = jiffies;
1868 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1869 return NETDEV_TX_OK;
1870 }
1871
1872 /*
1873 * nv_tx_done: check for completed packets, release the skbs.
1874 *
1875 * Caller must own np->lock.
1876 */
1877 static void nv_tx_done(struct net_device *dev)
1878 {
1879 struct fe_priv *np = netdev_priv(dev);
1880 u32 flags;
1881 struct ring_desc* orig_get_tx = np->get_tx.orig;
1882
1883 while ((np->get_tx.orig != np->put_tx.orig) &&
1884 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
1885
1886 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
1887 dev->name, flags);
1888
1889 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1890 np->get_tx_ctx->dma_len,
1891 PCI_DMA_TODEVICE);
1892 np->get_tx_ctx->dma = 0;
1893
1894 if (np->desc_ver == DESC_VER_1) {
1895 if (flags & NV_TX_LASTPACKET) {
1896 if (flags & NV_TX_ERROR) {
1897 if (flags & NV_TX_UNDERFLOW)
1898 np->stats.tx_fifo_errors++;
1899 if (flags & NV_TX_CARRIERLOST)
1900 np->stats.tx_carrier_errors++;
1901 np->stats.tx_errors++;
1902 } else {
1903 np->stats.tx_packets++;
1904 np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1905 }
1906 dev_kfree_skb_any(np->get_tx_ctx->skb);
1907 np->get_tx_ctx->skb = NULL;
1908 }
1909 } else {
1910 if (flags & NV_TX2_LASTPACKET) {
1911 if (flags & NV_TX2_ERROR) {
1912 if (flags & NV_TX2_UNDERFLOW)
1913 np->stats.tx_fifo_errors++;
1914 if (flags & NV_TX2_CARRIERLOST)
1915 np->stats.tx_carrier_errors++;
1916 np->stats.tx_errors++;
1917 } else {
1918 np->stats.tx_packets++;
1919 np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1920 }
1921 dev_kfree_skb_any(np->get_tx_ctx->skb);
1922 np->get_tx_ctx->skb = NULL;
1923 }
1924 }
1925 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
1926 np->get_tx.orig = np->first_tx.orig;
1927 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1928 np->get_tx_ctx = np->first_tx_ctx;
1929 }
1930 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
1931 np->tx_stop = 0;
1932 netif_wake_queue(dev);
1933 }
1934 }
1935
1936 static void nv_tx_done_optimized(struct net_device *dev, int limit)
1937 {
1938 struct fe_priv *np = netdev_priv(dev);
1939 u32 flags;
1940 struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
1941
1942 while ((np->get_tx.ex != np->put_tx.ex) &&
1943 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
1944 (limit-- > 0)) {
1945
1946 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
1947 dev->name, flags);
1948
1949 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1950 np->get_tx_ctx->dma_len,
1951 PCI_DMA_TODEVICE);
1952 np->get_tx_ctx->dma = 0;
1953
1954 if (flags & NV_TX2_LASTPACKET) {
1955 if (!(flags & NV_TX2_ERROR))
1956 np->stats.tx_packets++;
1957 dev_kfree_skb_any(np->get_tx_ctx->skb);
1958 np->get_tx_ctx->skb = NULL;
1959 }
1960 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
1961 np->get_tx.ex = np->first_tx.ex;
1962 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1963 np->get_tx_ctx = np->first_tx_ctx;
1964 }
1965 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
1966 np->tx_stop = 0;
1967 netif_wake_queue(dev);
1968 }
1969 }
1970
1971 /*
1972 * nv_tx_timeout: dev->tx_timeout function
1973 * Called with netif_tx_lock held.
1974 */
1975 static void nv_tx_timeout(struct net_device *dev)
1976 {
1977 struct fe_priv *np = netdev_priv(dev);
1978 u8 __iomem *base = get_hwbase(dev);
1979 u32 status;
1980
1981 if (np->msi_flags & NV_MSI_X_ENABLED)
1982 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1983 else
1984 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1985
1986 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1987
1988 {
1989 int i;
1990
1991 printk(KERN_INFO "%s: Ring at %lx\n",
1992 dev->name, (unsigned long)np->ring_addr);
1993 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1994 for (i=0;i<=np->register_size;i+= 32) {
1995 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1996 i,
1997 readl(base + i + 0), readl(base + i + 4),
1998 readl(base + i + 8), readl(base + i + 12),
1999 readl(base + i + 16), readl(base + i + 20),
2000 readl(base + i + 24), readl(base + i + 28));
2001 }
2002 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2003 for (i=0;i<np->tx_ring_size;i+= 4) {
2004 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2005 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2006 i,
2007 le32_to_cpu(np->tx_ring.orig[i].buf),
2008 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2009 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2010 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2011 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2012 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2013 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2014 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2015 } else {
2016 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2017 i,
2018 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2019 le32_to_cpu(np->tx_ring.ex[i].buflow),
2020 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2021 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2022 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2023 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2024 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2025 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2026 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2027 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2028 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2029 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2030 }
2031 }
2032 }
2033
2034 spin_lock_irq(&np->lock);
2035
2036 /* 1) stop tx engine */
2037 nv_stop_tx(dev);
2038
2039 /* 2) check that the packets were not sent already: */
2040 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2041 nv_tx_done(dev);
2042 else
2043 nv_tx_done_optimized(dev, np->tx_ring_size);
2044
2045 /* 3) if there are dead entries: clear everything */
2046 if (np->get_tx_ctx != np->put_tx_ctx) {
2047 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2048 nv_drain_tx(dev);
2049 nv_init_tx(dev);
2050 setup_hw_rings(dev, NV_SETUP_TX_RING);
2051 }
2052
2053 netif_wake_queue(dev);
2054
2055 /* 4) restart tx engine */
2056 nv_start_tx(dev);
2057 spin_unlock_irq(&np->lock);
2058 }
2059
2060 /*
2061 * Called when the nic notices a mismatch between the actual data len on the
2062 * wire and the len indicated in the 802 header
2063 */
2064 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2065 {
2066 int hdrlen; /* length of the 802 header */
2067 int protolen; /* length as stored in the proto field */
2068
2069 /* 1) calculate len according to header */
2070 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2071 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2072 hdrlen = VLAN_HLEN;
2073 } else {
2074 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2075 hdrlen = ETH_HLEN;
2076 }
2077 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2078 dev->name, datalen, protolen, hdrlen);
2079 if (protolen > ETH_DATA_LEN)
2080 return datalen; /* Value in proto field not a len, no checks possible */
2081
2082 protolen += hdrlen;
2083 /* consistency checks: */
2084 if (datalen > ETH_ZLEN) {
2085 if (datalen >= protolen) {
2086 /* more data on wire than in 802 header, trim of
2087 * additional data.
2088 */
2089 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2090 dev->name, protolen);
2091 return protolen;
2092 } else {
2093 /* less data on wire than mentioned in header.
2094 * Discard the packet.
2095 */
2096 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2097 dev->name);
2098 return -1;
2099 }
2100 } else {
2101 /* short packet. Accept only if 802 values are also short */
2102 if (protolen > ETH_ZLEN) {
2103 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2104 dev->name);
2105 return -1;
2106 }
2107 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2108 dev->name, datalen);
2109 return datalen;
2110 }
2111 }
2112
2113 static int nv_rx_process(struct net_device *dev, int limit)
2114 {
2115 struct fe_priv *np = netdev_priv(dev);
2116 u32 flags;
2117 u32 rx_processed_cnt = 0;
2118 struct sk_buff *skb;
2119 int len;
2120
2121 while((np->get_rx.orig != np->put_rx.orig) &&
2122 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2123 (rx_processed_cnt++ < limit)) {
2124
2125 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2126 dev->name, flags);
2127
2128 /*
2129 * the packet is for us - immediately tear down the pci mapping.
2130 * TODO: check if a prefetch of the first cacheline improves
2131 * the performance.
2132 */
2133 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2134 np->get_rx_ctx->dma_len,
2135 PCI_DMA_FROMDEVICE);
2136 skb = np->get_rx_ctx->skb;
2137 np->get_rx_ctx->skb = NULL;
2138
2139 {
2140 int j;
2141 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2142 for (j=0; j<64; j++) {
2143 if ((j%16) == 0)
2144 dprintk("\n%03x:", j);
2145 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2146 }
2147 dprintk("\n");
2148 }
2149 /* look at what we actually got: */
2150 if (np->desc_ver == DESC_VER_1) {
2151 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2152 len = flags & LEN_MASK_V1;
2153 if (unlikely(flags & NV_RX_ERROR)) {
2154 if (flags & NV_RX_ERROR4) {
2155 len = nv_getlen(dev, skb->data, len);
2156 if (len < 0) {
2157 np->stats.rx_errors++;
2158 dev_kfree_skb(skb);
2159 goto next_pkt;
2160 }
2161 }
2162 /* framing errors are soft errors */
2163 else if (flags & NV_RX_FRAMINGERR) {
2164 if (flags & NV_RX_SUBSTRACT1) {
2165 len--;
2166 }
2167 }
2168 /* the rest are hard errors */
2169 else {
2170 if (flags & NV_RX_MISSEDFRAME)
2171 np->stats.rx_missed_errors++;
2172 if (flags & NV_RX_CRCERR)
2173 np->stats.rx_crc_errors++;
2174 if (flags & NV_RX_OVERFLOW)
2175 np->stats.rx_over_errors++;
2176 np->stats.rx_errors++;
2177 dev_kfree_skb(skb);
2178 goto next_pkt;
2179 }
2180 }
2181 } else {
2182 dev_kfree_skb(skb);
2183 goto next_pkt;
2184 }
2185 } else {
2186 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2187 len = flags & LEN_MASK_V2;
2188 if (unlikely(flags & NV_RX2_ERROR)) {
2189 if (flags & NV_RX2_ERROR4) {
2190 len = nv_getlen(dev, skb->data, len);
2191 if (len < 0) {
2192 np->stats.rx_errors++;
2193 dev_kfree_skb(skb);
2194 goto next_pkt;
2195 }
2196 }
2197 /* framing errors are soft errors */
2198 else if (flags & NV_RX2_FRAMINGERR) {
2199 if (flags & NV_RX2_SUBSTRACT1) {
2200 len--;
2201 }
2202 }
2203 /* the rest are hard errors */
2204 else {
2205 if (flags & NV_RX2_CRCERR)
2206 np->stats.rx_crc_errors++;
2207 if (flags & NV_RX2_OVERFLOW)
2208 np->stats.rx_over_errors++;
2209 np->stats.rx_errors++;
2210 dev_kfree_skb(skb);
2211 goto next_pkt;
2212 }
2213 }
2214 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2215 skb->ip_summed = CHECKSUM_UNNECESSARY;
2216 } else {
2217 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2218 (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2219 skb->ip_summed = CHECKSUM_UNNECESSARY;
2220 }
2221 }
2222 } else {
2223 dev_kfree_skb(skb);
2224 goto next_pkt;
2225 }
2226 }
2227 /* got a valid packet - forward it to the network core */
2228 skb_put(skb, len);
2229 skb->protocol = eth_type_trans(skb, dev);
2230 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2231 dev->name, len, skb->protocol);
2232 #ifdef CONFIG_FORCEDETH_NAPI
2233 netif_receive_skb(skb);
2234 #else
2235 netif_rx(skb);
2236 #endif
2237 dev->last_rx = jiffies;
2238 np->stats.rx_packets++;
2239 np->stats.rx_bytes += len;
2240 next_pkt:
2241 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2242 np->get_rx.orig = np->first_rx.orig;
2243 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2244 np->get_rx_ctx = np->first_rx_ctx;
2245 }
2246
2247 return rx_processed_cnt;
2248 }
2249
2250 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2251 {
2252 struct fe_priv *np = netdev_priv(dev);
2253 u32 flags;
2254 u32 vlanflags = 0;
2255 u32 rx_processed_cnt = 0;
2256 struct sk_buff *skb;
2257 int len;
2258
2259 while((np->get_rx.ex != np->put_rx.ex) &&
2260 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2261 (rx_processed_cnt++ < limit)) {
2262
2263 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2264 dev->name, flags);
2265
2266 /*
2267 * the packet is for us - immediately tear down the pci mapping.
2268 * TODO: check if a prefetch of the first cacheline improves
2269 * the performance.
2270 */
2271 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2272 np->get_rx_ctx->dma_len,
2273 PCI_DMA_FROMDEVICE);
2274 skb = np->get_rx_ctx->skb;
2275 np->get_rx_ctx->skb = NULL;
2276
2277 {
2278 int j;
2279 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2280 for (j=0; j<64; j++) {
2281 if ((j%16) == 0)
2282 dprintk("\n%03x:", j);
2283 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2284 }
2285 dprintk("\n");
2286 }
2287 /* look at what we actually got: */
2288 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2289 len = flags & LEN_MASK_V2;
2290 if (unlikely(flags & NV_RX2_ERROR)) {
2291 if (flags & NV_RX2_ERROR4) {
2292 len = nv_getlen(dev, skb->data, len);
2293 if (len < 0) {
2294 dev_kfree_skb(skb);
2295 goto next_pkt;
2296 }
2297 }
2298 /* framing errors are soft errors */
2299 else if (flags & NV_RX2_FRAMINGERR) {
2300 if (flags & NV_RX2_SUBSTRACT1) {
2301 len--;
2302 }
2303 }
2304 /* the rest are hard errors */
2305 else {
2306 dev_kfree_skb(skb);
2307 goto next_pkt;
2308 }
2309 }
2310
2311 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2312 skb->ip_summed = CHECKSUM_UNNECESSARY;
2313 } else {
2314 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2315 (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2316 skb->ip_summed = CHECKSUM_UNNECESSARY;
2317 }
2318 }
2319
2320 /* got a valid packet - forward it to the network core */
2321 skb_put(skb, len);
2322 skb->protocol = eth_type_trans(skb, dev);
2323 prefetch(skb->data);
2324
2325 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2326 dev->name, len, skb->protocol);
2327
2328 if (likely(!np->vlangrp)) {
2329 #ifdef CONFIG_FORCEDETH_NAPI
2330 netif_receive_skb(skb);
2331 #else
2332 netif_rx(skb);
2333 #endif
2334 } else {
2335 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2336 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2337 #ifdef CONFIG_FORCEDETH_NAPI
2338 vlan_hwaccel_receive_skb(skb, np->vlangrp,
2339 vlanflags & NV_RX3_VLAN_TAG_MASK);
2340 #else
2341 vlan_hwaccel_rx(skb, np->vlangrp,
2342 vlanflags & NV_RX3_VLAN_TAG_MASK);
2343 #endif
2344 } else {
2345 #ifdef CONFIG_FORCEDETH_NAPI
2346 netif_receive_skb(skb);
2347 #else
2348 netif_rx(skb);
2349 #endif
2350 }
2351 }
2352
2353 dev->last_rx = jiffies;
2354 np->stats.rx_packets++;
2355 np->stats.rx_bytes += len;
2356 } else {
2357 dev_kfree_skb(skb);
2358 }
2359 next_pkt:
2360 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2361 np->get_rx.ex = np->first_rx.ex;
2362 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2363 np->get_rx_ctx = np->first_rx_ctx;
2364 }
2365
2366 return rx_processed_cnt;
2367 }
2368
2369 static void set_bufsize(struct net_device *dev)
2370 {
2371 struct fe_priv *np = netdev_priv(dev);
2372
2373 if (dev->mtu <= ETH_DATA_LEN)
2374 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2375 else
2376 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2377 }
2378
2379 /*
2380 * nv_change_mtu: dev->change_mtu function
2381 * Called with dev_base_lock held for read.
2382 */
2383 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2384 {
2385 struct fe_priv *np = netdev_priv(dev);
2386 int old_mtu;
2387
2388 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2389 return -EINVAL;
2390
2391 old_mtu = dev->mtu;
2392 dev->mtu = new_mtu;
2393
2394 /* return early if the buffer sizes will not change */
2395 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2396 return 0;
2397 if (old_mtu == new_mtu)
2398 return 0;
2399
2400 /* synchronized against open : rtnl_lock() held by caller */
2401 if (netif_running(dev)) {
2402 u8 __iomem *base = get_hwbase(dev);
2403 /*
2404 * It seems that the nic preloads valid ring entries into an
2405 * internal buffer. The procedure for flushing everything is
2406 * guessed, there is probably a simpler approach.
2407 * Changing the MTU is a rare event, it shouldn't matter.
2408 */
2409 nv_disable_irq(dev);
2410 netif_tx_lock_bh(dev);
2411 spin_lock(&np->lock);
2412 /* stop engines */
2413 nv_stop_rx(dev);
2414 nv_stop_tx(dev);
2415 nv_txrx_reset(dev);
2416 /* drain rx queue */
2417 nv_drain_rx(dev);
2418 nv_drain_tx(dev);
2419 /* reinit driver view of the rx queue */
2420 set_bufsize(dev);
2421 if (nv_init_ring(dev)) {
2422 if (!np->in_shutdown)
2423 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2424 }
2425 /* reinit nic view of the rx queue */
2426 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2427 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2428 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2429 base + NvRegRingSizes);
2430 pci_push(base);
2431 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2432 pci_push(base);
2433
2434 /* restart rx engine */
2435 nv_start_rx(dev);
2436 nv_start_tx(dev);
2437 spin_unlock(&np->lock);
2438 netif_tx_unlock_bh(dev);
2439 nv_enable_irq(dev);
2440 }
2441 return 0;
2442 }
2443
2444 static void nv_copy_mac_to_hw(struct net_device *dev)
2445 {
2446 u8 __iomem *base = get_hwbase(dev);
2447 u32 mac[2];
2448
2449 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2450 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2451 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2452
2453 writel(mac[0], base + NvRegMacAddrA);
2454 writel(mac[1], base + NvRegMacAddrB);
2455 }
2456
2457 /*
2458 * nv_set_mac_address: dev->set_mac_address function
2459 * Called with rtnl_lock() held.
2460 */
2461 static int nv_set_mac_address(struct net_device *dev, void *addr)
2462 {
2463 struct fe_priv *np = netdev_priv(dev);
2464 struct sockaddr *macaddr = (struct sockaddr*)addr;
2465
2466 if (!is_valid_ether_addr(macaddr->sa_data))
2467 return -EADDRNOTAVAIL;
2468
2469 /* synchronized against open : rtnl_lock() held by caller */
2470 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2471
2472 if (netif_running(dev)) {
2473 netif_tx_lock_bh(dev);
2474 spin_lock_irq(&np->lock);
2475
2476 /* stop rx engine */
2477 nv_stop_rx(dev);
2478
2479 /* set mac address */
2480 nv_copy_mac_to_hw(dev);
2481
2482 /* restart rx engine */
2483 nv_start_rx(dev);
2484 spin_unlock_irq(&np->lock);
2485 netif_tx_unlock_bh(dev);
2486 } else {
2487 nv_copy_mac_to_hw(dev);
2488 }
2489 return 0;
2490 }
2491
2492 /*
2493 * nv_set_multicast: dev->set_multicast function
2494 * Called with netif_tx_lock held.
2495 */
2496 static void nv_set_multicast(struct net_device *dev)
2497 {
2498 struct fe_priv *np = netdev_priv(dev);
2499 u8 __iomem *base = get_hwbase(dev);
2500 u32 addr[2];
2501 u32 mask[2];
2502 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2503
2504 memset(addr, 0, sizeof(addr));
2505 memset(mask, 0, sizeof(mask));
2506
2507 if (dev->flags & IFF_PROMISC) {
2508 pff |= NVREG_PFF_PROMISC;
2509 } else {
2510 pff |= NVREG_PFF_MYADDR;
2511
2512 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2513 u32 alwaysOff[2];
2514 u32 alwaysOn[2];
2515
2516 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2517 if (dev->flags & IFF_ALLMULTI) {
2518 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2519 } else {
2520 struct dev_mc_list *walk;
2521
2522 walk = dev->mc_list;
2523 while (walk != NULL) {
2524 u32 a, b;
2525 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2526 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2527 alwaysOn[0] &= a;
2528 alwaysOff[0] &= ~a;
2529 alwaysOn[1] &= b;
2530 alwaysOff[1] &= ~b;
2531 walk = walk->next;
2532 }
2533 }
2534 addr[0] = alwaysOn[0];
2535 addr[1] = alwaysOn[1];
2536 mask[0] = alwaysOn[0] | alwaysOff[0];
2537 mask[1] = alwaysOn[1] | alwaysOff[1];
2538 }
2539 }
2540 addr[0] |= NVREG_MCASTADDRA_FORCE;
2541 pff |= NVREG_PFF_ALWAYS;
2542 spin_lock_irq(&np->lock);
2543 nv_stop_rx(dev);
2544 writel(addr[0], base + NvRegMulticastAddrA);
2545 writel(addr[1], base + NvRegMulticastAddrB);
2546 writel(mask[0], base + NvRegMulticastMaskA);
2547 writel(mask[1], base + NvRegMulticastMaskB);
2548 writel(pff, base + NvRegPacketFilterFlags);
2549 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2550 dev->name);
2551 nv_start_rx(dev);
2552 spin_unlock_irq(&np->lock);
2553 }
2554
2555 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2556 {
2557 struct fe_priv *np = netdev_priv(dev);
2558 u8 __iomem *base = get_hwbase(dev);
2559
2560 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2561
2562 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2563 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2564 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2565 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2566 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2567 } else {
2568 writel(pff, base + NvRegPacketFilterFlags);
2569 }
2570 }
2571 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2572 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2573 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2574 writel(NVREG_TX_PAUSEFRAME_ENABLE, base + NvRegTxPauseFrame);
2575 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2576 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2577 } else {
2578 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
2579 writel(regmisc, base + NvRegMisc1);
2580 }
2581 }
2582 }
2583
2584 /**
2585 * nv_update_linkspeed: Setup the MAC according to the link partner
2586 * @dev: Network device to be configured
2587 *
2588 * The function queries the PHY and checks if there is a link partner.
2589 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2590 * set to 10 MBit HD.
2591 *
2592 * The function returns 0 if there is no link partner and 1 if there is
2593 * a good link partner.
2594 */
2595 static int nv_update_linkspeed(struct net_device *dev)
2596 {
2597 struct fe_priv *np = netdev_priv(dev);
2598 u8 __iomem *base = get_hwbase(dev);
2599 int adv = 0;
2600 int lpa = 0;
2601 int adv_lpa, adv_pause, lpa_pause;
2602 int newls = np->linkspeed;
2603 int newdup = np->duplex;
2604 int mii_status;
2605 int retval = 0;
2606 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2607
2608 /* BMSR_LSTATUS is latched, read it twice:
2609 * we want the current value.
2610 */
2611 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2612 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2613
2614 if (!(mii_status & BMSR_LSTATUS)) {
2615 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2616 dev->name);
2617 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2618 newdup = 0;
2619 retval = 0;
2620 goto set_speed;
2621 }
2622
2623 if (np->autoneg == 0) {
2624 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2625 dev->name, np->fixed_mode);
2626 if (np->fixed_mode & LPA_100FULL) {
2627 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2628 newdup = 1;
2629 } else if (np->fixed_mode & LPA_100HALF) {
2630 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2631 newdup = 0;
2632 } else if (np->fixed_mode & LPA_10FULL) {
2633 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2634 newdup = 1;
2635 } else {
2636 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2637 newdup = 0;
2638 }
2639 retval = 1;
2640 goto set_speed;
2641 }
2642 /* check auto negotiation is complete */
2643 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2644 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2645 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2646 newdup = 0;
2647 retval = 0;
2648 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2649 goto set_speed;
2650 }
2651
2652 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2653 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2654 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2655 dev->name, adv, lpa);
2656
2657 retval = 1;
2658 if (np->gigabit == PHY_GIGABIT) {
2659 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2660 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2661
2662 if ((control_1000 & ADVERTISE_1000FULL) &&
2663 (status_1000 & LPA_1000FULL)) {
2664 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2665 dev->name);
2666 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2667 newdup = 1;
2668 goto set_speed;
2669 }
2670 }
2671
2672 /* FIXME: handle parallel detection properly */
2673 adv_lpa = lpa & adv;
2674 if (adv_lpa & LPA_100FULL) {
2675 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2676 newdup = 1;
2677 } else if (adv_lpa & LPA_100HALF) {
2678 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2679 newdup = 0;
2680 } else if (adv_lpa & LPA_10FULL) {
2681 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2682 newdup = 1;
2683 } else if (adv_lpa & LPA_10HALF) {
2684 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2685 newdup = 0;
2686 } else {
2687 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2688 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2689 newdup = 0;
2690 }
2691
2692 set_speed:
2693 if (np->duplex == newdup && np->linkspeed == newls)
2694 return retval;
2695
2696 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2697 dev->name, np->linkspeed, np->duplex, newls, newdup);
2698
2699 np->duplex = newdup;
2700 np->linkspeed = newls;
2701
2702 if (np->gigabit == PHY_GIGABIT) {
2703 phyreg = readl(base + NvRegRandomSeed);
2704 phyreg &= ~(0x3FF00);
2705 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2706 phyreg |= NVREG_RNDSEED_FORCE3;
2707 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2708 phyreg |= NVREG_RNDSEED_FORCE2;
2709 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2710 phyreg |= NVREG_RNDSEED_FORCE;
2711 writel(phyreg, base + NvRegRandomSeed);
2712 }
2713
2714 phyreg = readl(base + NvRegPhyInterface);
2715 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2716 if (np->duplex == 0)
2717 phyreg |= PHY_HALF;
2718 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2719 phyreg |= PHY_100;
2720 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2721 phyreg |= PHY_1000;
2722 writel(phyreg, base + NvRegPhyInterface);
2723
2724 if (phyreg & PHY_RGMII) {
2725 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2726 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2727 else
2728 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2729 } else {
2730 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2731 }
2732 writel(txreg, base + NvRegTxDeferral);
2733
2734 if (np->desc_ver == DESC_VER_1) {
2735 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2736 } else {
2737 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2738 txreg = NVREG_TX_WM_DESC2_3_1000;
2739 else
2740 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2741 }
2742 writel(txreg, base + NvRegTxWatermark);
2743
2744 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2745 base + NvRegMisc1);
2746 pci_push(base);
2747 writel(np->linkspeed, base + NvRegLinkSpeed);
2748 pci_push(base);
2749
2750 pause_flags = 0;
2751 /* setup pause frame */
2752 if (np->duplex != 0) {
2753 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2754 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2755 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2756
2757 switch (adv_pause) {
2758 case ADVERTISE_PAUSE_CAP:
2759 if (lpa_pause & LPA_PAUSE_CAP) {
2760 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2761 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2762 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2763 }
2764 break;
2765 case ADVERTISE_PAUSE_ASYM:
2766 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2767 {
2768 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2769 }
2770 break;
2771 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2772 if (lpa_pause & LPA_PAUSE_CAP)
2773 {
2774 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2775 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2776 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2777 }
2778 if (lpa_pause == LPA_PAUSE_ASYM)
2779 {
2780 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2781 }
2782 break;
2783 }
2784 } else {
2785 pause_flags = np->pause_flags;
2786 }
2787 }
2788 nv_update_pause(dev, pause_flags);
2789
2790 return retval;
2791 }
2792
2793 static void nv_linkchange(struct net_device *dev)
2794 {
2795 if (nv_update_linkspeed(dev)) {
2796 if (!netif_carrier_ok(dev)) {
2797 netif_carrier_on(dev);
2798 printk(KERN_INFO "%s: link up.\n", dev->name);
2799 nv_start_rx(dev);
2800 }
2801 } else {
2802 if (netif_carrier_ok(dev)) {
2803 netif_carrier_off(dev);
2804 printk(KERN_INFO "%s: link down.\n", dev->name);
2805 nv_stop_rx(dev);
2806 }
2807 }
2808 }
2809
2810 static void nv_link_irq(struct net_device *dev)
2811 {
2812 u8 __iomem *base = get_hwbase(dev);
2813 u32 miistat;
2814
2815 miistat = readl(base + NvRegMIIStatus);
2816 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2817 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2818
2819 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2820 nv_linkchange(dev);
2821 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2822 }
2823
2824 static irqreturn_t nv_nic_irq(int foo, void *data)
2825 {
2826 struct net_device *dev = (struct net_device *) data;
2827 struct fe_priv *np = netdev_priv(dev);
2828 u8 __iomem *base = get_hwbase(dev);
2829 u32 events;
2830 int i;
2831
2832 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2833
2834 for (i=0; ; i++) {
2835 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2836 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2837 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2838 } else {
2839 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2840 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2841 }
2842 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2843 if (!(events & np->irqmask))
2844 break;
2845
2846 spin_lock(&np->lock);
2847 nv_tx_done(dev);
2848 spin_unlock(&np->lock);
2849
2850 #ifdef CONFIG_FORCEDETH_NAPI
2851 if (events & NVREG_IRQ_RX_ALL) {
2852 netif_rx_schedule(dev);
2853
2854 /* Disable furthur receive irq's */
2855 spin_lock(&np->lock);
2856 np->irqmask &= ~NVREG_IRQ_RX_ALL;
2857
2858 if (np->msi_flags & NV_MSI_X_ENABLED)
2859 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2860 else
2861 writel(np->irqmask, base + NvRegIrqMask);
2862 spin_unlock(&np->lock);
2863 }
2864 #else
2865 if (nv_rx_process(dev, dev->weight)) {
2866 if (unlikely(nv_alloc_rx(dev))) {
2867 spin_lock(&np->lock);
2868 if (!np->in_shutdown)
2869 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2870 spin_unlock(&np->lock);
2871 }
2872 }
2873 #endif
2874 if (unlikely(events & NVREG_IRQ_LINK)) {
2875 spin_lock(&np->lock);
2876 nv_link_irq(dev);
2877 spin_unlock(&np->lock);
2878 }
2879 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
2880 spin_lock(&np->lock);
2881 nv_linkchange(dev);
2882 spin_unlock(&np->lock);
2883 np->link_timeout = jiffies + LINK_TIMEOUT;
2884 }
2885 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
2886 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2887 dev->name, events);
2888 }
2889 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
2890 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2891 dev->name, events);
2892 }
2893 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2894 spin_lock(&np->lock);
2895 /* disable interrupts on the nic */
2896 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2897 writel(0, base + NvRegIrqMask);
2898 else
2899 writel(np->irqmask, base + NvRegIrqMask);
2900 pci_push(base);
2901
2902 if (!np->in_shutdown) {
2903 np->nic_poll_irq = np->irqmask;
2904 np->recover_error = 1;
2905 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2906 }
2907 spin_unlock(&np->lock);
2908 break;
2909 }
2910 if (unlikely(i > max_interrupt_work)) {
2911 spin_lock(&np->lock);
2912 /* disable interrupts on the nic */
2913 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2914 writel(0, base + NvRegIrqMask);
2915 else
2916 writel(np->irqmask, base + NvRegIrqMask);
2917 pci_push(base);
2918
2919 if (!np->in_shutdown) {
2920 np->nic_poll_irq = np->irqmask;
2921 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2922 }
2923 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2924 spin_unlock(&np->lock);
2925 break;
2926 }
2927
2928 }
2929 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2930
2931 return IRQ_RETVAL(i);
2932 }
2933
2934 #define TX_WORK_PER_LOOP 64
2935 #define RX_WORK_PER_LOOP 64
2936 /**
2937 * All _optimized functions are used to help increase performance
2938 * (reduce CPU and increase throughput). They use descripter version 3,
2939 * compiler directives, and reduce memory accesses.
2940 */
2941 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
2942 {
2943 struct net_device *dev = (struct net_device *) data;
2944 struct fe_priv *np = netdev_priv(dev);
2945 u8 __iomem *base = get_hwbase(dev);
2946 u32 events;
2947 int i;
2948
2949 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
2950
2951 for (i=0; ; i++) {
2952 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2953 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2954 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2955 } else {
2956 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2957 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2958 }
2959 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2960 if (!(events & np->irqmask))
2961 break;
2962
2963 spin_lock(&np->lock);
2964 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
2965 spin_unlock(&np->lock);
2966
2967 #ifdef CONFIG_FORCEDETH_NAPI
2968 if (events & NVREG_IRQ_RX_ALL) {
2969 netif_rx_schedule(dev);
2970
2971 /* Disable furthur receive irq's */
2972 spin_lock(&np->lock);
2973 np->irqmask &= ~NVREG_IRQ_RX_ALL;
2974
2975 if (np->msi_flags & NV_MSI_X_ENABLED)
2976 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2977 else
2978 writel(np->irqmask, base + NvRegIrqMask);
2979 spin_unlock(&np->lock);
2980 }
2981 #else
2982 if (nv_rx_process_optimized(dev, dev->weight)) {
2983 if (unlikely(nv_alloc_rx_optimized(dev))) {
2984 spin_lock(&np->lock);
2985 if (!np->in_shutdown)
2986 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2987 spin_unlock(&np->lock);
2988 }
2989 }
2990 #endif
2991 if (unlikely(events & NVREG_IRQ_LINK)) {
2992 spin_lock(&np->lock);
2993 nv_link_irq(dev);
2994 spin_unlock(&np->lock);
2995 }
2996 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
2997 spin_lock(&np->lock);
2998 nv_linkchange(dev);
2999 spin_unlock(&np->lock);
3000 np->link_timeout = jiffies + LINK_TIMEOUT;
3001 }
3002 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3003 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3004 dev->name, events);
3005 }
3006 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3007 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3008 dev->name, events);
3009 }
3010 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3011 spin_lock(&np->lock);
3012 /* disable interrupts on the nic */
3013 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3014 writel(0, base + NvRegIrqMask);
3015 else
3016 writel(np->irqmask, base + NvRegIrqMask);
3017 pci_push(base);
3018
3019 if (!np->in_shutdown) {
3020 np->nic_poll_irq = np->irqmask;
3021 np->recover_error = 1;
3022 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3023 }
3024 spin_unlock(&np->lock);
3025 break;
3026 }
3027
3028 if (unlikely(i > max_interrupt_work)) {
3029 spin_lock(&np->lock);
3030 /* disable interrupts on the nic */
3031 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3032 writel(0, base + NvRegIrqMask);
3033 else
3034 writel(np->irqmask, base + NvRegIrqMask);
3035 pci_push(base);
3036
3037 if (!np->in_shutdown) {
3038 np->nic_poll_irq = np->irqmask;
3039 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3040 }
3041 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3042 spin_unlock(&np->lock);
3043 break;
3044 }
3045
3046 }
3047 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3048
3049 return IRQ_RETVAL(i);
3050 }
3051
3052 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3053 {
3054 struct net_device *dev = (struct net_device *) data;
3055 struct fe_priv *np = netdev_priv(dev);
3056 u8 __iomem *base = get_hwbase(dev);
3057 u32 events;
3058 int i;
3059 unsigned long flags;
3060
3061 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3062
3063 for (i=0; ; i++) {
3064 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3065 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3066 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3067 if (!(events & np->irqmask))
3068 break;
3069
3070 spin_lock_irqsave(&np->lock, flags);
3071 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3072 spin_unlock_irqrestore(&np->lock, flags);
3073
3074 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3075 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3076 dev->name, events);
3077 }
3078 if (unlikely(i > max_interrupt_work)) {
3079 spin_lock_irqsave(&np->lock, flags);
3080 /* disable interrupts on the nic */
3081 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3082 pci_push(base);
3083
3084 if (!np->in_shutdown) {
3085 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3086 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3087 }
3088 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3089 spin_unlock_irqrestore(&np->lock, flags);
3090 break;
3091 }
3092
3093 }
3094 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3095
3096 return IRQ_RETVAL(i);
3097 }
3098
3099 #ifdef CONFIG_FORCEDETH_NAPI
3100 static int nv_napi_poll(struct net_device *dev, int *budget)
3101 {
3102 int pkts, limit = min(*budget, dev->quota);
3103 struct fe_priv *np = netdev_priv(dev);
3104 u8 __iomem *base = get_hwbase(dev);
3105 unsigned long flags;
3106 int retcode;
3107
3108 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3109 pkts = nv_rx_process(dev, limit);
3110 retcode = nv_alloc_rx(dev);
3111 } else {
3112 pkts = nv_rx_process_optimized(dev, limit);
3113 retcode = nv_alloc_rx_optimized(dev);
3114 }
3115
3116 if (retcode) {
3117 spin_lock_irqsave(&np->lock, flags);
3118 if (!np->in_shutdown)
3119 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3120 spin_unlock_irqrestore(&np->lock, flags);
3121 }
3122
3123 if (pkts < limit) {
3124 /* all done, no more packets present */
3125 netif_rx_complete(dev);
3126
3127 /* re-enable receive interrupts */
3128 spin_lock_irqsave(&np->lock, flags);
3129
3130 np->irqmask |= NVREG_IRQ_RX_ALL;
3131 if (np->msi_flags & NV_MSI_X_ENABLED)
3132 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3133 else
3134 writel(np->irqmask, base + NvRegIrqMask);
3135
3136 spin_unlock_irqrestore(&np->lock, flags);
3137 return 0;
3138 } else {
3139 /* used up our quantum, so reschedule */
3140 dev->quota -= pkts;
3141 *budget -= pkts;
3142 return 1;
3143 }
3144 }
3145 #endif
3146
3147 #ifdef CONFIG_FORCEDETH_NAPI
3148 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3149 {
3150 struct net_device *dev = (struct net_device *) data;
3151 u8 __iomem *base = get_hwbase(dev);
3152 u32 events;
3153
3154 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3155 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3156
3157 if (events) {
3158 netif_rx_schedule(dev);
3159 /* disable receive interrupts on the nic */
3160 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3161 pci_push(base);
3162 }
3163 return IRQ_HANDLED;
3164 }
3165 #else
3166 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3167 {
3168 struct net_device *dev = (struct net_device *) data;
3169 struct fe_priv *np = netdev_priv(dev);
3170 u8 __iomem *base = get_hwbase(dev);
3171 u32 events;
3172 int i;
3173 unsigned long flags;
3174
3175 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3176
3177 for (i=0; ; i++) {
3178 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3179 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3180 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3181 if (!(events & np->irqmask))
3182 break;
3183
3184 if (nv_rx_process_optimized(dev, dev->weight)) {
3185 if (unlikely(nv_alloc_rx_optimized(dev))) {
3186 spin_lock_irqsave(&np->lock, flags);
3187 if (!np->in_shutdown)
3188 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3189 spin_unlock_irqrestore(&np->lock, flags);
3190 }
3191 }
3192
3193 if (unlikely(i > max_interrupt_work)) {
3194 spin_lock_irqsave(&np->lock, flags);
3195 /* disable interrupts on the nic */
3196 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3197 pci_push(base);
3198
3199 if (!np->in_shutdown) {
3200 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3201 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3202 }
3203 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3204 spin_unlock_irqrestore(&np->lock, flags);
3205 break;
3206 }
3207 }
3208 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3209
3210 return IRQ_RETVAL(i);
3211 }
3212 #endif
3213
3214 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3215 {
3216 struct net_device *dev = (struct net_device *) data;
3217 struct fe_priv *np = netdev_priv(dev);
3218 u8 __iomem *base = get_hwbase(dev);
3219 u32 events;
3220 int i;
3221 unsigned long flags;
3222
3223 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3224
3225 for (i=0; ; i++) {
3226 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3227 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3228 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3229 if (!(events & np->irqmask))
3230 break;
3231
3232 /* check tx in case we reached max loop limit in tx isr */
3233 spin_lock_irqsave(&np->lock, flags);
3234 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3235 spin_unlock_irqrestore(&np->lock, flags);
3236
3237 if (events & NVREG_IRQ_LINK) {
3238 spin_lock_irqsave(&np->lock, flags);
3239 nv_link_irq(dev);
3240 spin_unlock_irqrestore(&np->lock, flags);
3241 }
3242 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3243 spin_lock_irqsave(&np->lock, flags);
3244 nv_linkchange(dev);
3245 spin_unlock_irqrestore(&np->lock, flags);
3246 np->link_timeout = jiffies + LINK_TIMEOUT;
3247 }
3248 if (events & NVREG_IRQ_RECOVER_ERROR) {
3249 spin_lock_irq(&np->lock);
3250 /* disable interrupts on the nic */
3251 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3252 pci_push(base);
3253
3254 if (!np->in_shutdown) {
3255 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3256 np->recover_error = 1;
3257 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3258 }
3259 spin_unlock_irq(&np->lock);
3260 break;
3261 }
3262 if (events & (NVREG_IRQ_UNKNOWN)) {
3263 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3264 dev->name, events);
3265 }
3266 if (unlikely(i > max_interrupt_work)) {
3267 spin_lock_irqsave(&np->lock, flags);
3268 /* disable interrupts on the nic */
3269 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3270 pci_push(base);
3271
3272 if (!np->in_shutdown) {
3273 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3274 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3275 }
3276 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3277 spin_unlock_irqrestore(&np->lock, flags);
3278 break;
3279 }
3280
3281 }
3282 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3283
3284 return IRQ_RETVAL(i);
3285 }
3286
3287 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3288 {
3289 struct net_device *dev = (struct net_device *) data;
3290 struct fe_priv *np = netdev_priv(dev);
3291 u8 __iomem *base = get_hwbase(dev);
3292 u32 events;
3293
3294 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3295
3296 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3297 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3298 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3299 } else {
3300 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3301 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3302 }
3303 pci_push(base);
3304 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3305 if (!(events & NVREG_IRQ_TIMER))
3306 return IRQ_RETVAL(0);
3307
3308 spin_lock(&np->lock);
3309 np->intr_test = 1;
3310 spin_unlock(&np->lock);
3311
3312 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3313
3314 return IRQ_RETVAL(1);
3315 }
3316
3317 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3318 {
3319 u8 __iomem *base = get_hwbase(dev);
3320 int i;
3321 u32 msixmap = 0;
3322
3323 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3324 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3325 * the remaining 8 interrupts.
3326 */
3327 for (i = 0; i < 8; i++) {
3328 if ((irqmask >> i) & 0x1) {
3329 msixmap |= vector << (i << 2);
3330 }
3331 }
3332 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3333
3334 msixmap = 0;
3335 for (i = 0; i < 8; i++) {
3336 if ((irqmask >> (i + 8)) & 0x1) {
3337 msixmap |= vector << (i << 2);
3338 }
3339 }
3340 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3341 }
3342
3343 static int nv_request_irq(struct net_device *dev, int intr_test)
3344 {
3345 struct fe_priv *np = get_nvpriv(dev);
3346 u8 __iomem *base = get_hwbase(dev);
3347 int ret = 1;
3348 int i;
3349 irqreturn_t (*handler)(int foo, void *data);
3350
3351 if (intr_test) {
3352 handler = nv_nic_irq_test;
3353 } else {
3354 if (np->desc_ver == DESC_VER_3)
3355 handler = nv_nic_irq_optimized;
3356 else
3357 handler = nv_nic_irq;
3358 }
3359
3360 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3361 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3362 np->msi_x_entry[i].entry = i;
3363 }
3364 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3365 np->msi_flags |= NV_MSI_X_ENABLED;
3366 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3367 /* Request irq for rx handling */
3368 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3369 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3370 pci_disable_msix(np->pci_dev);
3371 np->msi_flags &= ~NV_MSI_X_ENABLED;
3372 goto out_err;
3373 }
3374 /* Request irq for tx handling */
3375 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3376 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3377 pci_disable_msix(np->pci_dev);
3378 np->msi_flags &= ~NV_MSI_X_ENABLED;
3379 goto out_free_rx;
3380 }
3381 /* Request irq for link and timer handling */
3382 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3383 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3384 pci_disable_msix(np->pci_dev);
3385 np->msi_flags &= ~NV_MSI_X_ENABLED;
3386 goto out_free_tx;
3387 }
3388 /* map interrupts to their respective vector */
3389 writel(0, base + NvRegMSIXMap0);
3390 writel(0, base + NvRegMSIXMap1);
3391 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3392 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3393 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3394 } else {
3395 /* Request irq for all interrupts */
3396 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3397 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3398 pci_disable_msix(np->pci_dev);
3399 np->msi_flags &= ~NV_MSI_X_ENABLED;
3400 goto out_err;
3401 }
3402
3403 /* map interrupts to vector 0 */
3404 writel(0, base + NvRegMSIXMap0);
3405 writel(0, base + NvRegMSIXMap1);
3406 }
3407 }
3408 }
3409 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3410 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3411 np->msi_flags |= NV_MSI_ENABLED;
3412 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3413 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3414 pci_disable_msi(np->pci_dev);
3415 np->msi_flags &= ~NV_MSI_ENABLED;
3416 goto out_err;
3417 }
3418
3419 /* map interrupts to vector 0 */
3420 writel(0, base + NvRegMSIMap0);
3421 writel(0, base + NvRegMSIMap1);
3422 /* enable msi vector 0 */
3423 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3424 }
3425 }
3426 if (ret != 0) {
3427 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3428 goto out_err;
3429
3430 }
3431
3432 return 0;
3433 out_free_tx:
3434 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3435 out_free_rx:
3436 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3437 out_err:
3438 return 1;
3439 }
3440
3441 static void nv_free_irq(struct net_device *dev)
3442 {
3443 struct fe_priv *np = get_nvpriv(dev);
3444 int i;
3445
3446 if (np->msi_flags & NV_MSI_X_ENABLED) {
3447 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3448 free_irq(np->msi_x_entry[i].vector, dev);
3449 }
3450 pci_disable_msix(np->pci_dev);
3451 np->msi_flags &= ~NV_MSI_X_ENABLED;
3452 } else {
3453 free_irq(np->pci_dev->irq, dev);
3454 if (np->msi_flags & NV_MSI_ENABLED) {
3455 pci_disable_msi(np->pci_dev);
3456 np->msi_flags &= ~NV_MSI_ENABLED;
3457 }
3458 }
3459 }
3460
3461 static void nv_do_nic_poll(unsigned long data)
3462 {
3463 struct net_device *dev = (struct net_device *) data;
3464 struct fe_priv *np = netdev_priv(dev);
3465 u8 __iomem *base = get_hwbase(dev);
3466 u32 mask = 0;
3467
3468 /*
3469 * First disable irq(s) and then
3470 * reenable interrupts on the nic, we have to do this before calling
3471 * nv_nic_irq because that may decide to do otherwise
3472 */
3473
3474 if (!using_multi_irqs(dev)) {
3475 if (np->msi_flags & NV_MSI_X_ENABLED)
3476 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3477 else
3478 disable_irq_lockdep(dev->irq);
3479 mask = np->irqmask;
3480 } else {
3481 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3482 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3483 mask |= NVREG_IRQ_RX_ALL;
3484 }
3485 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3486 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3487 mask |= NVREG_IRQ_TX_ALL;
3488 }
3489 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3490 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3491 mask |= NVREG_IRQ_OTHER;
3492 }
3493 }
3494 np->nic_poll_irq = 0;
3495
3496 if (np->recover_error) {
3497 np->recover_error = 0;
3498 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3499 if (netif_running(dev)) {
3500 netif_tx_lock_bh(dev);
3501 spin_lock(&np->lock);
3502 /* stop engines */
3503 nv_stop_rx(dev);
3504 nv_stop_tx(dev);
3505 nv_txrx_reset(dev);
3506 /* drain rx queue */
3507 nv_drain_rx(dev);
3508 nv_drain_tx(dev);
3509 /* reinit driver view of the rx queue */
3510 set_bufsize(dev);
3511 if (nv_init_ring(dev)) {
3512 if (!np->in_shutdown)
3513 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3514 }
3515 /* reinit nic view of the rx queue */
3516 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3517 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3518 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3519 base + NvRegRingSizes);
3520 pci_push(base);
3521 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3522 pci_push(base);
3523
3524 /* restart rx engine */
3525 nv_start_rx(dev);
3526 nv_start_tx(dev);
3527 spin_unlock(&np->lock);
3528 netif_tx_unlock_bh(dev);
3529 }
3530 }
3531
3532 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
3533
3534 writel(mask, base + NvRegIrqMask);
3535 pci_push(base);
3536
3537 if (!using_multi_irqs(dev)) {
3538 if (np->desc_ver == DESC_VER_3)
3539 nv_nic_irq_optimized(0, dev);
3540 else
3541 nv_nic_irq(0, dev);
3542 if (np->msi_flags & NV_MSI_X_ENABLED)
3543 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3544 else
3545 enable_irq_lockdep(dev->irq);
3546 } else {
3547 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3548 nv_nic_irq_rx(0, dev);
3549 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3550 }
3551 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3552 nv_nic_irq_tx(0, dev);
3553 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3554 }
3555 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3556 nv_nic_irq_other(0, dev);
3557 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3558 }
3559 }
3560 }
3561
3562 #ifdef CONFIG_NET_POLL_CONTROLLER
3563 static void nv_poll_controller(struct net_device *dev)
3564 {
3565 nv_do_nic_poll((unsigned long) dev);
3566 }
3567 #endif
3568
3569 static void nv_do_stats_poll(unsigned long data)
3570 {
3571 struct net_device *dev = (struct net_device *) data;
3572 struct fe_priv *np = netdev_priv(dev);
3573
3574 nv_get_hw_stats(dev);
3575
3576 if (!np->in_shutdown)
3577 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3578 }
3579
3580 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3581 {
3582 struct fe_priv *np = netdev_priv(dev);
3583 strcpy(info->driver, "forcedeth");
3584 strcpy(info->version, FORCEDETH_VERSION);
3585 strcpy(info->bus_info, pci_name(np->pci_dev));
3586 }
3587
3588 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3589 {
3590 struct fe_priv *np = netdev_priv(dev);
3591 wolinfo->supported = WAKE_MAGIC;
3592
3593 spin_lock_irq(&np->lock);
3594 if (np->wolenabled)
3595 wolinfo->wolopts = WAKE_MAGIC;
3596 spin_unlock_irq(&np->lock);
3597 }
3598
3599 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3600 {
3601 struct fe_priv *np = netdev_priv(dev);
3602 u8 __iomem *base = get_hwbase(dev);
3603 u32 flags = 0;
3604
3605 if (wolinfo->wolopts == 0) {
3606 np->wolenabled = 0;
3607 } else if (wolinfo->wolopts & WAKE_MAGIC) {
3608 np->wolenabled = 1;
3609 flags = NVREG_WAKEUPFLAGS_ENABLE;
3610 }
3611 if (netif_running(dev)) {
3612 spin_lock_irq(&np->lock);
3613 writel(flags, base + NvRegWakeUpFlags);
3614 spin_unlock_irq(&np->lock);
3615 }
3616 return 0;
3617 }
3618
3619 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3620 {
3621 struct fe_priv *np = netdev_priv(dev);
3622 int adv;
3623
3624 spin_lock_irq(&np->lock);
3625 ecmd->port = PORT_MII;
3626 if (!netif_running(dev)) {
3627 /* We do not track link speed / duplex setting if the
3628 * interface is disabled. Force a link check */
3629 if (nv_update_linkspeed(dev)) {
3630 if (!netif_carrier_ok(dev))
3631 netif_carrier_on(dev);
3632 } else {
3633 if (netif_carrier_ok(dev))
3634 netif_carrier_off(dev);
3635 }
3636 }
3637
3638 if (netif_carrier_ok(dev)) {
3639 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3640 case NVREG_LINKSPEED_10:
3641 ecmd->speed = SPEED_10;
3642 break;
3643 case NVREG_LINKSPEED_100:
3644 ecmd->speed = SPEED_100;
3645 break;
3646 case NVREG_LINKSPEED_1000:
3647 ecmd->speed = SPEED_1000;
3648 break;
3649 }
3650 ecmd->duplex = DUPLEX_HALF;
3651 if (np->duplex)
3652 ecmd->duplex = DUPLEX_FULL;
3653 } else {
3654 ecmd->speed = -1;
3655 ecmd->duplex = -1;
3656 }
3657
3658 ecmd->autoneg = np->autoneg;
3659
3660 ecmd->advertising = ADVERTISED_MII;
3661 if (np->autoneg) {
3662 ecmd->advertising |= ADVERTISED_Autoneg;
3663 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3664 if (adv & ADVERTISE_10HALF)
3665 ecmd->advertising |= ADVERTISED_10baseT_Half;
3666 if (adv & ADVERTISE_10FULL)
3667 ecmd->advertising |= ADVERTISED_10baseT_Full;
3668 if (adv & ADVERTISE_100HALF)
3669 ecmd->advertising |= ADVERTISED_100baseT_Half;
3670 if (adv & ADVERTISE_100FULL)
3671 ecmd->advertising |= ADVERTISED_100baseT_Full;
3672 if (np->gigabit == PHY_GIGABIT) {
3673 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3674 if (adv & ADVERTISE_1000FULL)
3675 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3676 }
3677 }
3678 ecmd->supported = (SUPPORTED_Autoneg |
3679 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3680 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3681 SUPPORTED_MII);
3682 if (np->gigabit == PHY_GIGABIT)
3683 ecmd->supported |= SUPPORTED_1000baseT_Full;
3684
3685 ecmd->phy_address = np->phyaddr;
3686 ecmd->transceiver = XCVR_EXTERNAL;
3687
3688 /* ignore maxtxpkt, maxrxpkt for now */
3689 spin_unlock_irq(&np->lock);
3690 return 0;
3691 }
3692
3693 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3694 {
3695 struct fe_priv *np = netdev_priv(dev);
3696
3697 if (ecmd->port != PORT_MII)
3698 return -EINVAL;
3699 if (ecmd->transceiver != XCVR_EXTERNAL)
3700 return -EINVAL;
3701 if (ecmd->phy_address != np->phyaddr) {
3702 /* TODO: support switching between multiple phys. Should be
3703 * trivial, but not enabled due to lack of test hardware. */
3704 return -EINVAL;
3705 }
3706 if (ecmd->autoneg == AUTONEG_ENABLE) {
3707 u32 mask;
3708
3709 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3710 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3711 if (np->gigabit == PHY_GIGABIT)
3712 mask |= ADVERTISED_1000baseT_Full;
3713
3714 if ((ecmd->advertising & mask) == 0)
3715 return -EINVAL;
3716
3717 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3718 /* Note: autonegotiation disable, speed 1000 intentionally
3719 * forbidden - noone should need that. */
3720
3721 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3722 return -EINVAL;
3723 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3724 return -EINVAL;
3725 } else {
3726 return -EINVAL;
3727 }
3728
3729 netif_carrier_off(dev);
3730 if (netif_running(dev)) {
3731 nv_disable_irq(dev);
3732 netif_tx_lock_bh(dev);
3733 spin_lock(&np->lock);
3734 /* stop engines */
3735 nv_stop_rx(dev);
3736 nv_stop_tx(dev);
3737 spin_unlock(&np->lock);
3738 netif_tx_unlock_bh(dev);
3739 }
3740
3741 if (ecmd->autoneg == AUTONEG_ENABLE) {
3742 int adv, bmcr;
3743
3744 np->autoneg = 1;
3745
3746 /* advertise only what has been requested */
3747 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3748 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3749 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3750 adv |= ADVERTISE_10HALF;
3751 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3752 adv |= ADVERTISE_10FULL;
3753 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3754 adv |= ADVERTISE_100HALF;
3755 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3756 adv |= ADVERTISE_100FULL;
3757 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3758 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3759 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3760 adv |= ADVERTISE_PAUSE_ASYM;
3761 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3762
3763 if (np->gigabit == PHY_GIGABIT) {
3764 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3765 adv &= ~ADVERTISE_1000FULL;
3766 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3767 adv |= ADVERTISE_1000FULL;
3768 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3769 }
3770
3771 if (netif_running(dev))
3772 printk(KERN_INFO "%s: link down.\n", dev->name);
3773 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3774 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3775 bmcr |= BMCR_ANENABLE;
3776 /* reset the phy in order for settings to stick,
3777 * and cause autoneg to start */
3778 if (phy_reset(dev, bmcr)) {
3779 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3780 return -EINVAL;
3781 }
3782 } else {
3783 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3784 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3785 }
3786 } else {
3787 int adv, bmcr;
3788
3789 np->autoneg = 0;
3790
3791 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3792 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3793 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3794 adv |= ADVERTISE_10HALF;
3795 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3796 adv |= ADVERTISE_10FULL;
3797 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3798 adv |= ADVERTISE_100HALF;
3799 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3800 adv |= ADVERTISE_100FULL;
3801 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3802 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3803 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3804 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3805 }
3806 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3807 adv |= ADVERTISE_PAUSE_ASYM;
3808 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3809 }
3810 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3811 np->fixed_mode = adv;
3812
3813 if (np->gigabit == PHY_GIGABIT) {
3814 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3815 adv &= ~ADVERTISE_1000FULL;
3816 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3817 }
3818
3819 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3820 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3821 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3822 bmcr |= BMCR_FULLDPLX;
3823 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3824 bmcr |= BMCR_SPEED100;
3825 if (np->phy_oui == PHY_OUI_MARVELL) {
3826 /* reset the phy in order for forced mode settings to stick */
3827 if (phy_reset(dev, bmcr)) {
3828 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3829 return -EINVAL;
3830 }
3831 } else {
3832 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3833 if (netif_running(dev)) {
3834 /* Wait a bit and then reconfigure the nic. */
3835 udelay(10);
3836 nv_linkchange(dev);
3837 }
3838 }
3839 }
3840
3841 if (netif_running(dev)) {
3842 nv_start_rx(dev);
3843 nv_start_tx(dev);
3844 nv_enable_irq(dev);
3845 }
3846
3847 return 0;
3848 }
3849
3850 #define FORCEDETH_REGS_VER 1
3851
3852 static int nv_get_regs_len(struct net_device *dev)
3853 {
3854 struct fe_priv *np = netdev_priv(dev);
3855 return np->register_size;
3856 }
3857
3858 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3859 {
3860 struct fe_priv *np = netdev_priv(dev);
3861 u8 __iomem *base = get_hwbase(dev);
3862 u32 *rbuf = buf;
3863 int i;
3864
3865 regs->version = FORCEDETH_REGS_VER;
3866 spin_lock_irq(&np->lock);
3867 for (i = 0;i <= np->register_size/sizeof(u32); i++)
3868 rbuf[i] = readl(base + i*sizeof(u32));
3869 spin_unlock_irq(&np->lock);
3870 }
3871
3872 static int nv_nway_reset(struct net_device *dev)
3873 {
3874 struct fe_priv *np = netdev_priv(dev);
3875 int ret;
3876
3877 if (np->autoneg) {
3878 int bmcr;
3879
3880 netif_carrier_off(dev);
3881 if (netif_running(dev)) {
3882 nv_disable_irq(dev);
3883 netif_tx_lock_bh(dev);
3884 spin_lock(&np->lock);
3885 /* stop engines */
3886 nv_stop_rx(dev);
3887 nv_stop_tx(dev);
3888 spin_unlock(&np->lock);
3889 netif_tx_unlock_bh(dev);
3890 printk(KERN_INFO "%s: link down.\n", dev->name);
3891 }
3892
3893 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3894 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3895 bmcr |= BMCR_ANENABLE;
3896 /* reset the phy in order for settings to stick*/
3897 if (phy_reset(dev, bmcr)) {
3898 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3899 return -EINVAL;
3900 }
3901 } else {
3902 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3903 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3904 }
3905
3906 if (netif_running(dev)) {
3907 nv_start_rx(dev);
3908 nv_start_tx(dev);
3909 nv_enable_irq(dev);
3910 }
3911 ret = 0;
3912 } else {
3913 ret = -EINVAL;
3914 }
3915
3916 return ret;
3917 }
3918
3919 static int nv_set_tso(struct net_device *dev, u32 value)
3920 {
3921 struct fe_priv *np = netdev_priv(dev);
3922
3923 if ((np->driver_data & DEV_HAS_CHECKSUM))
3924 return ethtool_op_set_tso(dev, value);
3925 else
3926 return -EOPNOTSUPP;
3927 }
3928
3929 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3930 {
3931 struct fe_priv *np = netdev_priv(dev);
3932
3933 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3934 ring->rx_mini_max_pending = 0;
3935 ring->rx_jumbo_max_pending = 0;
3936 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3937
3938 ring->rx_pending = np->rx_ring_size;
3939 ring->rx_mini_pending = 0;
3940 ring->rx_jumbo_pending = 0;
3941 ring->tx_pending = np->tx_ring_size;
3942 }
3943
3944 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3945 {
3946 struct fe_priv *np = netdev_priv(dev);
3947 u8 __iomem *base = get_hwbase(dev);
3948 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
3949 dma_addr_t ring_addr;
3950
3951 if (ring->rx_pending < RX_RING_MIN ||
3952 ring->tx_pending < TX_RING_MIN ||
3953 ring->rx_mini_pending != 0 ||
3954 ring->rx_jumbo_pending != 0 ||
3955 (np->desc_ver == DESC_VER_1 &&
3956 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3957 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3958 (np->desc_ver != DESC_VER_1 &&
3959 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3960 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3961 return -EINVAL;
3962 }
3963
3964 /* allocate new rings */
3965 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3966 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3967 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3968 &ring_addr);
3969 } else {
3970 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3971 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3972 &ring_addr);
3973 }
3974 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
3975 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
3976 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
3977 /* fall back to old rings */
3978 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3979 if (rxtx_ring)
3980 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3981 rxtx_ring, ring_addr);
3982 } else {
3983 if (rxtx_ring)
3984 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3985 rxtx_ring, ring_addr);
3986 }
3987 if (rx_skbuff)
3988 kfree(rx_skbuff);
3989 if (tx_skbuff)
3990 kfree(tx_skbuff);
3991 goto exit;
3992 }
3993
3994 if (netif_running(dev)) {
3995 nv_disable_irq(dev);
3996 netif_tx_lock_bh(dev);
3997 spin_lock(&np->lock);
3998 /* stop engines */
3999 nv_stop_rx(dev);
4000 nv_stop_tx(dev);
4001 nv_txrx_reset(dev);
4002 /* drain queues */
4003 nv_drain_rx(dev);
4004 nv_drain_tx(dev);
4005 /* delete queues */
4006 free_rings(dev);
4007 }
4008
4009 /* set new values */
4010 np->rx_ring_size = ring->rx_pending;
4011 np->tx_ring_size = ring->tx_pending;
4012 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4013 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4014 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4015 } else {
4016 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4017 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4018 }
4019 np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4020 np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4021 np->ring_addr = ring_addr;
4022
4023 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4024 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4025
4026 if (netif_running(dev)) {
4027 /* reinit driver view of the queues */
4028 set_bufsize(dev);
4029 if (nv_init_ring(dev)) {
4030 if (!np->in_shutdown)
4031 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4032 }
4033
4034 /* reinit nic view of the queues */
4035 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4036 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4037 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4038 base + NvRegRingSizes);
4039 pci_push(base);
4040 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4041 pci_push(base);
4042
4043 /* restart engines */
4044 nv_start_rx(dev);
4045 nv_start_tx(dev);
4046 spin_unlock(&np->lock);
4047 netif_tx_unlock_bh(dev);
4048 nv_enable_irq(dev);
4049 }
4050 return 0;
4051 exit:
4052 return -ENOMEM;
4053 }
4054
4055 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4056 {
4057 struct fe_priv *np = netdev_priv(dev);
4058
4059 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4060 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4061 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4062 }
4063
4064 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4065 {
4066 struct fe_priv *np = netdev_priv(dev);
4067 int adv, bmcr;
4068
4069 if ((!np->autoneg && np->duplex == 0) ||
4070 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4071 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4072 dev->name);
4073 return -EINVAL;
4074 }
4075 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4076 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4077 return -EINVAL;
4078 }
4079
4080 netif_carrier_off(dev);
4081 if (netif_running(dev)) {
4082 nv_disable_irq(dev);
4083 netif_tx_lock_bh(dev);
4084 spin_lock(&np->lock);
4085 /* stop engines */
4086 nv_stop_rx(dev);
4087 nv_stop_tx(dev);
4088 spin_unlock(&np->lock);
4089 netif_tx_unlock_bh(dev);
4090 }
4091
4092 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4093 if (pause->rx_pause)
4094 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4095 if (pause->tx_pause)
4096 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4097
4098 if (np->autoneg && pause->autoneg) {
4099 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4100
4101 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4102 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4103 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4104 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4105 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4106 adv |= ADVERTISE_PAUSE_ASYM;
4107 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4108
4109 if (netif_running(dev))
4110 printk(KERN_INFO "%s: link down.\n", dev->name);
4111 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4112 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4113 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4114 } else {
4115 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4116 if (pause->rx_pause)
4117 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4118 if (pause->tx_pause)
4119 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4120
4121 if (!netif_running(dev))
4122 nv_update_linkspeed(dev);
4123 else
4124 nv_update_pause(dev, np->pause_flags);
4125 }
4126
4127 if (netif_running(dev)) {
4128 nv_start_rx(dev);
4129 nv_start_tx(dev);
4130 nv_enable_irq(dev);
4131 }
4132 return 0;
4133 }
4134
4135 static u32 nv_get_rx_csum(struct net_device *dev)
4136 {
4137 struct fe_priv *np = netdev_priv(dev);
4138 return (np->rx_csum) != 0;
4139 }
4140
4141 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4142 {
4143 struct fe_priv *np = netdev_priv(dev);
4144 u8 __iomem *base = get_hwbase(dev);
4145 int retcode = 0;
4146
4147 if (np->driver_data & DEV_HAS_CHECKSUM) {
4148 if (data) {
4149 np->rx_csum = 1;
4150 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4151 } else {
4152 np->rx_csum = 0;
4153 /* vlan is dependent on rx checksum offload */
4154 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4155 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4156 }
4157 if (netif_running(dev)) {
4158 spin_lock_irq(&np->lock);
4159 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4160 spin_unlock_irq(&np->lock);
4161 }
4162 } else {
4163 return -EINVAL;
4164 }
4165
4166 return retcode;
4167 }
4168
4169 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4170 {
4171 struct fe_priv *np = netdev_priv(dev);
4172
4173 if (np->driver_data & DEV_HAS_CHECKSUM)
4174 return ethtool_op_set_tx_hw_csum(dev, data);
4175 else
4176 return -EOPNOTSUPP;
4177 }
4178
4179 static int nv_set_sg(struct net_device *dev, u32 data)
4180 {
4181 struct fe_priv *np = netdev_priv(dev);
4182
4183 if (np->driver_data & DEV_HAS_CHECKSUM)
4184 return ethtool_op_set_sg(dev, data);
4185 else
4186 return -EOPNOTSUPP;
4187 }
4188
4189 static int nv_get_stats_count(struct net_device *dev)
4190 {
4191 struct fe_priv *np = netdev_priv(dev);
4192
4193 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4194 return NV_DEV_STATISTICS_V1_COUNT;
4195 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4196 return NV_DEV_STATISTICS_V2_COUNT;
4197 else
4198 return 0;
4199 }
4200
4201 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4202 {
4203 struct fe_priv *np = netdev_priv(dev);
4204
4205 /* update stats */
4206 nv_do_stats_poll((unsigned long)dev);
4207
4208 memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
4209 }
4210
4211 static int nv_self_test_count(struct net_device *dev)
4212 {
4213 struct fe_priv *np = netdev_priv(dev);
4214
4215 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4216 return NV_TEST_COUNT_EXTENDED;
4217 else
4218 return NV_TEST_COUNT_BASE;
4219 }
4220
4221 static int nv_link_test(struct net_device *dev)
4222 {
4223 struct fe_priv *np = netdev_priv(dev);
4224 int mii_status;
4225
4226 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4227 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4228
4229 /* check phy link status */
4230 if (!(mii_status & BMSR_LSTATUS))
4231 return 0;
4232 else
4233 return 1;
4234 }
4235
4236 static int nv_register_test(struct net_device *dev)
4237 {
4238 u8 __iomem *base = get_hwbase(dev);
4239 int i = 0;
4240 u32 orig_read, new_read;
4241
4242 do {
4243 orig_read = readl(base + nv_registers_test[i].reg);
4244
4245 /* xor with mask to toggle bits */
4246 orig_read ^= nv_registers_test[i].mask;
4247
4248 writel(orig_read, base + nv_registers_test[i].reg);
4249
4250 new_read = readl(base + nv_registers_test[i].reg);
4251
4252 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4253 return 0;
4254
4255 /* restore original value */
4256 orig_read ^= nv_registers_test[i].mask;
4257 writel(orig_read, base + nv_registers_test[i].reg);
4258
4259 } while (nv_registers_test[++i].reg != 0);
4260
4261 return 1;
4262 }
4263
4264 static int nv_interrupt_test(struct net_device *dev)
4265 {
4266 struct fe_priv *np = netdev_priv(dev);
4267 u8 __iomem *base = get_hwbase(dev);
4268 int ret = 1;
4269 int testcnt;
4270 u32 save_msi_flags, save_poll_interval = 0;
4271
4272 if (netif_running(dev)) {
4273 /* free current irq */
4274 nv_free_irq(dev);
4275 save_poll_interval = readl(base+NvRegPollingInterval);
4276 }
4277
4278 /* flag to test interrupt handler */
4279 np->intr_test = 0;
4280
4281 /* setup test irq */
4282 save_msi_flags = np->msi_flags;
4283 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4284 np->msi_flags |= 0x001; /* setup 1 vector */
4285 if (nv_request_irq(dev, 1))
4286 return 0;
4287
4288 /* setup timer interrupt */
4289 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4290 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4291
4292 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4293
4294 /* wait for at least one interrupt */
4295 msleep(100);
4296
4297 spin_lock_irq(&np->lock);
4298
4299 /* flag should be set within ISR */
4300 testcnt = np->intr_test;
4301 if (!testcnt)
4302 ret = 2;
4303
4304 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4305 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4306 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4307 else
4308 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4309
4310 spin_unlock_irq(&np->lock);
4311
4312 nv_free_irq(dev);
4313
4314 np->msi_flags = save_msi_flags;
4315
4316 if (netif_running(dev)) {
4317 writel(save_poll_interval, base + NvRegPollingInterval);
4318 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4319 /* restore original irq */
4320 if (nv_request_irq(dev, 0))
4321 return 0;
4322 }
4323
4324 return ret;
4325 }
4326
4327 static int nv_loopback_test(struct net_device *dev)
4328 {
4329 struct fe_priv *np = netdev_priv(dev);
4330 u8 __iomem *base = get_hwbase(dev);
4331 struct sk_buff *tx_skb, *rx_skb;
4332 dma_addr_t test_dma_addr;
4333 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4334 u32 flags;
4335 int len, i, pkt_len;
4336 u8 *pkt_data;
4337 u32 filter_flags = 0;
4338 u32 misc1_flags = 0;
4339 int ret = 1;
4340
4341 if (netif_running(dev)) {
4342 nv_disable_irq(dev);
4343 filter_flags = readl(base + NvRegPacketFilterFlags);
4344 misc1_flags = readl(base + NvRegMisc1);
4345 } else {
4346 nv_txrx_reset(dev);
4347 }
4348
4349 /* reinit driver view of the rx queue */
4350 set_bufsize(dev);
4351 nv_init_ring(dev);
4352
4353 /* setup hardware for loopback */
4354 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4355 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4356
4357 /* reinit nic view of the rx queue */
4358 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4359 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4360 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4361 base + NvRegRingSizes);
4362 pci_push(base);
4363
4364 /* restart rx engine */
4365 nv_start_rx(dev);
4366 nv_start_tx(dev);
4367
4368 /* setup packet for tx */
4369 pkt_len = ETH_DATA_LEN;
4370 tx_skb = dev_alloc_skb(pkt_len);
4371 if (!tx_skb) {
4372 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4373 " of %s\n", dev->name);
4374 ret = 0;
4375 goto out;
4376 }
4377 pkt_data = skb_put(tx_skb, pkt_len);
4378 for (i = 0; i < pkt_len; i++)
4379 pkt_data[i] = (u8)(i & 0xff);
4380 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4381 tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
4382
4383 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4384 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4385 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4386 } else {
4387 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
4388 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
4389 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4390 }
4391 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4392 pci_push(get_hwbase(dev));
4393
4394 msleep(500);
4395
4396 /* check for rx of the packet */
4397 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4398 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4399 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4400
4401 } else {
4402 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4403 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4404 }
4405
4406 if (flags & NV_RX_AVAIL) {
4407 ret = 0;
4408 } else if (np->desc_ver == DESC_VER_1) {
4409 if (flags & NV_RX_ERROR)
4410 ret = 0;
4411 } else {
4412 if (flags & NV_RX2_ERROR) {
4413 ret = 0;
4414 }
4415 }
4416
4417 if (ret) {
4418 if (len != pkt_len) {
4419 ret = 0;
4420 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4421 dev->name, len, pkt_len);
4422 } else {
4423 rx_skb = np->rx_skb[0].skb;
4424 for (i = 0; i < pkt_len; i++) {
4425 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4426 ret = 0;
4427 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4428 dev->name, i);
4429 break;
4430 }
4431 }
4432 }
4433 } else {
4434 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4435 }
4436
4437 pci_unmap_page(np->pci_dev, test_dma_addr,
4438 tx_skb->end-tx_skb->data,
4439 PCI_DMA_TODEVICE);
4440 dev_kfree_skb_any(tx_skb);
4441 out:
4442 /* stop engines */
4443 nv_stop_rx(dev);
4444 nv_stop_tx(dev);
4445 nv_txrx_reset(dev);
4446 /* drain rx queue */
4447 nv_drain_rx(dev);
4448 nv_drain_tx(dev);
4449
4450 if (netif_running(dev)) {
4451 writel(misc1_flags, base + NvRegMisc1);
4452 writel(filter_flags, base + NvRegPacketFilterFlags);
4453 nv_enable_irq(dev);
4454 }
4455
4456 return ret;
4457 }
4458
4459 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4460 {
4461 struct fe_priv *np = netdev_priv(dev);
4462 u8 __iomem *base = get_hwbase(dev);
4463 int result;
4464 memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
4465
4466 if (!nv_link_test(dev)) {
4467 test->flags |= ETH_TEST_FL_FAILED;
4468 buffer[0] = 1;
4469 }
4470
4471 if (test->flags & ETH_TEST_FL_OFFLINE) {
4472 if (netif_running(dev)) {
4473 netif_stop_queue(dev);
4474 netif_poll_disable(dev);
4475 netif_tx_lock_bh(dev);
4476 spin_lock_irq(&np->lock);
4477 nv_disable_hw_interrupts(dev, np->irqmask);
4478 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4479 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4480 } else {
4481 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4482 }
4483 /* stop engines */
4484 nv_stop_rx(dev);
4485 nv_stop_tx(dev);
4486 nv_txrx_reset(dev);
4487 /* drain rx queue */
4488 nv_drain_rx(dev);
4489 nv_drain_tx(dev);
4490 spin_unlock_irq(&np->lock);
4491 netif_tx_unlock_bh(dev);
4492 }
4493
4494 if (!nv_register_test(dev)) {
4495 test->flags |= ETH_TEST_FL_FAILED;
4496 buffer[1] = 1;
4497 }
4498
4499 result = nv_interrupt_test(dev);
4500 if (result != 1) {
4501 test->flags |= ETH_TEST_FL_FAILED;
4502 buffer[2] = 1;
4503 }
4504 if (result == 0) {
4505 /* bail out */
4506 return;
4507 }
4508
4509 if (!nv_loopback_test(dev)) {
4510 test->flags |= ETH_TEST_FL_FAILED;
4511 buffer[3] = 1;
4512 }
4513
4514 if (netif_running(dev)) {
4515 /* reinit driver view of the rx queue */
4516 set_bufsize(dev);
4517 if (nv_init_ring(dev)) {
4518 if (!np->in_shutdown)
4519 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4520 }
4521 /* reinit nic view of the rx queue */
4522 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4523 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4524 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4525 base + NvRegRingSizes);
4526 pci_push(base);
4527 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4528 pci_push(base);
4529 /* restart rx engine */
4530 nv_start_rx(dev);
4531 nv_start_tx(dev);
4532 netif_start_queue(dev);
4533 netif_poll_enable(dev);
4534 nv_enable_hw_interrupts(dev, np->irqmask);
4535 }
4536 }
4537 }
4538
4539 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4540 {
4541 switch (stringset) {
4542 case ETH_SS_STATS:
4543 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
4544 break;
4545 case ETH_SS_TEST:
4546 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
4547 break;
4548 }
4549 }
4550
4551 static const struct ethtool_ops ops = {
4552 .get_drvinfo = nv_get_drvinfo,
4553 .get_link = ethtool_op_get_link,
4554 .get_wol = nv_get_wol,
4555 .set_wol = nv_set_wol,
4556 .get_settings = nv_get_settings,
4557 .set_settings = nv_set_settings,
4558 .get_regs_len = nv_get_regs_len,
4559 .get_regs = nv_get_regs,
4560 .nway_reset = nv_nway_reset,
4561 .get_perm_addr = ethtool_op_get_perm_addr,
4562 .get_tso = ethtool_op_get_tso,
4563 .set_tso = nv_set_tso,
4564 .get_ringparam = nv_get_ringparam,
4565 .set_ringparam = nv_set_ringparam,
4566 .get_pauseparam = nv_get_pauseparam,
4567 .set_pauseparam = nv_set_pauseparam,
4568 .get_rx_csum = nv_get_rx_csum,
4569 .set_rx_csum = nv_set_rx_csum,
4570 .get_tx_csum = ethtool_op_get_tx_csum,
4571 .set_tx_csum = nv_set_tx_csum,
4572 .get_sg = ethtool_op_get_sg,
4573 .set_sg = nv_set_sg,
4574 .get_strings = nv_get_strings,
4575 .get_stats_count = nv_get_stats_count,
4576 .get_ethtool_stats = nv_get_ethtool_stats,
4577 .self_test_count = nv_self_test_count,
4578 .self_test = nv_self_test,
4579 };
4580
4581 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4582 {
4583 struct fe_priv *np = get_nvpriv(dev);
4584
4585 spin_lock_irq(&np->lock);
4586
4587 /* save vlan group */
4588 np->vlangrp = grp;
4589
4590 if (grp) {
4591 /* enable vlan on MAC */
4592 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4593 } else {
4594 /* disable vlan on MAC */
4595 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4596 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4597 }
4598
4599 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4600
4601 spin_unlock_irq(&np->lock);
4602 };
4603
4604 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4605 {
4606 /* nothing to do */
4607 };
4608
4609 /* The mgmt unit and driver use a semaphore to access the phy during init */
4610 static int nv_mgmt_acquire_sema(struct net_device *dev)
4611 {
4612 u8 __iomem *base = get_hwbase(dev);
4613 int i;
4614 u32 tx_ctrl, mgmt_sema;
4615
4616 for (i = 0; i < 10; i++) {
4617 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4618 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4619 break;
4620 msleep(500);
4621 }
4622
4623 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4624 return 0;
4625
4626 for (i = 0; i < 2; i++) {
4627 tx_ctrl = readl(base + NvRegTransmitterControl);
4628 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4629 writel(tx_ctrl, base + NvRegTransmitterControl);
4630
4631 /* verify that semaphore was acquired */
4632 tx_ctrl = readl(base + NvRegTransmitterControl);
4633 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4634 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4635 return 1;
4636 else
4637 udelay(50);
4638 }
4639
4640 return 0;
4641 }
4642
4643 static int nv_open(struct net_device *dev)
4644 {
4645 struct fe_priv *np = netdev_priv(dev);
4646 u8 __iomem *base = get_hwbase(dev);
4647 int ret = 1;
4648 int oom, i;
4649
4650 dprintk(KERN_DEBUG "nv_open: begin\n");
4651
4652 /* erase previous misconfiguration */
4653 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4654 nv_mac_reset(dev);
4655 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4656 writel(0, base + NvRegMulticastAddrB);
4657 writel(0, base + NvRegMulticastMaskA);
4658 writel(0, base + NvRegMulticastMaskB);
4659 writel(0, base + NvRegPacketFilterFlags);
4660
4661 writel(0, base + NvRegTransmitterControl);
4662 writel(0, base + NvRegReceiverControl);
4663
4664 writel(0, base + NvRegAdapterControl);
4665
4666 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4667 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
4668
4669 /* initialize descriptor rings */
4670 set_bufsize(dev);
4671 oom = nv_init_ring(dev);
4672
4673 writel(0, base + NvRegLinkSpeed);
4674 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4675 nv_txrx_reset(dev);
4676 writel(0, base + NvRegUnknownSetupReg6);
4677
4678 np->in_shutdown = 0;
4679
4680 /* give hw rings */
4681 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4682 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4683 base + NvRegRingSizes);
4684
4685 writel(np->linkspeed, base + NvRegLinkSpeed);
4686 if (np->desc_ver == DESC_VER_1)
4687 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4688 else
4689 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4690 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4691 writel(np->vlanctl_bits, base + NvRegVlanControl);
4692 pci_push(base);
4693 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4694 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4695 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4696 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4697
4698 writel(0, base + NvRegMIIMask);
4699 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4700 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4701
4702 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4703 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4704 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4705 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4706
4707 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4708 get_random_bytes(&i, sizeof(i));
4709 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4710 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4711 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4712 if (poll_interval == -1) {
4713 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4714 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4715 else
4716 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4717 }
4718 else
4719 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4720 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4721 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4722 base + NvRegAdapterControl);
4723 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4724 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4725 if (np->wolenabled)
4726 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4727
4728 i = readl(base + NvRegPowerState);
4729 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4730 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4731
4732 pci_push(base);
4733 udelay(10);
4734 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4735
4736 nv_disable_hw_interrupts(dev, np->irqmask);
4737 pci_push(base);
4738 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4739 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4740 pci_push(base);
4741
4742 if (nv_request_irq(dev, 0)) {
4743 goto out_drain;
4744 }
4745
4746 /* ask for interrupts */
4747 nv_enable_hw_interrupts(dev, np->irqmask);
4748
4749 spin_lock_irq(&np->lock);
4750 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4751 writel(0, base + NvRegMulticastAddrB);
4752 writel(0, base + NvRegMulticastMaskA);
4753 writel(0, base + NvRegMulticastMaskB);
4754 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4755 /* One manual link speed update: Interrupts are enabled, future link
4756 * speed changes cause interrupts and are handled by nv_link_irq().
4757 */
4758 {
4759 u32 miistat;
4760 miistat = readl(base + NvRegMIIStatus);
4761 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4762 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4763 }
4764 /* set linkspeed to invalid value, thus force nv_update_linkspeed
4765 * to init hw */
4766 np->linkspeed = 0;
4767 ret = nv_update_linkspeed(dev);
4768 nv_start_rx(dev);
4769 nv_start_tx(dev);
4770 netif_start_queue(dev);
4771 netif_poll_enable(dev);
4772
4773 if (ret) {
4774 netif_carrier_on(dev);
4775 } else {
4776 printk("%s: no link during initialization.\n", dev->name);
4777 netif_carrier_off(dev);
4778 }
4779 if (oom)
4780 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4781
4782 /* start statistics timer */
4783 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
4784 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4785
4786 spin_unlock_irq(&np->lock);
4787
4788 return 0;
4789 out_drain:
4790 drain_ring(dev);
4791 return ret;
4792 }
4793
4794 static int nv_close(struct net_device *dev)
4795 {
4796 struct fe_priv *np = netdev_priv(dev);
4797 u8 __iomem *base;
4798
4799 spin_lock_irq(&np->lock);
4800 np->in_shutdown = 1;
4801 spin_unlock_irq(&np->lock);
4802 netif_poll_disable(dev);
4803 synchronize_irq(dev->irq);
4804
4805 del_timer_sync(&np->oom_kick);
4806 del_timer_sync(&np->nic_poll);
4807 del_timer_sync(&np->stats_poll);
4808
4809 netif_stop_queue(dev);
4810 spin_lock_irq(&np->lock);
4811 nv_stop_tx(dev);
4812 nv_stop_rx(dev);
4813 nv_txrx_reset(dev);
4814
4815 /* disable interrupts on the nic or we will lock up */
4816 base = get_hwbase(dev);
4817 nv_disable_hw_interrupts(dev, np->irqmask);
4818 pci_push(base);
4819 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4820
4821 spin_unlock_irq(&np->lock);
4822
4823 nv_free_irq(dev);
4824
4825 drain_ring(dev);
4826
4827 if (np->wolenabled)
4828 nv_start_rx(dev);
4829
4830 /* FIXME: power down nic */
4831
4832 return 0;
4833 }
4834
4835 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4836 {
4837 struct net_device *dev;
4838 struct fe_priv *np;
4839 unsigned long addr;
4840 u8 __iomem *base;
4841 int err, i;
4842 u32 powerstate, txreg;
4843 u32 phystate_orig = 0, phystate;
4844 int phyinitialized = 0;
4845
4846 dev = alloc_etherdev(sizeof(struct fe_priv));
4847 err = -ENOMEM;
4848 if (!dev)
4849 goto out;
4850
4851 np = netdev_priv(dev);
4852 np->pci_dev = pci_dev;
4853 spin_lock_init(&np->lock);
4854 SET_MODULE_OWNER(dev);
4855 SET_NETDEV_DEV(dev, &pci_dev->dev);
4856
4857 init_timer(&np->oom_kick);
4858 np->oom_kick.data = (unsigned long) dev;
4859 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
4860 init_timer(&np->nic_poll);
4861 np->nic_poll.data = (unsigned long) dev;
4862 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
4863 init_timer(&np->stats_poll);
4864 np->stats_poll.data = (unsigned long) dev;
4865 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
4866
4867 err = pci_enable_device(pci_dev);
4868 if (err) {
4869 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4870 err, pci_name(pci_dev));
4871 goto out_free;
4872 }
4873
4874 pci_set_master(pci_dev);
4875
4876 err = pci_request_regions(pci_dev, DRV_NAME);
4877 if (err < 0)
4878 goto out_disable;
4879
4880 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
4881 np->register_size = NV_PCI_REGSZ_VER3;
4882 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
4883 np->register_size = NV_PCI_REGSZ_VER2;
4884 else
4885 np->register_size = NV_PCI_REGSZ_VER1;
4886
4887 err = -EINVAL;
4888 addr = 0;
4889 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4890 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4891 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4892 pci_resource_len(pci_dev, i),
4893 pci_resource_flags(pci_dev, i));
4894 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4895 pci_resource_len(pci_dev, i) >= np->register_size) {
4896 addr = pci_resource_start(pci_dev, i);
4897 break;
4898 }
4899 }
4900 if (i == DEVICE_COUNT_RESOURCE) {
4901 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4902 pci_name(pci_dev));
4903 goto out_relreg;
4904 }
4905
4906 /* copy of driver data */
4907 np->driver_data = id->driver_data;
4908
4909 /* handle different descriptor versions */
4910 if (id->driver_data & DEV_HAS_HIGH_DMA) {
4911 /* packet format 3: supports 40-bit addressing */
4912 np->desc_ver = DESC_VER_3;
4913 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4914 if (dma_64bit) {
4915 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4916 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4917 pci_name(pci_dev));
4918 } else {
4919 dev->features |= NETIF_F_HIGHDMA;
4920 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4921 }
4922 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4923 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4924 pci_name(pci_dev));
4925 }
4926 }
4927 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4928 /* packet format 2: supports jumbo frames */
4929 np->desc_ver = DESC_VER_2;
4930 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4931 } else {
4932 /* original packet format */
4933 np->desc_ver = DESC_VER_1;
4934 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4935 }
4936
4937 np->pkt_limit = NV_PKTLIMIT_1;
4938 if (id->driver_data & DEV_HAS_LARGEDESC)
4939 np->pkt_limit = NV_PKTLIMIT_2;
4940
4941 if (id->driver_data & DEV_HAS_CHECKSUM) {
4942 np->rx_csum = 1;
4943 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4944 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4945 dev->features |= NETIF_F_TSO;
4946 }
4947
4948 np->vlanctl_bits = 0;
4949 if (id->driver_data & DEV_HAS_VLAN) {
4950 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4951 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4952 dev->vlan_rx_register = nv_vlan_rx_register;
4953 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4954 }
4955
4956 np->msi_flags = 0;
4957 if ((id->driver_data & DEV_HAS_MSI) && msi) {
4958 np->msi_flags |= NV_MSI_CAPABLE;
4959 }
4960 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4961 np->msi_flags |= NV_MSI_X_CAPABLE;
4962 }
4963
4964 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4965 if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4966 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4967 }
4968
4969
4970 err = -ENOMEM;
4971 np->base = ioremap(addr, np->register_size);
4972 if (!np->base)
4973 goto out_relreg;
4974 dev->base_addr = (unsigned long)np->base;
4975
4976 dev->irq = pci_dev->irq;
4977
4978 np->rx_ring_size = RX_RING_DEFAULT;
4979 np->tx_ring_size = TX_RING_DEFAULT;
4980
4981 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4982 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4983 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4984 &np->ring_addr);
4985 if (!np->rx_ring.orig)
4986 goto out_unmap;
4987 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4988 } else {
4989 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4990 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4991 &np->ring_addr);
4992 if (!np->rx_ring.ex)
4993 goto out_unmap;
4994 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4995 }
4996 np->rx_skb = kmalloc(sizeof(struct nv_skb_map) * np->rx_ring_size, GFP_KERNEL);
4997 np->tx_skb = kmalloc(sizeof(struct nv_skb_map) * np->tx_ring_size, GFP_KERNEL);
4998 if (!np->rx_skb || !np->tx_skb)
4999 goto out_freering;
5000 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
5001 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
5002
5003 dev->open = nv_open;
5004 dev->stop = nv_close;
5005 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
5006 dev->hard_start_xmit = nv_start_xmit;
5007 else
5008 dev->hard_start_xmit = nv_start_xmit_optimized;
5009 dev->get_stats = nv_get_stats;
5010 dev->change_mtu = nv_change_mtu;
5011 dev->set_mac_address = nv_set_mac_address;
5012 dev->set_multicast_list = nv_set_multicast;
5013 #ifdef CONFIG_NET_POLL_CONTROLLER
5014 dev->poll_controller = nv_poll_controller;
5015 #endif
5016 dev->weight = RX_WORK_PER_LOOP;
5017 #ifdef CONFIG_FORCEDETH_NAPI
5018 dev->poll = nv_napi_poll;
5019 #endif
5020 SET_ETHTOOL_OPS(dev, &ops);
5021 dev->tx_timeout = nv_tx_timeout;
5022 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5023
5024 pci_set_drvdata(pci_dev, dev);
5025
5026 /* read the mac address */
5027 base = get_hwbase(dev);
5028 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5029 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5030
5031 /* check the workaround bit for correct mac address order */
5032 txreg = readl(base + NvRegTransmitPoll);
5033 if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5034 /* mac address is already in correct order */
5035 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5036 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5037 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5038 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5039 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5040 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5041 } else {
5042 /* need to reverse mac address to correct order */
5043 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5044 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5045 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5046 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5047 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5048 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5049 /* set permanent address to be correct aswell */
5050 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
5051 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
5052 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
5053 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5054 }
5055 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5056
5057 if (!is_valid_ether_addr(dev->perm_addr)) {
5058 /*
5059 * Bad mac address. At least one bios sets the mac address
5060 * to 01:23:45:67:89:ab
5061 */
5062 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
5063 pci_name(pci_dev),
5064 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
5065 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
5066 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
5067 dev->dev_addr[0] = 0x00;
5068 dev->dev_addr[1] = 0x00;
5069 dev->dev_addr[2] = 0x6c;
5070 get_random_bytes(&dev->dev_addr[3], 3);
5071 }
5072
5073 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
5074 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
5075 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
5076
5077 /* set mac address */
5078 nv_copy_mac_to_hw(dev);
5079
5080 /* disable WOL */
5081 writel(0, base + NvRegWakeUpFlags);
5082 np->wolenabled = 0;
5083
5084 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5085 u8 revision_id;
5086 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
5087
5088 /* take phy and nic out of low power mode */
5089 powerstate = readl(base + NvRegPowerState2);
5090 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5091 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5092 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5093 revision_id >= 0xA3)
5094 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5095 writel(powerstate, base + NvRegPowerState2);
5096 }
5097
5098 if (np->desc_ver == DESC_VER_1) {
5099 np->tx_flags = NV_TX_VALID;
5100 } else {
5101 np->tx_flags = NV_TX2_VALID;
5102 }
5103 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5104 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5105 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5106 np->msi_flags |= 0x0003;
5107 } else {
5108 np->irqmask = NVREG_IRQMASK_CPU;
5109 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5110 np->msi_flags |= 0x0001;
5111 }
5112
5113 if (id->driver_data & DEV_NEED_TIMERIRQ)
5114 np->irqmask |= NVREG_IRQ_TIMER;
5115 if (id->driver_data & DEV_NEED_LINKTIMER) {
5116 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5117 np->need_linktimer = 1;
5118 np->link_timeout = jiffies + LINK_TIMEOUT;
5119 } else {
5120 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5121 np->need_linktimer = 0;
5122 }
5123
5124 /* clear phy state and temporarily halt phy interrupts */
5125 writel(0, base + NvRegMIIMask);
5126 phystate = readl(base + NvRegAdapterControl);
5127 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5128 phystate_orig = 1;
5129 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5130 writel(phystate, base + NvRegAdapterControl);
5131 }
5132 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
5133
5134 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5135 /* management unit running on the mac? */
5136 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5137 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5138 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5139 for (i = 0; i < 5000; i++) {
5140 msleep(1);
5141 if (nv_mgmt_acquire_sema(dev)) {
5142 /* management unit setup the phy already? */
5143 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5144 NVREG_XMITCTL_SYNC_PHY_INIT) {
5145 /* phy is inited by mgmt unit */
5146 phyinitialized = 1;
5147 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5148 } else {
5149 /* we need to init the phy */
5150 }
5151 break;
5152 }
5153 }
5154 }
5155 }
5156
5157 /* find a suitable phy */
5158 for (i = 1; i <= 32; i++) {
5159 int id1, id2;
5160 int phyaddr = i & 0x1F;
5161
5162 spin_lock_irq(&np->lock);
5163 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5164 spin_unlock_irq(&np->lock);
5165 if (id1 < 0 || id1 == 0xffff)
5166 continue;
5167 spin_lock_irq(&np->lock);
5168 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5169 spin_unlock_irq(&np->lock);
5170 if (id2 < 0 || id2 == 0xffff)
5171 continue;
5172
5173 np->phy_model = id2 & PHYID2_MODEL_MASK;
5174 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5175 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5176 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5177 pci_name(pci_dev), id1, id2, phyaddr);
5178 np->phyaddr = phyaddr;
5179 np->phy_oui = id1 | id2;
5180 break;
5181 }
5182 if (i == 33) {
5183 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
5184 pci_name(pci_dev));
5185 goto out_error;
5186 }
5187
5188 if (!phyinitialized) {
5189 /* reset it */
5190 phy_init(dev);
5191 } else {
5192 /* see if it is a gigabit phy */
5193 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5194 if (mii_status & PHY_GIGABIT) {
5195 np->gigabit = PHY_GIGABIT;
5196 }
5197 }
5198
5199 /* set default link speed settings */
5200 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5201 np->duplex = 0;
5202 np->autoneg = 1;
5203
5204 err = register_netdev(dev);
5205 if (err) {
5206 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
5207 goto out_error;
5208 }
5209 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
5210 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
5211 pci_name(pci_dev));
5212
5213 return 0;
5214
5215 out_error:
5216 if (phystate_orig)
5217 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5218 pci_set_drvdata(pci_dev, NULL);
5219 out_freering:
5220 free_rings(dev);
5221 out_unmap:
5222 iounmap(get_hwbase(dev));
5223 out_relreg:
5224 pci_release_regions(pci_dev);
5225 out_disable:
5226 pci_disable_device(pci_dev);
5227 out_free:
5228 free_netdev(dev);
5229 out:
5230 return err;
5231 }
5232
5233 static void __devexit nv_remove(struct pci_dev *pci_dev)
5234 {
5235 struct net_device *dev = pci_get_drvdata(pci_dev);
5236 struct fe_priv *np = netdev_priv(dev);
5237 u8 __iomem *base = get_hwbase(dev);
5238
5239 unregister_netdev(dev);
5240
5241 /* special op: write back the misordered MAC address - otherwise
5242 * the next nv_probe would see a wrong address.
5243 */
5244 writel(np->orig_mac[0], base + NvRegMacAddrA);
5245 writel(np->orig_mac[1], base + NvRegMacAddrB);
5246
5247 /* free all structures */
5248 free_rings(dev);
5249 iounmap(get_hwbase(dev));
5250 pci_release_regions(pci_dev);
5251 pci_disable_device(pci_dev);
5252 free_netdev(dev);
5253 pci_set_drvdata(pci_dev, NULL);
5254 }
5255
5256 #ifdef CONFIG_PM
5257 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5258 {
5259 struct net_device *dev = pci_get_drvdata(pdev);
5260 struct fe_priv *np = netdev_priv(dev);
5261
5262 if (!netif_running(dev))
5263 goto out;
5264
5265 netif_device_detach(dev);
5266
5267 // Gross.
5268 nv_close(dev);
5269
5270 pci_save_state(pdev);
5271 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5272 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5273 out:
5274 return 0;
5275 }
5276
5277 static int nv_resume(struct pci_dev *pdev)
5278 {
5279 struct net_device *dev = pci_get_drvdata(pdev);
5280 int rc = 0;
5281
5282 if (!netif_running(dev))
5283 goto out;
5284
5285 netif_device_attach(dev);
5286
5287 pci_set_power_state(pdev, PCI_D0);
5288 pci_restore_state(pdev);
5289 pci_enable_wake(pdev, PCI_D0, 0);
5290
5291 rc = nv_open(dev);
5292 out:
5293 return rc;
5294 }
5295 #else
5296 #define nv_suspend NULL
5297 #define nv_resume NULL
5298 #endif /* CONFIG_PM */
5299
5300 static struct pci_device_id pci_tbl[] = {
5301 { /* nForce Ethernet Controller */
5302 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
5303 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5304 },
5305 { /* nForce2 Ethernet Controller */
5306 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
5307 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5308 },
5309 { /* nForce3 Ethernet Controller */
5310 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
5311 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5312 },
5313 { /* nForce3 Ethernet Controller */
5314 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
5315 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5316 },
5317 { /* nForce3 Ethernet Controller */
5318 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
5319 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5320 },
5321 { /* nForce3 Ethernet Controller */
5322 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
5323 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5324 },
5325 { /* nForce3 Ethernet Controller */
5326 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
5327 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5328 },
5329 { /* CK804 Ethernet Controller */
5330 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
5331 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5332 },
5333 { /* CK804 Ethernet Controller */
5334 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
5335 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5336 },
5337 { /* MCP04 Ethernet Controller */
5338 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
5339 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5340 },
5341 { /* MCP04 Ethernet Controller */
5342 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
5343 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5344 },
5345 { /* MCP51 Ethernet Controller */
5346 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
5347 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5348 },
5349 { /* MCP51 Ethernet Controller */
5350 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
5351 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5352 },
5353 { /* MCP55 Ethernet Controller */
5354 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
5355 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5356 },
5357 { /* MCP55 Ethernet Controller */
5358 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
5359 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5360 },
5361 { /* MCP61 Ethernet Controller */
5362 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
5363 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5364 },
5365 { /* MCP61 Ethernet Controller */
5366 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
5367 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5368 },
5369 { /* MCP61 Ethernet Controller */
5370 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
5371 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5372 },
5373 { /* MCP61 Ethernet Controller */
5374 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
5375 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5376 },
5377 { /* MCP65 Ethernet Controller */
5378 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5379 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5380 },
5381 { /* MCP65 Ethernet Controller */
5382 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5383 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5384 },
5385 { /* MCP65 Ethernet Controller */
5386 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5387 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5388 },
5389 { /* MCP65 Ethernet Controller */
5390 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5391 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5392 },
5393 { /* MCP67 Ethernet Controller */
5394 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5395 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5396 },
5397 { /* MCP67 Ethernet Controller */
5398 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5399 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5400 },
5401 { /* MCP67 Ethernet Controller */
5402 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5403 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5404 },
5405 { /* MCP67 Ethernet Controller */
5406 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5407 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5408 },
5409 {0,},
5410 };
5411
5412 static struct pci_driver driver = {
5413 .name = "forcedeth",
5414 .id_table = pci_tbl,
5415 .probe = nv_probe,
5416 .remove = __devexit_p(nv_remove),
5417 .suspend = nv_suspend,
5418 .resume = nv_resume,
5419 };
5420
5421 static int __init init_nic(void)
5422 {
5423 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
5424 return pci_register_driver(&driver);
5425 }
5426
5427 static void __exit exit_nic(void)
5428 {
5429 pci_unregister_driver(&driver);
5430 }
5431
5432 module_param(max_interrupt_work, int, 0);
5433 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5434 module_param(optimization_mode, int, 0);
5435 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5436 module_param(poll_interval, int, 0);
5437 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5438 module_param(msi, int, 0);
5439 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5440 module_param(msix, int, 0);
5441 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5442 module_param(dma_64bit, int, 0);
5443 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5444
5445 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5446 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5447 MODULE_LICENSE("GPL");
5448
5449 MODULE_DEVICE_TABLE(pci, pci_tbl);
5450
5451 module_init(init_nic);
5452 module_exit(exit_nic);
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