drivers/net/fsl_pq_mdio.c

   1 /*
   2  * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
   3  * Provides Bus interface for MIIM regs
   4  *
   5  * Author: Andy Fleming <afleming@freescale.com>
   6  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
   7  *
   8  * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
   9  *
  10  * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  *
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/string.h>
  21 #include <linux/errno.h>
  22 #include <linux/unistd.h>
  23 #include <linux/slab.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/skbuff.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/crc32.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/of.h>
  38 #include <linux/of_mdio.h>
  39 #include <linux/of_platform.h>
  40
  41 #include <asm/io.h>
  42 #include <asm/irq.h>
  43 #include <asm/uaccess.h>
  44 #include <asm/ucc.h>
  45
  46 #include "gianfar.h"
  47 #include "fsl_pq_mdio.h"
  48
  49 /*
  50  * Write value to the PHY at mii_id at register regnum,
  51  * on the bus attached to the local interface, which may be different from the
  52  * generic mdio bus (tied to a single interface), waiting until the write is
  53  * done before returning. This is helpful in programming interfaces like
  54  * the TBI which control interfaces like onchip SERDES and are always tied to
  55  * the local mdio pins, which may not be the same as system mdio bus, used for
  56  * controlling the external PHYs, for example.
  57  */
  58 int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
  59                 int regnum, u16 value)
  60 {
  61         /* Set the PHY address and the register address we want to write */
  62         out_be32(&regs->miimadd, (mii_id << 8) | regnum);
  63
  64         /* Write out the value we want */
  65         out_be32(&regs->miimcon, value);
  66
  67         /* Wait for the transaction to finish */
  68         while (in_be32(&regs->miimind) & MIIMIND_BUSY)
  69                 cpu_relax();
  70
  71         return 0;
  72 }
  73
  74 /*
  75  * Read the bus for PHY at addr mii_id, register regnum, and
  76  * return the value.  Clears miimcom first.  All PHY operation
  77  * done on the bus attached to the local interface,
  78  * which may be different from the generic mdio bus
  79  * This is helpful in programming interfaces like
  80  * the TBI which, in turn, control interfaces like onchip SERDES
  81  * and are always tied to the local mdio pins, which may not be the
  82  * same as system mdio bus, used for controlling the external PHYs, for eg.
  83  */
  84 int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
  85                 int mii_id, int regnum)
  86 {
  87         u16 value;
  88
  89         /* Set the PHY address and the register address we want to read */
  90         out_be32(&regs->miimadd, (mii_id << 8) | regnum);
  91
  92         /* Clear miimcom, and then initiate a read */
  93         out_be32(&regs->miimcom, 0);
  94         out_be32(&regs->miimcom, MII_READ_COMMAND);
  95
  96         /* Wait for the transaction to finish */
  97         while (in_be32(&regs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
  98                 cpu_relax();
  99
 100         /* Grab the value of the register from miimstat */
 101         value = in_be32(&regs->miimstat);
 102
 103         return value;
 104 }
 105
 106 static struct fsl_pq_mdio __iomem *fsl_pq_mdio_get_regs(struct mii_bus *bus)
 107 {
 108         return (void __iomem __force *)bus->priv;
 109 }
 110
 111 /*
 112  * Write value to the PHY at mii_id at register regnum,
 113  * on the bus, waiting until the write is done before returning.
 114  */
 115 int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
 116 {
 117         struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
 118
 119         /* Write to the local MII regs */
 120         return(fsl_pq_local_mdio_write(regs, mii_id, regnum, value));
 121 }
 122
 123 /*
 124  * Read the bus for PHY at addr mii_id, register regnum, and
 125  * return the value.  Clears miimcom first.
 126  */
 127 int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 128 {
 129         struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
 130
 131         /* Read the local MII regs */
 132         return(fsl_pq_local_mdio_read(regs, mii_id, regnum));
 133 }
 134
 135 /* Reset the MIIM registers, and wait for the bus to free */
 136 static int fsl_pq_mdio_reset(struct mii_bus *bus)
 137 {
 138         struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
 139         int timeout = PHY_INIT_TIMEOUT;
 140
 141         mutex_lock(&bus->mdio_lock);
 142
 143         /* Reset the management interface */
 144         out_be32(&regs->miimcfg, MIIMCFG_RESET);
 145
 146         /* Setup the MII Mgmt clock speed */
 147         out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
 148
 149         /* Wait until the bus is free */
 150         while ((in_be32(&regs->miimind) & MIIMIND_BUSY) && timeout--)
 151                 cpu_relax();
 152
 153         mutex_unlock(&bus->mdio_lock);
 154
 155         if (timeout < 0) {
 156                 printk(KERN_ERR "%s: The MII Bus is stuck!\n",
 157                                 bus->name);
 158                 return -EBUSY;
 159         }
 160
 161         return 0;
 162 }
 163
 164 void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
 165 {
 166         const u32 *addr;
 167         u64 taddr = OF_BAD_ADDR;
 168
 169         addr = of_get_address(np, 0, NULL, NULL);
 170         if (addr)
 171                 taddr = of_translate_address(np, addr);
 172
 173         snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
 174                 (unsigned long long)taddr);
 175 }
 176 EXPORT_SYMBOL_GPL(fsl_pq_mdio_bus_name);
 177
 178 /* Scan the bus in reverse, looking for an empty spot */
 179 static int fsl_pq_mdio_find_free(struct mii_bus *new_bus)
 180 {
 181         int i;
 182
 183         for (i = PHY_MAX_ADDR; i > 0; i--) {
 184                 u32 phy_id;
 185
 186                 if (get_phy_id(new_bus, i, &phy_id))
 187                         return -1;
 188
 189                 if (phy_id == 0xffffffff)
 190                         break;
 191         }
 192
 193         return i;
 194 }
 195
 196
 197 #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
 198 static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs, struct device_node *np)
 199 {
 200         struct gfar __iomem *enet_regs;
 201         u32 __iomem *ioremap_tbipa;
 202         u64 addr, size;
 203
 204         /*
 205          * This is mildly evil, but so is our hardware for doing this.
 206          * Also, we have to cast back to struct gfar because of
 207          * definition weirdness done in gianfar.h.
 208          */
 209         if(of_device_is_compatible(np, "fsl,gianfar-mdio") ||
 210                 of_device_is_compatible(np, "fsl,gianfar-tbi") ||
 211                 of_device_is_compatible(np, "gianfar")) {
 212                 enet_regs = (struct gfar __iomem *)regs;
 213                 return &enet_regs->tbipa;
 214         } else if (of_device_is_compatible(np, "fsl,etsec2-mdio") ||
 215                         of_device_is_compatible(np, "fsl,etsec2-tbi")) {
 216                 addr = of_translate_address(np, of_get_address(np, 1, &size, NULL));
 217                 ioremap_tbipa = ioremap(addr, size);
 218                 return ioremap_tbipa;
 219         } else
 220                 return NULL;
 221 }
 222 #endif
 223
 224
 225 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
 226 static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
 227 {
 228         struct device_node *np = NULL;
 229         int err = 0;
 230
 231         for_each_compatible_node(np, NULL, "ucc_geth") {
 232                 struct resource tempres;
 233
 234                 err = of_address_to_resource(np, 0, &tempres);
 235                 if (err)
 236                         continue;
 237
 238                 /* if our mdio regs fall within this UCC regs range */
 239                 if ((start >= tempres.start) && (end <= tempres.end)) {
 240                         /* Find the id of the UCC */
 241                         const u32 *id;
 242
 243                         id = of_get_property(np, "cell-index", NULL);
 244                         if (!id) {
 245                                 id = of_get_property(np, "device-id", NULL);
 246                                 if (!id)
 247                                         continue;
 248                         }
 249
 250                         *ucc_id = *id;
 251
 252                         return 0;
 253                 }
 254         }
 255
 256         if (err)
 257                 return err;
 258         else
 259                 return -EINVAL;
 260 }
 261 #endif
 262
 263
 264 static int fsl_pq_mdio_probe(struct of_device *ofdev,
 265                 const struct of_device_id *match)
 266 {
 267         struct device_node *np = ofdev->node;
 268         struct device_node *tbi;
 269         struct fsl_pq_mdio __iomem *regs = NULL;
 270         void __iomem *map;
 271         u32 __iomem *tbipa;
 272         struct mii_bus *new_bus;
 273         int tbiaddr = -1;
 274         u64 addr = 0, size = 0;
 275         int err = 0;
 276
 277         new_bus = mdiobus_alloc();
 278         if (NULL == new_bus)
 279                 return -ENOMEM;
 280
 281         new_bus->name = "Freescale PowerQUICC MII Bus",
 282         new_bus->read = &fsl_pq_mdio_read,
 283         new_bus->write = &fsl_pq_mdio_write,
 284         new_bus->reset = &fsl_pq_mdio_reset,
 285         fsl_pq_mdio_bus_name(new_bus->id, np);
 286
 287         /* Set the PHY base address */
 288         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
 289         map = ioremap(addr, size);
 290         if (!map) {
 291                 err = -ENOMEM;
 292                 goto err_free_bus;
 293         }
 294
 295         if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
 296                         of_device_is_compatible(np, "fsl,gianfar-tbi") ||
 297                         of_device_is_compatible(np, "fsl,ucc-mdio") ||
 298                         of_device_is_compatible(np, "ucc_geth_phy"))
 299                 map -= offsetof(struct fsl_pq_mdio, miimcfg);
 300         regs = map;
 301
 302         new_bus->priv = (void __force *)regs;
 303
 304         new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
 305
 306         if (NULL == new_bus->irq) {
 307                 err = -ENOMEM;
 308                 goto err_unmap_regs;
 309         }
 310
 311         new_bus->parent = &ofdev->dev;
 312         dev_set_drvdata(&ofdev->dev, new_bus);
 313
 314         if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
 315                         of_device_is_compatible(np, "fsl,gianfar-tbi") ||
 316                         of_device_is_compatible(np, "fsl,etsec2-mdio") ||
 317                         of_device_is_compatible(np, "fsl,etsec2-tbi") ||
 318                         of_device_is_compatible(np, "gianfar")) {
 319 #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
 320                 tbipa = get_gfar_tbipa(regs, np);
 321                 if (!tbipa) {
 322                         err = -EINVAL;
 323                         goto err_free_irqs;
 324                 }
 325 #else
 326                 err = -ENODEV;
 327                 goto err_free_irqs;
 328 #endif
 329         } else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
 330                         of_device_is_compatible(np, "ucc_geth_phy")) {
 331 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
 332                 u32 id;
 333                 static u32 mii_mng_master;
 334
 335                 tbipa = &regs->utbipar;
 336
 337                 if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
 338                         goto err_free_irqs;
 339
 340                 if (!mii_mng_master) {
 341                         mii_mng_master = id;
 342                         ucc_set_qe_mux_mii_mng(id - 1);
 343                 }
 344 #else
 345                 err = -ENODEV;
 346                 goto err_free_irqs;
 347 #endif
 348         } else {
 349                 err = -ENODEV;
 350                 goto err_free_irqs;
 351         }
 352
 353         for_each_child_of_node(np, tbi) {
 354                 if (!strncmp(tbi->type, "tbi-phy", 8))
 355                         break;
 356         }
 357
 358         if (tbi) {
 359                 const u32 *prop = of_get_property(tbi, "reg", NULL);
 360
 361                 if (prop)
 362                         tbiaddr = *prop;
 363         }
 364
 365         if (tbiaddr == -1) {
 366                 out_be32(tbipa, 0);
 367
 368                 tbiaddr = fsl_pq_mdio_find_free(new_bus);
 369         }
 370
 371         /*
 372          * We define TBIPA at 0 to be illegal, opting to fail for boards that
 373          * have PHYs at 1-31, rather than change tbipa and rescan.
 374          */
 375         if (tbiaddr == 0) {
 376                 err = -EBUSY;
 377
 378                 goto err_free_irqs;
 379         }
 380
 381         out_be32(tbipa, tbiaddr);
 382
 383         err = of_mdiobus_register(new_bus, np);
 384         if (err) {
 385                 printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
 386                                 new_bus->name);
 387                 goto err_free_irqs;
 388         }
 389
 390         return 0;
 391
 392 err_free_irqs:
 393         kfree(new_bus->irq);
 394 err_unmap_regs:
 395         iounmap(regs);
 396 err_free_bus:
 397         kfree(new_bus);
 398
 399         return err;
 400 }
 401
 402
 403 static int fsl_pq_mdio_remove(struct of_device *ofdev)
 404 {
 405         struct device *device = &ofdev->dev;
 406         struct mii_bus *bus = dev_get_drvdata(device);
 407
 408         mdiobus_unregister(bus);
 409
 410         dev_set_drvdata(device, NULL);
 411
 412         iounmap(fsl_pq_mdio_get_regs(bus));
 413         bus->priv = NULL;
 414         mdiobus_free(bus);
 415
 416         return 0;
 417 }
 418
 419 static struct of_device_id fsl_pq_mdio_match[] = {
 420         {
 421                 .type = "mdio",
 422                 .compatible = "ucc_geth_phy",
 423         },
 424         {
 425                 .type = "mdio",
 426                 .compatible = "gianfar",
 427         },
 428         {
 429                 .compatible = "fsl,ucc-mdio",
 430         },
 431         {
 432                 .compatible = "fsl,gianfar-tbi",
 433         },
 434         {
 435                 .compatible = "fsl,gianfar-mdio",
 436         },
 437         {
 438                 .compatible = "fsl,etsec2-tbi",
 439         },
 440         {
 441                 .compatible = "fsl,etsec2-mdio",
 442         },
 443         {},
 444 };
 445 MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
 446
 447 static struct of_platform_driver fsl_pq_mdio_driver = {
 448         .name = "fsl-pq_mdio",
 449         .probe = fsl_pq_mdio_probe,
 450         .remove = fsl_pq_mdio_remove,
 451         .match_table = fsl_pq_mdio_match,
 452 };
 453
 454 int __init fsl_pq_mdio_init(void)
 455 {
 456         return of_register_platform_driver(&fsl_pq_mdio_driver);
 457 }
 458 module_init(fsl_pq_mdio_init);
 459
 460 void fsl_pq_mdio_exit(void)
 461 {
 462         of_unregister_platform_driver(&fsl_pq_mdio_driver);
 463 }
 464 module_exit(fsl_pq_mdio_exit);
 465 MODULE_LICENSE("GPL");