2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
87 #include <asm/uaccess.h>
88 #include <linux/module.h>
89 #include <linux/dma-mapping.h>
90 #include <linux/crc32.h>
91 #include <linux/mii.h>
92 #include <linux/phy.h>
93 #include <linux/phy_fixed.h>
97 #include "fsl_pq_mdio.h"
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
103 const char gfar_driver_name
[] = "Gianfar Ethernet";
104 const char gfar_driver_version
[] = "1.3";
106 static int gfar_enet_open(struct net_device
*dev
);
107 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
108 static void gfar_reset_task(struct work_struct
*work
);
109 static void gfar_timeout(struct net_device
*dev
);
110 static int gfar_close(struct net_device
*dev
);
111 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
112 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
113 struct sk_buff
*skb
);
114 static int gfar_set_mac_address(struct net_device
*dev
);
115 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
116 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
117 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
118 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
119 static void adjust_link(struct net_device
*dev
);
120 static void init_registers(struct net_device
*dev
);
121 static int init_phy(struct net_device
*dev
);
122 static int gfar_probe(struct of_device
*ofdev
,
123 const struct of_device_id
*match
);
124 static int gfar_remove(struct of_device
*ofdev
);
125 static void free_skb_resources(struct gfar_private
*priv
);
126 static void gfar_set_multi(struct net_device
*dev
);
127 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
128 static void gfar_configure_serdes(struct net_device
*dev
);
129 static int gfar_poll(struct napi_struct
*napi
, int budget
);
130 #ifdef CONFIG_NET_POLL_CONTROLLER
131 static void gfar_netpoll(struct net_device
*dev
);
133 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
134 static int gfar_clean_tx_ring(struct net_device
*dev
);
135 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
137 static void gfar_vlan_rx_register(struct net_device
*netdev
,
138 struct vlan_group
*grp
);
139 void gfar_halt(struct net_device
*dev
);
140 static void gfar_halt_nodisable(struct net_device
*dev
);
141 void gfar_start(struct net_device
*dev
);
142 static void gfar_clear_exact_match(struct net_device
*dev
);
143 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
144 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 static const struct net_device_ops gfar_netdev_ops
= {
151 .ndo_open
= gfar_enet_open
,
152 .ndo_start_xmit
= gfar_start_xmit
,
153 .ndo_stop
= gfar_close
,
154 .ndo_change_mtu
= gfar_change_mtu
,
155 .ndo_set_multicast_list
= gfar_set_multi
,
156 .ndo_tx_timeout
= gfar_timeout
,
157 .ndo_do_ioctl
= gfar_ioctl
,
158 .ndo_vlan_rx_register
= gfar_vlan_rx_register
,
159 .ndo_set_mac_address
= eth_mac_addr
,
160 .ndo_validate_addr
= eth_validate_addr
,
161 #ifdef CONFIG_NET_POLL_CONTROLLER
162 .ndo_poll_controller
= gfar_netpoll
,
166 /* Returns 1 if incoming frames use an FCB */
167 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
169 return priv
->vlgrp
|| priv
->rx_csum_enable
;
172 static int gfar_of_init(struct net_device
*dev
)
176 const void *mac_addr
;
179 struct gfar_private
*priv
= netdev_priv(dev
);
180 struct device_node
*np
= priv
->node
;
182 const u32
*stash_len
;
183 const u32
*stash_idx
;
185 if (!np
|| !of_device_is_available(np
))
188 /* get a pointer to the register memory */
189 addr
= of_translate_address(np
, of_get_address(np
, 0, &size
, NULL
));
190 priv
->regs
= ioremap(addr
, size
);
192 if (priv
->regs
== NULL
)
195 priv
->interruptTransmit
= irq_of_parse_and_map(np
, 0);
197 model
= of_get_property(np
, "model", NULL
);
199 /* If we aren't the FEC we have multiple interrupts */
200 if (model
&& strcasecmp(model
, "FEC")) {
201 priv
->interruptReceive
= irq_of_parse_and_map(np
, 1);
203 priv
->interruptError
= irq_of_parse_and_map(np
, 2);
205 if (priv
->interruptTransmit
< 0 ||
206 priv
->interruptReceive
< 0 ||
207 priv
->interruptError
< 0) {
213 stash
= of_get_property(np
, "bd-stash", NULL
);
216 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BD_STASHING
;
217 priv
->bd_stash_en
= 1;
220 stash_len
= of_get_property(np
, "rx-stash-len", NULL
);
223 priv
->rx_stash_size
= *stash_len
;
225 stash_idx
= of_get_property(np
, "rx-stash-idx", NULL
);
228 priv
->rx_stash_index
= *stash_idx
;
230 if (stash_len
|| stash_idx
)
231 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BUF_STASHING
;
233 mac_addr
= of_get_mac_address(np
);
235 memcpy(dev
->dev_addr
, mac_addr
, MAC_ADDR_LEN
);
237 if (model
&& !strcasecmp(model
, "TSEC"))
239 FSL_GIANFAR_DEV_HAS_GIGABIT
|
240 FSL_GIANFAR_DEV_HAS_COALESCE
|
241 FSL_GIANFAR_DEV_HAS_RMON
|
242 FSL_GIANFAR_DEV_HAS_MULTI_INTR
;
243 if (model
&& !strcasecmp(model
, "eTSEC"))
245 FSL_GIANFAR_DEV_HAS_GIGABIT
|
246 FSL_GIANFAR_DEV_HAS_COALESCE
|
247 FSL_GIANFAR_DEV_HAS_RMON
|
248 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
249 FSL_GIANFAR_DEV_HAS_PADDING
|
250 FSL_GIANFAR_DEV_HAS_CSUM
|
251 FSL_GIANFAR_DEV_HAS_VLAN
|
252 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
|
253 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
;
255 ctype
= of_get_property(np
, "phy-connection-type", NULL
);
257 /* We only care about rgmii-id. The rest are autodetected */
258 if (ctype
&& !strcmp(ctype
, "rgmii-id"))
259 priv
->interface
= PHY_INTERFACE_MODE_RGMII_ID
;
261 priv
->interface
= PHY_INTERFACE_MODE_MII
;
263 if (of_get_property(np
, "fsl,magic-packet", NULL
))
264 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
;
266 priv
->phy_node
= of_parse_phandle(np
, "phy-handle", 0);
267 if (!priv
->phy_node
) {
270 fixed_link
= (u32
*)of_get_property(np
, "fixed-link", NULL
);
277 /* Find the TBI PHY. If it's not there, we don't support SGMII */
278 priv
->tbi_node
= of_parse_phandle(np
, "tbi-handle", 0);
287 /* Ioctl MII Interface */
288 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
290 struct gfar_private
*priv
= netdev_priv(dev
);
292 if (!netif_running(dev
))
298 return phy_mii_ioctl(priv
->phydev
, if_mii(rq
), cmd
);
301 /* Set up the ethernet device structure, private data,
302 * and anything else we need before we start */
303 static int gfar_probe(struct of_device
*ofdev
,
304 const struct of_device_id
*match
)
307 struct net_device
*dev
= NULL
;
308 struct gfar_private
*priv
= NULL
;
309 DECLARE_MAC_BUF(mac
);
313 /* Create an ethernet device instance */
314 dev
= alloc_etherdev(sizeof (*priv
));
319 priv
= netdev_priv(dev
);
322 priv
->node
= ofdev
->node
;
323 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
325 err
= gfar_of_init(dev
);
330 spin_lock_init(&priv
->txlock
);
331 spin_lock_init(&priv
->rxlock
);
332 spin_lock_init(&priv
->bflock
);
333 INIT_WORK(&priv
->reset_task
, gfar_reset_task
);
335 dev_set_drvdata(&ofdev
->dev
, priv
);
337 /* Stop the DMA engine now, in case it was running before */
338 /* (The firmware could have used it, and left it running). */
341 /* Reset MAC layer */
342 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
344 /* We need to delay at least 3 TX clocks */
347 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
348 gfar_write(&priv
->regs
->maccfg1
, tempval
);
350 /* Initialize MACCFG2. */
351 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
353 /* Initialize ECNTRL */
354 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
356 /* Set the dev->base_addr to the gfar reg region */
357 dev
->base_addr
= (unsigned long) (priv
->regs
);
359 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
361 /* Fill in the dev structure */
362 dev
->watchdog_timeo
= TX_TIMEOUT
;
363 netif_napi_add(dev
, &priv
->napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
366 dev
->netdev_ops
= &gfar_netdev_ops
;
367 dev
->ethtool_ops
= &gfar_ethtool_ops
;
369 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
370 priv
->rx_csum_enable
= 1;
371 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_HIGHDMA
;
373 priv
->rx_csum_enable
= 0;
377 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
)
378 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
380 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
381 priv
->extended_hash
= 1;
382 priv
->hash_width
= 9;
384 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
385 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
386 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
387 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
388 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
389 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
390 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
391 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
392 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
393 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
394 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
395 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
396 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
397 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
398 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
399 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
402 priv
->extended_hash
= 0;
403 priv
->hash_width
= 8;
405 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
406 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
407 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
408 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
409 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
410 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
411 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
412 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
415 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
416 priv
->padding
= DEFAULT_PADDING
;
420 if (dev
->features
& NETIF_F_IP_CSUM
)
421 dev
->hard_header_len
+= GMAC_FCB_LEN
;
423 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
424 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
425 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
426 priv
->num_txbdfree
= DEFAULT_TX_RING_SIZE
;
428 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
429 priv
->txic
= DEFAULT_TXIC
;
430 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
431 priv
->rxic
= DEFAULT_RXIC
;
433 /* Enable most messages by default */
434 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
436 /* Carrier starts down, phylib will bring it up */
437 netif_carrier_off(dev
);
439 err
= register_netdev(dev
);
442 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
447 device_init_wakeup(&dev
->dev
,
448 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
450 /* fill out IRQ number and name fields */
451 len_devname
= strlen(dev
->name
);
452 strncpy(&priv
->int_name_tx
[0], dev
->name
, len_devname
);
453 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
454 strncpy(&priv
->int_name_tx
[len_devname
],
455 "_tx", sizeof("_tx") + 1);
457 strncpy(&priv
->int_name_rx
[0], dev
->name
, len_devname
);
458 strncpy(&priv
->int_name_rx
[len_devname
],
459 "_rx", sizeof("_rx") + 1);
461 strncpy(&priv
->int_name_er
[0], dev
->name
, len_devname
);
462 strncpy(&priv
->int_name_er
[len_devname
],
463 "_er", sizeof("_er") + 1);
465 priv
->int_name_tx
[len_devname
] = '\0';
467 /* Create all the sysfs files */
468 gfar_init_sysfs(dev
);
470 /* Print out the device info */
471 printk(KERN_INFO DEVICE_NAME
"%pM\n", dev
->name
, dev
->dev_addr
);
473 /* Even more device info helps when determining which kernel */
474 /* provided which set of benchmarks. */
475 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
476 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
477 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
485 of_node_put(priv
->phy_node
);
487 of_node_put(priv
->tbi_node
);
492 static int gfar_remove(struct of_device
*ofdev
)
494 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
497 of_node_put(priv
->phy_node
);
499 of_node_put(priv
->tbi_node
);
501 dev_set_drvdata(&ofdev
->dev
, NULL
);
504 free_netdev(priv
->ndev
);
510 static int gfar_suspend(struct of_device
*ofdev
, pm_message_t state
)
512 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
513 struct net_device
*dev
= priv
->ndev
;
517 int magic_packet
= priv
->wol_en
&&
518 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
520 netif_device_detach(dev
);
522 if (netif_running(dev
)) {
523 spin_lock_irqsave(&priv
->txlock
, flags
);
524 spin_lock(&priv
->rxlock
);
526 gfar_halt_nodisable(dev
);
528 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
529 tempval
= gfar_read(&priv
->regs
->maccfg1
);
531 tempval
&= ~MACCFG1_TX_EN
;
534 tempval
&= ~MACCFG1_RX_EN
;
536 gfar_write(&priv
->regs
->maccfg1
, tempval
);
538 spin_unlock(&priv
->rxlock
);
539 spin_unlock_irqrestore(&priv
->txlock
, flags
);
541 napi_disable(&priv
->napi
);
544 /* Enable interrupt on Magic Packet */
545 gfar_write(&priv
->regs
->imask
, IMASK_MAG
);
547 /* Enable Magic Packet mode */
548 tempval
= gfar_read(&priv
->regs
->maccfg2
);
549 tempval
|= MACCFG2_MPEN
;
550 gfar_write(&priv
->regs
->maccfg2
, tempval
);
552 phy_stop(priv
->phydev
);
559 static int gfar_resume(struct of_device
*ofdev
)
561 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
562 struct net_device
*dev
= priv
->ndev
;
565 int magic_packet
= priv
->wol_en
&&
566 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
568 if (!netif_running(dev
)) {
569 netif_device_attach(dev
);
573 if (!magic_packet
&& priv
->phydev
)
574 phy_start(priv
->phydev
);
576 /* Disable Magic Packet mode, in case something
580 spin_lock_irqsave(&priv
->txlock
, flags
);
581 spin_lock(&priv
->rxlock
);
583 tempval
= gfar_read(&priv
->regs
->maccfg2
);
584 tempval
&= ~MACCFG2_MPEN
;
585 gfar_write(&priv
->regs
->maccfg2
, tempval
);
589 spin_unlock(&priv
->rxlock
);
590 spin_unlock_irqrestore(&priv
->txlock
, flags
);
592 netif_device_attach(dev
);
594 napi_enable(&priv
->napi
);
599 #define gfar_suspend NULL
600 #define gfar_resume NULL
603 /* Reads the controller's registers to determine what interface
604 * connects it to the PHY.
606 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
608 struct gfar_private
*priv
= netdev_priv(dev
);
609 u32 ecntrl
= gfar_read(&priv
->regs
->ecntrl
);
611 if (ecntrl
& ECNTRL_SGMII_MODE
)
612 return PHY_INTERFACE_MODE_SGMII
;
614 if (ecntrl
& ECNTRL_TBI_MODE
) {
615 if (ecntrl
& ECNTRL_REDUCED_MODE
)
616 return PHY_INTERFACE_MODE_RTBI
;
618 return PHY_INTERFACE_MODE_TBI
;
621 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
622 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
623 return PHY_INTERFACE_MODE_RMII
;
625 phy_interface_t interface
= priv
->interface
;
628 * This isn't autodetected right now, so it must
629 * be set by the device tree or platform code.
631 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
632 return PHY_INTERFACE_MODE_RGMII_ID
;
634 return PHY_INTERFACE_MODE_RGMII
;
638 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
639 return PHY_INTERFACE_MODE_GMII
;
641 return PHY_INTERFACE_MODE_MII
;
645 /* Initializes driver's PHY state, and attaches to the PHY.
646 * Returns 0 on success.
648 static int init_phy(struct net_device
*dev
)
650 struct gfar_private
*priv
= netdev_priv(dev
);
651 uint gigabit_support
=
652 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
653 SUPPORTED_1000baseT_Full
: 0;
654 phy_interface_t interface
;
658 priv
->oldduplex
= -1;
660 interface
= gfar_get_interface(dev
);
662 if (priv
->phy_node
) {
663 priv
->phydev
= of_phy_connect(dev
, priv
->phy_node
, &adjust_link
,
666 dev_err(&dev
->dev
, "error: Could not attach to PHY\n");
671 if (interface
== PHY_INTERFACE_MODE_SGMII
)
672 gfar_configure_serdes(dev
);
674 /* Remove any features not supported by the controller */
675 priv
->phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
676 priv
->phydev
->advertising
= priv
->phydev
->supported
;
682 * Initialize TBI PHY interface for communicating with the
683 * SERDES lynx PHY on the chip. We communicate with this PHY
684 * through the MDIO bus on each controller, treating it as a
685 * "normal" PHY at the address found in the TBIPA register. We assume
686 * that the TBIPA register is valid. Either the MDIO bus code will set
687 * it to a value that doesn't conflict with other PHYs on the bus, or the
688 * value doesn't matter, as there are no other PHYs on the bus.
690 static void gfar_configure_serdes(struct net_device
*dev
)
692 struct gfar_private
*priv
= netdev_priv(dev
);
693 struct phy_device
*tbiphy
;
695 if (!priv
->tbi_node
) {
696 dev_warn(&dev
->dev
, "error: SGMII mode requires that the "
697 "device tree specify a tbi-handle\n");
701 tbiphy
= of_phy_find_device(priv
->tbi_node
);
703 dev_err(&dev
->dev
, "error: Could not get TBI device\n");
708 * If the link is already up, we must already be ok, and don't need to
709 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
710 * everything for us? Resetting it takes the link down and requires
711 * several seconds for it to come back.
713 if (phy_read(tbiphy
, MII_BMSR
) & BMSR_LSTATUS
)
716 /* Single clk mode, mii mode off(for serdes communication) */
717 phy_write(tbiphy
, MII_TBICON
, TBICON_CLK_SELECT
);
719 phy_write(tbiphy
, MII_ADVERTISE
,
720 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
721 ADVERTISE_1000XPSE_ASYM
);
723 phy_write(tbiphy
, MII_BMCR
, BMCR_ANENABLE
|
724 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
727 static void init_registers(struct net_device
*dev
)
729 struct gfar_private
*priv
= netdev_priv(dev
);
732 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
734 /* Initialize IMASK */
735 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
737 /* Init hash registers to zero */
738 gfar_write(&priv
->regs
->igaddr0
, 0);
739 gfar_write(&priv
->regs
->igaddr1
, 0);
740 gfar_write(&priv
->regs
->igaddr2
, 0);
741 gfar_write(&priv
->regs
->igaddr3
, 0);
742 gfar_write(&priv
->regs
->igaddr4
, 0);
743 gfar_write(&priv
->regs
->igaddr5
, 0);
744 gfar_write(&priv
->regs
->igaddr6
, 0);
745 gfar_write(&priv
->regs
->igaddr7
, 0);
747 gfar_write(&priv
->regs
->gaddr0
, 0);
748 gfar_write(&priv
->regs
->gaddr1
, 0);
749 gfar_write(&priv
->regs
->gaddr2
, 0);
750 gfar_write(&priv
->regs
->gaddr3
, 0);
751 gfar_write(&priv
->regs
->gaddr4
, 0);
752 gfar_write(&priv
->regs
->gaddr5
, 0);
753 gfar_write(&priv
->regs
->gaddr6
, 0);
754 gfar_write(&priv
->regs
->gaddr7
, 0);
756 /* Zero out the rmon mib registers if it has them */
757 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
758 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
760 /* Mask off the CAM interrupts */
761 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
762 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
765 /* Initialize the max receive buffer length */
766 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
768 /* Initialize the Minimum Frame Length Register */
769 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
773 /* Halt the receive and transmit queues */
774 static void gfar_halt_nodisable(struct net_device
*dev
)
776 struct gfar_private
*priv
= netdev_priv(dev
);
777 struct gfar __iomem
*regs
= priv
->regs
;
780 /* Mask all interrupts */
781 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
783 /* Clear all interrupts */
784 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
786 /* Stop the DMA, and wait for it to stop */
787 tempval
= gfar_read(&priv
->regs
->dmactrl
);
788 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
789 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
790 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
791 gfar_write(&priv
->regs
->dmactrl
, tempval
);
793 while (!(gfar_read(&priv
->regs
->ievent
) &
794 (IEVENT_GRSC
| IEVENT_GTSC
)))
799 /* Halt the receive and transmit queues */
800 void gfar_halt(struct net_device
*dev
)
802 struct gfar_private
*priv
= netdev_priv(dev
);
803 struct gfar __iomem
*regs
= priv
->regs
;
806 gfar_halt_nodisable(dev
);
808 /* Disable Rx and Tx */
809 tempval
= gfar_read(®s
->maccfg1
);
810 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
811 gfar_write(®s
->maccfg1
, tempval
);
814 void stop_gfar(struct net_device
*dev
)
816 struct gfar_private
*priv
= netdev_priv(dev
);
817 struct gfar __iomem
*regs
= priv
->regs
;
820 phy_stop(priv
->phydev
);
823 spin_lock_irqsave(&priv
->txlock
, flags
);
824 spin_lock(&priv
->rxlock
);
828 spin_unlock(&priv
->rxlock
);
829 spin_unlock_irqrestore(&priv
->txlock
, flags
);
832 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
833 free_irq(priv
->interruptError
, dev
);
834 free_irq(priv
->interruptTransmit
, dev
);
835 free_irq(priv
->interruptReceive
, dev
);
837 free_irq(priv
->interruptTransmit
, dev
);
840 free_skb_resources(priv
);
842 dma_free_coherent(&priv
->ofdev
->dev
,
843 sizeof(struct txbd8
)*priv
->tx_ring_size
844 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
846 gfar_read(®s
->tbase0
));
849 /* If there are any tx skbs or rx skbs still around, free them.
850 * Then free tx_skbuff and rx_skbuff */
851 static void free_skb_resources(struct gfar_private
*priv
)
857 /* Go through all the buffer descriptors and free their data buffers */
858 txbdp
= priv
->tx_bd_base
;
860 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
861 if (!priv
->tx_skbuff
[i
])
864 dma_unmap_single(&priv
->ofdev
->dev
, txbdp
->bufPtr
,
865 txbdp
->length
, DMA_TO_DEVICE
);
867 for (j
= 0; j
< skb_shinfo(priv
->tx_skbuff
[i
])->nr_frags
; j
++) {
869 dma_unmap_page(&priv
->ofdev
->dev
, txbdp
->bufPtr
,
870 txbdp
->length
, DMA_TO_DEVICE
);
873 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
874 priv
->tx_skbuff
[i
] = NULL
;
877 kfree(priv
->tx_skbuff
);
879 rxbdp
= priv
->rx_bd_base
;
881 /* rx_skbuff is not guaranteed to be allocated, so only
882 * free it and its contents if it is allocated */
883 if(priv
->rx_skbuff
!= NULL
) {
884 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
885 if (priv
->rx_skbuff
[i
]) {
886 dma_unmap_single(&priv
->ofdev
->dev
, rxbdp
->bufPtr
,
887 priv
->rx_buffer_size
,
890 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
891 priv
->rx_skbuff
[i
] = NULL
;
900 kfree(priv
->rx_skbuff
);
904 void gfar_start(struct net_device
*dev
)
906 struct gfar_private
*priv
= netdev_priv(dev
);
907 struct gfar __iomem
*regs
= priv
->regs
;
910 /* Enable Rx and Tx in MACCFG1 */
911 tempval
= gfar_read(®s
->maccfg1
);
912 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
913 gfar_write(®s
->maccfg1
, tempval
);
915 /* Initialize DMACTRL to have WWR and WOP */
916 tempval
= gfar_read(&priv
->regs
->dmactrl
);
917 tempval
|= DMACTRL_INIT_SETTINGS
;
918 gfar_write(&priv
->regs
->dmactrl
, tempval
);
920 /* Make sure we aren't stopped */
921 tempval
= gfar_read(&priv
->regs
->dmactrl
);
922 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
923 gfar_write(&priv
->regs
->dmactrl
, tempval
);
925 /* Clear THLT/RHLT, so that the DMA starts polling now */
926 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
927 gfar_write(®s
->rstat
, RSTAT_CLEAR_RHALT
);
929 /* Unmask the interrupts we look for */
930 gfar_write(®s
->imask
, IMASK_DEFAULT
);
932 dev
->trans_start
= jiffies
;
935 /* Bring the controller up and running */
936 int startup_gfar(struct net_device
*dev
)
943 struct gfar_private
*priv
= netdev_priv(dev
);
944 struct gfar __iomem
*regs
= priv
->regs
;
949 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
951 /* Allocate memory for the buffer descriptors */
952 vaddr
= (unsigned long) dma_alloc_coherent(&priv
->ofdev
->dev
,
953 sizeof (struct txbd8
) * priv
->tx_ring_size
+
954 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
958 if (netif_msg_ifup(priv
))
959 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
964 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
966 /* enet DMA only understands physical addresses */
967 gfar_write(®s
->tbase0
, addr
);
969 /* Start the rx descriptor ring where the tx ring leaves off */
970 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
971 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
972 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
973 gfar_write(®s
->rbase0
, addr
);
975 /* Setup the skbuff rings */
977 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
978 priv
->tx_ring_size
, GFP_KERNEL
);
980 if (NULL
== priv
->tx_skbuff
) {
981 if (netif_msg_ifup(priv
))
982 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
988 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
989 priv
->tx_skbuff
[i
] = NULL
;
992 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
993 priv
->rx_ring_size
, GFP_KERNEL
);
995 if (NULL
== priv
->rx_skbuff
) {
996 if (netif_msg_ifup(priv
))
997 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
1003 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
1004 priv
->rx_skbuff
[i
] = NULL
;
1006 /* Initialize some variables in our dev structure */
1007 priv
->num_txbdfree
= priv
->tx_ring_size
;
1008 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
1009 priv
->cur_rx
= priv
->rx_bd_base
;
1010 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
1011 priv
->skb_currx
= 0;
1013 /* Initialize Transmit Descriptor Ring */
1014 txbdp
= priv
->tx_bd_base
;
1015 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
1021 /* Set the last descriptor in the ring to indicate wrap */
1023 txbdp
->status
|= TXBD_WRAP
;
1025 rxbdp
= priv
->rx_bd_base
;
1026 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
1027 struct sk_buff
*skb
;
1029 skb
= gfar_new_skb(dev
);
1032 printk(KERN_ERR
"%s: Can't allocate RX buffers\n",
1035 goto err_rxalloc_fail
;
1038 priv
->rx_skbuff
[i
] = skb
;
1040 gfar_new_rxbdp(dev
, rxbdp
, skb
);
1045 /* Set the last descriptor in the ring to wrap */
1047 rxbdp
->status
|= RXBD_WRAP
;
1049 /* If the device has multiple interrupts, register for
1050 * them. Otherwise, only register for the one */
1051 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1052 /* Install our interrupt handlers for Error,
1053 * Transmit, and Receive */
1054 if (request_irq(priv
->interruptError
, gfar_error
,
1055 0, priv
->int_name_er
, dev
) < 0) {
1056 if (netif_msg_intr(priv
))
1057 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1058 dev
->name
, priv
->interruptError
);
1064 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
1065 0, priv
->int_name_tx
, dev
) < 0) {
1066 if (netif_msg_intr(priv
))
1067 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1068 dev
->name
, priv
->interruptTransmit
);
1075 if (request_irq(priv
->interruptReceive
, gfar_receive
,
1076 0, priv
->int_name_rx
, dev
) < 0) {
1077 if (netif_msg_intr(priv
))
1078 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
1079 dev
->name
, priv
->interruptReceive
);
1085 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
1086 0, priv
->int_name_tx
, dev
) < 0) {
1087 if (netif_msg_intr(priv
))
1088 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1089 dev
->name
, priv
->interruptTransmit
);
1096 phy_start(priv
->phydev
);
1098 /* Configure the coalescing support */
1099 gfar_write(®s
->txic
, 0);
1100 if (priv
->txcoalescing
)
1101 gfar_write(®s
->txic
, priv
->txic
);
1103 gfar_write(®s
->rxic
, 0);
1104 if (priv
->rxcoalescing
)
1105 gfar_write(®s
->rxic
, priv
->rxic
);
1107 if (priv
->rx_csum_enable
)
1108 rctrl
|= RCTRL_CHECKSUMMING
;
1110 if (priv
->extended_hash
) {
1111 rctrl
|= RCTRL_EXTHASH
;
1113 gfar_clear_exact_match(dev
);
1114 rctrl
|= RCTRL_EMEN
;
1117 if (priv
->padding
) {
1118 rctrl
&= ~RCTRL_PAL_MASK
;
1119 rctrl
|= RCTRL_PADDING(priv
->padding
);
1122 /* Init rctrl based on our settings */
1123 gfar_write(&priv
->regs
->rctrl
, rctrl
);
1125 if (dev
->features
& NETIF_F_IP_CSUM
)
1126 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
1128 /* Set the extraction length and index */
1129 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
1130 ATTRELI_EI(priv
->rx_stash_index
);
1132 gfar_write(&priv
->regs
->attreli
, attrs
);
1134 /* Start with defaults, and add stashing or locking
1135 * depending on the approprate variables */
1136 attrs
= ATTR_INIT_SETTINGS
;
1138 if (priv
->bd_stash_en
)
1139 attrs
|= ATTR_BDSTASH
;
1141 if (priv
->rx_stash_size
!= 0)
1142 attrs
|= ATTR_BUFSTASH
;
1144 gfar_write(&priv
->regs
->attr
, attrs
);
1146 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
1147 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
1148 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
1150 /* Start the controller */
1156 free_irq(priv
->interruptTransmit
, dev
);
1158 free_irq(priv
->interruptError
, dev
);
1162 free_skb_resources(priv
);
1164 dma_free_coherent(&priv
->ofdev
->dev
,
1165 sizeof(struct txbd8
)*priv
->tx_ring_size
1166 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
1168 gfar_read(®s
->tbase0
));
1173 /* Called when something needs to use the ethernet device */
1174 /* Returns 0 for success. */
1175 static int gfar_enet_open(struct net_device
*dev
)
1177 struct gfar_private
*priv
= netdev_priv(dev
);
1180 napi_enable(&priv
->napi
);
1182 skb_queue_head_init(&priv
->rx_recycle
);
1184 /* Initialize a bunch of registers */
1185 init_registers(dev
);
1187 gfar_set_mac_address(dev
);
1189 err
= init_phy(dev
);
1192 napi_disable(&priv
->napi
);
1196 err
= startup_gfar(dev
);
1198 napi_disable(&priv
->napi
);
1202 netif_start_queue(dev
);
1204 device_set_wakeup_enable(&dev
->dev
, priv
->wol_en
);
1209 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
)
1211 struct txfcb
*fcb
= (struct txfcb
*)skb_push(skb
, GMAC_FCB_LEN
);
1213 memset(fcb
, 0, GMAC_FCB_LEN
);
1218 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
1222 /* If we're here, it's a IP packet with a TCP or UDP
1223 * payload. We set it to checksum, using a pseudo-header
1226 flags
= TXFCB_DEFAULT
;
1228 /* Tell the controller what the protocol is */
1229 /* And provide the already calculated phcs */
1230 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
1232 fcb
->phcs
= udp_hdr(skb
)->check
;
1234 fcb
->phcs
= tcp_hdr(skb
)->check
;
1236 /* l3os is the distance between the start of the
1237 * frame (skb->data) and the start of the IP hdr.
1238 * l4os is the distance between the start of the
1239 * l3 hdr and the l4 hdr */
1240 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
1241 fcb
->l4os
= skb_network_header_len(skb
);
1246 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1248 fcb
->flags
|= TXFCB_VLN
;
1249 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1252 static inline struct txbd8
*skip_txbd(struct txbd8
*bdp
, int stride
,
1253 struct txbd8
*base
, int ring_size
)
1255 struct txbd8
*new_bd
= bdp
+ stride
;
1257 return (new_bd
>= (base
+ ring_size
)) ? (new_bd
- ring_size
) : new_bd
;
1260 static inline struct txbd8
*next_txbd(struct txbd8
*bdp
, struct txbd8
*base
,
1263 return skip_txbd(bdp
, 1, base
, ring_size
);
1266 /* This is called by the kernel when a frame is ready for transmission. */
1267 /* It is pointed to by the dev->hard_start_xmit function pointer */
1268 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1270 struct gfar_private
*priv
= netdev_priv(dev
);
1271 struct txfcb
*fcb
= NULL
;
1272 struct txbd8
*txbdp
, *txbdp_start
, *base
;
1276 unsigned long flags
;
1277 unsigned int nr_frags
, length
;
1279 base
= priv
->tx_bd_base
;
1281 /* make space for additional header when fcb is needed */
1282 if (((skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
1283 (priv
->vlgrp
&& vlan_tx_tag_present(skb
))) &&
1284 (skb_headroom(skb
) < GMAC_FCB_LEN
)) {
1285 struct sk_buff
*skb_new
;
1287 skb_new
= skb_realloc_headroom(skb
, GMAC_FCB_LEN
);
1289 dev
->stats
.tx_errors
++;
1291 return NETDEV_TX_OK
;
1297 /* total number of fragments in the SKB */
1298 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1300 spin_lock_irqsave(&priv
->txlock
, flags
);
1302 /* check if there is space to queue this packet */
1303 if ((nr_frags
+1) > priv
->num_txbdfree
) {
1304 /* no space, stop the queue */
1305 netif_stop_queue(dev
);
1306 dev
->stats
.tx_fifo_errors
++;
1307 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1308 return NETDEV_TX_BUSY
;
1311 /* Update transmit stats */
1312 dev
->stats
.tx_bytes
+= skb
->len
;
1314 txbdp
= txbdp_start
= priv
->cur_tx
;
1316 if (nr_frags
== 0) {
1317 lstatus
= txbdp
->lstatus
| BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
1319 /* Place the fragment addresses and lengths into the TxBDs */
1320 for (i
= 0; i
< nr_frags
; i
++) {
1321 /* Point at the next BD, wrapping as needed */
1322 txbdp
= next_txbd(txbdp
, base
, priv
->tx_ring_size
);
1324 length
= skb_shinfo(skb
)->frags
[i
].size
;
1326 lstatus
= txbdp
->lstatus
| length
|
1327 BD_LFLAG(TXBD_READY
);
1329 /* Handle the last BD specially */
1330 if (i
== nr_frags
- 1)
1331 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
1333 bufaddr
= dma_map_page(&priv
->ofdev
->dev
,
1334 skb_shinfo(skb
)->frags
[i
].page
,
1335 skb_shinfo(skb
)->frags
[i
].page_offset
,
1339 /* set the TxBD length and buffer pointer */
1340 txbdp
->bufPtr
= bufaddr
;
1341 txbdp
->lstatus
= lstatus
;
1344 lstatus
= txbdp_start
->lstatus
;
1347 /* Set up checksumming */
1348 if (CHECKSUM_PARTIAL
== skb
->ip_summed
) {
1349 fcb
= gfar_add_fcb(skb
);
1350 lstatus
|= BD_LFLAG(TXBD_TOE
);
1351 gfar_tx_checksum(skb
, fcb
);
1354 if (priv
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1355 if (unlikely(NULL
== fcb
)) {
1356 fcb
= gfar_add_fcb(skb
);
1357 lstatus
|= BD_LFLAG(TXBD_TOE
);
1360 gfar_tx_vlan(skb
, fcb
);
1363 /* setup the TxBD length and buffer pointer for the first BD */
1364 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
1365 txbdp_start
->bufPtr
= dma_map_single(&priv
->ofdev
->dev
, skb
->data
,
1366 skb_headlen(skb
), DMA_TO_DEVICE
);
1368 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | skb_headlen(skb
);
1371 * The powerpc-specific eieio() is used, as wmb() has too strong
1372 * semantics (it requires synchronization between cacheable and
1373 * uncacheable mappings, which eieio doesn't provide and which we
1374 * don't need), thus requiring a more expensive sync instruction. At
1375 * some point, the set of architecture-independent barrier functions
1376 * should be expanded to include weaker barriers.
1380 txbdp_start
->lstatus
= lstatus
;
1382 /* Update the current skb pointer to the next entry we will use
1383 * (wrapping if necessary) */
1384 priv
->skb_curtx
= (priv
->skb_curtx
+ 1) &
1385 TX_RING_MOD_MASK(priv
->tx_ring_size
);
1387 priv
->cur_tx
= next_txbd(txbdp
, base
, priv
->tx_ring_size
);
1389 /* reduce TxBD free count */
1390 priv
->num_txbdfree
-= (nr_frags
+ 1);
1392 dev
->trans_start
= jiffies
;
1394 /* If the next BD still needs to be cleaned up, then the bds
1395 are full. We need to tell the kernel to stop sending us stuff. */
1396 if (!priv
->num_txbdfree
) {
1397 netif_stop_queue(dev
);
1399 dev
->stats
.tx_fifo_errors
++;
1402 /* Tell the DMA to go go go */
1403 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1406 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1408 return NETDEV_TX_OK
;
1411 /* Stops the kernel queue, and halts the controller */
1412 static int gfar_close(struct net_device
*dev
)
1414 struct gfar_private
*priv
= netdev_priv(dev
);
1416 napi_disable(&priv
->napi
);
1418 skb_queue_purge(&priv
->rx_recycle
);
1419 cancel_work_sync(&priv
->reset_task
);
1422 /* Disconnect from the PHY */
1423 phy_disconnect(priv
->phydev
);
1424 priv
->phydev
= NULL
;
1426 netif_stop_queue(dev
);
1431 /* Changes the mac address if the controller is not running. */
1432 static int gfar_set_mac_address(struct net_device
*dev
)
1434 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1440 /* Enables and disables VLAN insertion/extraction */
1441 static void gfar_vlan_rx_register(struct net_device
*dev
,
1442 struct vlan_group
*grp
)
1444 struct gfar_private
*priv
= netdev_priv(dev
);
1445 unsigned long flags
;
1448 spin_lock_irqsave(&priv
->rxlock
, flags
);
1453 /* Enable VLAN tag insertion */
1454 tempval
= gfar_read(&priv
->regs
->tctrl
);
1455 tempval
|= TCTRL_VLINS
;
1457 gfar_write(&priv
->regs
->tctrl
, tempval
);
1459 /* Enable VLAN tag extraction */
1460 tempval
= gfar_read(&priv
->regs
->rctrl
);
1461 tempval
|= RCTRL_VLEX
;
1462 tempval
|= (RCTRL_VLEX
| RCTRL_PRSDEP_INIT
);
1463 gfar_write(&priv
->regs
->rctrl
, tempval
);
1465 /* Disable VLAN tag insertion */
1466 tempval
= gfar_read(&priv
->regs
->tctrl
);
1467 tempval
&= ~TCTRL_VLINS
;
1468 gfar_write(&priv
->regs
->tctrl
, tempval
);
1470 /* Disable VLAN tag extraction */
1471 tempval
= gfar_read(&priv
->regs
->rctrl
);
1472 tempval
&= ~RCTRL_VLEX
;
1473 /* If parse is no longer required, then disable parser */
1474 if (tempval
& RCTRL_REQ_PARSER
)
1475 tempval
|= RCTRL_PRSDEP_INIT
;
1477 tempval
&= ~RCTRL_PRSDEP_INIT
;
1478 gfar_write(&priv
->regs
->rctrl
, tempval
);
1481 gfar_change_mtu(dev
, dev
->mtu
);
1483 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1486 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1488 int tempsize
, tempval
;
1489 struct gfar_private
*priv
= netdev_priv(dev
);
1490 int oldsize
= priv
->rx_buffer_size
;
1491 int frame_size
= new_mtu
+ ETH_HLEN
;
1494 frame_size
+= VLAN_HLEN
;
1496 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1497 if (netif_msg_drv(priv
))
1498 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1503 if (gfar_uses_fcb(priv
))
1504 frame_size
+= GMAC_FCB_LEN
;
1506 frame_size
+= priv
->padding
;
1509 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1510 INCREMENTAL_BUFFER_SIZE
;
1512 /* Only stop and start the controller if it isn't already
1513 * stopped, and we changed something */
1514 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1517 priv
->rx_buffer_size
= tempsize
;
1521 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1522 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1524 /* If the mtu is larger than the max size for standard
1525 * ethernet frames (ie, a jumbo frame), then set maccfg2
1526 * to allow huge frames, and to check the length */
1527 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1529 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1530 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1532 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1534 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1536 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1542 /* gfar_reset_task gets scheduled when a packet has not been
1543 * transmitted after a set amount of time.
1544 * For now, assume that clearing out all the structures, and
1545 * starting over will fix the problem.
1547 static void gfar_reset_task(struct work_struct
*work
)
1549 struct gfar_private
*priv
= container_of(work
, struct gfar_private
,
1551 struct net_device
*dev
= priv
->ndev
;
1553 if (dev
->flags
& IFF_UP
) {
1554 netif_stop_queue(dev
);
1557 netif_start_queue(dev
);
1560 netif_tx_schedule_all(dev
);
1563 static void gfar_timeout(struct net_device
*dev
)
1565 struct gfar_private
*priv
= netdev_priv(dev
);
1567 dev
->stats
.tx_errors
++;
1568 schedule_work(&priv
->reset_task
);
1571 /* Interrupt Handler for Transmit complete */
1572 static int gfar_clean_tx_ring(struct net_device
*dev
)
1574 struct gfar_private
*priv
= netdev_priv(dev
);
1576 struct txbd8
*lbdp
= NULL
;
1577 struct txbd8
*base
= priv
->tx_bd_base
;
1578 struct sk_buff
*skb
;
1580 int tx_ring_size
= priv
->tx_ring_size
;
1586 bdp
= priv
->dirty_tx
;
1587 skb_dirtytx
= priv
->skb_dirtytx
;
1589 while ((skb
= priv
->tx_skbuff
[skb_dirtytx
])) {
1590 frags
= skb_shinfo(skb
)->nr_frags
;
1591 lbdp
= skip_txbd(bdp
, frags
, base
, tx_ring_size
);
1593 lstatus
= lbdp
->lstatus
;
1595 /* Only clean completed frames */
1596 if ((lstatus
& BD_LFLAG(TXBD_READY
)) &&
1597 (lstatus
& BD_LENGTH_MASK
))
1600 dma_unmap_single(&priv
->ofdev
->dev
,
1605 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
1606 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
1608 for (i
= 0; i
< frags
; i
++) {
1609 dma_unmap_page(&priv
->ofdev
->dev
,
1613 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
1614 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
1618 * If there's room in the queue (limit it to rx_buffer_size)
1619 * we add this skb back into the pool, if it's the right size
1621 if (skb_queue_len(&priv
->rx_recycle
) < priv
->rx_ring_size
&&
1622 skb_recycle_check(skb
, priv
->rx_buffer_size
+
1624 __skb_queue_head(&priv
->rx_recycle
, skb
);
1626 dev_kfree_skb_any(skb
);
1628 priv
->tx_skbuff
[skb_dirtytx
] = NULL
;
1630 skb_dirtytx
= (skb_dirtytx
+ 1) &
1631 TX_RING_MOD_MASK(tx_ring_size
);
1634 priv
->num_txbdfree
+= frags
+ 1;
1637 /* If we freed a buffer, we can restart transmission, if necessary */
1638 if (netif_queue_stopped(dev
) && priv
->num_txbdfree
)
1639 netif_wake_queue(dev
);
1641 /* Update dirty indicators */
1642 priv
->skb_dirtytx
= skb_dirtytx
;
1643 priv
->dirty_tx
= bdp
;
1645 dev
->stats
.tx_packets
+= howmany
;
1650 static void gfar_schedule_cleanup(struct net_device
*dev
)
1652 struct gfar_private
*priv
= netdev_priv(dev
);
1653 unsigned long flags
;
1655 spin_lock_irqsave(&priv
->txlock
, flags
);
1656 spin_lock(&priv
->rxlock
);
1658 if (napi_schedule_prep(&priv
->napi
)) {
1659 gfar_write(&priv
->regs
->imask
, IMASK_RTX_DISABLED
);
1660 __napi_schedule(&priv
->napi
);
1663 * Clear IEVENT, so interrupts aren't called again
1664 * because of the packets that have already arrived.
1666 gfar_write(&priv
->regs
->ievent
, IEVENT_RTX_MASK
);
1669 spin_unlock(&priv
->rxlock
);
1670 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1673 /* Interrupt Handler for Transmit complete */
1674 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
)
1676 gfar_schedule_cleanup((struct net_device
*)dev_id
);
1680 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
1681 struct sk_buff
*skb
)
1683 struct gfar_private
*priv
= netdev_priv(dev
);
1686 bdp
->bufPtr
= dma_map_single(&priv
->ofdev
->dev
, skb
->data
,
1687 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1689 lstatus
= BD_LFLAG(RXBD_EMPTY
| RXBD_INTERRUPT
);
1691 if (bdp
== priv
->rx_bd_base
+ priv
->rx_ring_size
- 1)
1692 lstatus
|= BD_LFLAG(RXBD_WRAP
);
1696 bdp
->lstatus
= lstatus
;
1700 struct sk_buff
* gfar_new_skb(struct net_device
*dev
)
1702 unsigned int alignamount
;
1703 struct gfar_private
*priv
= netdev_priv(dev
);
1704 struct sk_buff
*skb
= NULL
;
1706 skb
= __skb_dequeue(&priv
->rx_recycle
);
1708 skb
= netdev_alloc_skb(dev
,
1709 priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1714 alignamount
= RXBUF_ALIGNMENT
-
1715 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1717 /* We need the data buffer to be aligned properly. We will reserve
1718 * as many bytes as needed to align the data properly
1720 skb_reserve(skb
, alignamount
);
1725 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
1727 struct gfar_private
*priv
= netdev_priv(dev
);
1728 struct net_device_stats
*stats
= &dev
->stats
;
1729 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1731 /* If the packet was truncated, none of the other errors
1733 if (status
& RXBD_TRUNCATED
) {
1734 stats
->rx_length_errors
++;
1740 /* Count the errors, if there were any */
1741 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1742 stats
->rx_length_errors
++;
1744 if (status
& RXBD_LARGE
)
1749 if (status
& RXBD_NONOCTET
) {
1750 stats
->rx_frame_errors
++;
1751 estats
->rx_nonoctet
++;
1753 if (status
& RXBD_CRCERR
) {
1754 estats
->rx_crcerr
++;
1755 stats
->rx_crc_errors
++;
1757 if (status
& RXBD_OVERRUN
) {
1758 estats
->rx_overrun
++;
1759 stats
->rx_crc_errors
++;
1763 irqreturn_t
gfar_receive(int irq
, void *dev_id
)
1765 gfar_schedule_cleanup((struct net_device
*)dev_id
);
1769 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1771 /* If valid headers were found, and valid sums
1772 * were verified, then we tell the kernel that no
1773 * checksumming is necessary. Otherwise, it is */
1774 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1775 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1777 skb
->ip_summed
= CHECKSUM_NONE
;
1781 /* gfar_process_frame() -- handle one incoming packet if skb
1783 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1786 struct gfar_private
*priv
= netdev_priv(dev
);
1787 struct rxfcb
*fcb
= NULL
;
1791 /* fcb is at the beginning if exists */
1792 fcb
= (struct rxfcb
*)skb
->data
;
1794 /* Remove the FCB from the skb */
1795 /* Remove the padded bytes, if there are any */
1797 skb_pull(skb
, amount_pull
);
1799 if (priv
->rx_csum_enable
)
1800 gfar_rx_checksum(skb
, fcb
);
1802 /* Tell the skb what kind of packet this is */
1803 skb
->protocol
= eth_type_trans(skb
, dev
);
1805 /* Send the packet up the stack */
1806 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
)))
1807 ret
= vlan_hwaccel_receive_skb(skb
, priv
->vlgrp
, fcb
->vlctl
);
1809 ret
= netif_receive_skb(skb
);
1811 if (NET_RX_DROP
== ret
)
1812 priv
->extra_stats
.kernel_dropped
++;
1817 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1818 * until the budget/quota has been reached. Returns the number
1821 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1823 struct rxbd8
*bdp
, *base
;
1824 struct sk_buff
*skb
;
1828 struct gfar_private
*priv
= netdev_priv(dev
);
1830 /* Get the first full descriptor */
1832 base
= priv
->rx_bd_base
;
1834 amount_pull
= (gfar_uses_fcb(priv
) ? GMAC_FCB_LEN
: 0) +
1837 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1838 struct sk_buff
*newskb
;
1841 /* Add another skb for the future */
1842 newskb
= gfar_new_skb(dev
);
1844 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1846 dma_unmap_single(&priv
->ofdev
->dev
, bdp
->bufPtr
,
1847 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1849 /* We drop the frame if we failed to allocate a new buffer */
1850 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
1851 bdp
->status
& RXBD_ERR
)) {
1852 count_errors(bdp
->status
, dev
);
1854 if (unlikely(!newskb
))
1858 * We need to reset ->data to what it
1859 * was before gfar_new_skb() re-aligned
1860 * it to an RXBUF_ALIGNMENT boundary
1861 * before we put the skb back on the
1864 skb
->data
= skb
->head
+ NET_SKB_PAD
;
1865 __skb_queue_head(&priv
->rx_recycle
, skb
);
1868 /* Increment the number of packets */
1869 dev
->stats
.rx_packets
++;
1873 pkt_len
= bdp
->length
- ETH_FCS_LEN
;
1874 /* Remove the FCS from the packet length */
1875 skb_put(skb
, pkt_len
);
1876 dev
->stats
.rx_bytes
+= pkt_len
;
1878 if (in_irq() || irqs_disabled())
1879 printk("Interrupt problem!\n");
1880 gfar_process_frame(dev
, skb
, amount_pull
);
1883 if (netif_msg_rx_err(priv
))
1885 "%s: Missing skb!\n", dev
->name
);
1886 dev
->stats
.rx_dropped
++;
1887 priv
->extra_stats
.rx_skbmissing
++;
1892 priv
->rx_skbuff
[priv
->skb_currx
] = newskb
;
1894 /* Setup the new bdp */
1895 gfar_new_rxbdp(dev
, bdp
, newskb
);
1897 /* Update to the next pointer */
1898 bdp
= next_bd(bdp
, base
, priv
->rx_ring_size
);
1900 /* update to point at the next skb */
1902 (priv
->skb_currx
+ 1) &
1903 RX_RING_MOD_MASK(priv
->rx_ring_size
);
1906 /* Update the current rxbd pointer to be the next one */
1912 static int gfar_poll(struct napi_struct
*napi
, int budget
)
1914 struct gfar_private
*priv
= container_of(napi
, struct gfar_private
, napi
);
1915 struct net_device
*dev
= priv
->ndev
;
1918 unsigned long flags
;
1920 /* Clear IEVENT, so interrupts aren't called again
1921 * because of the packets that have already arrived */
1922 gfar_write(&priv
->regs
->ievent
, IEVENT_RTX_MASK
);
1924 /* If we fail to get the lock, don't bother with the TX BDs */
1925 if (spin_trylock_irqsave(&priv
->txlock
, flags
)) {
1926 tx_cleaned
= gfar_clean_tx_ring(dev
);
1927 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1930 rx_cleaned
= gfar_clean_rx_ring(dev
, budget
);
1935 if (rx_cleaned
< budget
) {
1936 napi_complete(napi
);
1938 /* Clear the halt bit in RSTAT */
1939 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1941 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1943 /* If we are coalescing interrupts, update the timer */
1944 /* Otherwise, clear it */
1945 if (likely(priv
->rxcoalescing
)) {
1946 gfar_write(&priv
->regs
->rxic
, 0);
1947 gfar_write(&priv
->regs
->rxic
, priv
->rxic
);
1949 if (likely(priv
->txcoalescing
)) {
1950 gfar_write(&priv
->regs
->txic
, 0);
1951 gfar_write(&priv
->regs
->txic
, priv
->txic
);
1958 #ifdef CONFIG_NET_POLL_CONTROLLER
1960 * Polling 'interrupt' - used by things like netconsole to send skbs
1961 * without having to re-enable interrupts. It's not called while
1962 * the interrupt routine is executing.
1964 static void gfar_netpoll(struct net_device
*dev
)
1966 struct gfar_private
*priv
= netdev_priv(dev
);
1968 /* If the device has multiple interrupts, run tx/rx */
1969 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1970 disable_irq(priv
->interruptTransmit
);
1971 disable_irq(priv
->interruptReceive
);
1972 disable_irq(priv
->interruptError
);
1973 gfar_interrupt(priv
->interruptTransmit
, dev
);
1974 enable_irq(priv
->interruptError
);
1975 enable_irq(priv
->interruptReceive
);
1976 enable_irq(priv
->interruptTransmit
);
1978 disable_irq(priv
->interruptTransmit
);
1979 gfar_interrupt(priv
->interruptTransmit
, dev
);
1980 enable_irq(priv
->interruptTransmit
);
1985 /* The interrupt handler for devices with one interrupt */
1986 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
)
1988 struct net_device
*dev
= dev_id
;
1989 struct gfar_private
*priv
= netdev_priv(dev
);
1991 /* Save ievent for future reference */
1992 u32 events
= gfar_read(&priv
->regs
->ievent
);
1994 /* Check for reception */
1995 if (events
& IEVENT_RX_MASK
)
1996 gfar_receive(irq
, dev_id
);
1998 /* Check for transmit completion */
1999 if (events
& IEVENT_TX_MASK
)
2000 gfar_transmit(irq
, dev_id
);
2002 /* Check for errors */
2003 if (events
& IEVENT_ERR_MASK
)
2004 gfar_error(irq
, dev_id
);
2009 /* Called every time the controller might need to be made
2010 * aware of new link state. The PHY code conveys this
2011 * information through variables in the phydev structure, and this
2012 * function converts those variables into the appropriate
2013 * register values, and can bring down the device if needed.
2015 static void adjust_link(struct net_device
*dev
)
2017 struct gfar_private
*priv
= netdev_priv(dev
);
2018 struct gfar __iomem
*regs
= priv
->regs
;
2019 unsigned long flags
;
2020 struct phy_device
*phydev
= priv
->phydev
;
2023 spin_lock_irqsave(&priv
->txlock
, flags
);
2025 u32 tempval
= gfar_read(®s
->maccfg2
);
2026 u32 ecntrl
= gfar_read(®s
->ecntrl
);
2028 /* Now we make sure that we can be in full duplex mode.
2029 * If not, we operate in half-duplex mode. */
2030 if (phydev
->duplex
!= priv
->oldduplex
) {
2032 if (!(phydev
->duplex
))
2033 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
2035 tempval
|= MACCFG2_FULL_DUPLEX
;
2037 priv
->oldduplex
= phydev
->duplex
;
2040 if (phydev
->speed
!= priv
->oldspeed
) {
2042 switch (phydev
->speed
) {
2045 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
2047 ecntrl
&= ~(ECNTRL_R100
);
2052 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
2054 /* Reduced mode distinguishes
2055 * between 10 and 100 */
2056 if (phydev
->speed
== SPEED_100
)
2057 ecntrl
|= ECNTRL_R100
;
2059 ecntrl
&= ~(ECNTRL_R100
);
2062 if (netif_msg_link(priv
))
2064 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2065 dev
->name
, phydev
->speed
);
2069 priv
->oldspeed
= phydev
->speed
;
2072 gfar_write(®s
->maccfg2
, tempval
);
2073 gfar_write(®s
->ecntrl
, ecntrl
);
2075 if (!priv
->oldlink
) {
2079 } else if (priv
->oldlink
) {
2083 priv
->oldduplex
= -1;
2086 if (new_state
&& netif_msg_link(priv
))
2087 phy_print_status(phydev
);
2089 spin_unlock_irqrestore(&priv
->txlock
, flags
);
2092 /* Update the hash table based on the current list of multicast
2093 * addresses we subscribe to. Also, change the promiscuity of
2094 * the device based on the flags (this function is called
2095 * whenever dev->flags is changed */
2096 static void gfar_set_multi(struct net_device
*dev
)
2098 struct dev_mc_list
*mc_ptr
;
2099 struct gfar_private
*priv
= netdev_priv(dev
);
2100 struct gfar __iomem
*regs
= priv
->regs
;
2103 if(dev
->flags
& IFF_PROMISC
) {
2104 /* Set RCTRL to PROM */
2105 tempval
= gfar_read(®s
->rctrl
);
2106 tempval
|= RCTRL_PROM
;
2107 gfar_write(®s
->rctrl
, tempval
);
2109 /* Set RCTRL to not PROM */
2110 tempval
= gfar_read(®s
->rctrl
);
2111 tempval
&= ~(RCTRL_PROM
);
2112 gfar_write(®s
->rctrl
, tempval
);
2115 if(dev
->flags
& IFF_ALLMULTI
) {
2116 /* Set the hash to rx all multicast frames */
2117 gfar_write(®s
->igaddr0
, 0xffffffff);
2118 gfar_write(®s
->igaddr1
, 0xffffffff);
2119 gfar_write(®s
->igaddr2
, 0xffffffff);
2120 gfar_write(®s
->igaddr3
, 0xffffffff);
2121 gfar_write(®s
->igaddr4
, 0xffffffff);
2122 gfar_write(®s
->igaddr5
, 0xffffffff);
2123 gfar_write(®s
->igaddr6
, 0xffffffff);
2124 gfar_write(®s
->igaddr7
, 0xffffffff);
2125 gfar_write(®s
->gaddr0
, 0xffffffff);
2126 gfar_write(®s
->gaddr1
, 0xffffffff);
2127 gfar_write(®s
->gaddr2
, 0xffffffff);
2128 gfar_write(®s
->gaddr3
, 0xffffffff);
2129 gfar_write(®s
->gaddr4
, 0xffffffff);
2130 gfar_write(®s
->gaddr5
, 0xffffffff);
2131 gfar_write(®s
->gaddr6
, 0xffffffff);
2132 gfar_write(®s
->gaddr7
, 0xffffffff);
2137 /* zero out the hash */
2138 gfar_write(®s
->igaddr0
, 0x0);
2139 gfar_write(®s
->igaddr1
, 0x0);
2140 gfar_write(®s
->igaddr2
, 0x0);
2141 gfar_write(®s
->igaddr3
, 0x0);
2142 gfar_write(®s
->igaddr4
, 0x0);
2143 gfar_write(®s
->igaddr5
, 0x0);
2144 gfar_write(®s
->igaddr6
, 0x0);
2145 gfar_write(®s
->igaddr7
, 0x0);
2146 gfar_write(®s
->gaddr0
, 0x0);
2147 gfar_write(®s
->gaddr1
, 0x0);
2148 gfar_write(®s
->gaddr2
, 0x0);
2149 gfar_write(®s
->gaddr3
, 0x0);
2150 gfar_write(®s
->gaddr4
, 0x0);
2151 gfar_write(®s
->gaddr5
, 0x0);
2152 gfar_write(®s
->gaddr6
, 0x0);
2153 gfar_write(®s
->gaddr7
, 0x0);
2155 /* If we have extended hash tables, we need to
2156 * clear the exact match registers to prepare for
2158 if (priv
->extended_hash
) {
2159 em_num
= GFAR_EM_NUM
+ 1;
2160 gfar_clear_exact_match(dev
);
2167 if(dev
->mc_count
== 0)
2170 /* Parse the list, and set the appropriate bits */
2171 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
2173 gfar_set_mac_for_addr(dev
, idx
,
2177 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
2185 /* Clears each of the exact match registers to zero, so they
2186 * don't interfere with normal reception */
2187 static void gfar_clear_exact_match(struct net_device
*dev
)
2190 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
2192 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
2193 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
2196 /* Set the appropriate hash bit for the given addr */
2197 /* The algorithm works like so:
2198 * 1) Take the Destination Address (ie the multicast address), and
2199 * do a CRC on it (little endian), and reverse the bits of the
2201 * 2) Use the 8 most significant bits as a hash into a 256-entry
2202 * table. The table is controlled through 8 32-bit registers:
2203 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2204 * gaddr7. This means that the 3 most significant bits in the
2205 * hash index which gaddr register to use, and the 5 other bits
2206 * indicate which bit (assuming an IBM numbering scheme, which
2207 * for PowerPC (tm) is usually the case) in the register holds
2209 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
2212 struct gfar_private
*priv
= netdev_priv(dev
);
2213 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
2214 int width
= priv
->hash_width
;
2215 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
2216 u8 whichreg
= result
>> (32 - width
+ 5);
2217 u32 value
= (1 << (31-whichbit
));
2219 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
2221 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
2227 /* There are multiple MAC Address register pairs on some controllers
2228 * This function sets the numth pair to a given address
2230 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
2232 struct gfar_private
*priv
= netdev_priv(dev
);
2234 char tmpbuf
[MAC_ADDR_LEN
];
2236 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
2240 /* Now copy it into the mac registers backwards, cuz */
2241 /* little endian is silly */
2242 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
2243 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
2245 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
2247 tempval
= *((u32
*) (tmpbuf
+ 4));
2249 gfar_write(macptr
+1, tempval
);
2252 /* GFAR error interrupt handler */
2253 static irqreturn_t
gfar_error(int irq
, void *dev_id
)
2255 struct net_device
*dev
= dev_id
;
2256 struct gfar_private
*priv
= netdev_priv(dev
);
2258 /* Save ievent for future reference */
2259 u32 events
= gfar_read(&priv
->regs
->ievent
);
2262 gfar_write(&priv
->regs
->ievent
, events
& IEVENT_ERR_MASK
);
2264 /* Magic Packet is not an error. */
2265 if ((priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
2266 (events
& IEVENT_MAG
))
2267 events
&= ~IEVENT_MAG
;
2270 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
2271 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2272 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
2274 /* Update the error counters */
2275 if (events
& IEVENT_TXE
) {
2276 dev
->stats
.tx_errors
++;
2278 if (events
& IEVENT_LC
)
2279 dev
->stats
.tx_window_errors
++;
2280 if (events
& IEVENT_CRL
)
2281 dev
->stats
.tx_aborted_errors
++;
2282 if (events
& IEVENT_XFUN
) {
2283 if (netif_msg_tx_err(priv
))
2284 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
2285 "packet dropped.\n", dev
->name
);
2286 dev
->stats
.tx_dropped
++;
2287 priv
->extra_stats
.tx_underrun
++;
2289 /* Reactivate the Tx Queues */
2290 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
2292 if (netif_msg_tx_err(priv
))
2293 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
2295 if (events
& IEVENT_BSY
) {
2296 dev
->stats
.rx_errors
++;
2297 priv
->extra_stats
.rx_bsy
++;
2299 gfar_receive(irq
, dev_id
);
2301 if (netif_msg_rx_err(priv
))
2302 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
2303 dev
->name
, gfar_read(&priv
->regs
->rstat
));
2305 if (events
& IEVENT_BABR
) {
2306 dev
->stats
.rx_errors
++;
2307 priv
->extra_stats
.rx_babr
++;
2309 if (netif_msg_rx_err(priv
))
2310 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
2312 if (events
& IEVENT_EBERR
) {
2313 priv
->extra_stats
.eberr
++;
2314 if (netif_msg_rx_err(priv
))
2315 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
2317 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
2318 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
2320 if (events
& IEVENT_BABT
) {
2321 priv
->extra_stats
.tx_babt
++;
2322 if (netif_msg_tx_err(priv
))
2323 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
2328 /* work with hotplug and coldplug */
2329 MODULE_ALIAS("platform:fsl-gianfar");
2331 static struct of_device_id gfar_match
[] =
2335 .compatible
= "gianfar",
2340 /* Structure for a device driver */
2341 static struct of_platform_driver gfar_driver
= {
2342 .name
= "fsl-gianfar",
2343 .match_table
= gfar_match
,
2345 .probe
= gfar_probe
,
2346 .remove
= gfar_remove
,
2347 .suspend
= gfar_suspend
,
2348 .resume
= gfar_resume
,
2351 static int __init
gfar_init(void)
2353 return of_register_platform_driver(&gfar_driver
);
2356 static void __exit
gfar_exit(void)
2358 of_unregister_platform_driver(&gfar_driver
);
2361 module_init(gfar_init
);
2362 module_exit(gfar_exit
);