2 * AT86RF230/RF231 driver
4 * Copyright (C) 2009-2012 Siemens AG
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
21 * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/interrupt.h>
26 #include <linux/gpio.h>
27 #include <linux/delay.h>
28 #include <linux/mutex.h>
29 #include <linux/workqueue.h>
30 #include <linux/spinlock.h>
31 #include <linux/spi/spi.h>
32 #include <linux/spi/at86rf230.h>
33 #include <linux/skbuff.h>
35 #include <net/mac802154.h>
36 #include <net/wpan-phy.h>
38 struct at86rf230_local
{
39 struct spi_device
*spi
;
47 struct work_struct irqwork
;
48 struct completion tx_complete
;
50 struct ieee802154_dev
*dev
;
57 static inline int is_rf212(struct at86rf230_local
*local
)
59 return local
->part
== 7;
62 #define RG_TRX_STATUS (0x01)
63 #define SR_TRX_STATUS 0x01, 0x1f, 0
64 #define SR_RESERVED_01_3 0x01, 0x20, 5
65 #define SR_CCA_STATUS 0x01, 0x40, 6
66 #define SR_CCA_DONE 0x01, 0x80, 7
67 #define RG_TRX_STATE (0x02)
68 #define SR_TRX_CMD 0x02, 0x1f, 0
69 #define SR_TRAC_STATUS 0x02, 0xe0, 5
70 #define RG_TRX_CTRL_0 (0x03)
71 #define SR_CLKM_CTRL 0x03, 0x07, 0
72 #define SR_CLKM_SHA_SEL 0x03, 0x08, 3
73 #define SR_PAD_IO_CLKM 0x03, 0x30, 4
74 #define SR_PAD_IO 0x03, 0xc0, 6
75 #define RG_TRX_CTRL_1 (0x04)
76 #define SR_IRQ_POLARITY 0x04, 0x01, 0
77 #define SR_IRQ_MASK_MODE 0x04, 0x02, 1
78 #define SR_SPI_CMD_MODE 0x04, 0x0c, 2
79 #define SR_RX_BL_CTRL 0x04, 0x10, 4
80 #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
81 #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
82 #define SR_PA_EXT_EN 0x04, 0x80, 7
83 #define RG_PHY_TX_PWR (0x05)
84 #define SR_TX_PWR 0x05, 0x0f, 0
85 #define SR_PA_LT 0x05, 0x30, 4
86 #define SR_PA_BUF_LT 0x05, 0xc0, 6
87 #define RG_PHY_RSSI (0x06)
88 #define SR_RSSI 0x06, 0x1f, 0
89 #define SR_RND_VALUE 0x06, 0x60, 5
90 #define SR_RX_CRC_VALID 0x06, 0x80, 7
91 #define RG_PHY_ED_LEVEL (0x07)
92 #define SR_ED_LEVEL 0x07, 0xff, 0
93 #define RG_PHY_CC_CCA (0x08)
94 #define SR_CHANNEL 0x08, 0x1f, 0
95 #define SR_CCA_MODE 0x08, 0x60, 5
96 #define SR_CCA_REQUEST 0x08, 0x80, 7
97 #define RG_CCA_THRES (0x09)
98 #define SR_CCA_ED_THRES 0x09, 0x0f, 0
99 #define SR_RESERVED_09_1 0x09, 0xf0, 4
100 #define RG_RX_CTRL (0x0a)
101 #define SR_PDT_THRES 0x0a, 0x0f, 0
102 #define SR_RESERVED_0a_1 0x0a, 0xf0, 4
103 #define RG_SFD_VALUE (0x0b)
104 #define SR_SFD_VALUE 0x0b, 0xff, 0
105 #define RG_TRX_CTRL_2 (0x0c)
106 #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
107 #define SR_SUB_MODE 0x0c, 0x04, 2
108 #define SR_BPSK_QPSK 0x0c, 0x08, 3
109 #define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4
110 #define SR_RESERVED_0c_5 0x0c, 0x60, 5
111 #define SR_RX_SAFE_MODE 0x0c, 0x80, 7
112 #define RG_ANT_DIV (0x0d)
113 #define SR_ANT_CTRL 0x0d, 0x03, 0
114 #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
115 #define SR_ANT_DIV_EN 0x0d, 0x08, 3
116 #define SR_RESERVED_0d_2 0x0d, 0x70, 4
117 #define SR_ANT_SEL 0x0d, 0x80, 7
118 #define RG_IRQ_MASK (0x0e)
119 #define SR_IRQ_MASK 0x0e, 0xff, 0
120 #define RG_IRQ_STATUS (0x0f)
121 #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
122 #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
123 #define SR_IRQ_2_RX_START 0x0f, 0x04, 2
124 #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
125 #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
126 #define SR_IRQ_5_AMI 0x0f, 0x20, 5
127 #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
128 #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
129 #define RG_VREG_CTRL (0x10)
130 #define SR_RESERVED_10_6 0x10, 0x03, 0
131 #define SR_DVDD_OK 0x10, 0x04, 2
132 #define SR_DVREG_EXT 0x10, 0x08, 3
133 #define SR_RESERVED_10_3 0x10, 0x30, 4
134 #define SR_AVDD_OK 0x10, 0x40, 6
135 #define SR_AVREG_EXT 0x10, 0x80, 7
136 #define RG_BATMON (0x11)
137 #define SR_BATMON_VTH 0x11, 0x0f, 0
138 #define SR_BATMON_HR 0x11, 0x10, 4
139 #define SR_BATMON_OK 0x11, 0x20, 5
140 #define SR_RESERVED_11_1 0x11, 0xc0, 6
141 #define RG_XOSC_CTRL (0x12)
142 #define SR_XTAL_TRIM 0x12, 0x0f, 0
143 #define SR_XTAL_MODE 0x12, 0xf0, 4
144 #define RG_RX_SYN (0x15)
145 #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
146 #define SR_RESERVED_15_2 0x15, 0x70, 4
147 #define SR_RX_PDT_DIS 0x15, 0x80, 7
148 #define RG_XAH_CTRL_1 (0x17)
149 #define SR_RESERVED_17_8 0x17, 0x01, 0
150 #define SR_AACK_PROM_MODE 0x17, 0x02, 1
151 #define SR_AACK_ACK_TIME 0x17, 0x04, 2
152 #define SR_RESERVED_17_5 0x17, 0x08, 3
153 #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
154 #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
155 #define SR_CSMA_LBT_MODE 0x17, 0x40, 6
156 #define SR_RESERVED_17_1 0x17, 0x80, 7
157 #define RG_FTN_CTRL (0x18)
158 #define SR_RESERVED_18_2 0x18, 0x7f, 0
159 #define SR_FTN_START 0x18, 0x80, 7
160 #define RG_PLL_CF (0x1a)
161 #define SR_RESERVED_1a_2 0x1a, 0x7f, 0
162 #define SR_PLL_CF_START 0x1a, 0x80, 7
163 #define RG_PLL_DCU (0x1b)
164 #define SR_RESERVED_1b_3 0x1b, 0x3f, 0
165 #define SR_RESERVED_1b_2 0x1b, 0x40, 6
166 #define SR_PLL_DCU_START 0x1b, 0x80, 7
167 #define RG_PART_NUM (0x1c)
168 #define SR_PART_NUM 0x1c, 0xff, 0
169 #define RG_VERSION_NUM (0x1d)
170 #define SR_VERSION_NUM 0x1d, 0xff, 0
171 #define RG_MAN_ID_0 (0x1e)
172 #define SR_MAN_ID_0 0x1e, 0xff, 0
173 #define RG_MAN_ID_1 (0x1f)
174 #define SR_MAN_ID_1 0x1f, 0xff, 0
175 #define RG_SHORT_ADDR_0 (0x20)
176 #define SR_SHORT_ADDR_0 0x20, 0xff, 0
177 #define RG_SHORT_ADDR_1 (0x21)
178 #define SR_SHORT_ADDR_1 0x21, 0xff, 0
179 #define RG_PAN_ID_0 (0x22)
180 #define SR_PAN_ID_0 0x22, 0xff, 0
181 #define RG_PAN_ID_1 (0x23)
182 #define SR_PAN_ID_1 0x23, 0xff, 0
183 #define RG_IEEE_ADDR_0 (0x24)
184 #define SR_IEEE_ADDR_0 0x24, 0xff, 0
185 #define RG_IEEE_ADDR_1 (0x25)
186 #define SR_IEEE_ADDR_1 0x25, 0xff, 0
187 #define RG_IEEE_ADDR_2 (0x26)
188 #define SR_IEEE_ADDR_2 0x26, 0xff, 0
189 #define RG_IEEE_ADDR_3 (0x27)
190 #define SR_IEEE_ADDR_3 0x27, 0xff, 0
191 #define RG_IEEE_ADDR_4 (0x28)
192 #define SR_IEEE_ADDR_4 0x28, 0xff, 0
193 #define RG_IEEE_ADDR_5 (0x29)
194 #define SR_IEEE_ADDR_5 0x29, 0xff, 0
195 #define RG_IEEE_ADDR_6 (0x2a)
196 #define SR_IEEE_ADDR_6 0x2a, 0xff, 0
197 #define RG_IEEE_ADDR_7 (0x2b)
198 #define SR_IEEE_ADDR_7 0x2b, 0xff, 0
199 #define RG_XAH_CTRL_0 (0x2c)
200 #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
201 #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
202 #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
203 #define RG_CSMA_SEED_0 (0x2d)
204 #define SR_CSMA_SEED_0 0x2d, 0xff, 0
205 #define RG_CSMA_SEED_1 (0x2e)
206 #define SR_CSMA_SEED_1 0x2e, 0x07, 0
207 #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
208 #define SR_AACK_DIS_ACK 0x2e, 0x10, 4
209 #define SR_AACK_SET_PD 0x2e, 0x20, 5
210 #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
211 #define RG_CSMA_BE (0x2f)
212 #define SR_MIN_BE 0x2f, 0x0f, 0
213 #define SR_MAX_BE 0x2f, 0xf0, 4
216 #define CMD_REG_MASK 0x3f
217 #define CMD_WRITE 0x40
220 #define IRQ_BAT_LOW (1 << 7)
221 #define IRQ_TRX_UR (1 << 6)
222 #define IRQ_AMI (1 << 5)
223 #define IRQ_CCA_ED (1 << 4)
224 #define IRQ_TRX_END (1 << 3)
225 #define IRQ_RX_START (1 << 2)
226 #define IRQ_PLL_UNL (1 << 1)
227 #define IRQ_PLL_LOCK (1 << 0)
229 #define IRQ_ACTIVE_HIGH 0
230 #define IRQ_ACTIVE_LOW 1
232 #define STATE_P_ON 0x00 /* BUSY */
233 #define STATE_BUSY_RX 0x01
234 #define STATE_BUSY_TX 0x02
235 #define STATE_FORCE_TRX_OFF 0x03
236 #define STATE_FORCE_TX_ON 0x04 /* IDLE */
237 /* 0x05 */ /* INVALID_PARAMETER */
238 #define STATE_RX_ON 0x06
239 /* 0x07 */ /* SUCCESS */
240 #define STATE_TRX_OFF 0x08
241 #define STATE_TX_ON 0x09
242 /* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */
243 #define STATE_SLEEP 0x0F
244 #define STATE_BUSY_RX_AACK 0x11
245 #define STATE_BUSY_TX_ARET 0x12
246 #define STATE_RX_AACK_ON 0x16
247 #define STATE_TX_ARET_ON 0x19
248 #define STATE_RX_ON_NOCLK 0x1C
249 #define STATE_RX_AACK_ON_NOCLK 0x1D
250 #define STATE_BUSY_RX_AACK_NOCLK 0x1E
251 #define STATE_TRANSITION_IN_PROGRESS 0x1F
254 __at86rf230_detect_device(struct spi_device
*spi
, u16
*man_id
, u8
*part
,
258 u8
*buf
= kmalloc(2, GFP_KERNEL
);
260 struct spi_message msg
;
261 struct spi_transfer xfer
= {
271 for (reg
= RG_PART_NUM
; reg
<= RG_MAN_ID_1
; reg
++) {
272 buf
[0] = (reg
& CMD_REG_MASK
) | CMD_REG
;
274 dev_vdbg(&spi
->dev
, "buf[0] = %02x\n", buf
[0]);
275 spi_message_init(&msg
);
276 spi_message_add_tail(&xfer
, &msg
);
278 status
= spi_sync(spi
, &msg
);
279 dev_vdbg(&spi
->dev
, "status = %d\n", status
);
283 dev_vdbg(&spi
->dev
, "status = %d\n", status
);
284 dev_vdbg(&spi
->dev
, "buf[0] = %02x\n", buf
[0]);
285 dev_vdbg(&spi
->dev
, "buf[1] = %02x\n", buf
[1]);
288 data
[reg
- RG_PART_NUM
] = buf
[1];
296 *man_id
= (data
[3] << 8) | data
[2];
305 __at86rf230_write(struct at86rf230_local
*lp
, u8 addr
, u8 data
)
309 struct spi_message msg
;
310 struct spi_transfer xfer
= {
315 buf
[0] = (addr
& CMD_REG_MASK
) | CMD_REG
| CMD_WRITE
;
317 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
318 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
319 spi_message_init(&msg
);
320 spi_message_add_tail(&xfer
, &msg
);
322 status
= spi_sync(lp
->spi
, &msg
);
323 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
327 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
328 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
329 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
335 __at86rf230_read_subreg(struct at86rf230_local
*lp
,
336 u8 addr
, u8 mask
, int shift
, u8
*data
)
340 struct spi_message msg
;
341 struct spi_transfer xfer
= {
347 buf
[0] = (addr
& CMD_REG_MASK
) | CMD_REG
;
349 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
350 spi_message_init(&msg
);
351 spi_message_add_tail(&xfer
, &msg
);
353 status
= spi_sync(lp
->spi
, &msg
);
354 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
358 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
359 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
360 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
369 at86rf230_read_subreg(struct at86rf230_local
*lp
,
370 u8 addr
, u8 mask
, int shift
, u8
*data
)
374 mutex_lock(&lp
->bmux
);
375 status
= __at86rf230_read_subreg(lp
, addr
, mask
, shift
, data
);
376 mutex_unlock(&lp
->bmux
);
382 at86rf230_write_subreg(struct at86rf230_local
*lp
,
383 u8 addr
, u8 mask
, int shift
, u8 data
)
388 mutex_lock(&lp
->bmux
);
389 status
= __at86rf230_read_subreg(lp
, addr
, 0xff, 0, &val
);
394 val
|= (data
<< shift
) & mask
;
396 status
= __at86rf230_write(lp
, addr
, val
);
398 mutex_unlock(&lp
->bmux
);
404 at86rf230_write_fbuf(struct at86rf230_local
*lp
, u8
*data
, u8 len
)
408 struct spi_message msg
;
409 struct spi_transfer xfer_head
= {
414 struct spi_transfer xfer_buf
= {
419 mutex_lock(&lp
->bmux
);
420 buf
[0] = CMD_WRITE
| CMD_FB
;
421 buf
[1] = len
+ 2; /* 2 bytes for CRC that isn't written */
423 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
424 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
426 spi_message_init(&msg
);
427 spi_message_add_tail(&xfer_head
, &msg
);
428 spi_message_add_tail(&xfer_buf
, &msg
);
430 status
= spi_sync(lp
->spi
, &msg
);
431 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
435 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
436 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
437 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
439 mutex_unlock(&lp
->bmux
);
444 at86rf230_read_fbuf(struct at86rf230_local
*lp
, u8
*data
, u8
*len
, u8
*lqi
)
448 struct spi_message msg
;
449 struct spi_transfer xfer_head
= {
454 struct spi_transfer xfer_head1
= {
459 struct spi_transfer xfer_buf
= {
464 mutex_lock(&lp
->bmux
);
469 spi_message_init(&msg
);
470 spi_message_add_tail(&xfer_head
, &msg
);
472 status
= spi_sync(lp
->spi
, &msg
);
473 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
475 xfer_buf
.len
= *(buf
+ 1) + 1;
481 spi_message_init(&msg
);
482 spi_message_add_tail(&xfer_head1
, &msg
);
483 spi_message_add_tail(&xfer_buf
, &msg
);
485 status
= spi_sync(lp
->spi
, &msg
);
490 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
491 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
492 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
495 if (lqi
&& (*len
> lp
->buf
[1]))
496 *lqi
= data
[lp
->buf
[1]];
498 mutex_unlock(&lp
->bmux
);
504 at86rf230_ed(struct ieee802154_dev
*dev
, u8
*level
)
513 at86rf230_state(struct ieee802154_dev
*dev
, int state
)
515 struct at86rf230_local
*lp
= dev
->priv
;
522 if (state
== STATE_FORCE_TX_ON
)
523 desired_status
= STATE_TX_ON
;
524 else if (state
== STATE_FORCE_TRX_OFF
)
525 desired_status
= STATE_TRX_OFF
;
527 desired_status
= state
;
530 rc
= at86rf230_read_subreg(lp
, SR_TRX_STATUS
, &val
);
533 } while (val
== STATE_TRANSITION_IN_PROGRESS
);
535 if (val
== desired_status
)
538 /* state is equal to phy states */
539 rc
= at86rf230_write_subreg(lp
, SR_TRX_CMD
, state
);
544 rc
= at86rf230_read_subreg(lp
, SR_TRX_STATUS
, &val
);
547 } while (val
== STATE_TRANSITION_IN_PROGRESS
);
550 if (val
== desired_status
)
553 pr_err("unexpected state change: %d, asked for %d\n", val
, state
);
557 pr_err("error: %d\n", rc
);
562 at86rf230_start(struct ieee802154_dev
*dev
)
564 struct at86rf230_local
*lp
= dev
->priv
;
567 rc
= at86rf230_write_subreg(lp
, SR_RX_SAFE_MODE
, 1);
571 return at86rf230_state(dev
, STATE_RX_AACK_ON
);
575 at86rf230_stop(struct ieee802154_dev
*dev
)
577 at86rf230_state(dev
, STATE_FORCE_TRX_OFF
);
581 at86rf230_set_channel(struct at86rf230_local
*lp
, int page
, int channel
)
583 return at86rf230_write_subreg(lp
, SR_CHANNEL
, channel
);
587 at86rf212_set_channel(struct at86rf230_local
*lp
, int page
, int channel
)
592 rc
= at86rf230_write_subreg(lp
, SR_SUB_MODE
, 0);
594 rc
= at86rf230_write_subreg(lp
, SR_SUB_MODE
, 1);
599 rc
= at86rf230_write_subreg(lp
, SR_BPSK_QPSK
, 0);
601 rc
= at86rf230_write_subreg(lp
, SR_BPSK_QPSK
, 1);
605 return at86rf230_write_subreg(lp
, SR_CHANNEL
, channel
);
609 at86rf230_channel(struct ieee802154_dev
*dev
, int page
, int channel
)
611 struct at86rf230_local
*lp
= dev
->priv
;
616 if (page
< 0 || page
> 31 ||
617 !(lp
->dev
->phy
->channels_supported
[page
] & BIT(channel
))) {
623 rc
= at86rf212_set_channel(lp
, page
, channel
);
625 rc
= at86rf230_set_channel(lp
, page
, channel
);
629 msleep(1); /* Wait for PLL */
630 dev
->phy
->current_channel
= channel
;
631 dev
->phy
->current_page
= page
;
637 at86rf230_xmit(struct ieee802154_dev
*dev
, struct sk_buff
*skb
)
639 struct at86rf230_local
*lp
= dev
->priv
;
643 spin_lock(&lp
->lock
);
645 spin_unlock(&lp
->lock
);
648 spin_unlock(&lp
->lock
);
652 rc
= at86rf230_state(dev
, STATE_FORCE_TX_ON
);
656 spin_lock_irqsave(&lp
->lock
, flags
);
658 reinit_completion(&lp
->tx_complete
);
659 spin_unlock_irqrestore(&lp
->lock
, flags
);
661 rc
= at86rf230_write_fbuf(lp
, skb
->data
, skb
->len
);
665 rc
= at86rf230_write_subreg(lp
, SR_TRX_CMD
, STATE_BUSY_TX
);
669 rc
= wait_for_completion_interruptible(&lp
->tx_complete
);
673 rc
= at86rf230_start(dev
);
678 at86rf230_start(dev
);
680 pr_err("error: %d\n", rc
);
682 spin_lock_irqsave(&lp
->lock
, flags
);
684 spin_unlock_irqrestore(&lp
->lock
, flags
);
689 static int at86rf230_rx(struct at86rf230_local
*lp
)
691 u8 len
= 128, lqi
= 0;
694 skb
= alloc_skb(len
, GFP_KERNEL
);
699 if (at86rf230_read_fbuf(lp
, skb_put(skb
, len
), &len
, &lqi
))
705 skb_trim(skb
, len
- 2); /* We do not put CRC into the frame */
707 ieee802154_rx_irqsafe(lp
->dev
, skb
, lqi
);
709 dev_dbg(&lp
->spi
->dev
, "READ_FBUF: %d %x\n", len
, lqi
);
713 pr_debug("received frame is too small\n");
720 at86rf230_set_hw_addr_filt(struct ieee802154_dev
*dev
,
721 struct ieee802154_hw_addr_filt
*filt
,
722 unsigned long changed
)
724 struct at86rf230_local
*lp
= dev
->priv
;
726 if (changed
& IEEE802515_AFILT_SADDR_CHANGED
) {
727 dev_vdbg(&lp
->spi
->dev
,
728 "at86rf230_set_hw_addr_filt called for saddr\n");
729 __at86rf230_write(lp
, RG_SHORT_ADDR_0
, filt
->short_addr
);
730 __at86rf230_write(lp
, RG_SHORT_ADDR_1
, filt
->short_addr
>> 8);
733 if (changed
& IEEE802515_AFILT_PANID_CHANGED
) {
734 dev_vdbg(&lp
->spi
->dev
,
735 "at86rf230_set_hw_addr_filt called for pan id\n");
736 __at86rf230_write(lp
, RG_PAN_ID_0
, filt
->pan_id
);
737 __at86rf230_write(lp
, RG_PAN_ID_1
, filt
->pan_id
>> 8);
740 if (changed
& IEEE802515_AFILT_IEEEADDR_CHANGED
) {
741 dev_vdbg(&lp
->spi
->dev
,
742 "at86rf230_set_hw_addr_filt called for IEEE addr\n");
743 at86rf230_write_subreg(lp
, SR_IEEE_ADDR_0
, filt
->ieee_addr
[7]);
744 at86rf230_write_subreg(lp
, SR_IEEE_ADDR_1
, filt
->ieee_addr
[6]);
745 at86rf230_write_subreg(lp
, SR_IEEE_ADDR_2
, filt
->ieee_addr
[5]);
746 at86rf230_write_subreg(lp
, SR_IEEE_ADDR_3
, filt
->ieee_addr
[4]);
747 at86rf230_write_subreg(lp
, SR_IEEE_ADDR_4
, filt
->ieee_addr
[3]);
748 at86rf230_write_subreg(lp
, SR_IEEE_ADDR_5
, filt
->ieee_addr
[2]);
749 at86rf230_write_subreg(lp
, SR_IEEE_ADDR_6
, filt
->ieee_addr
[1]);
750 at86rf230_write_subreg(lp
, SR_IEEE_ADDR_7
, filt
->ieee_addr
[0]);
753 if (changed
& IEEE802515_AFILT_PANC_CHANGED
) {
754 dev_vdbg(&lp
->spi
->dev
,
755 "at86rf230_set_hw_addr_filt called for panc change\n");
757 at86rf230_write_subreg(lp
, SR_AACK_I_AM_COORD
, 1);
759 at86rf230_write_subreg(lp
, SR_AACK_I_AM_COORD
, 0);
766 at86rf212_set_txpower(struct ieee802154_dev
*dev
, int db
)
768 struct at86rf230_local
*lp
= dev
->priv
;
771 /* typical maximum output is 5dBm with RG_PHY_TX_PWR 0x60, lower five
772 * bits decrease power in 1dB steps. 0x60 represents extra PA gain of
774 * thus, supported values for db range from -26 to 5, for 31dB of
775 * reduction to 0dB of reduction.
777 if (db
> 5 || db
< -26)
782 rc
= __at86rf230_write(lp
, RG_PHY_TX_PWR
, 0x60 | db
);
790 at86rf212_set_lbt(struct ieee802154_dev
*dev
, bool on
)
792 struct at86rf230_local
*lp
= dev
->priv
;
794 return at86rf230_write_subreg(lp
, SR_CSMA_LBT_MODE
, on
);
797 static struct ieee802154_ops at86rf230_ops
= {
798 .owner
= THIS_MODULE
,
799 .xmit
= at86rf230_xmit
,
801 .set_channel
= at86rf230_channel
,
802 .start
= at86rf230_start
,
803 .stop
= at86rf230_stop
,
804 .set_hw_addr_filt
= at86rf230_set_hw_addr_filt
,
807 static struct ieee802154_ops at86rf212_ops
= {
808 .owner
= THIS_MODULE
,
809 .xmit
= at86rf230_xmit
,
811 .set_channel
= at86rf230_channel
,
812 .start
= at86rf230_start
,
813 .stop
= at86rf230_stop
,
814 .set_hw_addr_filt
= at86rf230_set_hw_addr_filt
,
815 .set_txpower
= at86rf212_set_txpower
,
816 .set_lbt
= at86rf212_set_lbt
,
819 static void at86rf230_irqwork(struct work_struct
*work
)
821 struct at86rf230_local
*lp
=
822 container_of(work
, struct at86rf230_local
, irqwork
);
827 rc
= at86rf230_read_subreg(lp
, RG_IRQ_STATUS
, 0xff, 0, &val
);
830 status
&= ~IRQ_PLL_LOCK
; /* ignore */
831 status
&= ~IRQ_RX_START
; /* ignore */
832 status
&= ~IRQ_AMI
; /* ignore */
833 status
&= ~IRQ_TRX_UR
; /* FIXME: possibly handle ???*/
835 if (status
& IRQ_TRX_END
) {
836 spin_lock_irqsave(&lp
->lock
, flags
);
837 status
&= ~IRQ_TRX_END
;
840 spin_unlock_irqrestore(&lp
->lock
, flags
);
841 complete(&lp
->tx_complete
);
843 spin_unlock_irqrestore(&lp
->lock
, flags
);
848 spin_lock_irqsave(&lp
->lock
, flags
);
850 spin_unlock_irqrestore(&lp
->lock
, flags
);
853 static void at86rf230_irqwork_level(struct work_struct
*work
)
855 struct at86rf230_local
*lp
=
856 container_of(work
, struct at86rf230_local
, irqwork
);
858 at86rf230_irqwork(work
);
860 enable_irq(lp
->spi
->irq
);
863 static irqreturn_t
at86rf230_isr(int irq
, void *data
)
865 struct at86rf230_local
*lp
= data
;
867 spin_lock(&lp
->lock
);
869 spin_unlock(&lp
->lock
);
871 schedule_work(&lp
->irqwork
);
876 static irqreturn_t
at86rf230_isr_level(int irq
, void *data
)
878 disable_irq_nosync(irq
);
880 return at86rf230_isr(irq
, data
);
883 static int at86rf230_irq_polarity(struct at86rf230_local
*lp
, int pol
)
885 return at86rf230_write_subreg(lp
, SR_IRQ_POLARITY
, pol
);
888 static int at86rf230_hw_init(struct at86rf230_local
*lp
)
890 struct at86rf230_platform_data
*pdata
= lp
->spi
->dev
.platform_data
;
894 rc
= at86rf230_read_subreg(lp
, SR_TRX_STATUS
, &status
);
898 dev_info(&lp
->spi
->dev
, "Status: %02x\n", status
);
899 if (status
== STATE_P_ON
) {
900 rc
= at86rf230_write_subreg(lp
, SR_TRX_CMD
,
901 STATE_FORCE_TRX_OFF
);
905 rc
= at86rf230_read_subreg(lp
, SR_TRX_STATUS
, &status
);
908 dev_info(&lp
->spi
->dev
, "Status: %02x\n", status
);
911 /* configure irq polarity, defaults to high active */
912 if (pdata
->irq_type
& (IRQF_TRIGGER_FALLING
| IRQF_TRIGGER_LOW
))
913 irq_pol
= IRQ_ACTIVE_LOW
;
915 irq_pol
= IRQ_ACTIVE_HIGH
;
917 rc
= at86rf230_irq_polarity(lp
, irq_pol
);
921 rc
= at86rf230_write_subreg(lp
, SR_IRQ_MASK
, IRQ_TRX_END
);
925 /* CLKM changes are applied immediately */
926 rc
= at86rf230_write_subreg(lp
, SR_CLKM_SHA_SEL
, 0x00);
931 rc
= at86rf230_write_subreg(lp
, SR_CLKM_CTRL
, 0x00);
934 /* Wait the next SLEEP cycle */
937 rc
= at86rf230_write_subreg(lp
, SR_TRX_CMD
, STATE_TX_ON
);
942 rc
= at86rf230_read_subreg(lp
, SR_TRX_STATUS
, &status
);
945 dev_info(&lp
->spi
->dev
, "Status: %02x\n", status
);
947 rc
= at86rf230_read_subreg(lp
, SR_DVDD_OK
, &status
);
951 dev_err(&lp
->spi
->dev
, "DVDD error\n");
955 rc
= at86rf230_read_subreg(lp
, SR_AVDD_OK
, &status
);
959 dev_err(&lp
->spi
->dev
, "AVDD error\n");
966 static int at86rf230_probe(struct spi_device
*spi
)
968 struct at86rf230_platform_data
*pdata
;
969 struct ieee802154_dev
*dev
;
970 struct at86rf230_local
*lp
;
972 u8 part
= 0, version
= 0, status
;
973 irq_handler_t irq_handler
;
974 work_func_t irq_worker
;
977 struct ieee802154_ops
*ops
= NULL
;
980 dev_err(&spi
->dev
, "no IRQ specified\n");
984 pdata
= spi
->dev
.platform_data
;
986 dev_err(&spi
->dev
, "no platform_data\n");
990 rc
= gpio_request(pdata
->rstn
, "rstn");
994 if (gpio_is_valid(pdata
->slp_tr
)) {
995 rc
= gpio_request(pdata
->slp_tr
, "slp_tr");
1000 rc
= gpio_direction_output(pdata
->rstn
, 1);
1004 if (gpio_is_valid(pdata
->slp_tr
)) {
1005 rc
= gpio_direction_output(pdata
->slp_tr
, 0);
1012 gpio_set_value(pdata
->rstn
, 0);
1014 gpio_set_value(pdata
->rstn
, 1);
1017 rc
= __at86rf230_detect_device(spi
, &man_id
, &part
, &version
);
1021 if (man_id
!= 0x001f) {
1022 dev_err(&spi
->dev
, "Non-Atmel dev found (MAN_ID %02x %02x)\n",
1023 man_id
>> 8, man_id
& 0xFF);
1031 /* FIXME: should be easy to support; */
1035 ops
= &at86rf230_ops
;
1040 ops
= &at86rf212_ops
;
1047 dev_info(&spi
->dev
, "Detected %s chip version %d\n", chip
, version
);
1053 dev
= ieee802154_alloc_device(sizeof(*lp
), ops
);
1066 dev
->parent
= &spi
->dev
;
1067 dev
->extra_tx_headroom
= 0;
1068 dev
->flags
= IEEE802154_HW_OMIT_CKSUM
| IEEE802154_HW_AACK
;
1070 if (pdata
->irq_type
& (IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
)) {
1071 irq_worker
= at86rf230_irqwork
;
1072 irq_handler
= at86rf230_isr
;
1074 irq_worker
= at86rf230_irqwork_level
;
1075 irq_handler
= at86rf230_isr_level
;
1078 mutex_init(&lp
->bmux
);
1079 INIT_WORK(&lp
->irqwork
, irq_worker
);
1080 spin_lock_init(&lp
->lock
);
1081 init_completion(&lp
->tx_complete
);
1083 spi_set_drvdata(spi
, lp
);
1086 dev
->phy
->channels_supported
[0] = 0x00007FF;
1087 dev
->phy
->channels_supported
[2] = 0x00007FF;
1089 dev
->phy
->channels_supported
[0] = 0x7FFF800;
1092 rc
= at86rf230_hw_init(lp
);
1096 rc
= request_irq(spi
->irq
, irq_handler
,
1097 IRQF_SHARED
| pdata
->irq_type
,
1098 dev_name(&spi
->dev
), lp
);
1102 /* Read irq status register to reset irq line */
1103 rc
= at86rf230_read_subreg(lp
, RG_IRQ_STATUS
, 0xff, 0, &status
);
1107 rc
= ieee802154_register_device(lp
->dev
);
1114 free_irq(spi
->irq
, lp
);
1116 flush_work(&lp
->irqwork
);
1117 spi_set_drvdata(spi
, NULL
);
1118 mutex_destroy(&lp
->bmux
);
1119 ieee802154_free_device(lp
->dev
);
1122 if (gpio_is_valid(pdata
->slp_tr
))
1123 gpio_free(pdata
->slp_tr
);
1125 gpio_free(pdata
->rstn
);
1129 static int at86rf230_remove(struct spi_device
*spi
)
1131 struct at86rf230_local
*lp
= spi_get_drvdata(spi
);
1132 struct at86rf230_platform_data
*pdata
= spi
->dev
.platform_data
;
1134 ieee802154_unregister_device(lp
->dev
);
1136 free_irq(spi
->irq
, lp
);
1137 flush_work(&lp
->irqwork
);
1139 if (gpio_is_valid(pdata
->slp_tr
))
1140 gpio_free(pdata
->slp_tr
);
1141 gpio_free(pdata
->rstn
);
1143 mutex_destroy(&lp
->bmux
);
1144 ieee802154_free_device(lp
->dev
);
1146 dev_dbg(&spi
->dev
, "unregistered at86rf230\n");
1150 static struct spi_driver at86rf230_driver
= {
1152 .name
= "at86rf230",
1153 .owner
= THIS_MODULE
,
1155 .probe
= at86rf230_probe
,
1156 .remove
= at86rf230_remove
,
1159 module_spi_driver(at86rf230_driver
);
1161 MODULE_DESCRIPTION("AT86RF230 Transceiver Driver");
1162 MODULE_LICENSE("GPL v2");