drivers/net/ieee802154/at86rf230.h

   1 /*
   2  * AT86RF230/RF231 driver
   3  *
   4  * Copyright (C) 2009-2012 Siemens AG
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2
   8  * as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * Written by:
  16  * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
  17  * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
  18  */
  19
  20 #ifndef _AT86RF230_H
  21 #define _AT86RF230_H
  22
  23 #define RG_TRX_STATUS   (0x01)
  24 #define SR_TRX_STATUS           0x01, 0x1f, 0
  25 #define SR_RESERVED_01_3        0x01, 0x20, 5
  26 #define SR_CCA_STATUS           0x01, 0x40, 6
  27 #define SR_CCA_DONE             0x01, 0x80, 7
  28 #define RG_TRX_STATE    (0x02)
  29 #define SR_TRX_CMD              0x02, 0x1f, 0
  30 #define SR_TRAC_STATUS          0x02, 0xe0, 5
  31 #define RG_TRX_CTRL_0   (0x03)
  32 #define SR_CLKM_CTRL            0x03, 0x07, 0
  33 #define SR_CLKM_SHA_SEL         0x03, 0x08, 3
  34 #define SR_PAD_IO_CLKM          0x03, 0x30, 4
  35 #define SR_PAD_IO               0x03, 0xc0, 6
  36 #define RG_TRX_CTRL_1   (0x04)
  37 #define SR_IRQ_POLARITY         0x04, 0x01, 0
  38 #define SR_IRQ_MASK_MODE        0x04, 0x02, 1
  39 #define SR_SPI_CMD_MODE         0x04, 0x0c, 2
  40 #define SR_RX_BL_CTRL           0x04, 0x10, 4
  41 #define SR_TX_AUTO_CRC_ON       0x04, 0x20, 5
  42 #define SR_IRQ_2_EXT_EN         0x04, 0x40, 6
  43 #define SR_PA_EXT_EN            0x04, 0x80, 7
  44 #define RG_PHY_TX_PWR   (0x05)
  45 #define SR_TX_PWR_23X           0x05, 0x0f, 0
  46 #define SR_PA_LT_230            0x05, 0x30, 4
  47 #define SR_PA_BUF_LT_230        0x05, 0xc0, 6
  48 #define SR_TX_PWR_212           0x05, 0x1f, 0
  49 #define SR_GC_PA_212            0x05, 0x60, 5
  50 #define SR_PA_BOOST_LT_212      0x05, 0x80, 7
  51 #define RG_PHY_RSSI     (0x06)
  52 #define SR_RSSI                 0x06, 0x1f, 0
  53 #define SR_RND_VALUE            0x06, 0x60, 5
  54 #define SR_RX_CRC_VALID         0x06, 0x80, 7
  55 #define RG_PHY_ED_LEVEL (0x07)
  56 #define SR_ED_LEVEL             0x07, 0xff, 0
  57 #define RG_PHY_CC_CCA   (0x08)
  58 #define SR_CHANNEL              0x08, 0x1f, 0
  59 #define SR_CCA_MODE             0x08, 0x60, 5
  60 #define SR_CCA_REQUEST          0x08, 0x80, 7
  61 #define RG_CCA_THRES    (0x09)
  62 #define SR_CCA_ED_THRES         0x09, 0x0f, 0
  63 #define SR_RESERVED_09_1        0x09, 0xf0, 4
  64 #define RG_RX_CTRL      (0x0a)
  65 #define SR_PDT_THRES            0x0a, 0x0f, 0
  66 #define SR_RESERVED_0a_1        0x0a, 0xf0, 4
  67 #define RG_SFD_VALUE    (0x0b)
  68 #define SR_SFD_VALUE            0x0b, 0xff, 0
  69 #define RG_TRX_CTRL_2   (0x0c)
  70 #define SR_OQPSK_DATA_RATE      0x0c, 0x03, 0
  71 #define SR_SUB_MODE             0x0c, 0x04, 2
  72 #define SR_BPSK_QPSK            0x0c, 0x08, 3
  73 #define SR_OQPSK_SUB1_RC_EN     0x0c, 0x10, 4
  74 #define SR_RESERVED_0c_5        0x0c, 0x60, 5
  75 #define SR_RX_SAFE_MODE         0x0c, 0x80, 7
  76 #define RG_ANT_DIV      (0x0d)
  77 #define SR_ANT_CTRL             0x0d, 0x03, 0
  78 #define SR_ANT_EXT_SW_EN        0x0d, 0x04, 2
  79 #define SR_ANT_DIV_EN           0x0d, 0x08, 3
  80 #define SR_RESERVED_0d_2        0x0d, 0x70, 4
  81 #define SR_ANT_SEL              0x0d, 0x80, 7
  82 #define RG_IRQ_MASK     (0x0e)
  83 #define SR_IRQ_MASK             0x0e, 0xff, 0
  84 #define RG_IRQ_STATUS   (0x0f)
  85 #define SR_IRQ_0_PLL_LOCK       0x0f, 0x01, 0
  86 #define SR_IRQ_1_PLL_UNLOCK     0x0f, 0x02, 1
  87 #define SR_IRQ_2_RX_START       0x0f, 0x04, 2
  88 #define SR_IRQ_3_TRX_END        0x0f, 0x08, 3
  89 #define SR_IRQ_4_CCA_ED_DONE    0x0f, 0x10, 4
  90 #define SR_IRQ_5_AMI            0x0f, 0x20, 5
  91 #define SR_IRQ_6_TRX_UR         0x0f, 0x40, 6
  92 #define SR_IRQ_7_BAT_LOW        0x0f, 0x80, 7
  93 #define RG_VREG_CTRL    (0x10)
  94 #define SR_RESERVED_10_6        0x10, 0x03, 0
  95 #define SR_DVDD_OK              0x10, 0x04, 2
  96 #define SR_DVREG_EXT            0x10, 0x08, 3
  97 #define SR_RESERVED_10_3        0x10, 0x30, 4
  98 #define SR_AVDD_OK              0x10, 0x40, 6
  99 #define SR_AVREG_EXT            0x10, 0x80, 7
 100 #define RG_BATMON       (0x11)
 101 #define SR_BATMON_VTH           0x11, 0x0f, 0
 102 #define SR_BATMON_HR            0x11, 0x10, 4
 103 #define SR_BATMON_OK            0x11, 0x20, 5
 104 #define SR_RESERVED_11_1        0x11, 0xc0, 6
 105 #define RG_XOSC_CTRL    (0x12)
 106 #define SR_XTAL_TRIM            0x12, 0x0f, 0
 107 #define SR_XTAL_MODE            0x12, 0xf0, 4
 108 #define RG_RX_SYN       (0x15)
 109 #define SR_RX_PDT_LEVEL         0x15, 0x0f, 0
 110 #define SR_RESERVED_15_2        0x15, 0x70, 4
 111 #define SR_RX_PDT_DIS           0x15, 0x80, 7
 112 #define RG_XAH_CTRL_1   (0x17)
 113 #define SR_RESERVED_17_8        0x17, 0x01, 0
 114 #define SR_AACK_PROM_MODE       0x17, 0x02, 1
 115 #define SR_AACK_ACK_TIME        0x17, 0x04, 2
 116 #define SR_RESERVED_17_5        0x17, 0x08, 3
 117 #define SR_AACK_UPLD_RES_FT     0x17, 0x10, 4
 118 #define SR_AACK_FLTR_RES_FT     0x17, 0x20, 5
 119 #define SR_CSMA_LBT_MODE        0x17, 0x40, 6
 120 #define SR_RESERVED_17_1        0x17, 0x80, 7
 121 #define RG_FTN_CTRL     (0x18)
 122 #define SR_RESERVED_18_2        0x18, 0x7f, 0
 123 #define SR_FTN_START            0x18, 0x80, 7
 124 #define RG_PLL_CF       (0x1a)
 125 #define SR_RESERVED_1a_2        0x1a, 0x7f, 0
 126 #define SR_PLL_CF_START         0x1a, 0x80, 7
 127 #define RG_PLL_DCU      (0x1b)
 128 #define SR_RESERVED_1b_3        0x1b, 0x3f, 0
 129 #define SR_RESERVED_1b_2        0x1b, 0x40, 6
 130 #define SR_PLL_DCU_START        0x1b, 0x80, 7
 131 #define RG_PART_NUM     (0x1c)
 132 #define SR_PART_NUM             0x1c, 0xff, 0
 133 #define RG_VERSION_NUM  (0x1d)
 134 #define SR_VERSION_NUM          0x1d, 0xff, 0
 135 #define RG_MAN_ID_0     (0x1e)
 136 #define SR_MAN_ID_0             0x1e, 0xff, 0
 137 #define RG_MAN_ID_1     (0x1f)
 138 #define SR_MAN_ID_1             0x1f, 0xff, 0
 139 #define RG_SHORT_ADDR_0 (0x20)
 140 #define SR_SHORT_ADDR_0         0x20, 0xff, 0
 141 #define RG_SHORT_ADDR_1 (0x21)
 142 #define SR_SHORT_ADDR_1         0x21, 0xff, 0
 143 #define RG_PAN_ID_0     (0x22)
 144 #define SR_PAN_ID_0             0x22, 0xff, 0
 145 #define RG_PAN_ID_1     (0x23)
 146 #define SR_PAN_ID_1             0x23, 0xff, 0
 147 #define RG_IEEE_ADDR_0  (0x24)
 148 #define SR_IEEE_ADDR_0          0x24, 0xff, 0
 149 #define RG_IEEE_ADDR_1  (0x25)
 150 #define SR_IEEE_ADDR_1          0x25, 0xff, 0
 151 #define RG_IEEE_ADDR_2  (0x26)
 152 #define SR_IEEE_ADDR_2          0x26, 0xff, 0
 153 #define RG_IEEE_ADDR_3  (0x27)
 154 #define SR_IEEE_ADDR_3          0x27, 0xff, 0
 155 #define RG_IEEE_ADDR_4  (0x28)
 156 #define SR_IEEE_ADDR_4          0x28, 0xff, 0
 157 #define RG_IEEE_ADDR_5  (0x29)
 158 #define SR_IEEE_ADDR_5          0x29, 0xff, 0
 159 #define RG_IEEE_ADDR_6  (0x2a)
 160 #define SR_IEEE_ADDR_6          0x2a, 0xff, 0
 161 #define RG_IEEE_ADDR_7  (0x2b)
 162 #define SR_IEEE_ADDR_7          0x2b, 0xff, 0
 163 #define RG_XAH_CTRL_0   (0x2c)
 164 #define SR_SLOTTED_OPERATION    0x2c, 0x01, 0
 165 #define SR_MAX_CSMA_RETRIES     0x2c, 0x0e, 1
 166 #define SR_MAX_FRAME_RETRIES    0x2c, 0xf0, 4
 167 #define RG_CSMA_SEED_0  (0x2d)
 168 #define SR_CSMA_SEED_0          0x2d, 0xff, 0
 169 #define RG_CSMA_SEED_1  (0x2e)
 170 #define SR_CSMA_SEED_1          0x2e, 0x07, 0
 171 #define SR_AACK_I_AM_COORD      0x2e, 0x08, 3
 172 #define SR_AACK_DIS_ACK         0x2e, 0x10, 4
 173 #define SR_AACK_SET_PD          0x2e, 0x20, 5
 174 #define SR_AACK_FVN_MODE        0x2e, 0xc0, 6
 175 #define RG_CSMA_BE      (0x2f)
 176 #define SR_MIN_BE               0x2f, 0x0f, 0
 177 #define SR_MAX_BE               0x2f, 0xf0, 4
 178
 179 #define CMD_REG         0x80
 180 #define CMD_REG_MASK    0x3f
 181 #define CMD_WRITE       0x40
 182 #define CMD_FB          0x20
 183
 184 #define IRQ_BAT_LOW     BIT(7)
 185 #define IRQ_TRX_UR      BIT(6)
 186 #define IRQ_AMI         BIT(5)
 187 #define IRQ_CCA_ED      BIT(4)
 188 #define IRQ_TRX_END     BIT(3)
 189 #define IRQ_RX_START    BIT(2)
 190 #define IRQ_PLL_UNL     BIT(1)
 191 #define IRQ_PLL_LOCK    BIT(0)
 192
 193 #define IRQ_ACTIVE_HIGH 0
 194 #define IRQ_ACTIVE_LOW  1
 195
 196 #define STATE_P_ON              0x00    /* BUSY */
 197 #define STATE_BUSY_RX           0x01
 198 #define STATE_BUSY_TX           0x02
 199 #define STATE_FORCE_TRX_OFF     0x03
 200 #define STATE_FORCE_TX_ON       0x04    /* IDLE */
 201 /* 0x05 */                              /* INVALID_PARAMETER */
 202 #define STATE_RX_ON             0x06
 203 /* 0x07 */                              /* SUCCESS */
 204 #define STATE_TRX_OFF           0x08
 205 #define STATE_TX_ON             0x09
 206 /* 0x0a - 0x0e */                       /* 0x0a - UNSUPPORTED_ATTRIBUTE */
 207 #define STATE_SLEEP             0x0F
 208 #define STATE_PREP_DEEP_SLEEP   0x10
 209 #define STATE_BUSY_RX_AACK      0x11
 210 #define STATE_BUSY_TX_ARET      0x12
 211 #define STATE_RX_AACK_ON        0x16
 212 #define STATE_TX_ARET_ON        0x19
 213 #define STATE_RX_ON_NOCLK       0x1C
 214 #define STATE_RX_AACK_ON_NOCLK  0x1D
 215 #define STATE_BUSY_RX_AACK_NOCLK 0x1E
 216 #define STATE_TRANSITION_IN_PROGRESS 0x1F
 217
 218 #define TRX_STATE_MASK          (0x1F)
 219 #define TRAC_MASK(x)            ((x & 0xe0) >> 5)
 220
 221 #define TRAC_SUCCESS                    0
 222 #define TRAC_SUCCESS_DATA_PENDING       1
 223 #define TRAC_SUCCESS_WAIT_FOR_ACK       2
 224 #define TRAC_CHANNEL_ACCESS_FAILURE     3
 225 #define TRAC_NO_ACK                     5
 226 #define TRAC_INVALID                    7
 227
 228 #endif /* !_AT86RF230_H */