2 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
4 * Copyright (C) 2012 Alan Ott <alan@signal11.us>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/spi/spi.h>
19 #include <linux/interrupt.h>
20 #include <linux/module.h>
21 #include <linux/regmap.h>
22 #include <linux/ieee802154.h>
23 #include <net/cfg802154.h>
24 #include <net/mac802154.h>
26 /* MRF24J40 Short Address Registers */
27 #define REG_RXMCR 0x00 /* Receive MAC control */
28 #define REG_PANIDL 0x01 /* PAN ID (low) */
29 #define REG_PANIDH 0x02 /* PAN ID (high) */
30 #define REG_SADRL 0x03 /* Short address (low) */
31 #define REG_SADRH 0x04 /* Short address (high) */
32 #define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */
33 #define REG_EADR1 0x06
34 #define REG_EADR2 0x07
35 #define REG_EADR3 0x08
36 #define REG_EADR4 0x09
37 #define REG_EADR5 0x0A
38 #define REG_EADR6 0x0B
39 #define REG_EADR7 0x0C
40 #define REG_RXFLUSH 0x0D
41 #define REG_ORDER 0x10
42 #define REG_TXMCR 0x11 /* Transmit MAC control */
43 #define REG_ACKTMOUT 0x12
44 #define REG_ESLOTG1 0x13
45 #define REG_SYMTICKL 0x14
46 #define REG_SYMTICKH 0x15
47 #define REG_PACON0 0x16 /* Power Amplifier Control */
48 #define REG_PACON1 0x17 /* Power Amplifier Control */
49 #define REG_PACON2 0x18 /* Power Amplifier Control */
50 #define REG_TXBCON0 0x1A
51 #define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
52 #define REG_TXG1CON 0x1C
53 #define REG_TXG2CON 0x1D
54 #define REG_ESLOTG23 0x1E
55 #define REG_ESLOTG45 0x1F
56 #define REG_ESLOTG67 0x20
57 #define REG_TXPEND 0x21
58 #define REG_WAKECON 0x22
59 #define REG_FROMOFFSET 0x23
60 #define REG_TXSTAT 0x24 /* TX MAC Status Register */
61 #define REG_TXBCON1 0x25
62 #define REG_GATECLK 0x26
63 #define REG_TXTIME 0x27
64 #define REG_HSYMTMRL 0x28
65 #define REG_HSYMTMRH 0x29
66 #define REG_SOFTRST 0x2A /* Soft Reset */
67 #define REG_SECCON0 0x2C
68 #define REG_SECCON1 0x2D
69 #define REG_TXSTBL 0x2E /* TX Stabilization */
71 #define REG_INTSTAT 0x31 /* Interrupt Status */
72 #define REG_INTCON 0x32 /* Interrupt Control */
73 #define REG_GPIO 0x33 /* GPIO */
74 #define REG_TRISGPIO 0x34 /* GPIO direction */
75 #define REG_SLPACK 0x35
76 #define REG_RFCTL 0x36 /* RF Control Mode Register */
77 #define REG_SECCR2 0x37
78 #define REG_BBREG0 0x38
79 #define REG_BBREG1 0x39 /* Baseband Registers */
80 #define REG_BBREG2 0x3A /* */
81 #define REG_BBREG3 0x3B
82 #define REG_BBREG4 0x3C
83 #define REG_BBREG6 0x3E /* */
84 #define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
86 /* MRF24J40 Long Address Registers */
87 #define REG_RFCON0 0x200 /* RF Control Registers */
88 #define REG_RFCON1 0x201
89 #define REG_RFCON2 0x202
90 #define REG_RFCON3 0x203
91 #define REG_RFCON5 0x205
92 #define REG_RFCON6 0x206
93 #define REG_RFCON7 0x207
94 #define REG_RFCON8 0x208
95 #define REG_SLPCAL0 0x209
96 #define REG_SLPCAL1 0x20A
97 #define REG_SLPCAL2 0x20B
98 #define REG_RFSTATE 0x20F
99 #define REG_RSSI 0x210
100 #define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
101 #define REG_SLPCON1 0x220
102 #define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
103 #define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
104 #define REG_REMCNTL 0x224
105 #define REG_REMCNTH 0x225
106 #define REG_MAINCNT0 0x226
107 #define REG_MAINCNT1 0x227
108 #define REG_MAINCNT2 0x228
109 #define REG_MAINCNT3 0x229
110 #define REG_TESTMODE 0x22F /* Test mode */
111 #define REG_ASSOEAR0 0x230
112 #define REG_ASSOEAR1 0x231
113 #define REG_ASSOEAR2 0x232
114 #define REG_ASSOEAR3 0x233
115 #define REG_ASSOEAR4 0x234
116 #define REG_ASSOEAR5 0x235
117 #define REG_ASSOEAR6 0x236
118 #define REG_ASSOEAR7 0x237
119 #define REG_ASSOSAR0 0x238
120 #define REG_ASSOSAR1 0x239
121 #define REG_UNONCE0 0x240
122 #define REG_UNONCE1 0x241
123 #define REG_UNONCE2 0x242
124 #define REG_UNONCE3 0x243
125 #define REG_UNONCE4 0x244
126 #define REG_UNONCE5 0x245
127 #define REG_UNONCE6 0x246
128 #define REG_UNONCE7 0x247
129 #define REG_UNONCE8 0x248
130 #define REG_UNONCE9 0x249
131 #define REG_UNONCE10 0x24A
132 #define REG_UNONCE11 0x24B
133 #define REG_UNONCE12 0x24C
134 #define REG_RX_FIFO 0x300 /* Receive FIFO */
136 /* Device configuration: Only channels 11-26 on page 0 are supported. */
137 #define MRF24J40_CHAN_MIN 11
138 #define MRF24J40_CHAN_MAX 26
139 #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
140 - ((u32)1 << MRF24J40_CHAN_MIN))
142 #define TX_FIFO_SIZE 128 /* From datasheet */
143 #define RX_FIFO_SIZE 144 /* From datasheet */
144 #define SET_CHANNEL_DELAY_US 192 /* From datasheet */
146 enum mrf24j40_modules
{ MRF24J40
, MRF24J40MA
, MRF24J40MC
};
148 /* Device Private Data */
150 struct spi_device
*spi
;
151 struct ieee802154_hw
*hw
;
153 struct regmap
*regmap_short
;
154 struct regmap
*regmap_long
;
155 struct mutex buffer_mutex
; /* only used to protect buf */
156 struct completion tx_complete
;
157 u8
*buf
; /* 3 bytes. Used for SPI single-register transfers. */
160 /* regmap information for short address register access */
161 #define MRF24J40_SHORT_WRITE 0x01
162 #define MRF24J40_SHORT_READ 0x00
163 #define MRF24J40_SHORT_NUMREGS 0x3F
165 /* regmap information for long address register access */
166 #define MRF24J40_LONG_ACCESS 0x80
167 #define MRF24J40_LONG_NUMREGS 0x38F
169 /* Read/Write SPI Commands for Short and Long Address registers. */
170 #define MRF24J40_READSHORT(reg) ((reg) << 1)
171 #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
172 #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
173 #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
175 /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
176 #define MAX_SPI_SPEED_HZ 10000000
178 #define printdev(X) (&X->spi->dev)
181 mrf24j40_short_reg_writeable(struct device
*dev
, unsigned int reg
)
246 mrf24j40_short_reg_readable(struct device
*dev
, unsigned int reg
)
250 /* all writeable are also readable */
251 rc
= mrf24j40_short_reg_writeable(dev
, reg
);
266 mrf24j40_short_reg_volatile(struct device
*dev
, unsigned int reg
)
268 /* can be changed during runtime */
285 /* use them in spi_async and regmap so it's volatile */
294 mrf24j40_short_reg_precious(struct device
*dev
, unsigned int reg
)
296 /* don't clear irq line on read */
305 static const struct regmap_config mrf24j40_short_regmap
= {
306 .name
= "mrf24j40_short",
310 .write_flag_mask
= MRF24J40_SHORT_WRITE
,
311 .read_flag_mask
= MRF24J40_SHORT_READ
,
312 .cache_type
= REGCACHE_RBTREE
,
313 .max_register
= MRF24J40_SHORT_NUMREGS
,
314 .writeable_reg
= mrf24j40_short_reg_writeable
,
315 .readable_reg
= mrf24j40_short_reg_readable
,
316 .volatile_reg
= mrf24j40_short_reg_volatile
,
317 .precious_reg
= mrf24j40_short_reg_precious
,
321 mrf24j40_long_reg_writeable(struct device
*dev
, unsigned int reg
)
374 mrf24j40_long_reg_readable(struct device
*dev
, unsigned int reg
)
378 /* all writeable are also readable */
379 rc
= mrf24j40_long_reg_writeable(dev
, reg
);
396 mrf24j40_long_reg_volatile(struct device
*dev
, unsigned int reg
)
398 /* can be changed during runtime */
412 static const struct regmap_config mrf24j40_long_regmap
= {
413 .name
= "mrf24j40_long",
417 .write_flag_mask
= MRF24J40_LONG_ACCESS
,
418 .read_flag_mask
= MRF24J40_LONG_ACCESS
,
419 .cache_type
= REGCACHE_RBTREE
,
420 .max_register
= MRF24J40_LONG_NUMREGS
,
421 .writeable_reg
= mrf24j40_long_reg_writeable
,
422 .readable_reg
= mrf24j40_long_reg_readable
,
423 .volatile_reg
= mrf24j40_long_reg_volatile
,
426 static int mrf24j40_long_regmap_write(void *context
, const void *data
,
429 struct spi_device
*spi
= context
;
435 /* regmap supports read/write mask only in frist byte
436 * long write access need to set the 12th bit, so we
437 * make special handling for write.
439 memcpy(buf
, data
, count
);
442 return spi_write(spi
, buf
, count
);
446 mrf24j40_long_regmap_read(void *context
, const void *reg
, size_t reg_size
,
447 void *val
, size_t val_size
)
449 struct spi_device
*spi
= context
;
451 return spi_write_then_read(spi
, reg
, reg_size
, val
, val_size
);
454 static const struct regmap_bus mrf24j40_long_regmap_bus
= {
455 .write
= mrf24j40_long_regmap_write
,
456 .read
= mrf24j40_long_regmap_read
,
457 .reg_format_endian_default
= REGMAP_ENDIAN_BIG
,
458 .val_format_endian_default
= REGMAP_ENDIAN_BIG
,
461 static int write_short_reg(struct mrf24j40
*devrec
, u8 reg
, u8 value
)
464 struct spi_message msg
;
465 struct spi_transfer xfer
= {
467 .tx_buf
= devrec
->buf
,
468 .rx_buf
= devrec
->buf
,
471 spi_message_init(&msg
);
472 spi_message_add_tail(&xfer
, &msg
);
474 mutex_lock(&devrec
->buffer_mutex
);
475 devrec
->buf
[0] = MRF24J40_WRITESHORT(reg
);
476 devrec
->buf
[1] = value
;
478 ret
= spi_sync(devrec
->spi
, &msg
);
480 dev_err(printdev(devrec
),
481 "SPI write Failed for short register 0x%hhx\n", reg
);
483 mutex_unlock(&devrec
->buffer_mutex
);
487 static int read_short_reg(struct mrf24j40
*devrec
, u8 reg
, u8
*val
)
490 struct spi_message msg
;
491 struct spi_transfer xfer
= {
493 .tx_buf
= devrec
->buf
,
494 .rx_buf
= devrec
->buf
,
497 spi_message_init(&msg
);
498 spi_message_add_tail(&xfer
, &msg
);
500 mutex_lock(&devrec
->buffer_mutex
);
501 devrec
->buf
[0] = MRF24J40_READSHORT(reg
);
504 ret
= spi_sync(devrec
->spi
, &msg
);
506 dev_err(printdev(devrec
),
507 "SPI read Failed for short register 0x%hhx\n", reg
);
509 *val
= devrec
->buf
[1];
511 mutex_unlock(&devrec
->buffer_mutex
);
515 static int read_long_reg(struct mrf24j40
*devrec
, u16 reg
, u8
*value
)
519 struct spi_message msg
;
520 struct spi_transfer xfer
= {
522 .tx_buf
= devrec
->buf
,
523 .rx_buf
= devrec
->buf
,
526 spi_message_init(&msg
);
527 spi_message_add_tail(&xfer
, &msg
);
529 cmd
= MRF24J40_READLONG(reg
);
530 mutex_lock(&devrec
->buffer_mutex
);
531 devrec
->buf
[0] = cmd
>> 8 & 0xff;
532 devrec
->buf
[1] = cmd
& 0xff;
535 ret
= spi_sync(devrec
->spi
, &msg
);
537 dev_err(printdev(devrec
),
538 "SPI read Failed for long register 0x%hx\n", reg
);
540 *value
= devrec
->buf
[2];
542 mutex_unlock(&devrec
->buffer_mutex
);
546 static int write_long_reg(struct mrf24j40
*devrec
, u16 reg
, u8 val
)
550 struct spi_message msg
;
551 struct spi_transfer xfer
= {
553 .tx_buf
= devrec
->buf
,
554 .rx_buf
= devrec
->buf
,
557 spi_message_init(&msg
);
558 spi_message_add_tail(&xfer
, &msg
);
560 cmd
= MRF24J40_WRITELONG(reg
);
561 mutex_lock(&devrec
->buffer_mutex
);
562 devrec
->buf
[0] = cmd
>> 8 & 0xff;
563 devrec
->buf
[1] = cmd
& 0xff;
564 devrec
->buf
[2] = val
;
566 ret
= spi_sync(devrec
->spi
, &msg
);
568 dev_err(printdev(devrec
),
569 "SPI write Failed for long register 0x%hx\n", reg
);
571 mutex_unlock(&devrec
->buffer_mutex
);
575 /* This function relies on an undocumented write method. Once a write command
576 and address is set, as many bytes of data as desired can be clocked into
577 the device. The datasheet only shows setting one byte at a time. */
578 static int write_tx_buf(struct mrf24j40
*devrec
, u16 reg
,
579 const u8
*data
, size_t length
)
584 struct spi_message msg
;
585 struct spi_transfer addr_xfer
= {
587 .tx_buf
= devrec
->buf
,
589 struct spi_transfer lengths_xfer
= {
591 .tx_buf
= &lengths
, /* TODO: Is DMA really required for SPI? */
593 struct spi_transfer data_xfer
= {
598 /* Range check the length. 2 bytes are used for the length fields.*/
599 if (length
> TX_FIFO_SIZE
-2) {
600 dev_err(printdev(devrec
), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
601 length
= TX_FIFO_SIZE
-2;
604 spi_message_init(&msg
);
605 spi_message_add_tail(&addr_xfer
, &msg
);
606 spi_message_add_tail(&lengths_xfer
, &msg
);
607 spi_message_add_tail(&data_xfer
, &msg
);
609 cmd
= MRF24J40_WRITELONG(reg
);
610 mutex_lock(&devrec
->buffer_mutex
);
611 devrec
->buf
[0] = cmd
>> 8 & 0xff;
612 devrec
->buf
[1] = cmd
& 0xff;
613 lengths
[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
614 lengths
[1] = length
; /* Total length */
616 ret
= spi_sync(devrec
->spi
, &msg
);
618 dev_err(printdev(devrec
), "SPI write Failed for TX buf\n");
620 mutex_unlock(&devrec
->buffer_mutex
);
624 static int mrf24j40_read_rx_buf(struct mrf24j40
*devrec
,
625 u8
*data
, u8
*len
, u8
*lqi
)
632 struct spi_message msg
;
633 struct spi_transfer addr_xfer
= {
637 struct spi_transfer data_xfer
= {
638 .len
= 0x0, /* set below */
641 struct spi_transfer status_xfer
= {
646 /* Get the length of the data in the RX FIFO. The length in this
647 * register exclues the 1-byte length field at the beginning. */
648 ret
= read_long_reg(devrec
, REG_RX_FIFO
, &rx_len
);
652 /* Range check the RX FIFO length, accounting for the one-byte
653 * length field at the beginning. */
654 if (rx_len
> RX_FIFO_SIZE
-1) {
655 dev_err(printdev(devrec
), "Invalid length read from device. Performing short read.\n");
656 rx_len
= RX_FIFO_SIZE
-1;
660 /* Passed in buffer wasn't big enough. Should never happen. */
661 dev_err(printdev(devrec
), "Buffer not big enough. Performing short read\n");
665 /* Set up the commands to read the data. */
666 cmd
= MRF24J40_READLONG(REG_RX_FIFO
+1);
667 addr
[0] = cmd
>> 8 & 0xff;
668 addr
[1] = cmd
& 0xff;
669 data_xfer
.len
= rx_len
;
671 spi_message_init(&msg
);
672 spi_message_add_tail(&addr_xfer
, &msg
);
673 spi_message_add_tail(&data_xfer
, &msg
);
674 spi_message_add_tail(&status_xfer
, &msg
);
676 ret
= spi_sync(devrec
->spi
, &msg
);
678 dev_err(printdev(devrec
), "SPI RX Buffer Read Failed.\n");
686 print_hex_dump(KERN_DEBUG
, "mrf24j40 rx: ",
687 DUMP_PREFIX_OFFSET
, 16, 1, data
, *len
, 0);
688 pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
689 lqi_rssi
[0], lqi_rssi
[1]);
696 static int mrf24j40_tx(struct ieee802154_hw
*hw
, struct sk_buff
*skb
)
698 struct mrf24j40
*devrec
= hw
->priv
;
702 dev_dbg(printdev(devrec
), "tx packet of %d bytes\n", skb
->len
);
704 ret
= write_tx_buf(devrec
, 0x000, skb
->data
, skb
->len
);
708 reinit_completion(&devrec
->tx_complete
);
710 /* Set TXNTRIG bit of TXNCON to send packet */
711 ret
= read_short_reg(devrec
, REG_TXNCON
, &val
);
715 /* Set TXNACKREQ if the ACK bit is set in the packet. */
716 if (skb
->data
[0] & IEEE802154_FC_ACK_REQ
)
718 write_short_reg(devrec
, REG_TXNCON
, val
);
720 /* Wait for the device to send the TX complete interrupt. */
721 ret
= wait_for_completion_interruptible_timeout(
722 &devrec
->tx_complete
,
724 if (ret
== -ERESTARTSYS
)
727 dev_warn(printdev(devrec
), "Timeout waiting for TX interrupt\n");
732 /* Check for send error from the device. */
733 ret
= read_short_reg(devrec
, REG_TXSTAT
, &val
);
737 dev_dbg(printdev(devrec
), "Error Sending. Retry count exceeded\n");
738 ret
= -ECOMM
; /* TODO: Better error code ? */
740 dev_dbg(printdev(devrec
), "Packet Sent\n");
747 static int mrf24j40_ed(struct ieee802154_hw
*hw
, u8
*level
)
750 pr_warn("mrf24j40: ed not implemented\n");
755 static int mrf24j40_start(struct ieee802154_hw
*hw
)
757 struct mrf24j40
*devrec
= hw
->priv
;
761 dev_dbg(printdev(devrec
), "start\n");
763 ret
= read_short_reg(devrec
, REG_INTCON
, &val
);
766 val
&= ~(0x1|0x8); /* Clear TXNIE and RXIE. Enable interrupts */
767 write_short_reg(devrec
, REG_INTCON
, val
);
772 static void mrf24j40_stop(struct ieee802154_hw
*hw
)
774 struct mrf24j40
*devrec
= hw
->priv
;
778 dev_dbg(printdev(devrec
), "stop\n");
780 ret
= read_short_reg(devrec
, REG_INTCON
, &val
);
783 val
|= 0x1|0x8; /* Set TXNIE and RXIE. Disable Interrupts */
784 write_short_reg(devrec
, REG_INTCON
, val
);
787 static int mrf24j40_set_channel(struct ieee802154_hw
*hw
, u8 page
, u8 channel
)
789 struct mrf24j40
*devrec
= hw
->priv
;
793 dev_dbg(printdev(devrec
), "Set Channel %d\n", channel
);
796 WARN_ON(channel
< MRF24J40_CHAN_MIN
);
797 WARN_ON(channel
> MRF24J40_CHAN_MAX
);
799 /* Set Channel TODO */
800 val
= (channel
-11) << 4 | 0x03;
801 write_long_reg(devrec
, REG_RFCON0
, val
);
804 ret
= read_short_reg(devrec
, REG_RFCTL
, &val
);
808 write_short_reg(devrec
, REG_RFCTL
, val
);
810 write_short_reg(devrec
, REG_RFCTL
, val
);
812 udelay(SET_CHANNEL_DELAY_US
); /* per datasheet */
817 static int mrf24j40_filter(struct ieee802154_hw
*hw
,
818 struct ieee802154_hw_addr_filt
*filt
,
819 unsigned long changed
)
821 struct mrf24j40
*devrec
= hw
->priv
;
823 dev_dbg(printdev(devrec
), "filter\n");
825 if (changed
& IEEE802154_AFILT_SADDR_CHANGED
) {
829 addrh
= le16_to_cpu(filt
->short_addr
) >> 8 & 0xff;
830 addrl
= le16_to_cpu(filt
->short_addr
) & 0xff;
832 write_short_reg(devrec
, REG_SADRH
, addrh
);
833 write_short_reg(devrec
, REG_SADRL
, addrl
);
834 dev_dbg(printdev(devrec
),
835 "Set short addr to %04hx\n", filt
->short_addr
);
838 if (changed
& IEEE802154_AFILT_IEEEADDR_CHANGED
) {
842 memcpy(addr
, &filt
->ieee_addr
, 8);
843 for (i
= 0; i
< 8; i
++)
844 write_short_reg(devrec
, REG_EADR0
+ i
, addr
[i
]);
847 pr_debug("Set long addr to: ");
848 for (i
= 0; i
< 8; i
++)
849 pr_debug("%02hhx ", addr
[7 - i
]);
854 if (changed
& IEEE802154_AFILT_PANID_CHANGED
) {
858 panidh
= le16_to_cpu(filt
->pan_id
) >> 8 & 0xff;
859 panidl
= le16_to_cpu(filt
->pan_id
) & 0xff;
860 write_short_reg(devrec
, REG_PANIDH
, panidh
);
861 write_short_reg(devrec
, REG_PANIDL
, panidl
);
863 dev_dbg(printdev(devrec
), "Set PANID to %04hx\n", filt
->pan_id
);
866 if (changed
& IEEE802154_AFILT_PANC_CHANGED
) {
867 /* Pan Coordinator */
871 ret
= read_short_reg(devrec
, REG_RXMCR
, &val
);
878 write_short_reg(devrec
, REG_RXMCR
, val
);
880 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
881 * REG_ORDER is maintained as default (no beacon/superframe).
884 dev_dbg(printdev(devrec
), "Set Pan Coord to %s\n",
885 filt
->pan_coord
? "on" : "off");
891 static int mrf24j40_handle_rx(struct mrf24j40
*devrec
)
893 u8 len
= RX_FIFO_SIZE
;
900 /* Turn off reception of packets off the air. This prevents the
901 * device from overwriting the buffer while we're reading it. */
902 ret
= read_short_reg(devrec
, REG_BBREG1
, &val
);
905 val
|= 4; /* SET RXDECINV */
906 write_short_reg(devrec
, REG_BBREG1
, val
);
908 skb
= dev_alloc_skb(len
);
914 ret
= mrf24j40_read_rx_buf(devrec
, skb_put(skb
, len
), &len
, &lqi
);
916 dev_err(printdev(devrec
), "Failure reading RX FIFO\n");
922 /* Cut off the checksum */
923 skb_trim(skb
, len
-2);
925 /* TODO: Other drivers call ieee20154_rx_irqsafe() here (eg: cc2040,
926 * also from a workqueue). I think irqsafe is not necessary here.
927 * Can someone confirm? */
928 ieee802154_rx_irqsafe(devrec
->hw
, skb
, lqi
);
930 dev_dbg(printdev(devrec
), "RX Handled\n");
933 /* Turn back on reception of packets off the air. */
934 ret2
= read_short_reg(devrec
, REG_BBREG1
, &val
);
937 val
&= ~0x4; /* Clear RXDECINV */
938 write_short_reg(devrec
, REG_BBREG1
, val
);
943 static const struct ieee802154_ops mrf24j40_ops
= {
944 .owner
= THIS_MODULE
,
945 .xmit_sync
= mrf24j40_tx
,
947 .start
= mrf24j40_start
,
948 .stop
= mrf24j40_stop
,
949 .set_channel
= mrf24j40_set_channel
,
950 .set_hw_addr_filt
= mrf24j40_filter
,
953 static irqreturn_t
mrf24j40_isr(int irq
, void *data
)
955 struct mrf24j40
*devrec
= data
;
959 /* Read the interrupt status */
960 ret
= read_short_reg(devrec
, REG_INTSTAT
, &intstat
);
964 /* Check for TX complete */
966 complete(&devrec
->tx_complete
);
970 mrf24j40_handle_rx(devrec
);
976 static int mrf24j40_hw_init(struct mrf24j40
*devrec
)
981 /* Initialize the device.
982 From datasheet section 3.2: Initialization. */
983 ret
= write_short_reg(devrec
, REG_SOFTRST
, 0x07);
987 ret
= write_short_reg(devrec
, REG_PACON2
, 0x98);
991 ret
= write_short_reg(devrec
, REG_TXSTBL
, 0x95);
995 ret
= write_long_reg(devrec
, REG_RFCON0
, 0x03);
999 ret
= write_long_reg(devrec
, REG_RFCON1
, 0x01);
1003 ret
= write_long_reg(devrec
, REG_RFCON2
, 0x80);
1007 ret
= write_long_reg(devrec
, REG_RFCON6
, 0x90);
1011 ret
= write_long_reg(devrec
, REG_RFCON7
, 0x80);
1015 ret
= write_long_reg(devrec
, REG_RFCON8
, 0x10);
1019 ret
= write_long_reg(devrec
, REG_SLPCON1
, 0x21);
1023 ret
= write_short_reg(devrec
, REG_BBREG2
, 0x80);
1027 ret
= write_short_reg(devrec
, REG_CCAEDTH
, 0x60);
1031 ret
= write_short_reg(devrec
, REG_BBREG6
, 0x40);
1035 ret
= write_short_reg(devrec
, REG_RFCTL
, 0x04);
1039 ret
= write_short_reg(devrec
, REG_RFCTL
, 0x0);
1045 /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
1046 ret
= read_short_reg(devrec
, REG_RXMCR
, &val
);
1050 val
&= ~0x3; /* Clear RX mode (normal) */
1052 ret
= write_short_reg(devrec
, REG_RXMCR
, val
);
1056 if (spi_get_device_id(devrec
->spi
)->driver_data
== MRF24J40MC
) {
1057 /* Enable external amplifier.
1058 * From MRF24J40MC datasheet section 1.3: Operation.
1060 read_long_reg(devrec
, REG_TESTMODE
, &val
);
1061 val
|= 0x7; /* Configure GPIO 0-2 to control amplifier */
1062 write_long_reg(devrec
, REG_TESTMODE
, val
);
1064 read_short_reg(devrec
, REG_TRISGPIO
, &val
);
1065 val
|= 0x8; /* Set GPIO3 as output. */
1066 write_short_reg(devrec
, REG_TRISGPIO
, val
);
1068 read_short_reg(devrec
, REG_GPIO
, &val
);
1069 val
|= 0x8; /* Set GPIO3 HIGH to enable U5 voltage regulator */
1070 write_short_reg(devrec
, REG_GPIO
, val
);
1072 /* Reduce TX pwr to meet FCC requirements.
1073 * From MRF24J40MC datasheet section 3.1.1
1075 write_long_reg(devrec
, REG_RFCON3
, 0x28);
1084 static void mrf24j40_phy_setup(struct mrf24j40
*devrec
)
1086 ieee802154_random_extended_addr(&devrec
->hw
->phy
->perm_extended_addr
);
1087 devrec
->hw
->phy
->current_channel
= 11;
1090 static int mrf24j40_probe(struct spi_device
*spi
)
1093 struct ieee802154_hw
*hw
;
1094 struct mrf24j40
*devrec
;
1096 dev_info(&spi
->dev
, "probe(). IRQ: %d\n", spi
->irq
);
1098 /* Register with the 802154 subsystem */
1100 hw
= ieee802154_alloc_hw(sizeof(*devrec
), &mrf24j40_ops
);
1106 spi_set_drvdata(spi
, devrec
);
1108 devrec
->hw
->parent
= &spi
->dev
;
1109 devrec
->hw
->phy
->supported
.channels
[0] = CHANNEL_MASK
;
1110 devrec
->hw
->flags
= IEEE802154_HW_OMIT_CKSUM
| IEEE802154_HW_AFILT
;
1112 devrec
->regmap_short
= devm_regmap_init_spi(spi
,
1113 &mrf24j40_short_regmap
);
1114 if (IS_ERR(devrec
->regmap_short
)) {
1115 ret
= PTR_ERR(devrec
->regmap_short
);
1116 dev_err(&spi
->dev
, "Failed to allocate short register map: %d\n",
1118 goto err_register_device
;
1121 devrec
->regmap_long
= devm_regmap_init(&spi
->dev
,
1122 &mrf24j40_long_regmap_bus
,
1123 spi
, &mrf24j40_long_regmap
);
1124 if (IS_ERR(devrec
->regmap_long
)) {
1125 ret
= PTR_ERR(devrec
->regmap_long
);
1126 dev_err(&spi
->dev
, "Failed to allocate long register map: %d\n",
1128 goto err_register_device
;
1131 devrec
->buf
= devm_kzalloc(&spi
->dev
, 3, GFP_KERNEL
);
1133 goto err_register_device
;
1135 if (spi
->max_speed_hz
> MAX_SPI_SPEED_HZ
) {
1136 dev_warn(&spi
->dev
, "spi clock above possible maximum: %d",
1141 mutex_init(&devrec
->buffer_mutex
);
1142 init_completion(&devrec
->tx_complete
);
1144 ret
= mrf24j40_hw_init(devrec
);
1146 goto err_register_device
;
1148 mrf24j40_phy_setup(devrec
);
1150 ret
= devm_request_threaded_irq(&spi
->dev
,
1154 IRQF_TRIGGER_LOW
|IRQF_ONESHOT
,
1155 dev_name(&spi
->dev
),
1159 dev_err(printdev(devrec
), "Unable to get IRQ");
1160 goto err_register_device
;
1163 dev_dbg(printdev(devrec
), "registered mrf24j40\n");
1164 ret
= ieee802154_register_hw(devrec
->hw
);
1166 goto err_register_device
;
1170 err_register_device
:
1171 ieee802154_free_hw(devrec
->hw
);
1176 static int mrf24j40_remove(struct spi_device
*spi
)
1178 struct mrf24j40
*devrec
= spi_get_drvdata(spi
);
1180 dev_dbg(printdev(devrec
), "remove\n");
1182 ieee802154_unregister_hw(devrec
->hw
);
1183 ieee802154_free_hw(devrec
->hw
);
1184 /* TODO: Will ieee802154_free_device() wait until ->xmit() is
1190 static const struct of_device_id mrf24j40_of_match
[] = {
1191 { .compatible
= "microchip,mrf24j40", .data
= (void *)MRF24J40
},
1192 { .compatible
= "microchip,mrf24j40ma", .data
= (void *)MRF24J40MA
},
1193 { .compatible
= "microchip,mrf24j40mc", .data
= (void *)MRF24J40MC
},
1196 MODULE_DEVICE_TABLE(of
, mrf24j40_of_match
);
1198 static const struct spi_device_id mrf24j40_ids
[] = {
1199 { "mrf24j40", MRF24J40
},
1200 { "mrf24j40ma", MRF24J40MA
},
1201 { "mrf24j40mc", MRF24J40MC
},
1204 MODULE_DEVICE_TABLE(spi
, mrf24j40_ids
);
1206 static struct spi_driver mrf24j40_driver
= {
1208 .of_match_table
= of_match_ptr(mrf24j40_of_match
),
1210 .owner
= THIS_MODULE
,
1212 .id_table
= mrf24j40_ids
,
1213 .probe
= mrf24j40_probe
,
1214 .remove
= mrf24j40_remove
,
1217 module_spi_driver(mrf24j40_driver
);
1219 MODULE_LICENSE("GPL");
1220 MODULE_AUTHOR("Alan Ott");
1221 MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");