drivers/net/irda/au1k_ir.c

   1 /*
   2  * Alchemy Semi Au1000 IrDA driver
   3  *
   4  * Copyright 2001 MontaVista Software Inc.
   5  * Author: MontaVista Software, Inc.
   6  *              ppopov@mvista.com or source@mvista.com
   7  *
   8  *  This program is free software; you can distribute it and/or modify it
   9  *  under the terms of the GNU General Public License (Version 2) as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15  *  for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/module.h>
  23 #include <linux/netdevice.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/types.h>
  28
  29 #include <net/irda/irda.h>
  30 #include <net/irda/irmod.h>
  31 #include <net/irda/wrapper.h>
  32 #include <net/irda/irda_device.h>
  33 #include <asm/mach-au1x00/au1000.h>
  34
  35 /* registers */
  36 #define IR_RING_PTR_STATUS      0x00
  37 #define IR_RING_BASE_ADDR_H     0x04
  38 #define IR_RING_BASE_ADDR_L     0x08
  39 #define IR_RING_SIZE            0x0C
  40 #define IR_RING_PROMPT          0x10
  41 #define IR_RING_ADDR_CMPR       0x14
  42 #define IR_INT_CLEAR            0x18
  43 #define IR_CONFIG_1             0x20
  44 #define IR_SIR_FLAGS            0x24
  45 #define IR_STATUS               0x28
  46 #define IR_READ_PHY_CONFIG      0x2C
  47 #define IR_WRITE_PHY_CONFIG     0x30
  48 #define IR_MAX_PKT_LEN          0x34
  49 #define IR_RX_BYTE_CNT          0x38
  50 #define IR_CONFIG_2             0x3C
  51 #define IR_ENABLE               0x40
  52
  53 /* Config1 */
  54 #define IR_RX_INVERT_LED        (1 << 0)
  55 #define IR_TX_INVERT_LED        (1 << 1)
  56 #define IR_ST                   (1 << 2)
  57 #define IR_SF                   (1 << 3)
  58 #define IR_SIR                  (1 << 4)
  59 #define IR_MIR                  (1 << 5)
  60 #define IR_FIR                  (1 << 6)
  61 #define IR_16CRC                (1 << 7)
  62 #define IR_TD                   (1 << 8)
  63 #define IR_RX_ALL               (1 << 9)
  64 #define IR_DMA_ENABLE           (1 << 10)
  65 #define IR_RX_ENABLE            (1 << 11)
  66 #define IR_TX_ENABLE            (1 << 12)
  67 #define IR_LOOPBACK             (1 << 14)
  68 #define IR_SIR_MODE             (IR_SIR | IR_DMA_ENABLE | \
  69                                  IR_RX_ALL | IR_RX_ENABLE | IR_SF | \
  70                                  IR_16CRC)
  71
  72 /* ir_status */
  73 #define IR_RX_STATUS            (1 << 9)
  74 #define IR_TX_STATUS            (1 << 10)
  75 #define IR_PHYEN                (1 << 15)
  76
  77 /* ir_write_phy_config */
  78 #define IR_BR(x)                (((x) & 0x3f) << 10)    /* baud rate */
  79 #define IR_PW(x)                (((x) & 0x1f) << 5)     /* pulse width */
  80 #define IR_P(x)                 ((x) & 0x1f)            /* preamble bits */
  81
  82 /* Config2 */
  83 #define IR_MODE_INV             (1 << 0)
  84 #define IR_ONE_PIN              (1 << 1)
  85 #define IR_PHYCLK_40MHZ         (0 << 2)
  86 #define IR_PHYCLK_48MHZ         (1 << 2)
  87 #define IR_PHYCLK_56MHZ         (2 << 2)
  88 #define IR_PHYCLK_64MHZ         (3 << 2)
  89 #define IR_DP                   (1 << 4)
  90 #define IR_DA                   (1 << 5)
  91 #define IR_FLT_HIGH             (0 << 6)
  92 #define IR_FLT_MEDHI            (1 << 6)
  93 #define IR_FLT_MEDLO            (2 << 6)
  94 #define IR_FLT_LO               (3 << 6)
  95 #define IR_IEN                  (1 << 8)
  96
  97 /* ir_enable */
  98 #define IR_HC                   (1 << 3)        /* divide SBUS clock by 2 */
  99 #define IR_CE                   (1 << 2)        /* clock enable */
 100 #define IR_C                    (1 << 1)        /* coherency bit */
 101 #define IR_BE                   (1 << 0)        /* set in big endian mode */
 102
 103 #define NUM_IR_DESC     64
 104 #define RING_SIZE_4     0x0
 105 #define RING_SIZE_16    0x3
 106 #define RING_SIZE_64    0xF
 107 #define MAX_NUM_IR_DESC 64
 108 #define MAX_BUF_SIZE    2048
 109
 110 /* Ring descriptor flags */
 111 #define AU_OWN          (1 << 7) /* tx,rx */
 112 #define IR_DIS_CRC      (1 << 6) /* tx */
 113 #define IR_BAD_CRC      (1 << 5) /* tx */
 114 #define IR_NEED_PULSE   (1 << 4) /* tx */
 115 #define IR_FORCE_UNDER  (1 << 3) /* tx */
 116 #define IR_DISABLE_TX   (1 << 2) /* tx */
 117 #define IR_HW_UNDER     (1 << 0) /* tx */
 118 #define IR_TX_ERROR     (IR_DIS_CRC | IR_BAD_CRC | IR_HW_UNDER)
 119
 120 #define IR_PHY_ERROR    (1 << 6) /* rx */
 121 #define IR_CRC_ERROR    (1 << 5) /* rx */
 122 #define IR_MAX_LEN      (1 << 4) /* rx */
 123 #define IR_FIFO_OVER    (1 << 3) /* rx */
 124 #define IR_SIR_ERROR    (1 << 2) /* rx */
 125 #define IR_RX_ERROR     (IR_PHY_ERROR | IR_CRC_ERROR | \
 126                          IR_MAX_LEN | IR_FIFO_OVER | IR_SIR_ERROR)
 127
 128 struct db_dest {
 129         struct db_dest *pnext;
 130         volatile u32 *vaddr;
 131         dma_addr_t dma_addr;
 132 };
 133
 134 struct ring_dest {
 135         u8 count_0;     /* 7:0  */
 136         u8 count_1;     /* 12:8 */
 137         u8 reserved;
 138         u8 flags;
 139         u8 addr_0;      /* 7:0   */
 140         u8 addr_1;      /* 15:8  */
 141         u8 addr_2;      /* 23:16 */
 142         u8 addr_3;      /* 31:24 */
 143 };
 144
 145 /* Private data for each instance */
 146 struct au1k_private {
 147         void __iomem *iobase;
 148         int irq_rx, irq_tx;
 149
 150         struct db_dest *pDBfree;
 151         struct db_dest db[2 * NUM_IR_DESC];
 152         volatile struct ring_dest *rx_ring[NUM_IR_DESC];
 153         volatile struct ring_dest *tx_ring[NUM_IR_DESC];
 154         struct db_dest *rx_db_inuse[NUM_IR_DESC];
 155         struct db_dest *tx_db_inuse[NUM_IR_DESC];
 156         u32 rx_head;
 157         u32 tx_head;
 158         u32 tx_tail;
 159         u32 tx_full;
 160
 161         iobuff_t rx_buff;
 162
 163         struct net_device *netdev;
 164         struct qos_info qos;
 165         struct irlap_cb *irlap;
 166
 167         u8 open;
 168         u32 speed;
 169         u32 newspeed;
 170
 171         struct resource *ioarea;
 172         struct au1k_irda_platform_data *platdata;
 173         struct clk *irda_clk;
 174 };
 175
 176 static int qos_mtt_bits = 0x07;  /* 1 ms or more */
 177
 178 static void au1k_irda_plat_set_phy_mode(struct au1k_private *p, int mode)
 179 {
 180         if (p->platdata && p->platdata->set_phy_mode)
 181                 p->platdata->set_phy_mode(mode);
 182 }
 183
 184 static inline unsigned long irda_read(struct au1k_private *p,
 185                                       unsigned long ofs)
 186 {
 187         /*
 188         * IrDA peripheral bug. You have to read the register
 189         * twice to get the right value.
 190         */
 191         (void)__raw_readl(p->iobase + ofs);
 192         return __raw_readl(p->iobase + ofs);
 193 }
 194
 195 static inline void irda_write(struct au1k_private *p, unsigned long ofs,
 196                               unsigned long val)
 197 {
 198         __raw_writel(val, p->iobase + ofs);
 199         wmb();
 200 }
 201
 202 /*
 203  * Buffer allocation/deallocation routines. The buffer descriptor returned
 204  * has the virtual and dma address of a buffer suitable for
 205  * both, receive and transmit operations.
 206  */
 207 static struct db_dest *GetFreeDB(struct au1k_private *aup)
 208 {
 209         struct db_dest *db;
 210         db = aup->pDBfree;
 211
 212         if (db)
 213                 aup->pDBfree = db->pnext;
 214         return db;
 215 }
 216
 217 /*
 218   DMA memory allocation, derived from pci_alloc_consistent.
 219   However, the Au1000 data cache is coherent (when programmed
 220   so), therefore we return KSEG0 address, not KSEG1.
 221 */
 222 static void *dma_alloc(size_t size, dma_addr_t *dma_handle)
 223 {
 224         void *ret;
 225         int gfp = GFP_ATOMIC | GFP_DMA;
 226
 227         ret = (void *)__get_free_pages(gfp, get_order(size));
 228
 229         if (ret != NULL) {
 230                 memset(ret, 0, size);
 231                 *dma_handle = virt_to_bus(ret);
 232                 ret = (void *)KSEG0ADDR(ret);
 233         }
 234         return ret;
 235 }
 236
 237 static void dma_free(void *vaddr, size_t size)
 238 {
 239         vaddr = (void *)KSEG0ADDR(vaddr);
 240         free_pages((unsigned long) vaddr, get_order(size));
 241 }
 242
 243
 244 static void setup_hw_rings(struct au1k_private *aup, u32 rx_base, u32 tx_base)
 245 {
 246         int i;
 247         for (i = 0; i < NUM_IR_DESC; i++) {
 248                 aup->rx_ring[i] = (volatile struct ring_dest *)
 249                         (rx_base + sizeof(struct ring_dest) * i);
 250         }
 251         for (i = 0; i < NUM_IR_DESC; i++) {
 252                 aup->tx_ring[i] = (volatile struct ring_dest *)
 253                         (tx_base + sizeof(struct ring_dest) * i);
 254         }
 255 }
 256
 257 static int au1k_irda_init_iobuf(iobuff_t *io, int size)
 258 {
 259         io->head = kmalloc(size, GFP_KERNEL);
 260         if (io->head != NULL) {
 261                 io->truesize    = size;
 262                 io->in_frame    = FALSE;
 263                 io->state       = OUTSIDE_FRAME;
 264                 io->data        = io->head;
 265         }
 266         return io->head ? 0 : -ENOMEM;
 267 }
 268
 269 /*
 270  * Set the IrDA communications speed.
 271  */
 272 static int au1k_irda_set_speed(struct net_device *dev, int speed)
 273 {
 274         struct au1k_private *aup = netdev_priv(dev);
 275         volatile struct ring_dest *ptxd;
 276         unsigned long control;
 277         int ret = 0, timeout = 10, i;
 278
 279         if (speed == aup->speed)
 280                 return ret;
 281
 282         /* disable PHY first */
 283         au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF);
 284         irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) & ~IR_PHYEN);
 285
 286         /* disable RX/TX */
 287         irda_write(aup, IR_CONFIG_1,
 288             irda_read(aup, IR_CONFIG_1) & ~(IR_RX_ENABLE | IR_TX_ENABLE));
 289         msleep(20);
 290         while (irda_read(aup, IR_STATUS) & (IR_RX_STATUS | IR_TX_STATUS)) {
 291                 msleep(20);
 292                 if (!timeout--) {
 293                         printk(KERN_ERR "%s: rx/tx disable timeout\n",
 294                                         dev->name);
 295                         break;
 296                 }
 297         }
 298
 299         /* disable DMA */
 300         irda_write(aup, IR_CONFIG_1,
 301                    irda_read(aup, IR_CONFIG_1) & ~IR_DMA_ENABLE);
 302         msleep(20);
 303
 304         /* After we disable tx/rx. the index pointers go back to zero. */
 305         aup->tx_head = aup->tx_tail = aup->rx_head = 0;
 306         for (i = 0; i < NUM_IR_DESC; i++) {
 307                 ptxd = aup->tx_ring[i];
 308                 ptxd->flags = 0;
 309                 ptxd->count_0 = 0;
 310                 ptxd->count_1 = 0;
 311         }
 312
 313         for (i = 0; i < NUM_IR_DESC; i++) {
 314                 ptxd = aup->rx_ring[i];
 315                 ptxd->count_0 = 0;
 316                 ptxd->count_1 = 0;
 317                 ptxd->flags = AU_OWN;
 318         }
 319
 320         if (speed == 4000000)
 321                 au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_FIR);
 322         else
 323                 au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR);
 324
 325         switch (speed) {
 326         case 9600:
 327                 irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(11) | IR_PW(12));
 328                 irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
 329                 break;
 330         case 19200:
 331                 irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(5) | IR_PW(12));
 332                 irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
 333                 break;
 334         case 38400:
 335                 irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(2) | IR_PW(12));
 336                 irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
 337                 break;
 338         case 57600:
 339                 irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(1) | IR_PW(12));
 340                 irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
 341                 break;
 342         case 115200:
 343                 irda_write(aup, IR_WRITE_PHY_CONFIG, IR_PW(12));
 344                 irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
 345                 break;
 346         case 4000000:
 347                 irda_write(aup, IR_WRITE_PHY_CONFIG, IR_P(15));
 348                 irda_write(aup, IR_CONFIG_1, IR_FIR | IR_DMA_ENABLE |
 349                                 IR_RX_ENABLE);
 350                 break;
 351         default:
 352                 printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed);
 353                 ret = -EINVAL;
 354                 break;
 355         }
 356
 357         aup->speed = speed;
 358         irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) | IR_PHYEN);
 359
 360         control = irda_read(aup, IR_STATUS);
 361         irda_write(aup, IR_RING_PROMPT, 0);
 362
 363         if (control & (1 << 14)) {
 364                 printk(KERN_ERR "%s: configuration error\n", dev->name);
 365         } else {
 366                 if (control & (1 << 11))
 367                         printk(KERN_DEBUG "%s Valid SIR config\n", dev->name);
 368                 if (control & (1 << 12))
 369                         printk(KERN_DEBUG "%s Valid MIR config\n", dev->name);
 370                 if (control & (1 << 13))
 371                         printk(KERN_DEBUG "%s Valid FIR config\n", dev->name);
 372                 if (control & (1 << 10))
 373                         printk(KERN_DEBUG "%s TX enabled\n", dev->name);
 374                 if (control & (1 << 9))
 375                         printk(KERN_DEBUG "%s RX enabled\n", dev->name);
 376         }
 377
 378         return ret;
 379 }
 380
 381 static void update_rx_stats(struct net_device *dev, u32 status, u32 count)
 382 {
 383         struct net_device_stats *ps = &dev->stats;
 384
 385         ps->rx_packets++;
 386
 387         if (status & IR_RX_ERROR) {
 388                 ps->rx_errors++;
 389                 if (status & (IR_PHY_ERROR | IR_FIFO_OVER))
 390                         ps->rx_missed_errors++;
 391                 if (status & IR_MAX_LEN)
 392                         ps->rx_length_errors++;
 393                 if (status & IR_CRC_ERROR)
 394                         ps->rx_crc_errors++;
 395         } else
 396                 ps->rx_bytes += count;
 397 }
 398
 399 static void update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len)
 400 {
 401         struct net_device_stats *ps = &dev->stats;
 402
 403         ps->tx_packets++;
 404         ps->tx_bytes += pkt_len;
 405
 406         if (status & IR_TX_ERROR) {
 407                 ps->tx_errors++;
 408                 ps->tx_aborted_errors++;
 409         }
 410 }
 411
 412 static void au1k_tx_ack(struct net_device *dev)
 413 {
 414         struct au1k_private *aup = netdev_priv(dev);
 415         volatile struct ring_dest *ptxd;
 416
 417         ptxd = aup->tx_ring[aup->tx_tail];
 418         while (!(ptxd->flags & AU_OWN) && (aup->tx_tail != aup->tx_head)) {
 419                 update_tx_stats(dev, ptxd->flags,
 420                                 (ptxd->count_1 << 8) | ptxd->count_0);
 421                 ptxd->count_0 = 0;
 422                 ptxd->count_1 = 0;
 423                 wmb();
 424                 aup->tx_tail = (aup->tx_tail + 1) & (NUM_IR_DESC - 1);
 425                 ptxd = aup->tx_ring[aup->tx_tail];
 426
 427                 if (aup->tx_full) {
 428                         aup->tx_full = 0;
 429                         netif_wake_queue(dev);
 430                 }
 431         }
 432
 433         if (aup->tx_tail == aup->tx_head) {
 434                 if (aup->newspeed) {
 435                         au1k_irda_set_speed(dev, aup->newspeed);
 436                         aup->newspeed = 0;
 437                 } else {
 438                         irda_write(aup, IR_CONFIG_1,
 439                             irda_read(aup, IR_CONFIG_1) & ~IR_TX_ENABLE);
 440                         irda_write(aup, IR_CONFIG_1,
 441                             irda_read(aup, IR_CONFIG_1) | IR_RX_ENABLE);
 442                         irda_write(aup, IR_RING_PROMPT, 0);
 443                 }
 444         }
 445 }
 446
 447 static int au1k_irda_rx(struct net_device *dev)
 448 {
 449         struct au1k_private *aup = netdev_priv(dev);
 450         volatile struct ring_dest *prxd;
 451         struct sk_buff *skb;
 452         struct db_dest *pDB;
 453         u32 flags, count;
 454
 455         prxd = aup->rx_ring[aup->rx_head];
 456         flags = prxd->flags;
 457
 458         while (!(flags & AU_OWN))  {
 459                 pDB = aup->rx_db_inuse[aup->rx_head];
 460                 count = (prxd->count_1 << 8) | prxd->count_0;
 461                 if (!(flags & IR_RX_ERROR)) {
 462                         /* good frame */
 463                         update_rx_stats(dev, flags, count);
 464                         skb = alloc_skb(count + 1, GFP_ATOMIC);
 465                         if (skb == NULL) {
 466                                 dev->stats.rx_dropped++;
 467                                 continue;
 468                         }
 469                         skb_reserve(skb, 1);
 470                         if (aup->speed == 4000000)
 471                                 skb_put(skb, count);
 472                         else
 473                                 skb_put(skb, count - 2);
 474                         skb_copy_to_linear_data(skb, (void *)pDB->vaddr,
 475                                                 count - 2);
 476                         skb->dev = dev;
 477                         skb_reset_mac_header(skb);
 478                         skb->protocol = htons(ETH_P_IRDA);
 479                         netif_rx(skb);
 480                         prxd->count_0 = 0;
 481                         prxd->count_1 = 0;
 482                 }
 483                 prxd->flags |= AU_OWN;
 484                 aup->rx_head = (aup->rx_head + 1) & (NUM_IR_DESC - 1);
 485                 irda_write(aup, IR_RING_PROMPT, 0);
 486
 487                 /* next descriptor */
 488                 prxd = aup->rx_ring[aup->rx_head];
 489                 flags = prxd->flags;
 490
 491         }
 492         return 0;
 493 }
 494
 495 static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id)
 496 {
 497         struct net_device *dev = dev_id;
 498         struct au1k_private *aup = netdev_priv(dev);
 499
 500         irda_write(aup, IR_INT_CLEAR, 0); /* ack irda interrupts */
 501
 502         au1k_irda_rx(dev);
 503         au1k_tx_ack(dev);
 504
 505         return IRQ_HANDLED;
 506 }
 507
 508 static int au1k_init(struct net_device *dev)
 509 {
 510         struct au1k_private *aup = netdev_priv(dev);
 511         u32 enable, ring_address, phyck;
 512         struct clk *c;
 513         int i;
 514
 515         c = clk_get(NULL, "irda_clk");
 516         if (IS_ERR(c))
 517                 return PTR_ERR(c);
 518         i = clk_prepare_enable(c);
 519         if (i) {
 520                 clk_put(c);
 521                 return i;
 522         }
 523
 524         switch (clk_get_rate(c)) {
 525         case 40000000:
 526                 phyck = IR_PHYCLK_40MHZ;
 527                 break;
 528         case 48000000:
 529                 phyck = IR_PHYCLK_48MHZ;
 530                 break;
 531         case 56000000:
 532                 phyck = IR_PHYCLK_56MHZ;
 533                 break;
 534         case 64000000:
 535                 phyck = IR_PHYCLK_64MHZ;
 536                 break;
 537         default:
 538                 clk_disable_unprepare(c);
 539                 clk_put(c);
 540                 return -EINVAL;
 541         }
 542         aup->irda_clk = c;
 543
 544         enable = IR_HC | IR_CE | IR_C;
 545 #ifndef CONFIG_CPU_LITTLE_ENDIAN
 546         enable |= IR_BE;
 547 #endif
 548         aup->tx_head = 0;
 549         aup->tx_tail = 0;
 550         aup->rx_head = 0;
 551
 552         for (i = 0; i < NUM_IR_DESC; i++)
 553                 aup->rx_ring[i]->flags = AU_OWN;
 554
 555         irda_write(aup, IR_ENABLE, enable);
 556         msleep(20);
 557
 558         /* disable PHY */
 559         au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF);
 560         irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) & ~IR_PHYEN);
 561         msleep(20);
 562
 563         irda_write(aup, IR_MAX_PKT_LEN, MAX_BUF_SIZE);
 564
 565         ring_address = (u32)virt_to_phys((void *)aup->rx_ring[0]);
 566         irda_write(aup, IR_RING_BASE_ADDR_H, ring_address >> 26);
 567         irda_write(aup, IR_RING_BASE_ADDR_L, (ring_address >> 10) & 0xffff);
 568
 569         irda_write(aup, IR_RING_SIZE,
 570                                 (RING_SIZE_64 << 8) | (RING_SIZE_64 << 12));
 571
 572         irda_write(aup, IR_CONFIG_2, phyck | IR_ONE_PIN);
 573         irda_write(aup, IR_RING_ADDR_CMPR, 0);
 574
 575         au1k_irda_set_speed(dev, 9600);
 576         return 0;
 577 }
 578
 579 static int au1k_irda_start(struct net_device *dev)
 580 {
 581         struct au1k_private *aup = netdev_priv(dev);
 582         char hwname[32];
 583         int retval;
 584
 585         retval = au1k_init(dev);
 586         if (retval) {
 587                 printk(KERN_ERR "%s: error in au1k_init\n", dev->name);
 588                 return retval;
 589         }
 590
 591         retval = request_irq(aup->irq_tx, &au1k_irda_interrupt, 0,
 592                              dev->name, dev);
 593         if (retval) {
 594                 printk(KERN_ERR "%s: unable to get IRQ %d\n",
 595                                 dev->name, dev->irq);
 596                 return retval;
 597         }
 598         retval = request_irq(aup->irq_rx, &au1k_irda_interrupt, 0,
 599                              dev->name, dev);
 600         if (retval) {
 601                 free_irq(aup->irq_tx, dev);
 602                 printk(KERN_ERR "%s: unable to get IRQ %d\n",
 603                                 dev->name, dev->irq);
 604                 return retval;
 605         }
 606
 607         /* Give self a hardware name */
 608         sprintf(hwname, "Au1000 SIR/FIR");
 609         aup->irlap = irlap_open(dev, &aup->qos, hwname);
 610         netif_start_queue(dev);
 611
 612         /* int enable */
 613         irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) | IR_IEN);
 614
 615         /* power up */
 616         au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR);
 617
 618         return 0;
 619 }
 620
 621 static int au1k_irda_stop(struct net_device *dev)
 622 {
 623         struct au1k_private *aup = netdev_priv(dev);
 624
 625         au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF);
 626
 627         /* disable interrupts */
 628         irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) & ~IR_IEN);
 629         irda_write(aup, IR_CONFIG_1, 0);
 630         irda_write(aup, IR_ENABLE, 0); /* disable clock */
 631
 632         if (aup->irlap) {
 633                 irlap_close(aup->irlap);
 634                 aup->irlap = NULL;
 635         }
 636
 637         netif_stop_queue(dev);
 638
 639         /* disable the interrupt */
 640         free_irq(aup->irq_tx, dev);
 641         free_irq(aup->irq_rx, dev);
 642
 643         clk_disable_unprepare(aup->irda_clk);
 644         clk_put(aup->irda_clk);
 645
 646         return 0;
 647 }
 648
 649 /*
 650  * Au1000 transmit routine.
 651  */
 652 static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
 653 {
 654         struct au1k_private *aup = netdev_priv(dev);
 655         int speed = irda_get_next_speed(skb);
 656         volatile struct ring_dest *ptxd;
 657         struct db_dest *pDB;
 658         u32 len, flags;
 659
 660         if (speed != aup->speed && speed != -1)
 661                 aup->newspeed = speed;
 662
 663         if ((skb->len == 0) && (aup->newspeed)) {
 664                 if (aup->tx_tail == aup->tx_head) {
 665                         au1k_irda_set_speed(dev, speed);
 666                         aup->newspeed = 0;
 667                 }
 668                 dev_kfree_skb(skb);
 669                 return NETDEV_TX_OK;
 670         }
 671
 672         ptxd = aup->tx_ring[aup->tx_head];
 673         flags = ptxd->flags;
 674
 675         if (flags & AU_OWN) {
 676                 printk(KERN_DEBUG "%s: tx_full\n", dev->name);
 677                 netif_stop_queue(dev);
 678                 aup->tx_full = 1;
 679                 return 1;
 680         } else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) {
 681                 printk(KERN_DEBUG "%s: tx_full\n", dev->name);
 682                 netif_stop_queue(dev);
 683                 aup->tx_full = 1;
 684                 return 1;
 685         }
 686
 687         pDB = aup->tx_db_inuse[aup->tx_head];
 688
 689 #if 0
 690         if (irda_read(aup, IR_RX_BYTE_CNT) != 0) {
 691                 printk(KERN_DEBUG "tx warning: rx byte cnt %x\n",
 692                                 irda_read(aup, IR_RX_BYTE_CNT));
 693         }
 694 #endif
 695
 696         if (aup->speed == 4000000) {
 697                 /* FIR */
 698                 skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
 699                 ptxd->count_0 = skb->len & 0xff;
 700                 ptxd->count_1 = (skb->len >> 8) & 0xff;
 701         } else {
 702                 /* SIR */
 703                 len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE);
 704                 ptxd->count_0 = len & 0xff;
 705                 ptxd->count_1 = (len >> 8) & 0xff;
 706                 ptxd->flags |= IR_DIS_CRC;
 707         }
 708         ptxd->flags |= AU_OWN;
 709         wmb();
 710
 711         irda_write(aup, IR_CONFIG_1,
 712                    irda_read(aup, IR_CONFIG_1) | IR_TX_ENABLE);
 713         irda_write(aup, IR_RING_PROMPT, 0);
 714
 715         dev_kfree_skb(skb);
 716         aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1);
 717         return NETDEV_TX_OK;
 718 }
 719
 720 /*
 721  * The Tx ring has been full longer than the watchdog timeout
 722  * value. The transmitter must be hung?
 723  */
 724 static void au1k_tx_timeout(struct net_device *dev)
 725 {
 726         u32 speed;
 727         struct au1k_private *aup = netdev_priv(dev);
 728
 729         printk(KERN_ERR "%s: tx timeout\n", dev->name);
 730         speed = aup->speed;
 731         aup->speed = 0;
 732         au1k_irda_set_speed(dev, speed);
 733         aup->tx_full = 0;
 734         netif_wake_queue(dev);
 735 }
 736
 737 static int au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
 738 {
 739         struct if_irda_req *rq = (struct if_irda_req *)ifreq;
 740         struct au1k_private *aup = netdev_priv(dev);
 741         int ret = -EOPNOTSUPP;
 742
 743         switch (cmd) {
 744         case SIOCSBANDWIDTH:
 745                 if (capable(CAP_NET_ADMIN)) {
 746                         /*
 747                          * We are unable to set the speed if the
 748                          * device is not running.
 749                          */
 750                         if (aup->open)
 751                                 ret = au1k_irda_set_speed(dev,
 752                                                 rq->ifr_baudrate);
 753                         else {
 754                                 printk(KERN_ERR "%s ioctl: !netif_running\n",
 755                                                 dev->name);
 756                                 ret = 0;
 757                         }
 758                 }
 759                 break;
 760
 761         case SIOCSMEDIABUSY:
 762                 ret = -EPERM;
 763                 if (capable(CAP_NET_ADMIN)) {
 764                         irda_device_set_media_busy(dev, TRUE);
 765                         ret = 0;
 766                 }
 767                 break;
 768
 769         case SIOCGRECEIVING:
 770                 rq->ifr_receiving = 0;
 771                 break;
 772         default:
 773                 break;
 774         }
 775         return ret;
 776 }
 777
 778 static const struct net_device_ops au1k_irda_netdev_ops = {
 779         .ndo_open               = au1k_irda_start,
 780         .ndo_stop               = au1k_irda_stop,
 781         .ndo_start_xmit         = au1k_irda_hard_xmit,
 782         .ndo_tx_timeout         = au1k_tx_timeout,
 783         .ndo_do_ioctl           = au1k_irda_ioctl,
 784 };
 785
 786 static int au1k_irda_net_init(struct net_device *dev)
 787 {
 788         struct au1k_private *aup = netdev_priv(dev);
 789         struct db_dest *pDB, *pDBfree;
 790         int i, err, retval = 0;
 791         dma_addr_t temp;
 792
 793         err = au1k_irda_init_iobuf(&aup->rx_buff, 14384);
 794         if (err)
 795                 goto out1;
 796
 797         dev->netdev_ops = &au1k_irda_netdev_ops;
 798
 799         irda_init_max_qos_capabilies(&aup->qos);
 800
 801         /* The only value we must override it the baudrate */
 802         aup->qos.baud_rate.bits = IR_9600 | IR_19200 | IR_38400 |
 803                 IR_57600 | IR_115200 | IR_576000 | (IR_4000000 << 8);
 804
 805         aup->qos.min_turn_time.bits = qos_mtt_bits;
 806         irda_qos_bits_to_value(&aup->qos);
 807
 808         retval = -ENOMEM;
 809
 810         /* Tx ring follows rx ring + 512 bytes */
 811         /* we need a 1k aligned buffer */
 812         aup->rx_ring[0] = (struct ring_dest *)
 813                 dma_alloc(2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)),
 814                           &temp);
 815         if (!aup->rx_ring[0])
 816                 goto out2;
 817
 818         /* allocate the data buffers */
 819         aup->db[0].vaddr =
 820                 dma_alloc(MAX_BUF_SIZE * 2 * NUM_IR_DESC, &temp);
 821         if (!aup->db[0].vaddr)
 822                 goto out3;
 823
 824         setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512);
 825
 826         pDBfree = NULL;
 827         pDB = aup->db;
 828         for (i = 0; i < (2 * NUM_IR_DESC); i++) {
 829                 pDB->pnext = pDBfree;
 830                 pDBfree = pDB;
 831                 pDB->vaddr =
 832                        (u32 *)((unsigned)aup->db[0].vaddr + (MAX_BUF_SIZE * i));
 833                 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
 834                 pDB++;
 835         }
 836         aup->pDBfree = pDBfree;
 837
 838         /* attach a data buffer to each descriptor */
 839         for (i = 0; i < NUM_IR_DESC; i++) {
 840                 pDB = GetFreeDB(aup);
 841                 if (!pDB)
 842                         goto out3;
 843                 aup->rx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff);
 844                 aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr >>  8) & 0xff);
 845                 aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr >> 16) & 0xff);
 846                 aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr >> 24) & 0xff);
 847                 aup->rx_db_inuse[i] = pDB;
 848         }
 849         for (i = 0; i < NUM_IR_DESC; i++) {
 850                 pDB = GetFreeDB(aup);
 851                 if (!pDB)
 852                         goto out3;
 853                 aup->tx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff);
 854                 aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr >>  8) & 0xff);
 855                 aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr >> 16) & 0xff);
 856                 aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr >> 24) & 0xff);
 857                 aup->tx_ring[i]->count_0 = 0;
 858                 aup->tx_ring[i]->count_1 = 0;
 859                 aup->tx_ring[i]->flags = 0;
 860                 aup->tx_db_inuse[i] = pDB;
 861         }
 862
 863         return 0;
 864
 865 out3:
 866         dma_free((void *)aup->rx_ring[0],
 867                 2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)));
 868 out2:
 869         kfree(aup->rx_buff.head);
 870 out1:
 871         printk(KERN_ERR "au1k_irda_net_init() failed.  Returns %d\n", retval);
 872         return retval;
 873 }
 874
 875 static int au1k_irda_probe(struct platform_device *pdev)
 876 {
 877         struct au1k_private *aup;
 878         struct net_device *dev;
 879         struct resource *r;
 880         struct clk *c;
 881         int err;
 882
 883         dev = alloc_irdadev(sizeof(struct au1k_private));
 884         if (!dev)
 885                 return -ENOMEM;
 886
 887         aup = netdev_priv(dev);
 888
 889         aup->platdata = pdev->dev.platform_data;
 890
 891         err = -EINVAL;
 892         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 893         if (!r)
 894                 goto out;
 895
 896         aup->irq_tx = r->start;
 897
 898         r = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 899         if (!r)
 900                 goto out;
 901
 902         aup->irq_rx = r->start;
 903
 904         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 905         if (!r)
 906                 goto out;
 907
 908         err = -EBUSY;
 909         aup->ioarea = request_mem_region(r->start, resource_size(r),
 910                                          pdev->name);
 911         if (!aup->ioarea)
 912                 goto out;
 913
 914         /* bail out early if clock doesn't exist */
 915         c = clk_get(NULL, "irda_clk");
 916         if (IS_ERR(c)) {
 917                 err = PTR_ERR(c);
 918                 goto out;
 919         }
 920         clk_put(c);
 921
 922         aup->iobase = ioremap_nocache(r->start, resource_size(r));
 923         if (!aup->iobase)
 924                 goto out2;
 925
 926         dev->irq = aup->irq_rx;
 927
 928         err = au1k_irda_net_init(dev);
 929         if (err)
 930                 goto out3;
 931         err = register_netdev(dev);
 932         if (err)
 933                 goto out4;
 934
 935         platform_set_drvdata(pdev, dev);
 936
 937         printk(KERN_INFO "IrDA: Registered device %s\n", dev->name);
 938         return 0;
 939
 940 out4:
 941         dma_free((void *)aup->db[0].vaddr,
 942                 MAX_BUF_SIZE * 2 * NUM_IR_DESC);
 943         dma_free((void *)aup->rx_ring[0],
 944                 2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)));
 945         kfree(aup->rx_buff.head);
 946 out3:
 947         iounmap(aup->iobase);
 948 out2:
 949         release_resource(aup->ioarea);
 950         kfree(aup->ioarea);
 951 out:
 952         free_netdev(dev);
 953         return err;
 954 }
 955
 956 static int au1k_irda_remove(struct platform_device *pdev)
 957 {
 958         struct net_device *dev = platform_get_drvdata(pdev);
 959         struct au1k_private *aup = netdev_priv(dev);
 960
 961         unregister_netdev(dev);
 962
 963         dma_free((void *)aup->db[0].vaddr,
 964                 MAX_BUF_SIZE * 2 * NUM_IR_DESC);
 965         dma_free((void *)aup->rx_ring[0],
 966                 2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)));
 967         kfree(aup->rx_buff.head);
 968
 969         iounmap(aup->iobase);
 970         release_resource(aup->ioarea);
 971         kfree(aup->ioarea);
 972
 973         free_netdev(dev);
 974
 975         return 0;
 976 }
 977
 978 static struct platform_driver au1k_irda_driver = {
 979         .driver = {
 980                 .name   = "au1000-irda",
 981         },
 982         .probe          = au1k_irda_probe,
 983         .remove         = au1k_irda_remove,
 984 };
 985
 986 module_platform_driver(au1k_irda_driver);
 987
 988 MODULE_AUTHOR("Pete Popov <ppopov@mvista.com>");
 989 MODULE_DESCRIPTION("Au1000 IrDA Device Driver");