4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Copyright 2006-2009 Analog Devices Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <net/irda/wrapper.h>
21 #include <net/irda/irda_device.h>
22 #include <asm/clock.h>
24 #define DRIVER_NAME "sh_sir"
26 #define RX_PHASE (1 << 0)
27 #define TX_PHASE (1 << 1)
28 #define TX_COMP_PHASE (1 << 2) /* tx complete */
29 #define NONE_PHASE (1 << 31)
31 #define IRIF_RINTCLR 0x0016 /* DMA rx interrupt source clear */
32 #define IRIF_TINTCLR 0x0018 /* DMA tx interrupt source clear */
33 #define IRIF_SIR0 0x0020 /* IrDA-SIR10 control */
34 #define IRIF_SIR1 0x0022 /* IrDA-SIR10 baudrate error correction */
35 #define IRIF_SIR2 0x0024 /* IrDA-SIR10 baudrate count */
36 #define IRIF_SIR3 0x0026 /* IrDA-SIR10 status */
37 #define IRIF_SIR_FRM 0x0028 /* Hardware frame processing set */
38 #define IRIF_SIR_EOF 0x002A /* EOF value */
39 #define IRIF_SIR_FLG 0x002C /* Flag clear */
40 #define IRIF_UART_STS2 0x002E /* UART status 2 */
41 #define IRIF_UART0 0x0030 /* UART control */
42 #define IRIF_UART1 0x0032 /* UART status */
43 #define IRIF_UART2 0x0034 /* UART mode */
44 #define IRIF_UART3 0x0036 /* UART transmit data */
45 #define IRIF_UART4 0x0038 /* UART receive data */
46 #define IRIF_UART5 0x003A /* UART interrupt mask */
47 #define IRIF_UART6 0x003C /* UART baud rate error correction */
48 #define IRIF_UART7 0x003E /* UART baud rate count set */
49 #define IRIF_CRC0 0x0040 /* CRC engine control */
50 #define IRIF_CRC1 0x0042 /* CRC engine input data */
51 #define IRIF_CRC2 0x0044 /* CRC engine calculation */
52 #define IRIF_CRC3 0x0046 /* CRC engine output data 1 */
53 #define IRIF_CRC4 0x0048 /* CRC engine output data 2 */
56 #define IRTPW (1 << 1) /* transmit pulse width select */
57 #define IRERRC (1 << 0) /* Clear receive pulse width error */
60 #define IRERR (1 << 0) /* received pulse width Error */
63 #define EOFD (1 << 9) /* EOF detection flag */
64 #define FRER (1 << 8) /* Frame Error bit */
65 #define FRP (1 << 0) /* Frame processing set */
68 #define IRSME (1 << 6) /* Receive Sum Error flag */
69 #define IROVE (1 << 5) /* Receive Overrun Error flag */
70 #define IRFRE (1 << 4) /* Receive Framing Error flag */
71 #define IRPRE (1 << 3) /* Receive Parity Error flag */
74 #define TBEC (1 << 2) /* Transmit Data Clear */
75 #define RIE (1 << 1) /* Receive Enable */
76 #define TIE (1 << 0) /* Transmit Enable */
79 #define URSME (1 << 6) /* Receive Sum Error Flag */
80 #define UROVE (1 << 5) /* Receive Overrun Error Flag */
81 #define URFRE (1 << 4) /* Receive Framing Error Flag */
82 #define URPRE (1 << 3) /* Receive Parity Error Flag */
83 #define RBF (1 << 2) /* Receive Buffer Full Flag */
84 #define TSBE (1 << 1) /* Transmit Shift Buffer Empty Flag */
85 #define TBE (1 << 0) /* Transmit Buffer Empty flag */
86 #define TBCOMP (TSBE | TBE)
89 #define RSEIM (1 << 6) /* Receive Sum Error Flag IRQ Mask */
90 #define RBFIM (1 << 2) /* Receive Buffer Full Flag IRQ Mask */
91 #define TSBEIM (1 << 1) /* Transmit Shift Buffer Empty Flag IRQ Mask */
92 #define TBEIM (1 << 0) /* Transmit Buffer Empty Flag IRQ Mask */
93 #define RX_MASK (RSEIM | RBFIM)
96 #define CRC_RST (1 << 15) /* CRC Engine Reset */
97 #define CRC_CT_MASK 0x0FFF
99 /************************************************************************
105 ************************************************************************/
107 void __iomem
*membase
;
111 struct net_device
*ndev
;
113 struct irlap_cb
*irlap
;
120 /************************************************************************
126 ************************************************************************/
127 static void sh_sir_write(struct sh_sir_self
*self
, u32 offset
, u16 data
)
129 iowrite16(data
, self
->membase
+ offset
);
132 static u16
sh_sir_read(struct sh_sir_self
*self
, u32 offset
)
134 return ioread16(self
->membase
+ offset
);
137 static void sh_sir_update_bits(struct sh_sir_self
*self
, u32 offset
,
142 old
= sh_sir_read(self
, offset
);
143 new = (old
& ~mask
) | data
;
145 sh_sir_write(self
, offset
, new);
148 /************************************************************************
154 ************************************************************************/
155 static void sh_sir_crc_reset(struct sh_sir_self
*self
)
157 sh_sir_write(self
, IRIF_CRC0
, CRC_RST
);
160 static void sh_sir_crc_add(struct sh_sir_self
*self
, u8 data
)
162 sh_sir_write(self
, IRIF_CRC1
, (u16
)data
);
165 static u16
sh_sir_crc_cnt(struct sh_sir_self
*self
)
167 return CRC_CT_MASK
& sh_sir_read(self
, IRIF_CRC0
);
170 static u16
sh_sir_crc_out(struct sh_sir_self
*self
)
172 return sh_sir_read(self
, IRIF_CRC4
);
175 static int sh_sir_crc_init(struct sh_sir_self
*self
)
177 struct device
*dev
= &self
->ndev
->dev
;
181 sh_sir_crc_reset(self
);
183 sh_sir_crc_add(self
, 0xCC);
184 sh_sir_crc_add(self
, 0xF5);
185 sh_sir_crc_add(self
, 0xF1);
186 sh_sir_crc_add(self
, 0xA7);
188 val
= sh_sir_crc_cnt(self
);
190 dev_err(dev
, "CRC count error %x\n", val
);
194 val
= sh_sir_crc_out(self
);
196 dev_err(dev
, "CRC result error%x\n", val
);
204 sh_sir_crc_reset(self
);
208 /************************************************************************
214 ************************************************************************/
215 #define SCLK_BASE 1843200 /* 1.8432MHz */
217 static u32
sh_sir_find_sclk(struct clk
*irda_clk
)
219 struct cpufreq_frequency_table
*freq_table
= irda_clk
->freq_table
;
220 struct clk
*pclk
= clk_get(NULL
, "peripheral_clk");
221 u32 limit
, min
= 0xffffffff, tmp
;
224 limit
= clk_get_rate(pclk
);
227 /* IrDA can not set over peripheral_clk */
229 freq_table
[i
].frequency
!= CPUFREQ_TABLE_END
;
231 u32 freq
= freq_table
[i
].frequency
;
233 if (freq
== CPUFREQ_ENTRY_INVALID
)
236 /* IrDA should not over peripheral_clk */
240 tmp
= freq
% SCLK_BASE
;
247 return freq_table
[index
].frequency
;
250 #define ERR_ROUNDING(a) ((a + 5000) / 10000)
251 static int sh_sir_set_baudrate(struct sh_sir_self
*self
, u32 baudrate
)
254 struct device
*dev
= &self
->ndev
->dev
;
261 /* Baud Rate Error Correction x 10000 */
262 u32 rate_err_array
[] = {
264 2500, 3125, 3750, 4375,
265 5000, 5625, 6250, 6875,
266 7500, 8125, 8750, 9375,
272 * it support 9600 only now
278 dev_err(dev
, "un-supported baudrate %d\n", baudrate
);
282 clk
= clk_get(NULL
, "irda_clk");
284 dev_err(dev
, "can not get irda_clk\n");
288 clk_set_rate(clk
, sh_sir_find_sclk(clk
));
289 rate
= clk_get_rate(clk
);
292 dev_dbg(dev
, "selected sclk = %d\n", rate
);
297 * 1843200 = system rate / (irbca + (irbc + 1))
300 irbc
= rate
/ SCLK_BASE
;
302 tmp
= rate
- (SCLK_BASE
* irbc
);
305 rerr
= tmp
/ SCLK_BASE
;
309 for (i
= 0; i
< ARRAY_SIZE(rate_err_array
); i
++) {
310 tmp
= abs(rate_err_array
[i
] - rerr
);
317 tmp
= rate
/ (irbc
+ ERR_ROUNDING(rate_err_array
[irbca
]));
318 if ((SCLK_BASE
/ 100) < abs(tmp
- SCLK_BASE
))
319 dev_warn(dev
, "IrDA freq error margin over %d\n", tmp
);
321 dev_dbg(dev
, "target = %d, result = %d, infrared = %d.%d\n",
322 SCLK_BASE
, tmp
, irbc
, rate_err_array
[irbca
]);
324 irbca
= (irbca
& 0xF) << 4;
325 irbc
= (irbc
- 1) & 0xF;
328 dev_err(dev
, "sh_sir can not set 0 in IRIF_SIR2\n");
332 sh_sir_write(self
, IRIF_SIR0
, IRTPW
| IRERRC
);
333 sh_sir_write(self
, IRIF_SIR1
, irbca
);
334 sh_sir_write(self
, IRIF_SIR2
, irbc
);
339 * BaudRate[bps] = system rate / (uabca + (uabc + 1) x 16)
342 uabc
= rate
/ baudrate
;
343 uabc
= (uabc
/ 16) - 1;
344 uabc
= (uabc
+ 1) * 16;
346 tmp
= rate
- (uabc
* baudrate
);
349 rerr
= tmp
/ baudrate
;
353 for (i
= 0; i
< ARRAY_SIZE(rate_err_array
); i
++) {
354 tmp
= abs(rate_err_array
[i
] - rerr
);
361 tmp
= rate
/ (uabc
+ ERR_ROUNDING(rate_err_array
[uabca
]));
362 if ((baudrate
/ 100) < abs(tmp
- baudrate
))
363 dev_warn(dev
, "UART freq error margin over %d\n", tmp
);
365 dev_dbg(dev
, "target = %d, result = %d, uart = %d.%d\n",
367 uabc
, rate_err_array
[uabca
]);
369 uabca
= (uabca
& 0xF) << 4;
370 uabc
= (uabc
/ 16) - 1;
372 sh_sir_write(self
, IRIF_UART6
, uabca
);
373 sh_sir_write(self
, IRIF_UART7
, uabc
);
378 /************************************************************************
384 ************************************************************************/
385 static int __sh_sir_init_iobuf(iobuff_t
*io
, int size
)
387 io
->head
= kmalloc(size
, GFP_KERNEL
);
392 io
->in_frame
= FALSE
;
393 io
->state
= OUTSIDE_FRAME
;
399 static void sh_sir_remove_iobuf(struct sh_sir_self
*self
)
401 kfree(self
->rx_buff
.head
);
402 kfree(self
->tx_buff
.head
);
404 self
->rx_buff
.head
= NULL
;
405 self
->tx_buff
.head
= NULL
;
408 static int sh_sir_init_iobuf(struct sh_sir_self
*self
, int rxsize
, int txsize
)
412 if (self
->rx_buff
.head
||
413 self
->tx_buff
.head
) {
414 dev_err(&self
->ndev
->dev
, "iobuff has already existed.");
418 err
= __sh_sir_init_iobuf(&self
->rx_buff
, rxsize
);
422 err
= __sh_sir_init_iobuf(&self
->tx_buff
, txsize
);
426 sh_sir_remove_iobuf(self
);
431 /************************************************************************
437 ************************************************************************/
438 static void sh_sir_clear_all_err(struct sh_sir_self
*self
)
440 /* Clear error flag for receive pulse width */
441 sh_sir_update_bits(self
, IRIF_SIR0
, IRERRC
, IRERRC
);
443 /* Clear frame / EOF error flag */
444 sh_sir_write(self
, IRIF_SIR_FLG
, 0xffff);
446 /* Clear all status error */
447 sh_sir_write(self
, IRIF_UART_STS2
, 0);
450 static void sh_sir_set_phase(struct sh_sir_self
*self
, int phase
)
472 sh_sir_write(self
, IRIF_UART5
, uart5
);
473 sh_sir_write(self
, IRIF_UART0
, uart0
);
476 static int sh_sir_is_which_phase(struct sh_sir_self
*self
)
478 u16 val
= sh_sir_read(self
, IRIF_UART5
);
484 return TX_COMP_PHASE
;
492 static void sh_sir_tx(struct sh_sir_self
*self
, int phase
)
496 if (0 >= self
->tx_buff
.len
) {
497 sh_sir_set_phase(self
, TX_COMP_PHASE
);
499 sh_sir_write(self
, IRIF_UART3
, self
->tx_buff
.data
[0]);
501 self
->tx_buff
.data
++;
505 sh_sir_set_phase(self
, RX_PHASE
);
506 netif_wake_queue(self
->ndev
);
509 dev_err(&self
->ndev
->dev
, "should not happen\n");
514 static int sh_sir_read_data(struct sh_sir_self
*self
)
520 val
= sh_sir_read(self
, IRIF_UART1
);
524 if (val
& (URSME
| UROVE
| URFRE
| URPRE
))
527 return (int)sh_sir_read(self
, IRIF_UART4
);
533 dev_err(&self
->ndev
->dev
, "UART1 %04x : STATUS %04x\n",
534 val
, sh_sir_read(self
, IRIF_UART_STS2
));
536 /* read data register for clear error */
537 sh_sir_read(self
, IRIF_UART4
);
542 static void sh_sir_rx(struct sh_sir_self
*self
)
548 data
= sh_sir_read_data(self
);
552 async_unwrap_char(self
->ndev
, &self
->ndev
->stats
,
553 &self
->rx_buff
, (u8
)data
);
554 self
->ndev
->last_rx
= jiffies
;
556 if (EOFD
& sh_sir_read(self
, IRIF_SIR_FRM
))
563 static irqreturn_t
sh_sir_irq(int irq
, void *dev_id
)
565 struct sh_sir_self
*self
= dev_id
;
566 struct device
*dev
= &self
->ndev
->dev
;
567 int phase
= sh_sir_is_which_phase(self
);
572 sh_sir_tx(self
, phase
);
575 if (sh_sir_read(self
, IRIF_SIR3
))
576 dev_err(dev
, "rcv pulse width error occurred\n");
579 sh_sir_clear_all_err(self
);
582 dev_err(dev
, "unknown interrupt\n");
588 /************************************************************************
591 net_device_ops function
594 ************************************************************************/
595 static int sh_sir_hard_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
597 struct sh_sir_self
*self
= netdev_priv(ndev
);
598 int speed
= irda_get_next_speed(skb
);
602 dev_err(&ndev
->dev
, "support 9600 only (%d)\n", speed
);
606 netif_stop_queue(ndev
);
608 self
->tx_buff
.data
= self
->tx_buff
.head
;
609 self
->tx_buff
.len
= 0;
611 self
->tx_buff
.len
= async_wrap_skb(skb
, self
->tx_buff
.data
,
612 self
->tx_buff
.truesize
);
614 sh_sir_set_phase(self
, TX_PHASE
);
620 static int sh_sir_ioctl(struct net_device
*ndev
, struct ifreq
*ifreq
, int cmd
)
625 * This function is needed for irda framework.
626 * But nothing to do now
631 static struct net_device_stats
*sh_sir_stats(struct net_device
*ndev
)
633 struct sh_sir_self
*self
= netdev_priv(ndev
);
635 return &self
->ndev
->stats
;
638 static int sh_sir_open(struct net_device
*ndev
)
640 struct sh_sir_self
*self
= netdev_priv(ndev
);
643 clk_enable(self
->clk
);
644 err
= sh_sir_crc_init(self
);
648 sh_sir_set_baudrate(self
, 9600);
650 self
->irlap
= irlap_open(ndev
, &self
->qos
, DRIVER_NAME
);
657 * Now enable the interrupt then start the queue
659 sh_sir_update_bits(self
, IRIF_SIR_FRM
, FRP
, FRP
);
660 sh_sir_read(self
, IRIF_UART1
); /* flag clear */
661 sh_sir_read(self
, IRIF_UART4
); /* flag clear */
662 sh_sir_set_phase(self
, RX_PHASE
);
664 netif_start_queue(ndev
);
666 dev_info(&self
->ndev
->dev
, "opened\n");
671 clk_disable(self
->clk
);
676 static int sh_sir_stop(struct net_device
*ndev
)
678 struct sh_sir_self
*self
= netdev_priv(ndev
);
682 irlap_close(self
->irlap
);
686 netif_stop_queue(ndev
);
688 dev_info(&ndev
->dev
, "stopped\n");
693 static const struct net_device_ops sh_sir_ndo
= {
694 .ndo_open
= sh_sir_open
,
695 .ndo_stop
= sh_sir_stop
,
696 .ndo_start_xmit
= sh_sir_hard_xmit
,
697 .ndo_do_ioctl
= sh_sir_ioctl
,
698 .ndo_get_stats
= sh_sir_stats
,
701 /************************************************************************
704 platform_driver function
707 ************************************************************************/
708 static int sh_sir_probe(struct platform_device
*pdev
)
710 struct net_device
*ndev
;
711 struct sh_sir_self
*self
;
712 struct resource
*res
;
717 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
718 irq
= platform_get_irq(pdev
, 0);
719 if (!res
|| irq
< 0) {
720 dev_err(&pdev
->dev
, "Not enough platform resources.\n");
724 ndev
= alloc_irdadev(sizeof(*self
));
728 self
= netdev_priv(ndev
);
729 self
->membase
= ioremap_nocache(res
->start
, resource_size(res
));
730 if (!self
->membase
) {
732 dev_err(&pdev
->dev
, "Unable to ioremap.\n");
736 err
= sh_sir_init_iobuf(self
, IRDA_SKB_MAX_MTU
, IRDA_SIR_MAX_FRAME
);
740 snprintf(clk_name
, sizeof(clk_name
), "irda%d", pdev
->id
);
741 self
->clk
= clk_get(&pdev
->dev
, clk_name
);
742 if (IS_ERR(self
->clk
)) {
743 dev_err(&pdev
->dev
, "cannot get clock \"%s\"\n", clk_name
);
748 irda_init_max_qos_capabilies(&self
->qos
);
750 ndev
->netdev_ops
= &sh_sir_ndo
;
754 self
->qos
.baud_rate
.bits
&= IR_9600
; /* FIXME */
755 self
->qos
.min_turn_time
.bits
= 1; /* 10 ms or more */
757 irda_qos_bits_to_value(&self
->qos
);
759 err
= register_netdev(ndev
);
763 platform_set_drvdata(pdev
, ndev
);
764 err
= request_irq(irq
, sh_sir_irq
, 0, "sh_sir", self
);
766 dev_warn(&pdev
->dev
, "Unable to attach sh_sir interrupt\n");
770 dev_info(&pdev
->dev
, "SuperH IrDA probed\n");
777 sh_sir_remove_iobuf(self
);
779 iounmap(self
->membase
);
786 static int sh_sir_remove(struct platform_device
*pdev
)
788 struct net_device
*ndev
= platform_get_drvdata(pdev
);
789 struct sh_sir_self
*self
= netdev_priv(ndev
);
794 unregister_netdev(ndev
);
796 sh_sir_remove_iobuf(self
);
797 iounmap(self
->membase
);
803 static struct platform_driver sh_sir_driver
= {
804 .probe
= sh_sir_probe
,
805 .remove
= sh_sir_remove
,
811 module_platform_driver(sh_sir_driver
);
813 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
814 MODULE_DESCRIPTION("SuperH IrDA driver");
815 MODULE_LICENSE("GPL");