]>
git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/net/irda/via-ircc.h
1 /*********************************************************************
5 * Description: Driver for the VIA VT8231/VT8233 IrDA chipsets
6 * Author: VIA Technologies, inc
9 Copyright (c) 1998-2003 VIA Technologies, Inc.
11 This program is free software; you can redistribute it and/or modify it under
12 the terms of the GNU General Public License as published by the Free Software
13 Foundation; either version 2, or (at your option) any later version.
15 This program is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
18 See the GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License along with
21 this program; if not, see <http://www.gnu.org/licenses/>.
24 * jul/08/2002 : Rx buffer length should use Rx ring ptr.
25 * Oct/28/2002 : Add SB id for 3147 and 3177.
26 * jul/09/2002 : only implement two kind of dongle currently.
27 * Oct/02/2002 : work on VT8231 and VT8233 .
28 * Aug/06/2003 : change driver format to pci driver .
29 ********************************************************************/
32 #include <linux/spinlock.h>
34 #include <linux/types.h>
37 #define MAX_TX_WINDOW 7
38 #define MAX_RX_WINDOW 7
40 struct st_fifo_entry
{
46 struct st_fifo_entry entries
[MAX_RX_WINDOW
+ 2];
54 void *start
; /* Start of frame in DMA mem */
55 int len
; /* Length of frame in DMA mem */
59 struct frame_cb queue
[MAX_TX_WINDOW
+ 2]; /* Info about frames in queue */
60 int ptr
; /* Currently being sent */
61 int len
; /* Length of queue */
62 int free
; /* Next free slot */
63 void *tail
; /* Next free start in DMA mem */
67 struct eventflag
// for keeping track of Interrupt Events
70 unsigned char TxFIFOUnderRun
;
71 unsigned char EOMessage
;
72 unsigned char TxFIFOReady
;
73 unsigned char EarlyEOM
;
77 unsigned char RxFIFOOverRun
;
78 unsigned char EOPacket
;
79 unsigned char RxAvail
;
80 unsigned char TooLargePacket
;
83 unsigned char Unknown
;
85 unsigned char TimeOut
;
86 unsigned char RxDMATC
;
87 unsigned char TxDMATC
;
90 /* Private data for each instance */
92 struct st_fifo st_fifo
; /* Info about received frames */
93 struct tx_fifo tx_fifo
; /* Info about frames to be transmitted */
95 struct net_device
*netdev
; /* Yes! we are some kind of netdevice */
97 struct irlap_cb
*irlap
; /* The link layer we are binded to */
98 struct qos_info qos
; /* QoS capabilities for this device */
100 chipio_t io
; /* IrDA controller information */
101 iobuff_t tx_buff
; /* Transmit buffer */
102 iobuff_t rx_buff
; /* Receive buffer */
103 dma_addr_t tx_buff_dma
;
104 dma_addr_t rx_buff_dma
;
106 __u8 ier
; /* Interrupt enable register */
108 spinlock_t lock
; /* For serializing operations */
110 __u32 flags
; /* Interface flags */
112 int index
; /* Instance index */
114 struct eventflag EventFlag
;
115 unsigned int chip_id
; /* to remember chip id */
116 unsigned int RetryCount
;
117 unsigned int RxDataReady
;
118 unsigned int RxLastCount
;
122 //---------I=Infrared, H=Host, M=Misc, T=Tx, R=Rx, ST=Status,
123 // CF=Config, CT=Control, L=Low, H=High, C=Count
124 #define I_CF_L_0 0x10
125 #define I_CF_H_0 0x11
126 #define I_SIR_BOF 0x12
127 #define I_SIR_EOF 0x13
128 #define I_ST_CT_0 0x15
129 #define I_ST_L_1 0x16
130 #define I_ST_H_1 0x17
131 #define I_CF_L_1 0x18
132 #define I_CF_H_1 0x19
133 #define I_CF_L_2 0x1a
134 #define I_CF_H_2 0x1b
157 //-------------------------------
158 #define StartAddr 0x10 // the first register address
159 #define EndAddr 0x3f // the last register address
160 #define GetBit(val,bit) val = (unsigned char) ((val>>bit) & 0x1)
162 #define SetBit(val,bit) val= (unsigned char ) (val | (0x1 << bit))
164 #define ResetBit(val,bit) val= (unsigned char ) (val & ~(0x1 << bit))
169 #define DMA_TX_MODE 0x08
170 #define DMA_RX_MODE 0x04
174 #define MASK1 DMA1+0x0a
175 #define MASK2 DMA2+0x14
179 #define Rd_Valid 0x08
182 static void DisableDmaChannel(unsigned int channel
)
184 switch (channel
) { // 8 Bit DMA channels DMAC1
186 outb(4, MASK1
); //mask channel 0
189 outb(5, MASK1
); //Mask channel 1
192 outb(6, MASK1
); //Mask channel 2
195 outb(7, MASK1
); //Mask channel 3
198 outb(5, MASK2
); //Mask channel 5
201 outb(6, MASK2
); //Mask channel 6
204 outb(7, MASK2
); //Mask channel 7
211 static unsigned char ReadLPCReg(int iRegNum
)
224 static void WriteLPCReg(int iRegNum
, unsigned char iVal
)
234 static __u8
ReadReg(unsigned int BaseAddr
, int iRegNum
)
236 return (__u8
) inb(BaseAddr
+ iRegNum
);
239 static void WriteReg(unsigned int BaseAddr
, int iRegNum
, unsigned char iVal
)
241 outb(iVal
, BaseAddr
+ iRegNum
);
244 static int WriteRegBit(unsigned int BaseAddr
, unsigned char RegNum
,
245 unsigned char BitPos
, unsigned char value
)
252 if ((RegNum
< StartAddr
) || (RegNum
> EndAddr
))
254 Rtemp
= ReadReg(BaseAddr
, RegNum
);
256 Wtemp
= ResetBit(Rtemp
, BitPos
);
259 Wtemp
= SetBit(Rtemp
, BitPos
);
263 WriteReg(BaseAddr
, RegNum
, Wtemp
);
267 static __u8
CheckRegBit(unsigned int BaseAddr
, unsigned char RegNum
,
268 unsigned char BitPos
)
274 if ((RegNum
< StartAddr
) || (RegNum
> EndAddr
)) {
275 // printf("what is the register %x!\n",RegNum);
277 temp
= ReadReg(BaseAddr
, RegNum
);
278 return GetBit(temp
, BitPos
);
281 static void SetMaxRxPacketSize(__u16 iobase
, __u16 size
)
284 if ((size
& 0xe000) == 0) {
286 high
= (size
& 0x1f00) >> 8;
287 WriteReg(iobase
, I_CF_L_2
, low
);
288 WriteReg(iobase
, I_CF_H_2
, high
);
296 static void SetFIFO(__u16 iobase
, __u16 value
)
300 WriteRegBit(iobase
, 0x11, 0, 0);
301 WriteRegBit(iobase
, 0x11, 7, 1);
304 WriteRegBit(iobase
, 0x11, 0, 0);
305 WriteRegBit(iobase
, 0x11, 7, 0);
308 WriteRegBit(iobase
, 0x11, 0, 1);
309 WriteRegBit(iobase
, 0x11, 7, 0);
312 WriteRegBit(iobase
, 0x11, 0, 0);
313 WriteRegBit(iobase
, 0x11, 7, 0);
318 #define CRC16(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,7,val) //0 for 32 CRC
320 #define SetVFIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,5,val)
321 #define SetFIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,6,val)
322 #define SetMIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,5,val)
323 #define SetSIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,4,val)
325 #define SIRFilter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,3,val)
326 #define Filter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,2,val)
327 #define InvertTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,1,val)
328 #define InvertRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,0,val)
329 //****************************I_CF_H_0
330 #define EnableTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,4,val)
331 #define EnableRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,3,val)
332 #define EnableDMA(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,2,val)
333 #define SIRRecvAny(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,1,val)
334 #define DiableTrans(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,0,val)
335 //***************************I_SIR_BOF,I_SIR_EOF
336 #define SetSIRBOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_BOF,val)
337 #define SetSIREOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_EOF,val)
338 #define GetSIRBOF(BaseAddr) ReadReg(BaseAddr,I_SIR_BOF)
339 #define GetSIREOF(BaseAddr) ReadReg(BaseAddr,I_SIR_EOF)
340 //*******************I_ST_CT_0
341 #define EnPhys(BaseAddr,val) WriteRegBit(BaseAddr,I_ST_CT_0,7,val)
342 #define IsModeError(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,6) //RO
343 #define IsVFIROn(BaseAddr) CheckRegBit(BaseAddr,0x14,0) //RO for VT1211 only
344 #define IsFIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,5) //RO
345 #define IsMIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,4) //RO
346 #define IsSIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,3) //RO
347 #define IsEnableTX(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,2) //RO
348 #define IsEnableRX(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,1) //RO
349 #define Is16CRC(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,0) //RO
350 //***************************I_CF_3
351 #define DisableAdjacentPulseWidth(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,5,val) //1 disable
352 #define DisablePulseWidthAdjust(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,4,val) //1 disable
353 #define UseOneRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,1,val) //0 use two RX
354 #define SlowIRRXLowActive(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,0,val) //0 show RX high=1 in SIR
355 //***************************H_CT
356 #define EnAllInt(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,7,val)
357 #define TXStart(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,6,val)
358 #define RXStart(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,5,val)
359 #define ClearRXInt(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,4,val) // 1 clear
360 //*****************H_ST
361 #define IsRXInt(BaseAddr) CheckRegBit(BaseAddr,H_ST,4)
362 #define GetIntIndentify(BaseAddr) ((ReadReg(BaseAddr,H_ST)&0xf1) >>1)
363 #define IsHostBusy(BaseAddr) CheckRegBit(BaseAddr,H_ST,0)
364 #define GetHostStatus(BaseAddr) ReadReg(BaseAddr,H_ST) //RO
365 //**************************M_CT
366 #define EnTXDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,7,val)
367 #define EnRXDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,6,val)
368 #define SwapDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,5,val)
369 #define EnInternalLoop(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,4,val)
370 #define EnExternalLoop(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,3,val)
371 //**************************TX_CT_1
372 #define EnTXFIFOHalfLevelInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,4,val) //half empty int (1 half)
373 #define EnTXFIFOUnderrunEOMInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,5,val)
374 #define EnTXFIFOReadyInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,6,val) //int when reach it threshold (setting by bit 4)
375 //**************************TX_CT_2
376 #define ForceUnderrun(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,7,val) // force an underrun int
377 #define EnTXCRC(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,6,val) //1 for FIR,MIR...0 (not SIR)
378 #define ForceBADCRC(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,5,val) //force an bad CRC
379 #define SendSIP(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,4,val) //send indication pulse for prevent SIR disturb
380 #define ClearEnTX(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,3,val) // opposite to EnTX
381 //*****************TX_ST
382 #define GetTXStatus(BaseAddr) ReadReg(BaseAddr,TX_ST) //RO
383 //**************************RX_CT
384 #define EnRXSpecInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,0,val)
385 #define EnRXFIFOReadyInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,1,val) //enable int when reach it threshold (setting by bit 7)
386 #define EnRXFIFOHalfLevelInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,7,val) //enable int when (1) half full...or (0) just not full
387 //*****************RX_ST
388 #define GetRXStatus(BaseAddr) ReadReg(BaseAddr,RX_ST) //RO
389 //***********************P_ADDR
390 #define SetPacketAddr(BaseAddr,addr) WriteReg(BaseAddr,P_ADDR,addr)
391 //***********************I_CF_4
392 #define EnGPIOtoRX2(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,7,val)
393 #define EnTimerInt(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,1,val)
394 #define ClearTimerInt(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,0,val)
395 //***********************I_T_C_L
396 #define WriteGIO(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_L,7,val)
397 #define ReadGIO(BaseAddr) CheckRegBit(BaseAddr,I_T_C_L,7)
398 #define ReadRX(BaseAddr) CheckRegBit(BaseAddr,I_T_C_L,3) //RO
399 #define WriteTX(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_L,0,val)
400 //***********************I_T_C_H
401 #define EnRX2(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_H,7,val)
402 #define ReadRX2(BaseAddr) CheckRegBit(BaseAddr,I_T_C_H,7)
403 //**********************Version
404 #define GetFIRVersion(BaseAddr) ReadReg(BaseAddr,VERSION)
407 static void SetTimer(__u16 iobase
, __u8 count
)
409 EnTimerInt(iobase
, OFF
);
410 WriteReg(iobase
, TIMER
, count
);
411 EnTimerInt(iobase
, ON
);
415 static void SetSendByte(__u16 iobase
, __u32 count
)
419 if ((count
& 0xf000) == 0) {
420 low
= count
& 0x00ff;
421 high
= (count
& 0x0f00) >> 8;
422 WriteReg(iobase
, TX_C_L
, low
);
423 WriteReg(iobase
, TX_C_H
, high
);
427 static void ResetChip(__u16 iobase
, __u8 type
)
431 value
= (type
+ 2) << 4;
432 WriteReg(iobase
, RESET
, type
);
435 static int CkRxRecv(__u16 iobase
, struct via_ircc_cb
*self
)
438 __u16 wTmp
= 0, wTmp1
= 0, wTmp_new
= 0;
440 low
= ReadReg(iobase
, RX_C_L
);
441 high
= ReadReg(iobase
, RX_C_H
);
443 wTmp
= (wTmp1
<< 8) | low
;
445 low
= ReadReg(iobase
, RX_C_L
);
446 high
= ReadReg(iobase
, RX_C_H
);
448 wTmp_new
= (wTmp1
<< 8) | low
;
449 if (wTmp_new
!= wTmp
)
456 static __u16
RxCurCount(__u16 iobase
, struct via_ircc_cb
* self
)
459 __u16 wTmp
= 0, wTmp1
= 0;
461 low
= ReadReg(iobase
, RX_P_L
);
462 high
= ReadReg(iobase
, RX_P_H
);
464 wTmp
= (wTmp1
<< 8) | low
;
468 /* This Routine can only use in recevie_complete
469 * for it will update last count.
472 static __u16
GetRecvByte(__u16 iobase
, struct via_ircc_cb
* self
)
475 __u16 wTmp
, wTmp1
, ret
;
477 low
= ReadReg(iobase
, RX_P_L
);
478 high
= ReadReg(iobase
, RX_P_H
);
480 wTmp
= (wTmp1
<< 8) | low
;
483 if (wTmp
>= self
->RxLastCount
)
484 ret
= wTmp
- self
->RxLastCount
;
486 ret
= (0x8000 - self
->RxLastCount
) + wTmp
;
487 self
->RxLastCount
= wTmp
;
489 /* RX_P is more actually the RX_C
490 low=ReadReg(iobase,RX_C_L);
491 high=ReadReg(iobase,RX_C_H);
502 static void Sdelay(__u16 scale
)
507 for (j
= 0; j
< scale
; j
++) {
508 for (i
= 0; i
< 0x20; i
++) {
515 static void Tdelay(__u16 scale
)
520 for (j
= 0; j
< scale
; j
++) {
521 for (i
= 0; i
< 0x50; i
++) {
529 static void ActClk(__u16 iobase
, __u8 value
)
532 bTmp
= ReadReg(iobase
, 0x34);
534 WriteReg(iobase
, 0x34, bTmp
| Clk_bit
);
536 WriteReg(iobase
, 0x34, bTmp
& ~Clk_bit
);
539 static void ClkTx(__u16 iobase
, __u8 Clk
, __u8 Tx
)
543 bTmp
= ReadReg(iobase
, 0x34);
550 WriteReg(iobase
, 0x34, bTmp
);
558 WriteReg(iobase
, 0x34, bTmp
);
561 static void Wr_Byte(__u16 iobase
, __u8 data
)
573 for (i
= 0; i
< 8; i
++) { //LDN
575 if ((bData
>> i
) & 0x01) {
576 ClkTx(iobase
, 0, 1); //bit data = 1;
578 ClkTx(iobase
, 0, 0); //bit data = 1;
582 ActClk(iobase
, 1); //clk hi
587 static __u8
Rd_Indx(__u16 iobase
, __u8 addr
, __u8 index
)
589 __u8 data
= 0, bTmp
, data_bit
;
592 bTmp
= addr
| (index
<< 1) | 0;
597 Wr_Byte(iobase
, bTmp
);
601 for (i
= 0; i
< 10; i
++) {
608 bTmp
= ReadReg(iobase
, 0x34);
609 if (!(bTmp
& Rd_Valid
))
612 if (!(bTmp
& Rd_Valid
)) {
613 for (i
= 0; i
< 8; i
++) {
617 bTmp
= ReadReg(iobase
, 0x34);
626 for (i
= 0; i
< 2; i
++) {
632 bTmp
= ReadReg(iobase
, 0x34);
634 for (i
= 0; i
< 1; i
++) {
642 for (i
= 0; i
< 3; i
++) {
651 static void Wr_Indx(__u16 iobase
, __u8 addr
, __u8 index
, __u8 data
)
660 bTmp
= addr
| (index
<< 1) | 1;
661 Wr_Byte(iobase
, bTmp
);
662 Wr_Byte(iobase
, data
);
663 for (i
= 0; i
< 2; i
++) {
672 static void ResetDongle(__u16 iobase
)
677 for (i
= 0; i
< 30; i
++) {
686 static void SetSITmode(__u16 iobase
)
691 bTmp
= ReadLPCReg(0x28);
692 WriteLPCReg(0x28, bTmp
| 0x10); //select ITMOFF
693 bTmp
= ReadReg(iobase
, 0x35);
694 WriteReg(iobase
, 0x35, bTmp
| 0x40); // Driver ITMOFF
695 WriteReg(iobase
, 0x28, bTmp
| 0x80); // enable All interrupt
698 static void SI_SetMode(__u16 iobase
, int mode
)
703 WriteLPCReg(0x28, 0x70); // S/W Reset
707 Wr_Indx(iobase
, 0x40, 0x0, 0x17); //RX ,APEN enable,Normal power
708 Wr_Indx(iobase
, 0x40, 0x1, mode
); //Set Mode
709 Wr_Indx(iobase
, 0x40, 0x2, 0xff); //Set power to FIR VFIR > 1m
710 bTmp
= Rd_Indx(iobase
, 0x40, 1);
713 static void InitCard(__u16 iobase
)
715 ResetChip(iobase
, 5);
716 WriteReg(iobase
, I_ST_CT_0
, 0x00); // open CHIP on
717 SetSIRBOF(iobase
, 0xc0); // hardware default value
718 SetSIREOF(iobase
, 0xc1);
721 static void CommonInit(__u16 iobase
)
723 // EnTXCRC(iobase,0);
724 SwapDMA(iobase
, OFF
);
725 SetMaxRxPacketSize(iobase
, 0x0fff); //set to max:4095
726 EnRXFIFOReadyInt(iobase
, OFF
);
727 EnRXFIFOHalfLevelInt(iobase
, OFF
);
728 EnTXFIFOHalfLevelInt(iobase
, OFF
);
729 EnTXFIFOUnderrunEOMInt(iobase
, ON
);
730 // EnTXFIFOReadyInt(iobase,ON);
731 InvertTX(iobase
, OFF
);
732 InvertRX(iobase
, OFF
);
733 // WriteLPCReg(0xF0,0); //(if VT1211 then do this)
734 if (IsSIROn(iobase
)) {
735 SIRFilter(iobase
, ON
);
736 SIRRecvAny(iobase
, ON
);
738 SIRFilter(iobase
, OFF
);
739 SIRRecvAny(iobase
, OFF
);
741 EnRXSpecInt(iobase
, ON
);
742 WriteReg(iobase
, I_ST_CT_0
, 0x80);
743 EnableDMA(iobase
, ON
);
746 static void SetBaudRate(__u16 iobase
, __u32 rate
)
748 __u8 value
= 11, temp
;
750 if (IsSIROn(iobase
)) {
752 case (__u32
) (2400L):
755 case (__u32
) (9600L):
758 case (__u32
) (19200L):
761 case (__u32
) (38400L):
764 case (__u32
) (57600L):
767 case (__u32
) (115200L):
773 } else if (IsMIROn(iobase
)) {
774 value
= 0; // will automatically be fixed in 1.152M
775 } else if (IsFIROn(iobase
)) {
776 value
= 0; // will automatically be fixed in 4M
778 temp
= (ReadReg(iobase
, I_CF_H_1
) & 0x03);
780 WriteReg(iobase
, I_CF_H_1
, temp
);
783 static void SetPulseWidth(__u16 iobase
, __u8 width
)
785 __u8 temp
, temp1
, temp2
;
787 temp
= (ReadReg(iobase
, I_CF_L_1
) & 0x1f);
788 temp1
= (ReadReg(iobase
, I_CF_H_1
) & 0xfc);
789 temp2
= (width
& 0x07) << 5;
791 temp2
= (width
& 0x18) >> 3;
793 WriteReg(iobase
, I_CF_L_1
, temp
);
794 WriteReg(iobase
, I_CF_H_1
, temp1
);
797 static void SetSendPreambleCount(__u16 iobase
, __u8 count
)
801 temp
= ReadReg(iobase
, I_CF_L_1
) & 0xe0;
803 WriteReg(iobase
, I_CF_L_1
, temp
);
807 static void SetVFIR(__u16 BaseAddr
, __u8 val
)
811 tmp
= ReadReg(BaseAddr
, I_CF_L_0
);
812 WriteReg(BaseAddr
, I_CF_L_0
, tmp
& 0x8f);
813 WriteRegBit(BaseAddr
, I_CF_H_0
, 5, val
);
816 static void SetFIR(__u16 BaseAddr
, __u8 val
)
820 WriteRegBit(BaseAddr
, I_CF_H_0
, 5, 0);
821 tmp
= ReadReg(BaseAddr
, I_CF_L_0
);
822 WriteReg(BaseAddr
, I_CF_L_0
, tmp
& 0x8f);
823 WriteRegBit(BaseAddr
, I_CF_L_0
, 6, val
);
826 static void SetMIR(__u16 BaseAddr
, __u8 val
)
830 WriteRegBit(BaseAddr
, I_CF_H_0
, 5, 0);
831 tmp
= ReadReg(BaseAddr
, I_CF_L_0
);
832 WriteReg(BaseAddr
, I_CF_L_0
, tmp
& 0x8f);
833 WriteRegBit(BaseAddr
, I_CF_L_0
, 5, val
);
836 static void SetSIR(__u16 BaseAddr
, __u8 val
)
840 WriteRegBit(BaseAddr
, I_CF_H_0
, 5, 0);
841 tmp
= ReadReg(BaseAddr
, I_CF_L_0
);
842 WriteReg(BaseAddr
, I_CF_L_0
, tmp
& 0x8f);
843 WriteRegBit(BaseAddr
, I_CF_L_0
, 4, val
);
846 #endif /* via_IRCC_H */