drivers/net/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _IXGBE_H_
  30 #define _IXGBE_H_
  31
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/inet_lro.h>
  36
  37 #include "ixgbe_type.h"
  38 #include "ixgbe_common.h"
  39
  40 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
  41 #include <linux/dca.h>
  42 #endif
  43
  44 #define PFX "ixgbe: "
  45 #define DPRINTK(nlevel, klevel, fmt, args...) \
  46         ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
  47         printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
  48                 __FUNCTION__ , ## args)))
  49
  50 /* TX/RX descriptor defines */
  51 #define IXGBE_DEFAULT_TXD                  1024
  52 #define IXGBE_MAX_TXD                      4096
  53 #define IXGBE_MIN_TXD                        64
  54
  55 #define IXGBE_DEFAULT_RXD                  1024
  56 #define IXGBE_MAX_RXD                      4096
  57 #define IXGBE_MIN_RXD                        64
  58
  59 #define IXGBE_DEFAULT_RXQ                          1
  60 #define IXGBE_MAX_RXQ                              1
  61 #define IXGBE_MIN_RXQ                              1
  62
  63 /* flow control */
  64 #define IXGBE_DEFAULT_FCRTL             0x10000
  65 #define IXGBE_MIN_FCRTL                    0x40
  66 #define IXGBE_MAX_FCRTL                 0x7FF80
  67 #define IXGBE_DEFAULT_FCRTH             0x20000
  68 #define IXGBE_MIN_FCRTH                   0x600
  69 #define IXGBE_MAX_FCRTH                 0x7FFF0
  70 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  71 #define IXGBE_MIN_FCPAUSE                     0
  72 #define IXGBE_MAX_FCPAUSE                0xFFFF
  73
  74 /* Supported Rx Buffer Sizes */
  75 #define IXGBE_RXBUFFER_64    64     /* Used for packet split */
  76 #define IXGBE_RXBUFFER_128   128    /* Used for packet split */
  77 #define IXGBE_RXBUFFER_256   256    /* Used for packet split */
  78 #define IXGBE_RXBUFFER_2048  2048
  79
  80 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
  81
  82 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  83
  84 /* How many Tx Descriptors do we need to call netif_wake_queue? */
  85 #define IXGBE_TX_QUEUE_WAKE 16
  86
  87 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  88 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  89
  90 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  91 #define IXGBE_TX_FLAGS_VLAN             (u32)(1 << 1)
  92 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 2)
  93 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 3)
  94 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
  95 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
  96
  97 #define IXGBE_MAX_LRO_DESCRIPTORS       8
  98 #define IXGBE_MAX_LRO_AGGREGATE         32
  99
 100 /* wrapper around a pointer to a socket buffer,
 101  * so a DMA handle can be stored along with the buffer */
 102 struct ixgbe_tx_buffer {
 103         struct sk_buff *skb;
 104         dma_addr_t dma;
 105         unsigned long time_stamp;
 106         u16 length;
 107         u16 next_to_watch;
 108 };
 109
 110 struct ixgbe_rx_buffer {
 111         struct sk_buff *skb;
 112         dma_addr_t dma;
 113         struct page *page;
 114         dma_addr_t page_dma;
 115         unsigned int page_offset;
 116 };
 117
 118 struct ixgbe_queue_stats {
 119         u64 packets;
 120         u64 bytes;
 121 };
 122
 123 struct ixgbe_ring {
 124         void *desc;                     /* descriptor ring memory */
 125         dma_addr_t dma;                 /* phys. address of descriptor ring */
 126         unsigned int size;              /* length in bytes */
 127         unsigned int count;             /* amount of descriptors */
 128         unsigned int next_to_use;
 129         unsigned int next_to_clean;
 130
 131         int queue_index; /* needed for multiqueue queue management */
 132         union {
 133                 struct ixgbe_tx_buffer *tx_buffer_info;
 134                 struct ixgbe_rx_buffer *rx_buffer_info;
 135         };
 136
 137         u16 head;
 138         u16 tail;
 139
 140         unsigned int total_bytes;
 141         unsigned int total_packets;
 142
 143         u16 reg_idx; /* holds the special value that gets the hardware register
 144                       * offset associated with this ring, which is different
 145                       * for DCE and RSS modes */
 146
 147 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
 148         /* cpu for tx queue */
 149         int cpu;
 150 #endif
 151         struct net_lro_mgr lro_mgr;
 152         bool lro_used;
 153         struct ixgbe_queue_stats stats;
 154         u16 v_idx; /* maps directly to the index for this ring in the hardware
 155                    * vector array, can also be used for finding the bit in EICR
 156                    * and friends that represents the vector for this ring */
 157
 158
 159         u16 work_limit;                /* max work per interrupt */
 160         u16 rx_buf_len;
 161 };
 162
 163 #define RING_F_VMDQ 1
 164 #define RING_F_RSS  2
 165 #define IXGBE_MAX_RSS_INDICES  16
 166 #define IXGBE_MAX_VMDQ_INDICES 16
 167 struct ixgbe_ring_feature {
 168         int indices;
 169         int mask;
 170 };
 171
 172 #define MAX_RX_QUEUES 64
 173 #define MAX_TX_QUEUES 32
 174
 175 /* MAX_MSIX_Q_VECTORS of these are allocated,
 176  * but we only use one per queue-specific vector.
 177  */
 178 struct ixgbe_q_vector {
 179         struct ixgbe_adapter *adapter;
 180         struct napi_struct napi;
 181         DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
 182         DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
 183         u8 rxr_count;     /* Rx ring count assigned to this vector */
 184         u8 txr_count;     /* Tx ring count assigned to this vector */
 185         u8 tx_itr;
 186         u8 rx_itr;
 187         u32 eitr;
 188 };
 189
 190 /* Helper macros to switch between ints/sec and what the register uses.
 191  * And yes, it's the same math going both ways.
 192  */
 193 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
 194         ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
 195 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
 196
 197 #define IXGBE_DESC_UNUSED(R) \
 198         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 199         (R)->next_to_clean - (R)->next_to_use - 1)
 200
 201 #define IXGBE_RX_DESC_ADV(R, i)     \
 202         (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
 203 #define IXGBE_TX_DESC_ADV(R, i)     \
 204         (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
 205 #define IXGBE_TX_CTXTDESC_ADV(R, i)         \
 206         (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
 207
 208 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 209
 210 #define OTHER_VECTOR 1
 211 #define NON_Q_VECTORS (OTHER_VECTOR)
 212
 213 #define MAX_MSIX_Q_VECTORS 16
 214 #define MIN_MSIX_Q_VECTORS 2
 215 #define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
 216 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 217
 218 /* board specific private data structure */
 219 struct ixgbe_adapter {
 220         struct timer_list watchdog_timer;
 221         struct vlan_group *vlgrp;
 222         u16 bd_number;
 223         struct work_struct reset_task;
 224         struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
 225         char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
 226
 227         /* Interrupt Throttle Rate */
 228         u32 itr_setting;
 229         u16 eitr_low;
 230         u16 eitr_high;
 231
 232         /* TX */
 233         struct ixgbe_ring *tx_ring;     /* One per active queue */
 234         int num_tx_queues;
 235         u64 restart_queue;
 236         u64 hw_csum_tx_good;
 237         u64 lsc_int;
 238         u64 hw_tso_ctxt;
 239         u64 hw_tso6_ctxt;
 240         u32 tx_timeout_count;
 241         bool detect_tx_hung;
 242
 243         /* RX */
 244         struct ixgbe_ring *rx_ring;     /* One per active queue */
 245         int num_rx_queues;
 246         u64 hw_csum_rx_error;
 247         u64 hw_csum_rx_good;
 248         u64 non_eop_descs;
 249         int num_msix_vectors;
 250         struct ixgbe_ring_feature ring_feature[3];
 251         struct msix_entry *msix_entries;
 252
 253         u64 rx_hdr_split;
 254         u32 alloc_rx_page_failed;
 255         u32 alloc_rx_buff_failed;
 256
 257         /* Some features need tri-state capability,
 258          * thus the additional *_CAPABLE flags.
 259          */
 260         u32 flags;
 261 #define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
 262 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
 263 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
 264 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
 265 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
 266 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
 267 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
 268 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
 269 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
 270 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
 271 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
 272 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
 273 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
 274 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
 275 #define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
 276 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
 277 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
 278 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
 279 #define IXGBE_FLAG_IN_WATCHDOG_TASK             (u32)(1 << 23)
 280
 281 /* default to trying for four seconds */
 282 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 283
 284         /* OS defined structs */
 285         struct net_device *netdev;
 286         struct pci_dev *pdev;
 287         struct net_device_stats net_stats;
 288
 289         /* structs defined in ixgbe_hw.h */
 290         struct ixgbe_hw hw;
 291         u16 msg_enable;
 292         struct ixgbe_hw_stats stats;
 293
 294         /* Interrupt Throttle Rate */
 295         u32 eitr_param;
 296
 297         unsigned long state;
 298         u64 tx_busy;
 299         u64 lro_aggregated;
 300         u64 lro_flushed;
 301         u64 lro_no_desc;
 302         unsigned int tx_ring_count;
 303         unsigned int rx_ring_count;
 304
 305         u32 link_speed;
 306         bool link_up;
 307         unsigned long link_check_timeout;
 308
 309         struct work_struct watchdog_task;
 310 };
 311
 312 enum ixbge_state_t {
 313         __IXGBE_TESTING,
 314         __IXGBE_RESETTING,
 315         __IXGBE_DOWN
 316 };
 317
 318 enum ixgbe_boards {
 319         board_82598,
 320 };
 321
 322 extern struct ixgbe_info ixgbe_82598_info;
 323
 324 extern char ixgbe_driver_name[];
 325 extern const char ixgbe_driver_version[];
 326
 327 extern int ixgbe_up(struct ixgbe_adapter *adapter);
 328 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 329 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 330 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 331 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 332 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 333 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
 334                                     struct ixgbe_ring *rxdr);
 335 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
 336                                     struct ixgbe_ring *txdr);
 337 extern void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
 338                                     struct ixgbe_ring *rxdr);
 339 extern void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
 340                                     struct ixgbe_ring *txdr);
 341
 342 #endif /* _IXGBE_H_ */