1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/bitops.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/cpumask.h>
36 #include <linux/aer.h>
37 #include <linux/if_vlan.h>
39 #include "ixgbe_type.h"
40 #include "ixgbe_common.h"
41 #include "ixgbe_dcb.h"
42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
44 #include "ixgbe_fcoe.h"
45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
46 #ifdef CONFIG_IXGBE_DCA
47 #include <linux/dca.h>
50 /* common prefix used by pr_<> macros */
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
54 /* TX/RX descriptor defines */
55 #define IXGBE_DEFAULT_TXD 512
56 #define IXGBE_MAX_TXD 4096
57 #define IXGBE_MIN_TXD 64
59 #define IXGBE_DEFAULT_RXD 512
60 #define IXGBE_MAX_RXD 4096
61 #define IXGBE_MIN_RXD 64
64 #define IXGBE_MIN_FCRTL 0x40
65 #define IXGBE_MAX_FCRTL 0x7FF80
66 #define IXGBE_MIN_FCRTH 0x600
67 #define IXGBE_MAX_FCRTH 0x7FFF0
68 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
69 #define IXGBE_MIN_FCPAUSE 0
70 #define IXGBE_MAX_FCPAUSE 0xFFFF
72 /* Supported Rx Buffer Sizes */
73 #define IXGBE_RXBUFFER_512 512 /* Used for packet split */
74 #define IXGBE_RXBUFFER_2048 2048
75 #define IXGBE_RXBUFFER_4096 4096
76 #define IXGBE_RXBUFFER_8192 8192
77 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
80 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
81 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
82 * this adds up to 512 bytes of extra data meaning the smallest allocation
83 * we could have is 1K.
84 * i.e. RXBUFFER_512 --> size-1024 slab
86 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
88 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
90 /* How many Rx Buffers do we bundle into one write to the hardware ? */
91 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
93 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
94 #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
95 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
96 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
97 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
98 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
99 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
100 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
101 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
103 #define IXGBE_MAX_RSC_INT_RATE 162760
105 #define IXGBE_MAX_VF_MC_ENTRIES 30
106 #define IXGBE_MAX_VF_FUNCTIONS 64
107 #define IXGBE_MAX_VFTA_ENTRIES 128
108 #define MAX_EMULATION_MAC_ADDRS 16
109 #define VMDQ_P(p) ((p) + adapter->num_vfs)
111 struct vf_data_storage
{
112 unsigned char vf_mac_addresses
[ETH_ALEN
];
113 u16 vf_mc_hashes
[IXGBE_MAX_VF_MC_ENTRIES
];
114 u16 num_vf_mc_hashes
;
115 u16 default_vf_vlan_id
;
119 u16 pf_vlan
; /* When set, guest VLAN config not allowed. */
123 /* wrapper around a pointer to a socket buffer,
124 * so a DMA handle can be stored along with the buffer */
125 struct ixgbe_tx_buffer
{
128 unsigned long time_stamp
;
131 unsigned int bytecount
;
136 struct ixgbe_rx_buffer
{
141 unsigned int page_offset
;
144 struct ixgbe_queue_stats
{
149 struct ixgbe_tx_queue_stats
{
156 struct ixgbe_rx_queue_stats
{
160 u64 alloc_rx_page_failed
;
161 u64 alloc_rx_buff_failed
;
164 enum ixbge_ring_state_t
{
165 __IXGBE_TX_FDIR_INIT_DONE
,
166 __IXGBE_TX_DETECT_HANG
,
167 __IXGBE_HANG_CHECK_ARMED
,
168 __IXGBE_RX_PS_ENABLED
,
169 __IXGBE_RX_RSC_ENABLED
,
172 #define ring_is_ps_enabled(ring) \
173 test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
174 #define set_ring_ps_enabled(ring) \
175 set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
176 #define clear_ring_ps_enabled(ring) \
177 clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
178 #define check_for_tx_hang(ring) \
179 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
180 #define set_check_for_tx_hang(ring) \
181 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
182 #define clear_check_for_tx_hang(ring) \
183 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
184 #define ring_is_rsc_enabled(ring) \
185 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
186 #define set_ring_rsc_enabled(ring) \
187 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
188 #define clear_ring_rsc_enabled(ring) \
189 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
191 void *desc
; /* descriptor ring memory */
192 struct device
*dev
; /* device for DMA mapping */
193 struct net_device
*netdev
; /* netdev ring belongs to */
195 struct ixgbe_tx_buffer
*tx_buffer_info
;
196 struct ixgbe_rx_buffer
*rx_buffer_info
;
201 u16 count
; /* amount of descriptors */
206 u8 queue_index
; /* needed for multiqueue queue management */
207 u8 reg_idx
; /* holds the special value that gets
208 * the hardware register offset
209 * associated with this ring, which is
210 * different for DCB and RSS modes
213 u16 work_limit
; /* max work per interrupt */
217 unsigned int total_bytes
;
218 unsigned int total_packets
;
220 struct ixgbe_queue_stats stats
;
221 struct u64_stats_sync syncp
;
223 struct ixgbe_tx_queue_stats tx_stats
;
224 struct ixgbe_rx_queue_stats rx_stats
;
227 unsigned int size
; /* length in bytes */
228 dma_addr_t dma
; /* phys. address of descriptor ring */
230 struct ixgbe_q_vector
*q_vector
; /* back-pointer to host q_vector */
231 } ____cacheline_internodealigned_in_smp
;
233 enum ixgbe_ring_f_enum
{
236 RING_F_VMDQ
, /* SR-IOV uses the same ring feature */
241 #endif /* IXGBE_FCOE */
243 RING_F_ARRAY_SIZE
/* must be last in enum set */
246 #define IXGBE_MAX_DCB_INDICES 8
247 #define IXGBE_MAX_RSS_INDICES 16
248 #define IXGBE_MAX_VMDQ_INDICES 64
249 #define IXGBE_MAX_FDIR_INDICES 64
251 #define IXGBE_MAX_FCOE_INDICES 8
252 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
253 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
255 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
256 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
257 #endif /* IXGBE_FCOE */
258 struct ixgbe_ring_feature
{
261 } ____cacheline_internodealigned_in_smp
;
264 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
266 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
268 /* MAX_MSIX_Q_VECTORS of these are allocated,
269 * but we only use one per queue-specific vector.
271 struct ixgbe_q_vector
{
272 struct ixgbe_adapter
*adapter
;
273 unsigned int v_idx
; /* index of q_vector within array, also used for
274 * finding the bit in EICR and friends that
275 * represents the vector for this ring */
276 #ifdef CONFIG_IXGBE_DCA
277 int cpu
; /* CPU for DCA */
279 struct napi_struct napi
;
280 DECLARE_BITMAP(rxr_idx
, MAX_RX_QUEUES
); /* Rx ring indices */
281 DECLARE_BITMAP(txr_idx
, MAX_TX_QUEUES
); /* Tx ring indices */
282 u8 rxr_count
; /* Rx ring count assigned to this vector */
283 u8 txr_count
; /* Tx ring count assigned to this vector */
287 cpumask_var_t affinity_mask
;
288 char name
[IFNAMSIZ
+ 9];
291 /* Helper macros to switch between ints/sec and what the register uses.
292 * And yes, it's the same math going both ways. The lowest value
293 * supported by all of the ixgbe hardware is 8.
295 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
296 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
297 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
299 #define IXGBE_DESC_UNUSED(R) \
300 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
301 (R)->next_to_clean - (R)->next_to_use - 1)
303 #define IXGBE_RX_DESC_ADV(R, i) \
304 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
305 #define IXGBE_TX_DESC_ADV(R, i) \
306 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
307 #define IXGBE_TX_CTXTDESC_ADV(R, i) \
308 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
310 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
312 /* Use 3K as the baby jumbo frame size for FCoE */
313 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
314 #endif /* IXGBE_FCOE */
316 #define OTHER_VECTOR 1
317 #define NON_Q_VECTORS (OTHER_VECTOR)
319 #define MAX_MSIX_VECTORS_82599 64
320 #define MAX_MSIX_Q_VECTORS_82599 64
321 #define MAX_MSIX_VECTORS_82598 18
322 #define MAX_MSIX_Q_VECTORS_82598 16
324 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
325 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
327 #define MIN_MSIX_Q_VECTORS 2
328 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
330 /* board specific private data structure */
331 struct ixgbe_adapter
{
332 struct timer_list watchdog_timer
;
333 unsigned long active_vlans
[BITS_TO_LONGS(VLAN_N_VID
)];
335 struct work_struct reset_task
;
336 struct ixgbe_q_vector
*q_vector
[MAX_MSIX_Q_VECTORS
];
337 struct ixgbe_dcb_config dcb_cfg
;
338 struct ixgbe_dcb_config temp_dcb_cfg
;
340 enum ixgbe_fc_mode last_lfc_mode
;
342 /* Interrupt Throttle Rate */
349 struct ixgbe_ring
*tx_ring
[MAX_TX_QUEUES
] ____cacheline_aligned_in_smp
;
351 u32 tx_timeout_count
;
358 struct ixgbe_ring
*rx_ring
[MAX_RX_QUEUES
] ____cacheline_aligned_in_smp
;
360 int num_rx_pools
; /* == num_rx_queues in 82598 */
361 int num_rx_queues_per_pool
; /* 1 if 82598, can be many if 82599 */
362 u64 hw_csum_rx_error
;
363 u64 hw_rx_no_dma_resources
;
365 int num_msix_vectors
;
366 int max_msix_q_vectors
; /* true count of q_vectors for device */
367 struct ixgbe_ring_feature ring_feature
[RING_F_ARRAY_SIZE
];
368 struct msix_entry
*msix_entries
;
370 u32 alloc_rx_page_failed
;
371 u32 alloc_rx_buff_failed
;
373 /* Some features need tri-state capability,
374 * thus the additional *_CAPABLE flags.
377 #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
378 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
379 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
380 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
381 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
382 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
383 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
384 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
385 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
386 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
387 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
388 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
389 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
390 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
391 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
392 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
393 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
394 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
395 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
396 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
397 #define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23)
398 #define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24)
399 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25)
400 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26)
401 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27)
402 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28)
403 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29)
404 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30)
407 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
408 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
409 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
410 /* default to trying for four seconds */
411 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
413 /* OS defined structs */
414 struct net_device
*netdev
;
415 struct pci_dev
*pdev
;
418 struct ixgbe_ring test_tx_ring
;
419 struct ixgbe_ring test_rx_ring
;
421 /* structs defined in ixgbe_hw.h */
424 struct ixgbe_hw_stats stats
;
426 /* Interrupt Throttle Rate */
432 unsigned int tx_ring_count
;
433 unsigned int rx_ring_count
;
437 unsigned long link_check_timeout
;
439 struct work_struct watchdog_task
;
440 struct work_struct sfp_task
;
441 struct timer_list sfp_timer
;
442 struct work_struct multispeed_fiber_task
;
443 struct work_struct sfp_config_module_task
;
446 spinlock_t fdir_perfect_lock
;
447 struct work_struct fdir_reinit_task
;
449 struct ixgbe_fcoe fcoe
;
450 #endif /* IXGBE_FCOE */
457 struct work_struct check_overtemp_task
;
459 char lsc_int_name
[IFNAMSIZ
+ 9];
462 DECLARE_BITMAP(active_vfs
, IXGBE_MAX_VF_FUNCTIONS
);
463 unsigned int num_vfs
;
464 struct vf_data_storage
*vfinfo
;
471 __IXGBE_SFP_MODULE_NOT_FOUND
474 struct ixgbe_rsc_cb
{
479 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
487 extern struct ixgbe_info ixgbe_82598_info
;
488 extern struct ixgbe_info ixgbe_82599_info
;
489 extern struct ixgbe_info ixgbe_X540_info
;
490 #ifdef CONFIG_IXGBE_DCB
491 extern const struct dcbnl_rtnl_ops dcbnl_ops
;
492 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config
*src_dcb_cfg
,
493 struct ixgbe_dcb_config
*dst_dcb_cfg
,
497 extern char ixgbe_driver_name
[];
498 extern const char ixgbe_driver_version
[];
500 extern int ixgbe_up(struct ixgbe_adapter
*adapter
);
501 extern void ixgbe_down(struct ixgbe_adapter
*adapter
);
502 extern void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
);
503 extern void ixgbe_reset(struct ixgbe_adapter
*adapter
);
504 extern void ixgbe_set_ethtool_ops(struct net_device
*netdev
);
505 extern int ixgbe_setup_rx_resources(struct ixgbe_ring
*);
506 extern int ixgbe_setup_tx_resources(struct ixgbe_ring
*);
507 extern void ixgbe_free_rx_resources(struct ixgbe_ring
*);
508 extern void ixgbe_free_tx_resources(struct ixgbe_ring
*);
509 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter
*,struct ixgbe_ring
*);
510 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter
*,struct ixgbe_ring
*);
511 extern void ixgbe_update_stats(struct ixgbe_adapter
*adapter
);
512 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
);
513 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
);
514 extern netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*,
515 struct ixgbe_adapter
*,
516 struct ixgbe_ring
*);
517 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring
*,
518 struct ixgbe_tx_buffer
*);
519 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring
*, u16
);
520 extern void ixgbe_write_eitr(struct ixgbe_q_vector
*);
521 extern int ethtool_ioctl(struct ifreq
*ifr
);
522 extern u8
ixgbe_dcb_txq_to_tc(struct ixgbe_adapter
*adapter
, u8 index
);
523 extern s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
);
524 extern s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 pballoc
);
525 extern s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 pballoc
);
526 extern s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
527 struct ixgbe_atr_input
*input
,
529 extern s32
ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw
*hw
,
530 struct ixgbe_atr_input
*input
,
531 struct ixgbe_atr_input_masks
*input_masks
,
532 u16 soft_id
, u8 queue
);
533 extern s32
ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input
*input
,
535 extern s32
ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input
*input
,
537 extern s32
ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input
*input
,
539 extern s32
ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input
*input
,
541 extern s32
ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input
*input
,
543 extern s32
ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input
*input
,
545 extern s32
ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input
*input
,
547 extern void ixgbe_set_rx_mode(struct net_device
*netdev
);
549 extern void ixgbe_configure_fcoe(struct ixgbe_adapter
*adapter
);
550 extern int ixgbe_fso(struct ixgbe_adapter
*adapter
,
551 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
552 u32 tx_flags
, u8
*hdr_len
);
553 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter
*adapter
);
554 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter
*adapter
,
555 union ixgbe_adv_rx_desc
*rx_desc
,
556 struct sk_buff
*skb
);
557 extern int ixgbe_fcoe_ddp_get(struct net_device
*netdev
, u16 xid
,
558 struct scatterlist
*sgl
, unsigned int sgc
);
559 extern int ixgbe_fcoe_ddp_put(struct net_device
*netdev
, u16 xid
);
560 extern int ixgbe_fcoe_enable(struct net_device
*netdev
);
561 extern int ixgbe_fcoe_disable(struct net_device
*netdev
);
562 #ifdef CONFIG_IXGBE_DCB
563 extern u8
ixgbe_fcoe_getapp(struct ixgbe_adapter
*adapter
);
564 extern u8
ixgbe_fcoe_setapp(struct ixgbe_adapter
*adapter
, u8 up
);
565 #endif /* CONFIG_IXGBE_DCB */
566 extern int ixgbe_fcoe_get_wwn(struct net_device
*netdev
, u64
*wwn
, int type
);
567 #endif /* IXGBE_FCOE */
569 #endif /* _IXGBE_H_ */