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[mirror_ubuntu-artful-kernel.git] / drivers / net / ixgbe / ixgbe_82599.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34
35 #define IXGBE_82599_MAX_TX_QUEUES 128
36 #define IXGBE_82599_MAX_RX_QUEUES 128
37 #define IXGBE_82599_RAR_ENTRIES 128
38 #define IXGBE_82599_MC_TBL_SIZE 128
39 #define IXGBE_82599_VFT_TBL_SIZE 128
40
41 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
45 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
46 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed, bool autoneg,
48 bool autoneg_wait_to_complete);
49 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
50 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
51 ixgbe_link_speed *speed,
52 bool *link_up, bool link_up_wait_to_complete);
53 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
55 bool autoneg,
56 bool autoneg_wait_to_complete);
57 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed *speed,
59 bool *autoneg);
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
61 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
62 ixgbe_link_speed speed,
63 bool autoneg,
64 bool autoneg_wait_to_complete);
65 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
66 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
68 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
69 u32 vind, bool vlan_on);
70 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
71 s32 ixgbe_blink_led_stop_82599(struct ixgbe_hw *hw, u32 index);
72 s32 ixgbe_blink_led_start_82599(struct ixgbe_hw *hw, u32 index);
73 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
74 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
75 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
76 s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
77 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
78 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
79 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
80
81 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
82 {
83 struct ixgbe_mac_info *mac = &hw->mac;
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link =
87 &ixgbe_setup_mac_link_multispeed_fiber;
88 mac->ops.setup_link_speed =
89 &ixgbe_setup_mac_link_speed_multispeed_fiber;
90 } else {
91 mac->ops.setup_link =
92 &ixgbe_setup_mac_link_82599;
93 mac->ops.setup_link_speed =
94 &ixgbe_setup_mac_link_speed_82599;
95 }
96 }
97
98 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
99 {
100 s32 ret_val = 0;
101 u16 list_offset, data_offset, data_value;
102
103 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
104 ixgbe_init_mac_link_ops_82599(hw);
105 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
106 &data_offset);
107
108 if (ret_val != 0)
109 goto setup_sfp_out;
110
111 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
112 while (data_value != 0xffff) {
113 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
114 IXGBE_WRITE_FLUSH(hw);
115 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
116 }
117 /* Now restart DSP */
118 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102);
119 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d);
120 IXGBE_WRITE_FLUSH(hw);
121 }
122
123 setup_sfp_out:
124 return ret_val;
125 }
126
127 /**
128 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
129 * @hw: pointer to hardware structure
130 *
131 * Read PCIe configuration space, and get the MSI-X vector count from
132 * the capabilities table.
133 **/
134 u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
135 {
136 struct ixgbe_adapter *adapter = hw->back;
137 u16 msix_count;
138 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
139 &msix_count);
140 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
141
142 /* MSI-X count is zero-based in HW, so increment to give proper value */
143 msix_count++;
144
145 return msix_count;
146 }
147
148 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
149 {
150 struct ixgbe_mac_info *mac = &hw->mac;
151 struct ixgbe_phy_info *phy = &hw->phy;
152 s32 ret_val;
153
154 /* Set the bus information prior to PHY identification */
155 mac->ops.get_bus_info(hw);
156
157 /* Call PHY identify routine to get the Cu or SFI phy type */
158 ret_val = phy->ops.identify(hw);
159
160 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
161 goto get_invariants_out;
162
163 ixgbe_init_mac_link_ops_82599(hw);
164
165 /* Setup SFP module if there is one present. */
166 ret_val = mac->ops.setup_sfp(hw);
167
168 /* If copper media, overwrite with copper function pointers */
169 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
170 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
171 mac->ops.setup_link_speed =
172 &ixgbe_setup_copper_link_speed_82599;
173 mac->ops.get_link_capabilities =
174 &ixgbe_get_copper_link_capabilities_82599;
175 }
176
177 /* PHY Init */
178 switch (hw->phy.type) {
179 case ixgbe_phy_tn:
180 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
181 phy->ops.get_firmware_version =
182 &ixgbe_get_phy_firmware_version_tnx;
183 break;
184 default:
185 break;
186 }
187
188 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
189 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
190 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
191 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
192 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
193 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
194
195 get_invariants_out:
196 return ret_val;
197 }
198
199 /**
200 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
201 * @hw: pointer to hardware structure
202 * @speed: pointer to link speed
203 * @negotiation: true when autoneg or autotry is enabled
204 *
205 * Determines the link capabilities by reading the AUTOC register.
206 **/
207 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
208 ixgbe_link_speed *speed,
209 bool *negotiation)
210 {
211 s32 status = 0;
212
213 switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
214 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
215 *speed = IXGBE_LINK_SPEED_1GB_FULL;
216 *negotiation = false;
217 break;
218
219 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
220 *speed = IXGBE_LINK_SPEED_10GB_FULL;
221 *negotiation = false;
222 break;
223
224 case IXGBE_AUTOC_LMS_1G_AN:
225 *speed = IXGBE_LINK_SPEED_1GB_FULL;
226 *negotiation = true;
227 break;
228
229 case IXGBE_AUTOC_LMS_10G_SERIAL:
230 *speed = IXGBE_LINK_SPEED_10GB_FULL;
231 *negotiation = false;
232 break;
233
234 case IXGBE_AUTOC_LMS_KX4_KX_KR:
235 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
236 *speed = IXGBE_LINK_SPEED_UNKNOWN;
237 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
238 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
239 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
240 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
241 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
242 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
243 *negotiation = true;
244 break;
245
246 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
247 *speed = IXGBE_LINK_SPEED_100_FULL;
248 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
249 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
250 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
251 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
252 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
253 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
254 *negotiation = true;
255 break;
256
257 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
258 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
259 *negotiation = false;
260 break;
261
262 default:
263 status = IXGBE_ERR_LINK_SETUP;
264 goto out;
265 break;
266 }
267
268 if (hw->phy.multispeed_fiber) {
269 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
270 IXGBE_LINK_SPEED_1GB_FULL;
271 *negotiation = true;
272 }
273
274 out:
275 return status;
276 }
277
278 /**
279 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
280 * @hw: pointer to hardware structure
281 * @speed: pointer to link speed
282 * @autoneg: boolean auto-negotiation value
283 *
284 * Determines the link capabilities by reading the AUTOC register.
285 **/
286 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
287 ixgbe_link_speed *speed,
288 bool *autoneg)
289 {
290 s32 status = IXGBE_ERR_LINK_SETUP;
291 u16 speed_ability;
292
293 *speed = 0;
294 *autoneg = true;
295
296 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
297 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
298 &speed_ability);
299
300 if (status == 0) {
301 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
302 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
303 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
304 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
305 }
306
307 return status;
308 }
309
310 /**
311 * ixgbe_get_media_type_82599 - Get media type
312 * @hw: pointer to hardware structure
313 *
314 * Returns the media type (fiber, copper, backplane)
315 **/
316 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
317 {
318 enum ixgbe_media_type media_type;
319
320 /* Detect if there is a copper PHY attached. */
321 if (hw->phy.type == ixgbe_phy_cu_unknown ||
322 hw->phy.type == ixgbe_phy_tn) {
323 media_type = ixgbe_media_type_copper;
324 goto out;
325 }
326
327 switch (hw->device_id) {
328 case IXGBE_DEV_ID_82599:
329 case IXGBE_DEV_ID_82599_KX4:
330 /* Default device ID is mezzanine card KX/KX4 */
331 media_type = ixgbe_media_type_backplane;
332 break;
333 case IXGBE_DEV_ID_82599_SFP:
334 media_type = ixgbe_media_type_fiber;
335 break;
336 default:
337 media_type = ixgbe_media_type_unknown;
338 break;
339 }
340 out:
341 return media_type;
342 }
343
344 /**
345 * ixgbe_setup_mac_link_82599 - Setup MAC link settings
346 * @hw: pointer to hardware structure
347 *
348 * Configures link settings based on values in the ixgbe_hw struct.
349 * Restarts the link. Performs autonegotiation if needed.
350 **/
351 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
352 {
353 u32 autoc_reg;
354 u32 links_reg;
355 u32 i;
356 s32 status = 0;
357
358 /* Restart link */
359 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
360 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
361 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
362
363 /* Only poll for autoneg to complete if specified to do so */
364 if (hw->phy.autoneg_wait_to_complete) {
365 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
366 IXGBE_AUTOC_LMS_KX4_KX_KR ||
367 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
368 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
369 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
370 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
371 links_reg = 0; /* Just in case Autoneg time = 0 */
372 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
373 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
374 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
375 break;
376 msleep(100);
377 }
378 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
379 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
380 hw_dbg(hw, "Autoneg did not complete.\n");
381 }
382 }
383 }
384
385 /* Set up flow control */
386 status = ixgbe_setup_fc_generic(hw, 0);
387
388 /* Add delay to filter out noises during initial link setup */
389 msleep(50);
390
391 return status;
392 }
393
394 /**
395 * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
396 * @hw: pointer to hardware structure
397 *
398 * Configures link settings based on values in the ixgbe_hw struct.
399 * Restarts the link for multi-speed fiber at 1G speed, if link
400 * fails at 10G.
401 * Performs autonegotiation if needed.
402 **/
403 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
404 {
405 s32 status = 0;
406 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
407 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
408 true, true);
409 return status;
410 }
411
412 /**
413 * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
414 * @hw: pointer to hardware structure
415 * @speed: new link speed
416 * @autoneg: true if autonegotiation enabled
417 * @autoneg_wait_to_complete: true when waiting for completion is needed
418 *
419 * Set the link speed in the AUTOC register and restarts link.
420 **/
421 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
422 ixgbe_link_speed speed,
423 bool autoneg,
424 bool autoneg_wait_to_complete)
425 {
426 s32 status = 0;
427 ixgbe_link_speed phy_link_speed;
428 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
429 u32 speedcnt = 0;
430 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
431 bool link_up = false;
432 bool negotiation;
433
434 /* Mask off requested but non-supported speeds */
435 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
436 speed &= phy_link_speed;
437
438 /*
439 * Try each speed one by one, highest priority first. We do this in
440 * software because 10gb fiber doesn't support speed autonegotiation.
441 */
442 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
443 speedcnt++;
444 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
445
446 /* Set hardware SDP's */
447 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
448 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
449
450 ixgbe_setup_mac_link_speed_82599(hw,
451 IXGBE_LINK_SPEED_10GB_FULL,
452 autoneg,
453 autoneg_wait_to_complete);
454
455 msleep(50);
456
457 /* If we have link, just jump out */
458 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
459 if (link_up)
460 goto out;
461 }
462
463 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
464 speedcnt++;
465 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
466 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
467
468 /* Set hardware SDP's */
469 esdp_reg &= ~IXGBE_ESDP_SDP5;
470 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
471 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
472
473 ixgbe_setup_mac_link_speed_82599(
474 hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
475 autoneg_wait_to_complete);
476
477 msleep(50);
478
479 /* If we have link, just jump out */
480 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
481 if (link_up)
482 goto out;
483 }
484
485 /*
486 * We didn't get link. Configure back to the highest speed we tried,
487 * (if there was more than one). We call ourselves back with just the
488 * single highest speed that the user requested.
489 */
490 if (speedcnt > 1)
491 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
492 highest_link_speed,
493 autoneg,
494 autoneg_wait_to_complete);
495
496 out:
497 return status;
498 }
499
500 /**
501 * ixgbe_check_mac_link_82599 - Determine link and speed status
502 * @hw: pointer to hardware structure
503 * @speed: pointer to link speed
504 * @link_up: true when link is up
505 * @link_up_wait_to_complete: bool used to wait for link up or not
506 *
507 * Reads the links register to determine if link is up and the current speed
508 **/
509 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
510 bool *link_up, bool link_up_wait_to_complete)
511 {
512 u32 links_reg;
513 u32 i;
514
515 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
516 if (link_up_wait_to_complete) {
517 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
518 if (links_reg & IXGBE_LINKS_UP) {
519 *link_up = true;
520 break;
521 } else {
522 *link_up = false;
523 }
524 msleep(100);
525 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
526 }
527 } else {
528 if (links_reg & IXGBE_LINKS_UP)
529 *link_up = true;
530 else
531 *link_up = false;
532 }
533
534 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
535 IXGBE_LINKS_SPEED_10G_82599)
536 *speed = IXGBE_LINK_SPEED_10GB_FULL;
537 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
538 IXGBE_LINKS_SPEED_1G_82599)
539 *speed = IXGBE_LINK_SPEED_1GB_FULL;
540 else
541 *speed = IXGBE_LINK_SPEED_100_FULL;
542
543
544 return 0;
545 }
546
547 /**
548 * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
549 * @hw: pointer to hardware structure
550 * @speed: new link speed
551 * @autoneg: true if autonegotiation enabled
552 * @autoneg_wait_to_complete: true when waiting for completion is needed
553 *
554 * Set the link speed in the AUTOC register and restarts link.
555 **/
556 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
557 ixgbe_link_speed speed, bool autoneg,
558 bool autoneg_wait_to_complete)
559 {
560 s32 status = 0;
561 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
562 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
563 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
564 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
565 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
566 u32 links_reg;
567 u32 i;
568 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
569
570 /* Check to see if speed passed in is supported. */
571 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
572 speed &= link_capabilities;
573
574 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
575 status = IXGBE_ERR_LINK_SETUP;
576 } else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
577 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
578 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
579 /* Set KX4/KX/KR support according to speed requested */
580 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
581 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
582 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
583 autoc |= IXGBE_AUTOC_KX4_SUPP;
584 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
585 autoc |= IXGBE_AUTOC_KR_SUPP;
586 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
587 autoc |= IXGBE_AUTOC_KX_SUPP;
588 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
589 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
590 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
591 /* Switch from 1G SFI to 10G SFI if requested */
592 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
593 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
594 autoc &= ~IXGBE_AUTOC_LMS_MASK;
595 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
596 }
597 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
598 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
599 /* Switch from 10G SFI to 1G SFI if requested */
600 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
601 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
602 autoc &= ~IXGBE_AUTOC_LMS_MASK;
603 if (autoneg)
604 autoc |= IXGBE_AUTOC_LMS_1G_AN;
605 else
606 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
607 }
608 }
609
610 if (status == 0) {
611 /* Restart link */
612 autoc |= IXGBE_AUTOC_AN_RESTART;
613 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
614
615 /* Only poll for autoneg to complete if specified to do so */
616 if (autoneg_wait_to_complete) {
617 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
618 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
619 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
620 links_reg = 0; /*Just in case Autoneg time=0*/
621 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
622 links_reg =
623 IXGBE_READ_REG(hw, IXGBE_LINKS);
624 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
625 break;
626 msleep(100);
627 }
628 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
629 status =
630 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
631 hw_dbg(hw, "Autoneg did not "
632 "complete.\n");
633 }
634 }
635 }
636
637 /* Set up flow control */
638 status = ixgbe_setup_fc_generic(hw, 0);
639
640 /* Add delay to filter out noises during initial link setup */
641 msleep(50);
642 }
643
644 return status;
645 }
646
647 /**
648 * ixgbe_setup_copper_link_82599 - Setup copper link settings
649 * @hw: pointer to hardware structure
650 *
651 * Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
652 **/
653 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
654 {
655 s32 status;
656
657 /* Restart autonegotiation on PHY */
658 status = hw->phy.ops.setup_link(hw);
659
660 /* Set up MAC */
661 ixgbe_setup_mac_link_82599(hw);
662
663 return status;
664 }
665
666 /**
667 * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
668 * @hw: pointer to hardware structure
669 * @speed: new link speed
670 * @autoneg: true if autonegotiation enabled
671 * @autoneg_wait_to_complete: true if waiting is needed to complete
672 *
673 * Restarts link on PHY and MAC based on settings passed in.
674 **/
675 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
676 ixgbe_link_speed speed,
677 bool autoneg,
678 bool autoneg_wait_to_complete)
679 {
680 s32 status;
681
682 /* Setup the PHY according to input speed */
683 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
684 autoneg_wait_to_complete);
685 /* Set up MAC */
686 ixgbe_setup_mac_link_82599(hw);
687
688 return status;
689 }
690
691 /**
692 * ixgbe_reset_hw_82599 - Perform hardware reset
693 * @hw: pointer to hardware structure
694 *
695 * Resets the hardware by resetting the transmit and receive units, masks
696 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
697 * reset.
698 **/
699 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
700 {
701 s32 status = 0;
702 u32 ctrl, ctrl_ext;
703 u32 i;
704 u32 autoc;
705 u32 autoc2;
706
707 /* Call adapter stop to disable tx/rx and clear interrupts */
708 hw->mac.ops.stop_adapter(hw);
709
710 /* Reset PHY */
711 hw->phy.ops.reset(hw);
712
713 /*
714 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
715 * access and verify no pending requests before reset
716 */
717 if (ixgbe_disable_pcie_master(hw) != 0) {
718 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
719 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
720 }
721
722 /*
723 * Issue global reset to the MAC. This needs to be a SW reset.
724 * If link reset is used, it might reset the MAC when mng is using it
725 */
726 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
727 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
728 IXGBE_WRITE_FLUSH(hw);
729
730 /* Poll for reset bit to self-clear indicating reset is complete */
731 for (i = 0; i < 10; i++) {
732 udelay(1);
733 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
734 if (!(ctrl & IXGBE_CTRL_RST))
735 break;
736 }
737 if (ctrl & IXGBE_CTRL_RST) {
738 status = IXGBE_ERR_RESET_FAILED;
739 hw_dbg(hw, "Reset polling failed to complete.\n");
740 }
741 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
742 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
743 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
744 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
745
746 msleep(50);
747
748
749
750 /*
751 * Store the original AUTOC/AUTOC2 values if they have not been
752 * stored off yet. Otherwise restore the stored original
753 * values since the reset operation sets back to defaults.
754 */
755 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
756 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
757 if (hw->mac.orig_link_settings_stored == false) {
758 hw->mac.orig_autoc = autoc;
759 hw->mac.orig_autoc2 = autoc2;
760 hw->mac.orig_link_settings_stored = true;
761 } else {
762 if (autoc != hw->mac.orig_autoc)
763 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
764 IXGBE_AUTOC_AN_RESTART));
765
766 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
767 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
768 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
769 autoc2 |= (hw->mac.orig_autoc2 &
770 IXGBE_AUTOC2_UPPER_MASK);
771 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
772 }
773 }
774
775 /* Store the permanent mac address */
776 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
777
778 return status;
779 }
780
781 /**
782 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
783 * @hw: pointer to hardware struct
784 * @rar: receive address register index to disassociate
785 * @vmdq: VMDq pool index to remove from the rar
786 **/
787 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
788 {
789 u32 mpsar_lo, mpsar_hi;
790 u32 rar_entries = hw->mac.num_rar_entries;
791
792 if (rar < rar_entries) {
793 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
794 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
795
796 if (!mpsar_lo && !mpsar_hi)
797 goto done;
798
799 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
800 if (mpsar_lo) {
801 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
802 mpsar_lo = 0;
803 }
804 if (mpsar_hi) {
805 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
806 mpsar_hi = 0;
807 }
808 } else if (vmdq < 32) {
809 mpsar_lo &= ~(1 << vmdq);
810 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
811 } else {
812 mpsar_hi &= ~(1 << (vmdq - 32));
813 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
814 }
815
816 /* was that the last pool using this rar? */
817 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
818 hw->mac.ops.clear_rar(hw, rar);
819 } else {
820 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
821 }
822
823 done:
824 return 0;
825 }
826
827 /**
828 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
829 * @hw: pointer to hardware struct
830 * @rar: receive address register index to associate with a VMDq index
831 * @vmdq: VMDq pool index
832 **/
833 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
834 {
835 u32 mpsar;
836 u32 rar_entries = hw->mac.num_rar_entries;
837
838 if (rar < rar_entries) {
839 if (vmdq < 32) {
840 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
841 mpsar |= 1 << vmdq;
842 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
843 } else {
844 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
845 mpsar |= 1 << (vmdq - 32);
846 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
847 }
848 } else {
849 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
850 }
851 return 0;
852 }
853
854 /**
855 * ixgbe_set_vfta_82599 - Set VLAN filter table
856 * @hw: pointer to hardware structure
857 * @vlan: VLAN id to write to VLAN filter
858 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
859 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
860 *
861 * Turn on/off specified VLAN in the VLAN filter table.
862 **/
863 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
864 bool vlan_on)
865 {
866 u32 regindex;
867 u32 bitindex;
868 u32 bits;
869 u32 first_empty_slot;
870
871 if (vlan > 4095)
872 return IXGBE_ERR_PARAM;
873
874 /*
875 * this is a 2 part operation - first the VFTA, then the
876 * VLVF and VLVFB if vind is set
877 */
878
879 /* Part 1
880 * The VFTA is a bitstring made up of 128 32-bit registers
881 * that enable the particular VLAN id, much like the MTA:
882 * bits[11-5]: which register
883 * bits[4-0]: which bit in the register
884 */
885 regindex = (vlan >> 5) & 0x7F;
886 bitindex = vlan & 0x1F;
887 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
888 if (vlan_on)
889 bits |= (1 << bitindex);
890 else
891 bits &= ~(1 << bitindex);
892 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
893
894
895 /* Part 2
896 * If the vind is set
897 * Either vlan_on
898 * make sure the vlan is in VLVF
899 * set the vind bit in the matching VLVFB
900 * Or !vlan_on
901 * clear the pool bit and possibly the vind
902 */
903 if (vind) {
904 /* find the vlanid or the first empty slot */
905 first_empty_slot = 0;
906
907 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
908 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
909 if (!bits && !first_empty_slot)
910 first_empty_slot = regindex;
911 else if ((bits & 0x0FFF) == vlan)
912 break;
913 }
914
915 if (regindex >= IXGBE_VLVF_ENTRIES) {
916 if (first_empty_slot)
917 regindex = first_empty_slot;
918 else {
919 hw_dbg(hw, "No space in VLVF.\n");
920 goto out;
921 }
922 }
923
924 if (vlan_on) {
925 /* set the pool bit */
926 if (vind < 32) {
927 bits = IXGBE_READ_REG(hw,
928 IXGBE_VLVFB(regindex * 2));
929 bits |= (1 << vind);
930 IXGBE_WRITE_REG(hw,
931 IXGBE_VLVFB(regindex * 2), bits);
932 } else {
933 bits = IXGBE_READ_REG(hw,
934 IXGBE_VLVFB((regindex * 2) + 1));
935 bits |= (1 << vind);
936 IXGBE_WRITE_REG(hw,
937 IXGBE_VLVFB((regindex * 2) + 1), bits);
938 }
939 } else {
940 /* clear the pool bit */
941 if (vind < 32) {
942 bits = IXGBE_READ_REG(hw,
943 IXGBE_VLVFB(regindex * 2));
944 bits &= ~(1 << vind);
945 IXGBE_WRITE_REG(hw,
946 IXGBE_VLVFB(regindex * 2), bits);
947 bits |= IXGBE_READ_REG(hw,
948 IXGBE_VLVFB((regindex * 2) + 1));
949 } else {
950 bits = IXGBE_READ_REG(hw,
951 IXGBE_VLVFB((regindex * 2) + 1));
952 bits &= ~(1 << vind);
953 IXGBE_WRITE_REG(hw,
954 IXGBE_VLVFB((regindex * 2) + 1), bits);
955 bits |= IXGBE_READ_REG(hw,
956 IXGBE_VLVFB(regindex * 2));
957 }
958 }
959
960 if (bits)
961 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
962 (IXGBE_VLVF_VIEN | vlan));
963 else
964 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
965 }
966
967 out:
968 return 0;
969 }
970
971 /**
972 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
973 * @hw: pointer to hardware structure
974 *
975 * Clears the VLAN filer table, and the VMDq index associated with the filter
976 **/
977 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
978 {
979 u32 offset;
980
981 for (offset = 0; offset < hw->mac.vft_size; offset++)
982 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
983
984 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
985 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
986 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
987 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
988 }
989
990 return 0;
991 }
992
993 /**
994 * ixgbe_blink_led_start_82599 - Blink LED based on index.
995 * @hw: pointer to hardware structure
996 * @index: led number to blink
997 **/
998 s32 ixgbe_blink_led_start_82599(struct ixgbe_hw *hw, u32 index)
999 {
1000 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1001
1002 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1003 led_reg |= IXGBE_LED_BLINK(index);
1004 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1005 IXGBE_WRITE_FLUSH(hw);
1006
1007 return 0;
1008 }
1009
1010 /**
1011 * ixgbe_blink_led_stop_82599 - Stop blinking LED based on index.
1012 * @hw: pointer to hardware structure
1013 * @index: led number to stop blinking
1014 **/
1015 s32 ixgbe_blink_led_stop_82599(struct ixgbe_hw *hw, u32 index)
1016 {
1017 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1018
1019 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1020 led_reg &= ~IXGBE_LED_BLINK(index);
1021 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1022 IXGBE_WRITE_FLUSH(hw);
1023
1024 return 0;
1025 }
1026
1027 /**
1028 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1029 * @hw: pointer to hardware structure
1030 **/
1031 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1032 {
1033 int i;
1034 hw_dbg(hw, " Clearing UTA\n");
1035
1036 for (i = 0; i < 128; i++)
1037 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1038
1039 return 0;
1040 }
1041
1042 /**
1043 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1044 * @hw: pointer to hardware structure
1045 * @reg: analog register to read
1046 * @val: read value
1047 *
1048 * Performs read operation to Omer analog register specified.
1049 **/
1050 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1051 {
1052 u32 core_ctl;
1053
1054 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1055 (reg << 8));
1056 IXGBE_WRITE_FLUSH(hw);
1057 udelay(10);
1058 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1059 *val = (u8)core_ctl;
1060
1061 return 0;
1062 }
1063
1064 /**
1065 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1066 * @hw: pointer to hardware structure
1067 * @reg: atlas register to write
1068 * @val: value to write
1069 *
1070 * Performs write operation to Omer analog register specified.
1071 **/
1072 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1073 {
1074 u32 core_ctl;
1075
1076 core_ctl = (reg << 8) | val;
1077 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1078 IXGBE_WRITE_FLUSH(hw);
1079 udelay(10);
1080
1081 return 0;
1082 }
1083
1084 /**
1085 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1086 * @hw: pointer to hardware structure
1087 *
1088 * Starts the hardware using the generic start_hw function.
1089 * Then performs device-specific:
1090 * Clears the rate limiter registers.
1091 **/
1092 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1093 {
1094 u32 q_num;
1095
1096 ixgbe_start_hw_generic(hw);
1097
1098 /* Clear the rate limiters */
1099 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1100 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1101 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1102 }
1103 IXGBE_WRITE_FLUSH(hw);
1104
1105 return 0;
1106 }
1107
1108 /**
1109 * ixgbe_identify_phy_82599 - Get physical layer module
1110 * @hw: pointer to hardware structure
1111 *
1112 * Determines the physical layer module found on the current adapter.
1113 **/
1114 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1115 {
1116 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1117 status = ixgbe_identify_phy_generic(hw);
1118 if (status != 0)
1119 status = ixgbe_identify_sfp_module_generic(hw);
1120 return status;
1121 }
1122
1123 /**
1124 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1125 * @hw: pointer to hardware structure
1126 *
1127 * Determines physical layer capabilities of the current configuration.
1128 **/
1129 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1130 {
1131 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1132 u8 comp_codes_10g = 0;
1133
1134 switch (hw->device_id) {
1135 case IXGBE_DEV_ID_82599:
1136 case IXGBE_DEV_ID_82599_KX4:
1137 /* Default device ID is mezzanine card KX/KX4 */
1138 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1139 IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1140 break;
1141 case IXGBE_DEV_ID_82599_SFP:
1142 hw->phy.ops.identify_sfp(hw);
1143
1144 switch (hw->phy.sfp_type) {
1145 case ixgbe_sfp_type_da_cu:
1146 case ixgbe_sfp_type_da_cu_core0:
1147 case ixgbe_sfp_type_da_cu_core1:
1148 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1149 break;
1150 case ixgbe_sfp_type_sr:
1151 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1152 break;
1153 case ixgbe_sfp_type_lr:
1154 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1155 break;
1156 case ixgbe_sfp_type_srlr_core0:
1157 case ixgbe_sfp_type_srlr_core1:
1158 hw->phy.ops.read_i2c_eeprom(hw,
1159 IXGBE_SFF_10GBE_COMP_CODES,
1160 &comp_codes_10g);
1161 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1162 physical_layer =
1163 IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1164 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1165 physical_layer =
1166 IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1167 else
1168 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1169 default:
1170 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1171 break;
1172 }
1173 break;
1174 default:
1175 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1176 break;
1177 }
1178
1179 return physical_layer;
1180 }
1181
1182 /**
1183 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1184 * @hw: pointer to hardware structure
1185 * @regval: register value to write to RXCTRL
1186 *
1187 * Enables the Rx DMA unit for 82599
1188 **/
1189 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1190 {
1191 #define IXGBE_MAX_SECRX_POLL 30
1192 int i;
1193 int secrxreg;
1194
1195 /*
1196 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1197 * If traffic is incoming before we enable the Rx unit, it could hang
1198 * the Rx DMA unit. Therefore, make sure the security engine is
1199 * completely disabled prior to enabling the Rx unit.
1200 */
1201 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1202 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1203 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1204 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1205 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1206 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1207 break;
1208 else
1209 udelay(10);
1210 }
1211
1212 /* For informational purposes only */
1213 if (i >= IXGBE_MAX_SECRX_POLL)
1214 hw_dbg(hw, "Rx unit being enabled before security "
1215 "path fully disabled. Continuing with init.\n");
1216
1217 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1218 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1219 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1220 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1221 IXGBE_WRITE_FLUSH(hw);
1222
1223 return 0;
1224 }
1225
1226 static struct ixgbe_mac_operations mac_ops_82599 = {
1227 .init_hw = &ixgbe_init_hw_generic,
1228 .reset_hw = &ixgbe_reset_hw_82599,
1229 .start_hw = &ixgbe_start_hw_82599,
1230 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1231 .get_media_type = &ixgbe_get_media_type_82599,
1232 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1233 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
1234 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1235 .stop_adapter = &ixgbe_stop_adapter_generic,
1236 .get_bus_info = &ixgbe_get_bus_info_generic,
1237 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1238 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
1239 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
1240 .setup_link = &ixgbe_setup_mac_link_82599,
1241 .setup_link_speed = &ixgbe_setup_mac_link_speed_82599,
1242 .check_link = &ixgbe_check_mac_link_82599,
1243 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
1244 .led_on = &ixgbe_led_on_generic,
1245 .led_off = &ixgbe_led_off_generic,
1246 .blink_led_start = &ixgbe_blink_led_start_82599,
1247 .blink_led_stop = &ixgbe_blink_led_stop_82599,
1248 .set_rar = &ixgbe_set_rar_generic,
1249 .clear_rar = &ixgbe_clear_rar_generic,
1250 .set_vmdq = &ixgbe_set_vmdq_82599,
1251 .clear_vmdq = &ixgbe_clear_vmdq_82599,
1252 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1253 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1254 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1255 .enable_mc = &ixgbe_enable_mc_generic,
1256 .disable_mc = &ixgbe_disable_mc_generic,
1257 .clear_vfta = &ixgbe_clear_vfta_82599,
1258 .set_vfta = &ixgbe_set_vfta_82599,
1259 .setup_fc = &ixgbe_setup_fc_generic,
1260 .init_uta_tables = &ixgbe_init_uta_tables_82599,
1261 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
1262 };
1263
1264 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1265 .init_params = &ixgbe_init_eeprom_params_generic,
1266 .read = &ixgbe_read_eeprom_generic,
1267 .write = &ixgbe_write_eeprom_generic,
1268 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1269 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1270 };
1271
1272 static struct ixgbe_phy_operations phy_ops_82599 = {
1273 .identify = &ixgbe_identify_phy_82599,
1274 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1275 .reset = &ixgbe_reset_phy_generic,
1276 .read_reg = &ixgbe_read_phy_reg_generic,
1277 .write_reg = &ixgbe_write_phy_reg_generic,
1278 .setup_link = &ixgbe_setup_phy_link_generic,
1279 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1280 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
1281 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
1282 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
1283 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
1284 };
1285
1286 struct ixgbe_info ixgbe_82599_info = {
1287 .mac = ixgbe_mac_82599EB,
1288 .get_invariants = &ixgbe_get_invariants_82599,
1289 .mac_ops = &mac_ops_82599,
1290 .eeprom_ops = &eeprom_ops_82599,
1291 .phy_ops = &phy_ops_82599,
1292 };
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