1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
42 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
43 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
44 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
45 static s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
46 ixgbe_link_speed speed
,
48 bool autoneg_wait_to_complete
);
49 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
50 ixgbe_link_speed speed
,
52 bool autoneg_wait_to_complete
);
53 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
54 bool autoneg_wait_to_complete
);
55 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
56 ixgbe_link_speed speed
,
58 bool autoneg_wait_to_complete
);
59 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
60 ixgbe_link_speed speed
,
62 bool autoneg_wait_to_complete
);
63 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
);
65 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw
*hw
)
67 struct ixgbe_mac_info
*mac
= &hw
->mac
;
68 if (hw
->phy
.multispeed_fiber
) {
69 /* Set up dual speed SFP+ support */
70 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_multispeed_fiber
;
71 mac
->ops
.disable_tx_laser
=
72 &ixgbe_disable_tx_laser_multispeed_fiber
;
73 mac
->ops
.enable_tx_laser
=
74 &ixgbe_enable_tx_laser_multispeed_fiber
;
75 mac
->ops
.flap_tx_laser
= &ixgbe_flap_tx_laser_multispeed_fiber
;
77 mac
->ops
.disable_tx_laser
= NULL
;
78 mac
->ops
.enable_tx_laser
= NULL
;
79 mac
->ops
.flap_tx_laser
= NULL
;
80 if ((mac
->ops
.get_media_type(hw
) ==
81 ixgbe_media_type_backplane
) &&
82 (hw
->phy
.smart_speed
== ixgbe_smart_speed_auto
||
83 hw
->phy
.smart_speed
== ixgbe_smart_speed_on
))
84 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_smartspeed
;
86 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_82599
;
90 static s32
ixgbe_setup_sfp_modules_82599(struct ixgbe_hw
*hw
)
93 u16 list_offset
, data_offset
, data_value
;
95 if (hw
->phy
.sfp_type
!= ixgbe_sfp_type_unknown
) {
96 ixgbe_init_mac_link_ops_82599(hw
);
98 hw
->phy
.ops
.reset
= NULL
;
100 ret_val
= ixgbe_get_sfp_init_sequence_offsets(hw
, &list_offset
,
106 /* PHY config will finish before releasing the semaphore */
107 ret_val
= ixgbe_acquire_swfw_sync(hw
, IXGBE_GSSR_MAC_CSR_SM
);
109 ret_val
= IXGBE_ERR_SWFW_SYNC
;
113 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
114 while (data_value
!= 0xffff) {
115 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, data_value
);
116 IXGBE_WRITE_FLUSH(hw
);
117 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
119 /* Now restart DSP by setting Restart_AN */
120 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
,
121 (IXGBE_READ_REG(hw
, IXGBE_AUTOC
) | IXGBE_AUTOC_AN_RESTART
));
123 /* Release the semaphore */
124 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_MAC_CSR_SM
);
125 /* Delay obtaining semaphore again to allow FW access */
126 msleep(hw
->eeprom
.semaphore_delay
);
133 static s32
ixgbe_get_invariants_82599(struct ixgbe_hw
*hw
)
135 struct ixgbe_mac_info
*mac
= &hw
->mac
;
137 ixgbe_init_mac_link_ops_82599(hw
);
139 mac
->mcft_size
= IXGBE_82599_MC_TBL_SIZE
;
140 mac
->vft_size
= IXGBE_82599_VFT_TBL_SIZE
;
141 mac
->num_rar_entries
= IXGBE_82599_RAR_ENTRIES
;
142 mac
->max_rx_queues
= IXGBE_82599_MAX_RX_QUEUES
;
143 mac
->max_tx_queues
= IXGBE_82599_MAX_TX_QUEUES
;
144 mac
->max_msix_vectors
= ixgbe_get_pcie_msix_count_generic(hw
);
150 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
151 * @hw: pointer to hardware structure
153 * Initialize any function pointers that were not able to be
154 * set during get_invariants because the PHY/SFP type was
155 * not known. Perform the SFP init if necessary.
158 static s32
ixgbe_init_phy_ops_82599(struct ixgbe_hw
*hw
)
160 struct ixgbe_mac_info
*mac
= &hw
->mac
;
161 struct ixgbe_phy_info
*phy
= &hw
->phy
;
164 /* Identify the PHY or SFP module */
165 ret_val
= phy
->ops
.identify(hw
);
167 /* Setup function pointers based on detected SFP module and speeds */
168 ixgbe_init_mac_link_ops_82599(hw
);
170 /* If copper media, overwrite with copper function pointers */
171 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_copper
) {
172 mac
->ops
.setup_link
= &ixgbe_setup_copper_link_82599
;
173 mac
->ops
.get_link_capabilities
=
174 &ixgbe_get_copper_link_capabilities_generic
;
177 /* Set necessary function pointers based on phy type */
178 switch (hw
->phy
.type
) {
180 phy
->ops
.check_link
= &ixgbe_check_phy_link_tnx
;
181 phy
->ops
.get_firmware_version
=
182 &ixgbe_get_phy_firmware_version_tnx
;
185 phy
->ops
.get_firmware_version
=
186 &ixgbe_get_phy_firmware_version_generic
;
196 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
197 * @hw: pointer to hardware structure
198 * @speed: pointer to link speed
199 * @negotiation: true when autoneg or autotry is enabled
201 * Determines the link capabilities by reading the AUTOC register.
203 static s32
ixgbe_get_link_capabilities_82599(struct ixgbe_hw
*hw
,
204 ixgbe_link_speed
*speed
,
210 /* Determine 1G link capabilities off of SFP+ type */
211 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core0
||
212 hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core1
) {
213 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
219 * Determine link capabilities based on the stored value of AUTOC,
220 * which represents EEPROM defaults. If AUTOC value has not been
221 * stored, use the current register value.
223 if (hw
->mac
.orig_link_settings_stored
)
224 autoc
= hw
->mac
.orig_autoc
;
226 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
228 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
229 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
230 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
231 *negotiation
= false;
234 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
235 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
236 *negotiation
= false;
239 case IXGBE_AUTOC_LMS_1G_AN
:
240 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
244 case IXGBE_AUTOC_LMS_10G_SERIAL
:
245 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
246 *negotiation
= false;
249 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
250 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
251 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
252 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
253 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
254 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
255 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
256 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
257 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
261 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
:
262 *speed
= IXGBE_LINK_SPEED_100_FULL
;
263 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
264 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
265 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
266 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
267 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
268 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
272 case IXGBE_AUTOC_LMS_SGMII_1G_100M
:
273 *speed
= IXGBE_LINK_SPEED_1GB_FULL
| IXGBE_LINK_SPEED_100_FULL
;
274 *negotiation
= false;
278 status
= IXGBE_ERR_LINK_SETUP
;
283 if (hw
->phy
.multispeed_fiber
) {
284 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
|
285 IXGBE_LINK_SPEED_1GB_FULL
;
294 * ixgbe_get_media_type_82599 - Get media type
295 * @hw: pointer to hardware structure
297 * Returns the media type (fiber, copper, backplane)
299 static enum ixgbe_media_type
ixgbe_get_media_type_82599(struct ixgbe_hw
*hw
)
301 enum ixgbe_media_type media_type
;
303 /* Detect if there is a copper PHY attached. */
304 if (hw
->phy
.type
== ixgbe_phy_cu_unknown
||
305 hw
->phy
.type
== ixgbe_phy_tn
||
306 hw
->phy
.type
== ixgbe_phy_aq
) {
307 media_type
= ixgbe_media_type_copper
;
311 switch (hw
->device_id
) {
312 case IXGBE_DEV_ID_82599_KX4
:
313 case IXGBE_DEV_ID_82599_KX4_MEZZ
:
314 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
315 case IXGBE_DEV_ID_82599_KR
:
316 case IXGBE_DEV_ID_82599_XAUI_LOM
:
317 /* Default device ID is mezzanine card KX/KX4 */
318 media_type
= ixgbe_media_type_backplane
;
320 case IXGBE_DEV_ID_82599_SFP
:
321 case IXGBE_DEV_ID_82599_SFP_EM
:
322 media_type
= ixgbe_media_type_fiber
;
324 case IXGBE_DEV_ID_82599_CX4
:
325 media_type
= ixgbe_media_type_cx4
;
328 media_type
= ixgbe_media_type_unknown
;
336 * ixgbe_start_mac_link_82599 - Setup MAC link settings
337 * @hw: pointer to hardware structure
338 * @autoneg_wait_to_complete: true when waiting for completion is needed
340 * Configures link settings based on values in the ixgbe_hw struct.
341 * Restarts the link. Performs autonegotiation if needed.
343 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
344 bool autoneg_wait_to_complete
)
352 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
353 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
354 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
356 /* Only poll for autoneg to complete if specified to do so */
357 if (autoneg_wait_to_complete
) {
358 if ((autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
359 IXGBE_AUTOC_LMS_KX4_KX_KR
||
360 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
361 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
362 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
363 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
364 links_reg
= 0; /* Just in case Autoneg time = 0 */
365 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
366 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
367 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
371 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
372 status
= IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
373 hw_dbg(hw
, "Autoneg did not complete.\n");
378 /* Add delay to filter out noises during initial link setup */
385 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
386 * @hw: pointer to hardware structure
388 * The base drivers may require better control over SFP+ module
389 * PHY states. This includes selectively shutting down the Tx
390 * laser on the PHY, effectively halting physical link.
392 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
394 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
396 /* Disable tx laser; allow 100us to go dark per spec */
397 esdp_reg
|= IXGBE_ESDP_SDP3
;
398 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
399 IXGBE_WRITE_FLUSH(hw
);
404 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
405 * @hw: pointer to hardware structure
407 * The base drivers may require better control over SFP+ module
408 * PHY states. This includes selectively turning on the Tx
409 * laser on the PHY, effectively starting physical link.
411 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
413 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
415 /* Enable tx laser; allow 100ms to light up */
416 esdp_reg
&= ~IXGBE_ESDP_SDP3
;
417 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
418 IXGBE_WRITE_FLUSH(hw
);
423 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
424 * @hw: pointer to hardware structure
426 * When the driver changes the link speeds that it can support,
427 * it sets autotry_restart to true to indicate that we need to
428 * initiate a new autotry session with the link partner. To do
429 * so, we set the speed then disable and re-enable the tx laser, to
430 * alert the link partner that it also needs to restart autotry on its
431 * end. This is consistent with true clause 37 autoneg, which also
432 * involves a loss of signal.
434 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
436 hw_dbg(hw
, "ixgbe_flap_tx_laser_multispeed_fiber\n");
438 if (hw
->mac
.autotry_restart
) {
439 ixgbe_disable_tx_laser_multispeed_fiber(hw
);
440 ixgbe_enable_tx_laser_multispeed_fiber(hw
);
441 hw
->mac
.autotry_restart
= false;
446 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
447 * @hw: pointer to hardware structure
448 * @speed: new link speed
449 * @autoneg: true if autonegotiation enabled
450 * @autoneg_wait_to_complete: true when waiting for completion is needed
452 * Set the link speed in the AUTOC register and restarts link.
454 s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
455 ixgbe_link_speed speed
,
457 bool autoneg_wait_to_complete
)
460 ixgbe_link_speed phy_link_speed
;
461 ixgbe_link_speed highest_link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
463 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
464 bool link_up
= false;
468 /* Mask off requested but non-supported speeds */
469 hw
->mac
.ops
.get_link_capabilities(hw
, &phy_link_speed
, &negotiation
);
470 speed
&= phy_link_speed
;
473 * Try each speed one by one, highest priority first. We do this in
474 * software because 10gb fiber doesn't support speed autonegotiation.
476 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
) {
478 highest_link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
480 /* If we already have link at this speed, just jump out */
481 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
, &link_up
, false);
483 if ((phy_link_speed
== IXGBE_LINK_SPEED_10GB_FULL
) && link_up
)
486 /* Set the module link speed */
487 esdp_reg
|= (IXGBE_ESDP_SDP5_DIR
| IXGBE_ESDP_SDP5
);
488 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
489 IXGBE_WRITE_FLUSH(hw
);
491 /* Allow module to change analog characteristics (1G->10G) */
494 status
= ixgbe_setup_mac_link_82599(hw
,
495 IXGBE_LINK_SPEED_10GB_FULL
,
497 autoneg_wait_to_complete
);
501 /* Flap the tx laser if it has not already been done */
502 hw
->mac
.ops
.flap_tx_laser(hw
);
505 * Wait for the controller to acquire link. Per IEEE 802.3ap,
506 * Section 73.10.2, we may have to wait up to 500ms if KR is
507 * attempted. 82599 uses the same timing for 10g SFI.
510 for (i
= 0; i
< 5; i
++) {
511 /* Wait for the link partner to also set speed */
514 /* If we have link, just jump out */
515 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
,
522 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
) {
524 if (highest_link_speed
== IXGBE_LINK_SPEED_UNKNOWN
)
525 highest_link_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
527 /* If we already have link at this speed, just jump out */
528 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
, &link_up
, false);
530 if ((phy_link_speed
== IXGBE_LINK_SPEED_1GB_FULL
) && link_up
)
533 /* Set the module link speed */
534 esdp_reg
&= ~IXGBE_ESDP_SDP5
;
535 esdp_reg
|= IXGBE_ESDP_SDP5_DIR
;
536 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
537 IXGBE_WRITE_FLUSH(hw
);
539 /* Allow module to change analog characteristics (10G->1G) */
542 status
= ixgbe_setup_mac_link_82599(hw
,
543 IXGBE_LINK_SPEED_1GB_FULL
,
545 autoneg_wait_to_complete
);
549 /* Flap the tx laser if it has not already been done */
550 hw
->mac
.ops
.flap_tx_laser(hw
);
552 /* Wait for the link partner to also set speed */
555 /* If we have link, just jump out */
556 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
, &link_up
, false);
562 * We didn't get link. Configure back to the highest speed we tried,
563 * (if there was more than one). We call ourselves back with just the
564 * single highest speed that the user requested.
567 status
= ixgbe_setup_mac_link_multispeed_fiber(hw
,
570 autoneg_wait_to_complete
);
573 /* Set autoneg_advertised value based on input link speed */
574 hw
->phy
.autoneg_advertised
= 0;
576 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
577 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
579 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
580 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
586 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
587 * @hw: pointer to hardware structure
588 * @speed: new link speed
589 * @autoneg: true if autonegotiation enabled
590 * @autoneg_wait_to_complete: true when waiting for completion is needed
592 * Implements the Intel SmartSpeed algorithm.
594 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
595 ixgbe_link_speed speed
, bool autoneg
,
596 bool autoneg_wait_to_complete
)
599 ixgbe_link_speed link_speed
;
601 bool link_up
= false;
602 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
603 struct ixgbe_adapter
*adapter
= hw
->back
;
605 hw_dbg(hw
, "ixgbe_setup_mac_link_smartspeed.\n");
607 /* Set autoneg_advertised value based on input link speed */
608 hw
->phy
.autoneg_advertised
= 0;
610 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
611 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
613 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
614 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
616 if (speed
& IXGBE_LINK_SPEED_100_FULL
)
617 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_100_FULL
;
620 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
621 * autoneg advertisement if link is unable to be established at the
622 * highest negotiated rate. This can sometimes happen due to integrity
623 * issues with the physical media connection.
626 /* First, try to get link with full advertisement */
627 hw
->phy
.smart_speed_active
= false;
628 for (j
= 0; j
< IXGBE_SMARTSPEED_MAX_RETRIES
; j
++) {
629 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
630 autoneg_wait_to_complete
);
635 * Wait for the controller to acquire link. Per IEEE 802.3ap,
636 * Section 73.10.2, we may have to wait up to 500ms if KR is
637 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
638 * Table 9 in the AN MAS.
640 for (i
= 0; i
< 5; i
++) {
643 /* If we have link, just jump out */
644 hw
->mac
.ops
.check_link(hw
, &link_speed
,
652 * We didn't get link. If we advertised KR plus one of KX4/KX
653 * (or BX4/BX), then disable KR and try again.
655 if (((autoc_reg
& IXGBE_AUTOC_KR_SUPP
) == 0) ||
656 ((autoc_reg
& IXGBE_AUTOC_KX4_KX_SUPP_MASK
) == 0))
659 /* Turn SmartSpeed on to disable KR support */
660 hw
->phy
.smart_speed_active
= true;
661 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
662 autoneg_wait_to_complete
);
667 * Wait for the controller to acquire link. 600ms will allow for
668 * the AN link_fail_inhibit_timer as well for multiple cycles of
669 * parallel detect, both 10g and 1g. This allows for the maximum
670 * connect attempts as defined in the AN MAS table 73-7.
672 for (i
= 0; i
< 6; i
++) {
675 /* If we have link, just jump out */
676 hw
->mac
.ops
.check_link(hw
, &link_speed
,
682 /* We didn't get link. Turn SmartSpeed back off. */
683 hw
->phy
.smart_speed_active
= false;
684 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
685 autoneg_wait_to_complete
);
688 if (link_up
&& (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
))
689 e_info(hw
, "Smartspeed has downgraded the link speed from "
690 "the maximum advertised\n");
695 * ixgbe_setup_mac_link_82599 - Set MAC link speed
696 * @hw: pointer to hardware structure
697 * @speed: new link speed
698 * @autoneg: true if autonegotiation enabled
699 * @autoneg_wait_to_complete: true when waiting for completion is needed
701 * Set the link speed in the AUTOC register and restarts link.
703 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
704 ixgbe_link_speed speed
, bool autoneg
,
705 bool autoneg_wait_to_complete
)
708 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
709 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
710 u32 start_autoc
= autoc
;
712 u32 link_mode
= autoc
& IXGBE_AUTOC_LMS_MASK
;
713 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
714 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
717 ixgbe_link_speed link_capabilities
= IXGBE_LINK_SPEED_UNKNOWN
;
719 /* Check to see if speed passed in is supported. */
720 hw
->mac
.ops
.get_link_capabilities(hw
, &link_capabilities
, &autoneg
);
721 speed
&= link_capabilities
;
723 if (speed
== IXGBE_LINK_SPEED_UNKNOWN
) {
724 status
= IXGBE_ERR_LINK_SETUP
;
728 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
729 if (hw
->mac
.orig_link_settings_stored
)
730 orig_autoc
= hw
->mac
.orig_autoc
;
735 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
736 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
737 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
738 /* Set KX4/KX/KR support according to speed requested */
739 autoc
&= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK
| IXGBE_AUTOC_KR_SUPP
);
740 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
741 if (orig_autoc
& IXGBE_AUTOC_KX4_SUPP
)
742 autoc
|= IXGBE_AUTOC_KX4_SUPP
;
743 if ((orig_autoc
& IXGBE_AUTOC_KR_SUPP
) &&
744 (hw
->phy
.smart_speed_active
== false))
745 autoc
|= IXGBE_AUTOC_KR_SUPP
;
746 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
747 autoc
|= IXGBE_AUTOC_KX_SUPP
;
748 } else if ((pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
) &&
749 (link_mode
== IXGBE_AUTOC_LMS_1G_LINK_NO_AN
||
750 link_mode
== IXGBE_AUTOC_LMS_1G_AN
)) {
751 /* Switch from 1G SFI to 10G SFI if requested */
752 if ((speed
== IXGBE_LINK_SPEED_10GB_FULL
) &&
753 (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)) {
754 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
755 autoc
|= IXGBE_AUTOC_LMS_10G_SERIAL
;
757 } else if ((pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
) &&
758 (link_mode
== IXGBE_AUTOC_LMS_10G_SERIAL
)) {
759 /* Switch from 10G SFI to 1G SFI if requested */
760 if ((speed
== IXGBE_LINK_SPEED_1GB_FULL
) &&
761 (pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
)) {
762 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
764 autoc
|= IXGBE_AUTOC_LMS_1G_AN
;
766 autoc
|= IXGBE_AUTOC_LMS_1G_LINK_NO_AN
;
770 if (autoc
!= start_autoc
) {
772 autoc
|= IXGBE_AUTOC_AN_RESTART
;
773 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc
);
775 /* Only poll for autoneg to complete if specified to do so */
776 if (autoneg_wait_to_complete
) {
777 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
778 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
779 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
780 links_reg
= 0; /*Just in case Autoneg time=0*/
781 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
783 IXGBE_READ_REG(hw
, IXGBE_LINKS
);
784 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
788 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
790 IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
791 hw_dbg(hw
, "Autoneg did not "
797 /* Add delay to filter out noises during initial link setup */
806 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
807 * @hw: pointer to hardware structure
808 * @speed: new link speed
809 * @autoneg: true if autonegotiation enabled
810 * @autoneg_wait_to_complete: true if waiting is needed to complete
812 * Restarts link on PHY and MAC based on settings passed in.
814 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
815 ixgbe_link_speed speed
,
817 bool autoneg_wait_to_complete
)
821 /* Setup the PHY according to input speed */
822 status
= hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg
,
823 autoneg_wait_to_complete
);
825 ixgbe_start_mac_link_82599(hw
, autoneg_wait_to_complete
);
831 * ixgbe_reset_hw_82599 - Perform hardware reset
832 * @hw: pointer to hardware structure
834 * Resets the hardware by resetting the transmit and receive units, masks
835 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
838 static s32
ixgbe_reset_hw_82599(struct ixgbe_hw
*hw
)
846 /* Call adapter stop to disable tx/rx and clear interrupts */
847 hw
->mac
.ops
.stop_adapter(hw
);
849 /* PHY ops must be identified and initialized prior to reset */
851 /* Init PHY and function pointers, perform SFP setup */
852 status
= hw
->phy
.ops
.init(hw
);
854 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
857 /* Setup SFP module if there is one present. */
858 if (hw
->phy
.sfp_setup_needed
) {
859 status
= hw
->mac
.ops
.setup_sfp(hw
);
860 hw
->phy
.sfp_setup_needed
= false;
864 if (hw
->phy
.reset_disable
== false && hw
->phy
.ops
.reset
!= NULL
)
865 hw
->phy
.ops
.reset(hw
);
868 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
869 * access and verify no pending requests before reset
871 status
= ixgbe_disable_pcie_master(hw
);
873 status
= IXGBE_ERR_MASTER_REQUESTS_PENDING
;
874 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
878 * Issue global reset to the MAC. This needs to be a SW reset.
879 * If link reset is used, it might reset the MAC when mng is using it
881 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
882 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, (ctrl
| IXGBE_CTRL_RST
));
883 IXGBE_WRITE_FLUSH(hw
);
885 /* Poll for reset bit to self-clear indicating reset is complete */
886 for (i
= 0; i
< 10; i
++) {
888 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
889 if (!(ctrl
& IXGBE_CTRL_RST
))
892 if (ctrl
& IXGBE_CTRL_RST
) {
893 status
= IXGBE_ERR_RESET_FAILED
;
894 hw_dbg(hw
, "Reset polling failed to complete.\n");
900 * Store the original AUTOC/AUTOC2 values if they have not been
901 * stored off yet. Otherwise restore the stored original
902 * values since the reset operation sets back to defaults.
904 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
905 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
906 if (hw
->mac
.orig_link_settings_stored
== false) {
907 hw
->mac
.orig_autoc
= autoc
;
908 hw
->mac
.orig_autoc2
= autoc2
;
909 hw
->mac
.orig_link_settings_stored
= true;
911 if (autoc
!= hw
->mac
.orig_autoc
)
912 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (hw
->mac
.orig_autoc
|
913 IXGBE_AUTOC_AN_RESTART
));
915 if ((autoc2
& IXGBE_AUTOC2_UPPER_MASK
) !=
916 (hw
->mac
.orig_autoc2
& IXGBE_AUTOC2_UPPER_MASK
)) {
917 autoc2
&= ~IXGBE_AUTOC2_UPPER_MASK
;
918 autoc2
|= (hw
->mac
.orig_autoc2
&
919 IXGBE_AUTOC2_UPPER_MASK
);
920 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC2
, autoc2
);
925 * Store MAC address from RAR0, clear receive address registers, and
926 * clear the multicast table. Also reset num_rar_entries to 128,
927 * since we modify this value when programming the SAN MAC address.
929 hw
->mac
.num_rar_entries
= 128;
930 hw
->mac
.ops
.init_rx_addrs(hw
);
932 /* Store the permanent mac address */
933 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
935 /* Store the permanent SAN mac address */
936 hw
->mac
.ops
.get_san_mac_addr(hw
, hw
->mac
.san_addr
);
938 /* Add the SAN MAC address to the RAR only if it's a valid address */
939 if (ixgbe_validate_mac_addr(hw
->mac
.san_addr
) == 0) {
940 hw
->mac
.ops
.set_rar(hw
, hw
->mac
.num_rar_entries
- 1,
941 hw
->mac
.san_addr
, 0, IXGBE_RAH_AV
);
943 /* Reserve the last RAR for the SAN MAC address */
944 hw
->mac
.num_rar_entries
--;
947 /* Store the alternative WWNN/WWPN prefix */
948 hw
->mac
.ops
.get_wwn_prefix(hw
, &hw
->mac
.wwnn_prefix
,
949 &hw
->mac
.wwpn_prefix
);
956 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
957 * @hw: pointer to hardware structure
959 s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
)
962 u32 fdirctrl
= IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
);
963 fdirctrl
&= ~IXGBE_FDIRCTRL_INIT_DONE
;
966 * Before starting reinitialization process,
967 * FDIRCMD.CMD must be zero.
969 for (i
= 0; i
< IXGBE_FDIRCMD_CMD_POLL
; i
++) {
970 if (!(IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
971 IXGBE_FDIRCMD_CMD_MASK
))
975 if (i
>= IXGBE_FDIRCMD_CMD_POLL
) {
976 hw_dbg(hw
,"Flow Director previous command isn't complete, "
977 "aborting table re-initialization.\n");
978 return IXGBE_ERR_FDIR_REINIT_FAILED
;
981 IXGBE_WRITE_REG(hw
, IXGBE_FDIRFREE
, 0);
982 IXGBE_WRITE_FLUSH(hw
);
984 * 82599 adapters flow director init flow cannot be restarted,
985 * Workaround 82599 silicon errata by performing the following steps
986 * before re-writing the FDIRCTRL control register with the same value.
987 * - write 1 to bit 8 of FDIRCMD register &
988 * - write 0 to bit 8 of FDIRCMD register
990 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
991 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) |
992 IXGBE_FDIRCMD_CLEARHT
));
993 IXGBE_WRITE_FLUSH(hw
);
994 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
995 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
996 ~IXGBE_FDIRCMD_CLEARHT
));
997 IXGBE_WRITE_FLUSH(hw
);
999 * Clear FDIR Hash register to clear any leftover hashes
1000 * waiting to be programmed.
1002 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, 0x00);
1003 IXGBE_WRITE_FLUSH(hw
);
1005 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1006 IXGBE_WRITE_FLUSH(hw
);
1008 /* Poll init-done after we write FDIRCTRL register */
1009 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1010 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1011 IXGBE_FDIRCTRL_INIT_DONE
)
1015 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
) {
1016 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1017 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1020 /* Clear FDIR statistics registers (read to clear) */
1021 IXGBE_READ_REG(hw
, IXGBE_FDIRUSTAT
);
1022 IXGBE_READ_REG(hw
, IXGBE_FDIRFSTAT
);
1023 IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
1024 IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
1025 IXGBE_READ_REG(hw
, IXGBE_FDIRLEN
);
1031 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1032 * @hw: pointer to hardware structure
1033 * @pballoc: which mode to allocate filters with
1035 s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1042 * Before enabling Flow Director, the Rx Packet Buffer size
1043 * must be reduced. The new value is the current size minus
1044 * flow director memory usage size.
1046 pbsize
= (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT
+ pballoc
));
1047 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0),
1048 (IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(0)) - pbsize
));
1051 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1052 * intialized to zero for non DCB mode otherwise actual total RX PB
1053 * would be bigger than programmed and filter space would run into
1056 for (i
= 1; i
< 8; i
++)
1057 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
1059 /* Send interrupt when 64 filters are left */
1060 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1062 /* Set the maximum length per hash bucket to 0xA filters */
1063 fdirctrl
|= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
;
1066 case IXGBE_FDIR_PBALLOC_64K
:
1067 /* 8k - 1 signature filters */
1068 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1070 case IXGBE_FDIR_PBALLOC_128K
:
1071 /* 16k - 1 signature filters */
1072 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1074 case IXGBE_FDIR_PBALLOC_256K
:
1075 /* 32k - 1 signature filters */
1076 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1080 return IXGBE_ERR_CONFIG
;
1083 /* Move the flexible bytes to use the ethertype - shift 6 words */
1084 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1086 fdirctrl
|= IXGBE_FDIRCTRL_REPORT_STATUS
;
1088 /* Prime the keys for hashing */
1089 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
,
1090 htonl(IXGBE_ATR_BUCKET_HASH_KEY
));
1091 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
,
1092 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY
));
1095 * Poll init-done after we write the register. Estimated times:
1096 * 10G: PBALLOC = 11b, timing is 60us
1097 * 1G: PBALLOC = 11b, timing is 600us
1098 * 100M: PBALLOC = 11b, timing is 6ms
1100 * Multiple these timings by 4 if under full Rx load
1102 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1103 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1104 * this might not finish in our poll time, but we can live with that
1107 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1108 IXGBE_WRITE_FLUSH(hw
);
1109 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1110 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1111 IXGBE_FDIRCTRL_INIT_DONE
)
1115 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1116 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1122 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1123 * @hw: pointer to hardware structure
1124 * @pballoc: which mode to allocate filters with
1126 s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1133 * Before enabling Flow Director, the Rx Packet Buffer size
1134 * must be reduced. The new value is the current size minus
1135 * flow director memory usage size.
1137 pbsize
= (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT
+ pballoc
));
1138 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0),
1139 (IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(0)) - pbsize
));
1142 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1143 * intialized to zero for non DCB mode otherwise actual total RX PB
1144 * would be bigger than programmed and filter space would run into
1147 for (i
= 1; i
< 8; i
++)
1148 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
1150 /* Send interrupt when 64 filters are left */
1151 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1153 /* Initialize the drop queue to Rx queue 127 */
1154 fdirctrl
|= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT
);
1157 case IXGBE_FDIR_PBALLOC_64K
:
1158 /* 2k - 1 perfect filters */
1159 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1161 case IXGBE_FDIR_PBALLOC_128K
:
1162 /* 4k - 1 perfect filters */
1163 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1165 case IXGBE_FDIR_PBALLOC_256K
:
1166 /* 8k - 1 perfect filters */
1167 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1171 return IXGBE_ERR_CONFIG
;
1174 /* Turn perfect match filtering on */
1175 fdirctrl
|= IXGBE_FDIRCTRL_PERFECT_MATCH
;
1176 fdirctrl
|= IXGBE_FDIRCTRL_REPORT_STATUS
;
1178 /* Move the flexible bytes to use the ethertype - shift 6 words */
1179 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1181 /* Prime the keys for hashing */
1182 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
,
1183 htonl(IXGBE_ATR_BUCKET_HASH_KEY
));
1184 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
,
1185 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY
));
1188 * Poll init-done after we write the register. Estimated times:
1189 * 10G: PBALLOC = 11b, timing is 60us
1190 * 1G: PBALLOC = 11b, timing is 600us
1191 * 100M: PBALLOC = 11b, timing is 6ms
1193 * Multiple these timings by 4 if under full Rx load
1195 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1196 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1197 * this might not finish in our poll time, but we can live with that
1201 /* Set the maximum length per hash bucket to 0xA filters */
1202 fdirctrl
|= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
);
1204 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1205 IXGBE_WRITE_FLUSH(hw
);
1206 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1207 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1208 IXGBE_FDIRCTRL_INIT_DONE
)
1212 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1213 hw_dbg(hw
, "Flow Director Perfect poll time exceeded!\n");
1220 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1221 * @stream: input bitstream to compute the hash on
1222 * @key: 32-bit hash key
1224 static u16
ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input
*atr_input
,
1228 * The algorithm is as follows:
1229 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1230 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1231 * and A[n] x B[n] is bitwise AND between same length strings
1233 * K[n] is 16 bits, defined as:
1234 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1235 * for n modulo 32 < 15, K[n] =
1236 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1238 * S[n] is 16 bits, defined as:
1239 * for n >= 15, S[n] = S[n:n - 15]
1240 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1242 * To simplify for programming, the algorithm is implemented
1243 * in software this way:
1245 * Key[31:0], Stream[335:0]
1247 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1248 * int_key[350:0] = tmp_key[351:1]
1249 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1252 * for (i = 0; i < 351; i++) {
1254 * hash ^= int_stream[(i + 15):i];
1264 u8
*stream
= (u8
*)atr_input
;
1265 u8 int_key
[44]; /* upper-most bit unused */
1266 u8 hash_str
[46]; /* upper-most 2 bits unused */
1267 u16 hash_result
= 0;
1271 * Initialize the fill member to prevent warnings
1274 tmp_key
.fill
[0] = 0;
1276 /* First load the temporary key stream */
1277 for (i
= 0; i
< 6; i
++) {
1278 u64 fillkey
= ((u64
)key
<< 32) | key
;
1279 tmp_key
.fill
[i
] = fillkey
;
1283 * Set the interim key for the hashing. Bit 352 is unused, so we must
1284 * shift and compensate when building the key.
1287 int_key
[0] = tmp_key
.key_stream
[0] >> 1;
1288 for (i
= 1, j
= 0; i
< 44; i
++) {
1289 unsigned int this_key
= tmp_key
.key_stream
[j
] << 7;
1291 int_key
[i
] = (u8
)(this_key
| (tmp_key
.key_stream
[j
] >> 1));
1295 * Set the interim bit string for the hashing. Bits 368 and 367 are
1296 * unused, so shift and compensate when building the string.
1298 hash_str
[0] = (stream
[40] & 0x7f) >> 1;
1299 for (i
= 1, j
= 40; i
< 46; i
++) {
1300 unsigned int this_str
= stream
[j
] << 7;
1304 hash_str
[i
] = (u8
)(this_str
| (stream
[j
] >> 1));
1308 * Now compute the hash. i is the index into hash_str, j is into our
1309 * key stream, k is counting the number of bits, and h interates within
1312 for (i
= 45, j
= 43, k
= 0; k
< 351 && i
>= 2 && j
>= 0; i
--, j
--) {
1313 for (h
= 0; h
< 8 && k
< 351; h
++, k
++) {
1314 if (int_key
[j
] & (1 << h
)) {
1316 * Key bit is set, XOR in the current 16-bit
1317 * string. Example of processing:
1319 * tmp = (hash_str[i - 2] & 0 << 16) |
1320 * (hash_str[i - 1] & 0xff << 8) |
1321 * (hash_str[i] & 0xff >> 0)
1322 * So tmp = hash_str[15 + k:k], since the
1323 * i + 2 clause rolls off the 16-bit value
1325 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1326 * (hash_str[i - 1] & 0xff << 1) |
1327 * (hash_str[i] & 0x80 >> 7)
1329 int tmp
= (hash_str
[i
] >> h
);
1330 tmp
|= (hash_str
[i
- 1] << (8 - h
));
1331 tmp
|= (int)(hash_str
[i
- 2] & ((1 << h
) - 1))
1333 hash_result
^= (u16
)tmp
;
1342 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1343 * @input: input stream to modify
1344 * @vlan: the VLAN id to load
1346 s32
ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input
*input
, u16 vlan
)
1348 input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
+ 1] = vlan
>> 8;
1349 input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
] = vlan
& 0xff;
1355 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1356 * @input: input stream to modify
1357 * @src_addr: the IP address to load
1359 s32
ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input
*input
, u32 src_addr
)
1361 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 3] = src_addr
>> 24;
1362 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 2] =
1363 (src_addr
>> 16) & 0xff;
1364 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 1] =
1365 (src_addr
>> 8) & 0xff;
1366 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
] = src_addr
& 0xff;
1372 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1373 * @input: input stream to modify
1374 * @dst_addr: the IP address to load
1376 s32
ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input
*input
, u32 dst_addr
)
1378 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 3] = dst_addr
>> 24;
1379 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 2] =
1380 (dst_addr
>> 16) & 0xff;
1381 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 1] =
1382 (dst_addr
>> 8) & 0xff;
1383 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
] = dst_addr
& 0xff;
1389 * ixgbe_atr_set_src_port_82599 - Sets the source port
1390 * @input: input stream to modify
1391 * @src_port: the source port to load
1393 s32
ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input
*input
, u16 src_port
)
1395 input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
+ 1] = src_port
>> 8;
1396 input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
] = src_port
& 0xff;
1402 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1403 * @input: input stream to modify
1404 * @dst_port: the destination port to load
1406 s32
ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input
*input
, u16 dst_port
)
1408 input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
+ 1] = dst_port
>> 8;
1409 input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
] = dst_port
& 0xff;
1415 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1416 * @input: input stream to modify
1417 * @flex_bytes: the flexible bytes to load
1419 s32
ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input
*input
, u16 flex_byte
)
1421 input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
+ 1] = flex_byte
>> 8;
1422 input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
] = flex_byte
& 0xff;
1428 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1429 * @input: input stream to modify
1430 * @l4type: the layer 4 type value to load
1432 s32
ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input
*input
, u8 l4type
)
1434 input
->byte_stream
[IXGBE_ATR_L4TYPE_OFFSET
] = l4type
;
1440 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1441 * @input: input stream to search
1442 * @vlan: the VLAN id to load
1444 static s32
ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input
*input
, u16
*vlan
)
1446 *vlan
= input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
];
1447 *vlan
|= input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
+ 1] << 8;
1453 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1454 * @input: input stream to search
1455 * @src_addr: the IP address to load
1457 static s32
ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input
*input
,
1460 *src_addr
= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
];
1461 *src_addr
|= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 1] << 8;
1462 *src_addr
|= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 2] << 16;
1463 *src_addr
|= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 3] << 24;
1469 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1470 * @input: input stream to search
1471 * @dst_addr: the IP address to load
1473 static s32
ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input
*input
,
1476 *dst_addr
= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
];
1477 *dst_addr
|= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 1] << 8;
1478 *dst_addr
|= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 2] << 16;
1479 *dst_addr
|= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 3] << 24;
1485 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1486 * @input: input stream to search
1487 * @src_addr_1: the first 4 bytes of the IP address to load
1488 * @src_addr_2: the second 4 bytes of the IP address to load
1489 * @src_addr_3: the third 4 bytes of the IP address to load
1490 * @src_addr_4: the fourth 4 bytes of the IP address to load
1492 static s32
ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input
*input
,
1493 u32
*src_addr_1
, u32
*src_addr_2
,
1494 u32
*src_addr_3
, u32
*src_addr_4
)
1496 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 12];
1497 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 13] << 8;
1498 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 14] << 16;
1499 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 15] << 24;
1501 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 8];
1502 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 9] << 8;
1503 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 10] << 16;
1504 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 11] << 24;
1506 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 4];
1507 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 5] << 8;
1508 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 6] << 16;
1509 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 7] << 24;
1511 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
];
1512 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 1] << 8;
1513 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 2] << 16;
1514 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 3] << 24;
1520 * ixgbe_atr_get_src_port_82599 - Gets the source port
1521 * @input: input stream to modify
1522 * @src_port: the source port to load
1524 * Even though the input is given in big-endian, the FDIRPORT registers
1525 * expect the ports to be programmed in little-endian. Hence the need to swap
1526 * endianness when retrieving the data. This can be confusing since the
1527 * internal hash engine expects it to be big-endian.
1529 static s32
ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input
*input
,
1532 *src_port
= input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
] << 8;
1533 *src_port
|= input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
+ 1];
1539 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1540 * @input: input stream to modify
1541 * @dst_port: the destination port to load
1543 * Even though the input is given in big-endian, the FDIRPORT registers
1544 * expect the ports to be programmed in little-endian. Hence the need to swap
1545 * endianness when retrieving the data. This can be confusing since the
1546 * internal hash engine expects it to be big-endian.
1548 static s32
ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input
*input
,
1551 *dst_port
= input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
] << 8;
1552 *dst_port
|= input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
+ 1];
1558 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1559 * @input: input stream to modify
1560 * @flex_bytes: the flexible bytes to load
1562 static s32
ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input
*input
,
1565 *flex_byte
= input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
];
1566 *flex_byte
|= input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
+ 1] << 8;
1572 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1573 * @input: input stream to modify
1574 * @l4type: the layer 4 type value to load
1576 static s32
ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input
*input
,
1579 *l4type
= input
->byte_stream
[IXGBE_ATR_L4TYPE_OFFSET
];
1585 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1586 * @hw: pointer to hardware structure
1587 * @stream: input bitstream
1588 * @queue: queue index to direct traffic to
1590 s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
1591 struct ixgbe_atr_input
*input
,
1597 u16 bucket_hash
, sig_hash
;
1600 bucket_hash
= ixgbe_atr_compute_hash_82599(input
,
1601 IXGBE_ATR_BUCKET_HASH_KEY
);
1603 /* bucket_hash is only 15 bits */
1604 bucket_hash
&= IXGBE_ATR_HASH_MASK
;
1606 sig_hash
= ixgbe_atr_compute_hash_82599(input
,
1607 IXGBE_ATR_SIGNATURE_HASH_KEY
);
1609 /* Get the l4type in order to program FDIRCMD properly */
1610 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1611 ixgbe_atr_get_l4type_82599(input
, &l4type
);
1614 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1615 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1617 fdirhash
= sig_hash
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
| bucket_hash
;
1619 fdircmd
= (IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
1620 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
);
1622 switch (l4type
& IXGBE_ATR_L4TYPE_MASK
) {
1623 case IXGBE_ATR_L4TYPE_TCP
:
1624 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_TCP
;
1626 case IXGBE_ATR_L4TYPE_UDP
:
1627 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_UDP
;
1629 case IXGBE_ATR_L4TYPE_SCTP
:
1630 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_SCTP
;
1633 hw_dbg(hw
, "Error on l4type input\n");
1634 return IXGBE_ERR_CONFIG
;
1637 if (l4type
& IXGBE_ATR_L4TYPE_IPV6_MASK
)
1638 fdircmd
|= IXGBE_FDIRCMD_IPV6
;
1640 fdircmd
|= ((u64
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
);
1641 fdirhashcmd
= ((fdircmd
<< 32) | fdirhash
);
1643 IXGBE_WRITE_REG64(hw
, IXGBE_FDIRHASH
, fdirhashcmd
);
1649 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1650 * @hw: pointer to hardware structure
1651 * @input: input bitstream
1652 * @input_masks: bitwise masks for relevant fields
1653 * @soft_id: software index into the silicon hash tables for filter storage
1654 * @queue: queue index to direct traffic to
1656 * Note that the caller to this function must lock before calling, since the
1657 * hardware writes must be protected from one another.
1659 s32
ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw
*hw
,
1660 struct ixgbe_atr_input
*input
,
1661 struct ixgbe_atr_input_masks
*input_masks
,
1662 u16 soft_id
, u8 queue
)
1666 u32 src_ipv4
= 0, dst_ipv4
= 0;
1667 u32 src_ipv6_1
, src_ipv6_2
, src_ipv6_3
, src_ipv6_4
;
1668 u16 src_port
, dst_port
, vlan_id
, flex_bytes
;
1673 /* Get our input values */
1674 ixgbe_atr_get_l4type_82599(input
, &l4type
);
1677 * Check l4type formatting, and bail out before we touch the hardware
1678 * if there's a configuration issue
1680 switch (l4type
& IXGBE_ATR_L4TYPE_MASK
) {
1681 case IXGBE_ATR_L4TYPE_TCP
:
1682 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_TCP
;
1684 case IXGBE_ATR_L4TYPE_UDP
:
1685 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_UDP
;
1687 case IXGBE_ATR_L4TYPE_SCTP
:
1688 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_SCTP
;
1691 hw_dbg(hw
, "Error on l4type input\n");
1692 return IXGBE_ERR_CONFIG
;
1695 bucket_hash
= ixgbe_atr_compute_hash_82599(input
,
1696 IXGBE_ATR_BUCKET_HASH_KEY
);
1698 /* bucket_hash is only 15 bits */
1699 bucket_hash
&= IXGBE_ATR_HASH_MASK
;
1701 ixgbe_atr_get_vlan_id_82599(input
, &vlan_id
);
1702 ixgbe_atr_get_src_port_82599(input
, &src_port
);
1703 ixgbe_atr_get_dst_port_82599(input
, &dst_port
);
1704 ixgbe_atr_get_flex_byte_82599(input
, &flex_bytes
);
1706 fdirhash
= soft_id
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
| bucket_hash
;
1708 /* Now figure out if we're IPv4 or IPv6 */
1709 if (l4type
& IXGBE_ATR_L4TYPE_IPV6_MASK
) {
1711 ixgbe_atr_get_src_ipv6_82599(input
, &src_ipv6_1
, &src_ipv6_2
,
1712 &src_ipv6_3
, &src_ipv6_4
);
1714 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIPv6(0), src_ipv6_1
);
1715 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIPv6(1), src_ipv6_2
);
1716 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIPv6(2), src_ipv6_3
);
1717 /* The last 4 bytes is the same register as IPv4 */
1718 IXGBE_WRITE_REG(hw
, IXGBE_FDIRIPSA
, src_ipv6_4
);
1720 fdircmd
|= IXGBE_FDIRCMD_IPV6
;
1721 fdircmd
|= IXGBE_FDIRCMD_IPv6DMATCH
;
1724 ixgbe_atr_get_src_ipv4_82599(input
, &src_ipv4
);
1725 IXGBE_WRITE_REG(hw
, IXGBE_FDIRIPSA
, src_ipv4
);
1728 ixgbe_atr_get_dst_ipv4_82599(input
, &dst_ipv4
);
1729 IXGBE_WRITE_REG(hw
, IXGBE_FDIRIPDA
, dst_ipv4
);
1731 IXGBE_WRITE_REG(hw
, IXGBE_FDIRVLAN
, (vlan_id
|
1732 (flex_bytes
<< IXGBE_FDIRVLAN_FLEX_SHIFT
)));
1733 IXGBE_WRITE_REG(hw
, IXGBE_FDIRPORT
, (src_port
|
1734 (dst_port
<< IXGBE_FDIRPORT_DESTINATION_SHIFT
)));
1737 * Program the relevant mask registers. L4type cannot be
1738 * masked out in this implementation.
1740 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1743 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIP4M
, input_masks
->src_ip_mask
);
1744 IXGBE_WRITE_REG(hw
, IXGBE_FDIRDIP4M
, input_masks
->dst_ip_mask
);
1746 switch (l4type
& IXGBE_ATR_L4TYPE_MASK
) {
1747 case IXGBE_ATR_L4TYPE_TCP
:
1748 IXGBE_WRITE_REG(hw
, IXGBE_FDIRTCPM
, input_masks
->src_port_mask
);
1749 IXGBE_WRITE_REG(hw
, IXGBE_FDIRTCPM
,
1750 (IXGBE_READ_REG(hw
, IXGBE_FDIRTCPM
) |
1751 (input_masks
->dst_port_mask
<< 16)));
1753 case IXGBE_ATR_L4TYPE_UDP
:
1754 IXGBE_WRITE_REG(hw
, IXGBE_FDIRUDPM
, input_masks
->src_port_mask
);
1755 IXGBE_WRITE_REG(hw
, IXGBE_FDIRUDPM
,
1756 (IXGBE_READ_REG(hw
, IXGBE_FDIRUDPM
) |
1757 (input_masks
->src_port_mask
<< 16)));
1760 /* this already would have failed above */
1764 /* Program the last mask register, FDIRM */
1765 if (input_masks
->vlan_id_mask
)
1766 /* Mask both VLAN and VLANP - bits 0 and 1 */
1769 if (input_masks
->data_mask
)
1770 /* Flex bytes need masking, so mask the whole thing - bit 4 */
1773 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1776 IXGBE_WRITE_REG(hw
, IXGBE_FDIRM
, fdirm
);
1778 fdircmd
|= IXGBE_FDIRCMD_CMD_ADD_FLOW
;
1779 fdircmd
|= IXGBE_FDIRCMD_FILTER_UPDATE
;
1780 fdircmd
|= IXGBE_FDIRCMD_LAST
;
1781 fdircmd
|= IXGBE_FDIRCMD_QUEUE_EN
;
1782 fdircmd
|= queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
1784 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, fdirhash
);
1785 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
, fdircmd
);
1790 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1791 * @hw: pointer to hardware structure
1792 * @reg: analog register to read
1795 * Performs read operation to Omer analog register specified.
1797 static s32
ixgbe_read_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8
*val
)
1801 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, IXGBE_CORECTL_WRITE_CMD
|
1803 IXGBE_WRITE_FLUSH(hw
);
1805 core_ctl
= IXGBE_READ_REG(hw
, IXGBE_CORECTL
);
1806 *val
= (u8
)core_ctl
;
1812 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1813 * @hw: pointer to hardware structure
1814 * @reg: atlas register to write
1815 * @val: value to write
1817 * Performs write operation to Omer analog register specified.
1819 static s32
ixgbe_write_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8 val
)
1823 core_ctl
= (reg
<< 8) | val
;
1824 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, core_ctl
);
1825 IXGBE_WRITE_FLUSH(hw
);
1832 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1833 * @hw: pointer to hardware structure
1835 * Starts the hardware using the generic start_hw function.
1836 * Then performs device-specific:
1837 * Clears the rate limiter registers.
1839 static s32
ixgbe_start_hw_82599(struct ixgbe_hw
*hw
)
1844 ret_val
= ixgbe_start_hw_generic(hw
);
1846 /* Clear the rate limiters */
1847 for (q_num
= 0; q_num
< hw
->mac
.max_tx_queues
; q_num
++) {
1848 IXGBE_WRITE_REG(hw
, IXGBE_RTTDQSEL
, q_num
);
1849 IXGBE_WRITE_REG(hw
, IXGBE_RTTBCNRC
, 0);
1851 IXGBE_WRITE_FLUSH(hw
);
1853 /* We need to run link autotry after the driver loads */
1854 hw
->mac
.autotry_restart
= true;
1857 ret_val
= ixgbe_verify_fw_version_82599(hw
);
1863 * ixgbe_identify_phy_82599 - Get physical layer module
1864 * @hw: pointer to hardware structure
1866 * Determines the physical layer module found on the current adapter.
1868 static s32
ixgbe_identify_phy_82599(struct ixgbe_hw
*hw
)
1870 s32 status
= IXGBE_ERR_PHY_ADDR_INVALID
;
1871 status
= ixgbe_identify_phy_generic(hw
);
1873 status
= ixgbe_identify_sfp_module_generic(hw
);
1878 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1879 * @hw: pointer to hardware structure
1881 * Determines physical layer capabilities of the current configuration.
1883 static u32
ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw
*hw
)
1885 u32 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
1886 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
1887 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
1888 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
1889 u32 pma_pmd_10g_parallel
= autoc
& IXGBE_AUTOC_10G_PMA_PMD_MASK
;
1890 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
1891 u16 ext_ability
= 0;
1892 u8 comp_codes_10g
= 0;
1893 u8 comp_codes_1g
= 0;
1895 hw
->phy
.ops
.identify(hw
);
1897 if (hw
->phy
.type
== ixgbe_phy_tn
||
1898 hw
->phy
.type
== ixgbe_phy_aq
||
1899 hw
->phy
.type
== ixgbe_phy_cu_unknown
) {
1900 hw
->phy
.ops
.read_reg(hw
, MDIO_PMA_EXTABLE
, MDIO_MMD_PMAPMD
,
1902 if (ext_ability
& MDIO_PMA_EXTABLE_10GBT
)
1903 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_T
;
1904 if (ext_ability
& MDIO_PMA_EXTABLE_1000BT
)
1905 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1906 if (ext_ability
& MDIO_PMA_EXTABLE_100BTX
)
1907 physical_layer
|= IXGBE_PHYSICAL_LAYER_100BASE_TX
;
1911 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
1912 case IXGBE_AUTOC_LMS_1G_AN
:
1913 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
1914 if (pma_pmd_1g
== IXGBE_AUTOC_1G_KX_BX
) {
1915 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_KX
|
1916 IXGBE_PHYSICAL_LAYER_1000BASE_BX
;
1919 /* SFI mode so read SFP module */
1922 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
1923 if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_CX4
)
1924 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_CX4
;
1925 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_KX4
)
1926 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1927 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_XAUI
)
1928 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_XAUI
;
1931 case IXGBE_AUTOC_LMS_10G_SERIAL
:
1932 if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_KR
) {
1933 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1935 } else if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)
1938 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
1939 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
1940 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
1941 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_KX
;
1942 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
1943 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1944 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
1945 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1954 /* SFP check must be done last since DA modules are sometimes used to
1955 * test KR mode - we need to id KR mode correctly before SFP module.
1956 * Call identify_sfp because the pluggable module may have changed */
1957 hw
->phy
.ops
.identify_sfp(hw
);
1958 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)
1961 switch (hw
->phy
.type
) {
1962 case ixgbe_phy_sfp_passive_tyco
:
1963 case ixgbe_phy_sfp_passive_unknown
:
1964 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
;
1966 case ixgbe_phy_sfp_ftl_active
:
1967 case ixgbe_phy_sfp_active_unknown
:
1968 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA
;
1970 case ixgbe_phy_sfp_avago
:
1971 case ixgbe_phy_sfp_ftl
:
1972 case ixgbe_phy_sfp_intel
:
1973 case ixgbe_phy_sfp_unknown
:
1974 hw
->phy
.ops
.read_i2c_eeprom(hw
,
1975 IXGBE_SFF_1GBE_COMP_CODES
, &comp_codes_1g
);
1976 hw
->phy
.ops
.read_i2c_eeprom(hw
,
1977 IXGBE_SFF_10GBE_COMP_CODES
, &comp_codes_10g
);
1978 if (comp_codes_10g
& IXGBE_SFF_10GBASESR_CAPABLE
)
1979 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_SR
;
1980 else if (comp_codes_10g
& IXGBE_SFF_10GBASELR_CAPABLE
)
1981 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_LR
;
1982 else if (comp_codes_1g
& IXGBE_SFF_1GBASET_CAPABLE
)
1983 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1990 return physical_layer
;
1994 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1995 * @hw: pointer to hardware structure
1996 * @regval: register value to write to RXCTRL
1998 * Enables the Rx DMA unit for 82599
2000 static s32
ixgbe_enable_rx_dma_82599(struct ixgbe_hw
*hw
, u32 regval
)
2002 #define IXGBE_MAX_SECRX_POLL 30
2007 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2008 * If traffic is incoming before we enable the Rx unit, it could hang
2009 * the Rx DMA unit. Therefore, make sure the security engine is
2010 * completely disabled prior to enabling the Rx unit.
2012 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2013 secrxreg
|= IXGBE_SECRXCTRL_RX_DIS
;
2014 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2015 for (i
= 0; i
< IXGBE_MAX_SECRX_POLL
; i
++) {
2016 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXSTAT
);
2017 if (secrxreg
& IXGBE_SECRXSTAT_SECRX_RDY
)
2023 /* For informational purposes only */
2024 if (i
>= IXGBE_MAX_SECRX_POLL
)
2025 hw_dbg(hw
, "Rx unit being enabled before security "
2026 "path fully disabled. Continuing with init.\n");
2028 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
2029 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2030 secrxreg
&= ~IXGBE_SECRXCTRL_RX_DIS
;
2031 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2032 IXGBE_WRITE_FLUSH(hw
);
2038 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2039 * @hw: pointer to hardware structure
2040 * @device_caps: the EEPROM word with the extra device capabilities
2042 * This function will read the EEPROM location for the device capabilities,
2043 * and return the word through device_caps.
2045 static s32
ixgbe_get_device_caps_82599(struct ixgbe_hw
*hw
, u16
*device_caps
)
2047 hw
->eeprom
.ops
.read(hw
, IXGBE_DEVICE_CAPS
, device_caps
);
2053 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2054 * @hw: pointer to hardware structure
2056 * Verifies that installed the firmware version is 0.6 or higher
2057 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2059 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2060 * if the FW version is not supported.
2062 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
)
2064 s32 status
= IXGBE_ERR_EEPROM_VERSION
;
2065 u16 fw_offset
, fw_ptp_cfg_offset
;
2068 /* firmware check is only necessary for SFI devices */
2069 if (hw
->phy
.media_type
!= ixgbe_media_type_fiber
) {
2071 goto fw_version_out
;
2074 /* get the offset to the Firmware Module block */
2075 hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
2077 if ((fw_offset
== 0) || (fw_offset
== 0xFFFF))
2078 goto fw_version_out
;
2080 /* get the offset to the Pass Through Patch Configuration block */
2081 hw
->eeprom
.ops
.read(hw
, (fw_offset
+
2082 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR
),
2083 &fw_ptp_cfg_offset
);
2085 if ((fw_ptp_cfg_offset
== 0) || (fw_ptp_cfg_offset
== 0xFFFF))
2086 goto fw_version_out
;
2088 /* get the firmware version */
2089 hw
->eeprom
.ops
.read(hw
, (fw_ptp_cfg_offset
+
2090 IXGBE_FW_PATCH_VERSION_4
),
2093 if (fw_version
> 0x5)
2100 static struct ixgbe_mac_operations mac_ops_82599
= {
2101 .init_hw
= &ixgbe_init_hw_generic
,
2102 .reset_hw
= &ixgbe_reset_hw_82599
,
2103 .start_hw
= &ixgbe_start_hw_82599
,
2104 .clear_hw_cntrs
= &ixgbe_clear_hw_cntrs_generic
,
2105 .get_media_type
= &ixgbe_get_media_type_82599
,
2106 .get_supported_physical_layer
= &ixgbe_get_supported_physical_layer_82599
,
2107 .enable_rx_dma
= &ixgbe_enable_rx_dma_82599
,
2108 .get_mac_addr
= &ixgbe_get_mac_addr_generic
,
2109 .get_san_mac_addr
= &ixgbe_get_san_mac_addr_generic
,
2110 .get_device_caps
= &ixgbe_get_device_caps_82599
,
2111 .get_wwn_prefix
= &ixgbe_get_wwn_prefix_generic
,
2112 .stop_adapter
= &ixgbe_stop_adapter_generic
,
2113 .get_bus_info
= &ixgbe_get_bus_info_generic
,
2114 .set_lan_id
= &ixgbe_set_lan_id_multi_port_pcie
,
2115 .read_analog_reg8
= &ixgbe_read_analog_reg8_82599
,
2116 .write_analog_reg8
= &ixgbe_write_analog_reg8_82599
,
2117 .setup_link
= &ixgbe_setup_mac_link_82599
,
2118 .check_link
= &ixgbe_check_mac_link_generic
,
2119 .get_link_capabilities
= &ixgbe_get_link_capabilities_82599
,
2120 .led_on
= &ixgbe_led_on_generic
,
2121 .led_off
= &ixgbe_led_off_generic
,
2122 .blink_led_start
= &ixgbe_blink_led_start_generic
,
2123 .blink_led_stop
= &ixgbe_blink_led_stop_generic
,
2124 .set_rar
= &ixgbe_set_rar_generic
,
2125 .clear_rar
= &ixgbe_clear_rar_generic
,
2126 .set_vmdq
= &ixgbe_set_vmdq_generic
,
2127 .clear_vmdq
= &ixgbe_clear_vmdq_generic
,
2128 .init_rx_addrs
= &ixgbe_init_rx_addrs_generic
,
2129 .update_uc_addr_list
= &ixgbe_update_uc_addr_list_generic
,
2130 .update_mc_addr_list
= &ixgbe_update_mc_addr_list_generic
,
2131 .enable_mc
= &ixgbe_enable_mc_generic
,
2132 .disable_mc
= &ixgbe_disable_mc_generic
,
2133 .clear_vfta
= &ixgbe_clear_vfta_generic
,
2134 .set_vfta
= &ixgbe_set_vfta_generic
,
2135 .fc_enable
= &ixgbe_fc_enable_generic
,
2136 .init_uta_tables
= &ixgbe_init_uta_tables_generic
,
2137 .setup_sfp
= &ixgbe_setup_sfp_modules_82599
,
2140 static struct ixgbe_eeprom_operations eeprom_ops_82599
= {
2141 .init_params
= &ixgbe_init_eeprom_params_generic
,
2142 .read
= &ixgbe_read_eerd_generic
,
2143 .write
= &ixgbe_write_eeprom_generic
,
2144 .calc_checksum
= &ixgbe_calc_eeprom_checksum_generic
,
2145 .validate_checksum
= &ixgbe_validate_eeprom_checksum_generic
,
2146 .update_checksum
= &ixgbe_update_eeprom_checksum_generic
,
2149 static struct ixgbe_phy_operations phy_ops_82599
= {
2150 .identify
= &ixgbe_identify_phy_82599
,
2151 .identify_sfp
= &ixgbe_identify_sfp_module_generic
,
2152 .init
= &ixgbe_init_phy_ops_82599
,
2153 .reset
= &ixgbe_reset_phy_generic
,
2154 .read_reg
= &ixgbe_read_phy_reg_generic
,
2155 .write_reg
= &ixgbe_write_phy_reg_generic
,
2156 .setup_link
= &ixgbe_setup_phy_link_generic
,
2157 .setup_link_speed
= &ixgbe_setup_phy_link_speed_generic
,
2158 .read_i2c_byte
= &ixgbe_read_i2c_byte_generic
,
2159 .write_i2c_byte
= &ixgbe_write_i2c_byte_generic
,
2160 .read_i2c_eeprom
= &ixgbe_read_i2c_eeprom_generic
,
2161 .write_i2c_eeprom
= &ixgbe_write_i2c_eeprom_generic
,
2162 .check_overtemp
= &ixgbe_tn_check_overtemp
,
2165 struct ixgbe_info ixgbe_82599_info
= {
2166 .mac
= ixgbe_mac_82599EB
,
2167 .get_invariants
= &ixgbe_get_invariants_82599
,
2168 .mac_ops
= &mac_ops_82599
,
2169 .eeprom_ops
= &eeprom_ops_82599
,
2170 .phy_ops
= &phy_ops_82599
,
2171 .mbx_ops
= &mbx_ops_generic
,