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Merge branch 'x86/urgent' into x86/setup
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ixgbe / ixgbe_common.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_common.h"
34 #include "ixgbe_phy.h"
35
36 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
37 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
38 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
40 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
43 u16 count);
44 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
48 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
49
50 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
51 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
52 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
54
55 /**
56 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
57 * @hw: pointer to hardware structure
58 *
59 * Starts the hardware by filling the bus info structure and media type, clears
60 * all on chip counters, initializes receive address registers, multicast
61 * table, VLAN filter table, calls routine to set up link and flow control
62 * settings, and leaves transmit and receive units disabled and uninitialized
63 **/
64 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
65 {
66 u32 ctrl_ext;
67
68 /* Set the media type */
69 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
70
71 /* Identify the PHY */
72 hw->phy.ops.identify(hw);
73
74 /*
75 * Store MAC address from RAR0, clear receive address registers, and
76 * clear the multicast table
77 */
78 hw->mac.ops.init_rx_addrs(hw);
79
80 /* Clear the VLAN filter table */
81 hw->mac.ops.clear_vfta(hw);
82
83 /* Clear statistics registers */
84 hw->mac.ops.clear_hw_cntrs(hw);
85
86 /* Set No Snoop Disable */
87 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
88 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
89 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
90 IXGBE_WRITE_FLUSH(hw);
91
92 /* Clear adapter stopped flag */
93 hw->adapter_stopped = false;
94
95 return 0;
96 }
97
98 /**
99 * ixgbe_init_hw_generic - Generic hardware initialization
100 * @hw: pointer to hardware structure
101 *
102 * Initialize the hardware by resetting the hardware, filling the bus info
103 * structure and media type, clears all on chip counters, initializes receive
104 * address registers, multicast table, VLAN filter table, calls routine to set
105 * up link and flow control settings, and leaves transmit and receive units
106 * disabled and uninitialized
107 **/
108 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
109 {
110 /* Reset the hardware */
111 hw->mac.ops.reset_hw(hw);
112
113 /* Start the HW */
114 hw->mac.ops.start_hw(hw);
115
116 return 0;
117 }
118
119 /**
120 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
121 * @hw: pointer to hardware structure
122 *
123 * Clears all hardware statistics counters by reading them from the hardware
124 * Statistics counters are clear on read.
125 **/
126 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
127 {
128 u16 i = 0;
129
130 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
131 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
132 IXGBE_READ_REG(hw, IXGBE_ERRBC);
133 IXGBE_READ_REG(hw, IXGBE_MSPDC);
134 for (i = 0; i < 8; i++)
135 IXGBE_READ_REG(hw, IXGBE_MPC(i));
136
137 IXGBE_READ_REG(hw, IXGBE_MLFC);
138 IXGBE_READ_REG(hw, IXGBE_MRFC);
139 IXGBE_READ_REG(hw, IXGBE_RLEC);
140 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
141 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
142 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
143 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
144
145 for (i = 0; i < 8; i++) {
146 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
147 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
148 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
149 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
150 }
151
152 IXGBE_READ_REG(hw, IXGBE_PRC64);
153 IXGBE_READ_REG(hw, IXGBE_PRC127);
154 IXGBE_READ_REG(hw, IXGBE_PRC255);
155 IXGBE_READ_REG(hw, IXGBE_PRC511);
156 IXGBE_READ_REG(hw, IXGBE_PRC1023);
157 IXGBE_READ_REG(hw, IXGBE_PRC1522);
158 IXGBE_READ_REG(hw, IXGBE_GPRC);
159 IXGBE_READ_REG(hw, IXGBE_BPRC);
160 IXGBE_READ_REG(hw, IXGBE_MPRC);
161 IXGBE_READ_REG(hw, IXGBE_GPTC);
162 IXGBE_READ_REG(hw, IXGBE_GORCL);
163 IXGBE_READ_REG(hw, IXGBE_GORCH);
164 IXGBE_READ_REG(hw, IXGBE_GOTCL);
165 IXGBE_READ_REG(hw, IXGBE_GOTCH);
166 for (i = 0; i < 8; i++)
167 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
168 IXGBE_READ_REG(hw, IXGBE_RUC);
169 IXGBE_READ_REG(hw, IXGBE_RFC);
170 IXGBE_READ_REG(hw, IXGBE_ROC);
171 IXGBE_READ_REG(hw, IXGBE_RJC);
172 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
173 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
174 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
175 IXGBE_READ_REG(hw, IXGBE_TORL);
176 IXGBE_READ_REG(hw, IXGBE_TORH);
177 IXGBE_READ_REG(hw, IXGBE_TPR);
178 IXGBE_READ_REG(hw, IXGBE_TPT);
179 IXGBE_READ_REG(hw, IXGBE_PTC64);
180 IXGBE_READ_REG(hw, IXGBE_PTC127);
181 IXGBE_READ_REG(hw, IXGBE_PTC255);
182 IXGBE_READ_REG(hw, IXGBE_PTC511);
183 IXGBE_READ_REG(hw, IXGBE_PTC1023);
184 IXGBE_READ_REG(hw, IXGBE_PTC1522);
185 IXGBE_READ_REG(hw, IXGBE_MPTC);
186 IXGBE_READ_REG(hw, IXGBE_BPTC);
187 for (i = 0; i < 16; i++) {
188 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
189 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
190 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
191 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
192 }
193
194 return 0;
195 }
196
197 /**
198 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
199 * @hw: pointer to hardware structure
200 * @pba_num: stores the part number from the EEPROM
201 *
202 * Reads the part number from the EEPROM.
203 **/
204 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
205 {
206 s32 ret_val;
207 u16 data;
208
209 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
210 if (ret_val) {
211 hw_dbg(hw, "NVM Read Error\n");
212 return ret_val;
213 }
214 *pba_num = (u32)(data << 16);
215
216 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
217 if (ret_val) {
218 hw_dbg(hw, "NVM Read Error\n");
219 return ret_val;
220 }
221 *pba_num |= data;
222
223 return 0;
224 }
225
226 /**
227 * ixgbe_get_mac_addr_generic - Generic get MAC address
228 * @hw: pointer to hardware structure
229 * @mac_addr: Adapter MAC address
230 *
231 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
232 * A reset of the adapter must be performed prior to calling this function
233 * in order for the MAC address to have been loaded from the EEPROM into RAR0
234 **/
235 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
236 {
237 u32 rar_high;
238 u32 rar_low;
239 u16 i;
240
241 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
242 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
243
244 for (i = 0; i < 4; i++)
245 mac_addr[i] = (u8)(rar_low >> (i*8));
246
247 for (i = 0; i < 2; i++)
248 mac_addr[i+4] = (u8)(rar_high >> (i*8));
249
250 return 0;
251 }
252
253 /**
254 * ixgbe_get_bus_info_generic - Generic set PCI bus info
255 * @hw: pointer to hardware structure
256 *
257 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
258 **/
259 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
260 {
261 struct ixgbe_adapter *adapter = hw->back;
262 struct ixgbe_mac_info *mac = &hw->mac;
263 u16 link_status;
264
265 hw->bus.type = ixgbe_bus_type_pci_express;
266
267 /* Get the negotiated link width and speed from PCI config space */
268 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
269 &link_status);
270
271 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
272 case IXGBE_PCI_LINK_WIDTH_1:
273 hw->bus.width = ixgbe_bus_width_pcie_x1;
274 break;
275 case IXGBE_PCI_LINK_WIDTH_2:
276 hw->bus.width = ixgbe_bus_width_pcie_x2;
277 break;
278 case IXGBE_PCI_LINK_WIDTH_4:
279 hw->bus.width = ixgbe_bus_width_pcie_x4;
280 break;
281 case IXGBE_PCI_LINK_WIDTH_8:
282 hw->bus.width = ixgbe_bus_width_pcie_x8;
283 break;
284 default:
285 hw->bus.width = ixgbe_bus_width_unknown;
286 break;
287 }
288
289 switch (link_status & IXGBE_PCI_LINK_SPEED) {
290 case IXGBE_PCI_LINK_SPEED_2500:
291 hw->bus.speed = ixgbe_bus_speed_2500;
292 break;
293 case IXGBE_PCI_LINK_SPEED_5000:
294 hw->bus.speed = ixgbe_bus_speed_5000;
295 break;
296 default:
297 hw->bus.speed = ixgbe_bus_speed_unknown;
298 break;
299 }
300
301 mac->ops.set_lan_id(hw);
302
303 return 0;
304 }
305
306 /**
307 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
308 * @hw: pointer to the HW structure
309 *
310 * Determines the LAN function id by reading memory-mapped registers
311 * and swaps the port value if requested.
312 **/
313 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
314 {
315 struct ixgbe_bus_info *bus = &hw->bus;
316 u32 reg;
317
318 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
319 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
320 bus->lan_id = bus->func;
321
322 /* check for a port swap */
323 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
324 if (reg & IXGBE_FACTPS_LFS)
325 bus->func ^= 0x1;
326 }
327
328 /**
329 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
330 * @hw: pointer to hardware structure
331 *
332 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
333 * disables transmit and receive units. The adapter_stopped flag is used by
334 * the shared code and drivers to determine if the adapter is in a stopped
335 * state and should not touch the hardware.
336 **/
337 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
338 {
339 u32 number_of_queues;
340 u32 reg_val;
341 u16 i;
342
343 /*
344 * Set the adapter_stopped flag so other driver functions stop touching
345 * the hardware
346 */
347 hw->adapter_stopped = true;
348
349 /* Disable the receive unit */
350 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
351 reg_val &= ~(IXGBE_RXCTRL_RXEN);
352 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
353 IXGBE_WRITE_FLUSH(hw);
354 msleep(2);
355
356 /* Clear interrupt mask to stop from interrupts being generated */
357 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
358
359 /* Clear any pending interrupts */
360 IXGBE_READ_REG(hw, IXGBE_EICR);
361
362 /* Disable the transmit unit. Each queue must be disabled. */
363 number_of_queues = hw->mac.max_tx_queues;
364 for (i = 0; i < number_of_queues; i++) {
365 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
366 if (reg_val & IXGBE_TXDCTL_ENABLE) {
367 reg_val &= ~IXGBE_TXDCTL_ENABLE;
368 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
369 }
370 }
371
372 /*
373 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
374 * access and verify no pending requests
375 */
376 if (ixgbe_disable_pcie_master(hw) != 0)
377 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
378
379 return 0;
380 }
381
382 /**
383 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
384 * @hw: pointer to hardware structure
385 * @index: led number to turn on
386 **/
387 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
388 {
389 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
390
391 /* To turn on the LED, set mode to ON. */
392 led_reg &= ~IXGBE_LED_MODE_MASK(index);
393 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
394 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
395 IXGBE_WRITE_FLUSH(hw);
396
397 return 0;
398 }
399
400 /**
401 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
402 * @hw: pointer to hardware structure
403 * @index: led number to turn off
404 **/
405 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
406 {
407 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
408
409 /* To turn off the LED, set mode to OFF. */
410 led_reg &= ~IXGBE_LED_MODE_MASK(index);
411 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
412 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
413 IXGBE_WRITE_FLUSH(hw);
414
415 return 0;
416 }
417
418 /**
419 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
420 * @hw: pointer to hardware structure
421 *
422 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
423 * ixgbe_hw struct in order to set up EEPROM access.
424 **/
425 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
426 {
427 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
428 u32 eec;
429 u16 eeprom_size;
430
431 if (eeprom->type == ixgbe_eeprom_uninitialized) {
432 eeprom->type = ixgbe_eeprom_none;
433 /* Set default semaphore delay to 10ms which is a well
434 * tested value */
435 eeprom->semaphore_delay = 10;
436
437 /*
438 * Check for EEPROM present first.
439 * If not present leave as none
440 */
441 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
442 if (eec & IXGBE_EEC_PRES) {
443 eeprom->type = ixgbe_eeprom_spi;
444
445 /*
446 * SPI EEPROM is assumed here. This code would need to
447 * change if a future EEPROM is not SPI.
448 */
449 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
450 IXGBE_EEC_SIZE_SHIFT);
451 eeprom->word_size = 1 << (eeprom_size +
452 IXGBE_EEPROM_WORD_SIZE_SHIFT);
453 }
454
455 if (eec & IXGBE_EEC_ADDR_SIZE)
456 eeprom->address_bits = 16;
457 else
458 eeprom->address_bits = 8;
459 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
460 "%d\n", eeprom->type, eeprom->word_size,
461 eeprom->address_bits);
462 }
463
464 return 0;
465 }
466
467 /**
468 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
469 * @hw: pointer to hardware structure
470 * @offset: offset within the EEPROM to be written to
471 * @data: 16 bit word to be written to the EEPROM
472 *
473 * If ixgbe_eeprom_update_checksum is not called after this function, the
474 * EEPROM will most likely contain an invalid checksum.
475 **/
476 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
477 {
478 s32 status;
479 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
480
481 hw->eeprom.ops.init_params(hw);
482
483 if (offset >= hw->eeprom.word_size) {
484 status = IXGBE_ERR_EEPROM;
485 goto out;
486 }
487
488 /* Prepare the EEPROM for writing */
489 status = ixgbe_acquire_eeprom(hw);
490
491 if (status == 0) {
492 if (ixgbe_ready_eeprom(hw) != 0) {
493 ixgbe_release_eeprom(hw);
494 status = IXGBE_ERR_EEPROM;
495 }
496 }
497
498 if (status == 0) {
499 ixgbe_standby_eeprom(hw);
500
501 /* Send the WRITE ENABLE command (8 bit opcode ) */
502 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
503 IXGBE_EEPROM_OPCODE_BITS);
504
505 ixgbe_standby_eeprom(hw);
506
507 /*
508 * Some SPI eeproms use the 8th address bit embedded in the
509 * opcode
510 */
511 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
512 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
513
514 /* Send the Write command (8-bit opcode + addr) */
515 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
516 IXGBE_EEPROM_OPCODE_BITS);
517 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
518 hw->eeprom.address_bits);
519
520 /* Send the data */
521 data = (data >> 8) | (data << 8);
522 ixgbe_shift_out_eeprom_bits(hw, data, 16);
523 ixgbe_standby_eeprom(hw);
524
525 msleep(hw->eeprom.semaphore_delay);
526 /* Done with writing - release the EEPROM */
527 ixgbe_release_eeprom(hw);
528 }
529
530 out:
531 return status;
532 }
533
534 /**
535 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
536 * @hw: pointer to hardware structure
537 * @offset: offset within the EEPROM to be read
538 * @data: read 16 bit value from EEPROM
539 *
540 * Reads 16 bit value from EEPROM through bit-bang method
541 **/
542 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
543 u16 *data)
544 {
545 s32 status;
546 u16 word_in;
547 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
548
549 hw->eeprom.ops.init_params(hw);
550
551 if (offset >= hw->eeprom.word_size) {
552 status = IXGBE_ERR_EEPROM;
553 goto out;
554 }
555
556 /* Prepare the EEPROM for reading */
557 status = ixgbe_acquire_eeprom(hw);
558
559 if (status == 0) {
560 if (ixgbe_ready_eeprom(hw) != 0) {
561 ixgbe_release_eeprom(hw);
562 status = IXGBE_ERR_EEPROM;
563 }
564 }
565
566 if (status == 0) {
567 ixgbe_standby_eeprom(hw);
568
569 /*
570 * Some SPI eeproms use the 8th address bit embedded in the
571 * opcode
572 */
573 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
574 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
575
576 /* Send the READ command (opcode + addr) */
577 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
578 IXGBE_EEPROM_OPCODE_BITS);
579 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
580 hw->eeprom.address_bits);
581
582 /* Read the data. */
583 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
584 *data = (word_in >> 8) | (word_in << 8);
585
586 /* End this read operation */
587 ixgbe_release_eeprom(hw);
588 }
589
590 out:
591 return status;
592 }
593
594 /**
595 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
596 * @hw: pointer to hardware structure
597 * @offset: offset of word in the EEPROM to read
598 * @data: word read from the EEPROM
599 *
600 * Reads a 16 bit word from the EEPROM using the EERD register.
601 **/
602 s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
603 {
604 u32 eerd;
605 s32 status;
606
607 hw->eeprom.ops.init_params(hw);
608
609 if (offset >= hw->eeprom.word_size) {
610 status = IXGBE_ERR_EEPROM;
611 goto out;
612 }
613
614 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
615 IXGBE_EEPROM_READ_REG_START;
616
617 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
618 status = ixgbe_poll_eeprom_eerd_done(hw);
619
620 if (status == 0)
621 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
622 IXGBE_EEPROM_READ_REG_DATA);
623 else
624 hw_dbg(hw, "Eeprom read timed out\n");
625
626 out:
627 return status;
628 }
629
630 /**
631 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
632 * @hw: pointer to hardware structure
633 *
634 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
635 **/
636 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
637 {
638 u32 i;
639 u32 reg;
640 s32 status = IXGBE_ERR_EEPROM;
641
642 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
643 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
644 if (reg & IXGBE_EEPROM_READ_REG_DONE) {
645 status = 0;
646 break;
647 }
648 udelay(5);
649 }
650 return status;
651 }
652
653 /**
654 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
655 * @hw: pointer to hardware structure
656 *
657 * Prepares EEPROM for access using bit-bang method. This function should
658 * be called before issuing a command to the EEPROM.
659 **/
660 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
661 {
662 s32 status = 0;
663 u32 eec = 0;
664 u32 i;
665
666 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
667 status = IXGBE_ERR_SWFW_SYNC;
668
669 if (status == 0) {
670 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
671
672 /* Request EEPROM Access */
673 eec |= IXGBE_EEC_REQ;
674 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
675
676 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
677 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
678 if (eec & IXGBE_EEC_GNT)
679 break;
680 udelay(5);
681 }
682
683 /* Release if grant not acquired */
684 if (!(eec & IXGBE_EEC_GNT)) {
685 eec &= ~IXGBE_EEC_REQ;
686 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
687 hw_dbg(hw, "Could not acquire EEPROM grant\n");
688
689 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
690 status = IXGBE_ERR_EEPROM;
691 }
692 }
693
694 /* Setup EEPROM for Read/Write */
695 if (status == 0) {
696 /* Clear CS and SK */
697 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
698 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
699 IXGBE_WRITE_FLUSH(hw);
700 udelay(1);
701 }
702 return status;
703 }
704
705 /**
706 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
707 * @hw: pointer to hardware structure
708 *
709 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
710 **/
711 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
712 {
713 s32 status = IXGBE_ERR_EEPROM;
714 u32 timeout;
715 u32 i;
716 u32 swsm;
717
718 /* Set timeout value based on size of EEPROM */
719 timeout = hw->eeprom.word_size + 1;
720
721 /* Get SMBI software semaphore between device drivers first */
722 for (i = 0; i < timeout; i++) {
723 /*
724 * If the SMBI bit is 0 when we read it, then the bit will be
725 * set and we have the semaphore
726 */
727 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
728 if (!(swsm & IXGBE_SWSM_SMBI)) {
729 status = 0;
730 break;
731 }
732 msleep(1);
733 }
734
735 /* Now get the semaphore between SW/FW through the SWESMBI bit */
736 if (status == 0) {
737 for (i = 0; i < timeout; i++) {
738 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
739
740 /* Set the SW EEPROM semaphore bit to request access */
741 swsm |= IXGBE_SWSM_SWESMBI;
742 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
743
744 /*
745 * If we set the bit successfully then we got the
746 * semaphore.
747 */
748 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
749 if (swsm & IXGBE_SWSM_SWESMBI)
750 break;
751
752 udelay(50);
753 }
754
755 /*
756 * Release semaphores and return error if SW EEPROM semaphore
757 * was not granted because we don't have access to the EEPROM
758 */
759 if (i >= timeout) {
760 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
761 "not granted.\n");
762 ixgbe_release_eeprom_semaphore(hw);
763 status = IXGBE_ERR_EEPROM;
764 }
765 }
766
767 return status;
768 }
769
770 /**
771 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
772 * @hw: pointer to hardware structure
773 *
774 * This function clears hardware semaphore bits.
775 **/
776 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
777 {
778 u32 swsm;
779
780 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
781
782 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
783 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
784 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
785 IXGBE_WRITE_FLUSH(hw);
786 }
787
788 /**
789 * ixgbe_ready_eeprom - Polls for EEPROM ready
790 * @hw: pointer to hardware structure
791 **/
792 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
793 {
794 s32 status = 0;
795 u16 i;
796 u8 spi_stat_reg;
797
798 /*
799 * Read "Status Register" repeatedly until the LSB is cleared. The
800 * EEPROM will signal that the command has been completed by clearing
801 * bit 0 of the internal status register. If it's not cleared within
802 * 5 milliseconds, then error out.
803 */
804 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
805 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
806 IXGBE_EEPROM_OPCODE_BITS);
807 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
808 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
809 break;
810
811 udelay(5);
812 ixgbe_standby_eeprom(hw);
813 };
814
815 /*
816 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
817 * devices (and only 0-5mSec on 5V devices)
818 */
819 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
820 hw_dbg(hw, "SPI EEPROM Status error\n");
821 status = IXGBE_ERR_EEPROM;
822 }
823
824 return status;
825 }
826
827 /**
828 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
829 * @hw: pointer to hardware structure
830 **/
831 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
832 {
833 u32 eec;
834
835 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
836
837 /* Toggle CS to flush commands */
838 eec |= IXGBE_EEC_CS;
839 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
840 IXGBE_WRITE_FLUSH(hw);
841 udelay(1);
842 eec &= ~IXGBE_EEC_CS;
843 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
844 IXGBE_WRITE_FLUSH(hw);
845 udelay(1);
846 }
847
848 /**
849 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
850 * @hw: pointer to hardware structure
851 * @data: data to send to the EEPROM
852 * @count: number of bits to shift out
853 **/
854 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
855 u16 count)
856 {
857 u32 eec;
858 u32 mask;
859 u32 i;
860
861 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
862
863 /*
864 * Mask is used to shift "count" bits of "data" out to the EEPROM
865 * one bit at a time. Determine the starting bit based on count
866 */
867 mask = 0x01 << (count - 1);
868
869 for (i = 0; i < count; i++) {
870 /*
871 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
872 * "1", and then raising and then lowering the clock (the SK
873 * bit controls the clock input to the EEPROM). A "0" is
874 * shifted out to the EEPROM by setting "DI" to "0" and then
875 * raising and then lowering the clock.
876 */
877 if (data & mask)
878 eec |= IXGBE_EEC_DI;
879 else
880 eec &= ~IXGBE_EEC_DI;
881
882 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
883 IXGBE_WRITE_FLUSH(hw);
884
885 udelay(1);
886
887 ixgbe_raise_eeprom_clk(hw, &eec);
888 ixgbe_lower_eeprom_clk(hw, &eec);
889
890 /*
891 * Shift mask to signify next bit of data to shift in to the
892 * EEPROM
893 */
894 mask = mask >> 1;
895 };
896
897 /* We leave the "DI" bit set to "0" when we leave this routine. */
898 eec &= ~IXGBE_EEC_DI;
899 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
900 IXGBE_WRITE_FLUSH(hw);
901 }
902
903 /**
904 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
905 * @hw: pointer to hardware structure
906 **/
907 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
908 {
909 u32 eec;
910 u32 i;
911 u16 data = 0;
912
913 /*
914 * In order to read a register from the EEPROM, we need to shift
915 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
916 * the clock input to the EEPROM (setting the SK bit), and then reading
917 * the value of the "DO" bit. During this "shifting in" process the
918 * "DI" bit should always be clear.
919 */
920 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
921
922 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
923
924 for (i = 0; i < count; i++) {
925 data = data << 1;
926 ixgbe_raise_eeprom_clk(hw, &eec);
927
928 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
929
930 eec &= ~(IXGBE_EEC_DI);
931 if (eec & IXGBE_EEC_DO)
932 data |= 1;
933
934 ixgbe_lower_eeprom_clk(hw, &eec);
935 }
936
937 return data;
938 }
939
940 /**
941 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
942 * @hw: pointer to hardware structure
943 * @eec: EEC register's current value
944 **/
945 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
946 {
947 /*
948 * Raise the clock input to the EEPROM
949 * (setting the SK bit), then delay
950 */
951 *eec = *eec | IXGBE_EEC_SK;
952 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
953 IXGBE_WRITE_FLUSH(hw);
954 udelay(1);
955 }
956
957 /**
958 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
959 * @hw: pointer to hardware structure
960 * @eecd: EECD's current value
961 **/
962 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
963 {
964 /*
965 * Lower the clock input to the EEPROM (clearing the SK bit), then
966 * delay
967 */
968 *eec = *eec & ~IXGBE_EEC_SK;
969 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
970 IXGBE_WRITE_FLUSH(hw);
971 udelay(1);
972 }
973
974 /**
975 * ixgbe_release_eeprom - Release EEPROM, release semaphores
976 * @hw: pointer to hardware structure
977 **/
978 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
979 {
980 u32 eec;
981
982 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
983
984 eec |= IXGBE_EEC_CS; /* Pull CS high */
985 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
986
987 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
988 IXGBE_WRITE_FLUSH(hw);
989
990 udelay(1);
991
992 /* Stop requesting EEPROM access */
993 eec &= ~IXGBE_EEC_REQ;
994 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
995
996 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
997 }
998
999 /**
1000 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1001 * @hw: pointer to hardware structure
1002 **/
1003 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1004 {
1005 u16 i;
1006 u16 j;
1007 u16 checksum = 0;
1008 u16 length = 0;
1009 u16 pointer = 0;
1010 u16 word = 0;
1011
1012 /* Include 0x0-0x3F in the checksum */
1013 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1014 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1015 hw_dbg(hw, "EEPROM read failed\n");
1016 break;
1017 }
1018 checksum += word;
1019 }
1020
1021 /* Include all data from pointers except for the fw pointer */
1022 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1023 hw->eeprom.ops.read(hw, i, &pointer);
1024
1025 /* Make sure the pointer seems valid */
1026 if (pointer != 0xFFFF && pointer != 0) {
1027 hw->eeprom.ops.read(hw, pointer, &length);
1028
1029 if (length != 0xFFFF && length != 0) {
1030 for (j = pointer+1; j <= pointer+length; j++) {
1031 hw->eeprom.ops.read(hw, j, &word);
1032 checksum += word;
1033 }
1034 }
1035 }
1036 }
1037
1038 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1039
1040 return checksum;
1041 }
1042
1043 /**
1044 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1045 * @hw: pointer to hardware structure
1046 * @checksum_val: calculated checksum
1047 *
1048 * Performs checksum calculation and validates the EEPROM checksum. If the
1049 * caller does not need checksum_val, the value can be NULL.
1050 **/
1051 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1052 u16 *checksum_val)
1053 {
1054 s32 status;
1055 u16 checksum;
1056 u16 read_checksum = 0;
1057
1058 /*
1059 * Read the first word from the EEPROM. If this times out or fails, do
1060 * not continue or we could be in for a very long wait while every
1061 * EEPROM read fails
1062 */
1063 status = hw->eeprom.ops.read(hw, 0, &checksum);
1064
1065 if (status == 0) {
1066 checksum = ixgbe_calc_eeprom_checksum(hw);
1067
1068 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1069
1070 /*
1071 * Verify read checksum from EEPROM is the same as
1072 * calculated checksum
1073 */
1074 if (read_checksum != checksum)
1075 status = IXGBE_ERR_EEPROM_CHECKSUM;
1076
1077 /* If the user cares, return the calculated checksum */
1078 if (checksum_val)
1079 *checksum_val = checksum;
1080 } else {
1081 hw_dbg(hw, "EEPROM read failed\n");
1082 }
1083
1084 return status;
1085 }
1086
1087 /**
1088 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1089 * @hw: pointer to hardware structure
1090 **/
1091 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1092 {
1093 s32 status;
1094 u16 checksum;
1095
1096 /*
1097 * Read the first word from the EEPROM. If this times out or fails, do
1098 * not continue or we could be in for a very long wait while every
1099 * EEPROM read fails
1100 */
1101 status = hw->eeprom.ops.read(hw, 0, &checksum);
1102
1103 if (status == 0) {
1104 checksum = ixgbe_calc_eeprom_checksum(hw);
1105 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1106 checksum);
1107 } else {
1108 hw_dbg(hw, "EEPROM read failed\n");
1109 }
1110
1111 return status;
1112 }
1113
1114 /**
1115 * ixgbe_validate_mac_addr - Validate MAC address
1116 * @mac_addr: pointer to MAC address.
1117 *
1118 * Tests a MAC address to ensure it is a valid Individual Address
1119 **/
1120 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1121 {
1122 s32 status = 0;
1123
1124 /* Make sure it is not a multicast address */
1125 if (IXGBE_IS_MULTICAST(mac_addr))
1126 status = IXGBE_ERR_INVALID_MAC_ADDR;
1127 /* Not a broadcast address */
1128 else if (IXGBE_IS_BROADCAST(mac_addr))
1129 status = IXGBE_ERR_INVALID_MAC_ADDR;
1130 /* Reject the zero address */
1131 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1132 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
1133 status = IXGBE_ERR_INVALID_MAC_ADDR;
1134
1135 return status;
1136 }
1137
1138 /**
1139 * ixgbe_set_rar_generic - Set Rx address register
1140 * @hw: pointer to hardware structure
1141 * @index: Receive address register to write
1142 * @addr: Address to put into receive address register
1143 * @vmdq: VMDq "set" or "pool" index
1144 * @enable_addr: set flag that address is active
1145 *
1146 * Puts an ethernet address into a receive address register.
1147 **/
1148 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1149 u32 enable_addr)
1150 {
1151 u32 rar_low, rar_high;
1152 u32 rar_entries = hw->mac.num_rar_entries;
1153
1154 /* setup VMDq pool selection before this RAR gets enabled */
1155 hw->mac.ops.set_vmdq(hw, index, vmdq);
1156
1157 /* Make sure we are using a valid rar index range */
1158 if (index < rar_entries) {
1159 /*
1160 * HW expects these in little endian so we reverse the byte
1161 * order from network order (big endian) to little endian
1162 */
1163 rar_low = ((u32)addr[0] |
1164 ((u32)addr[1] << 8) |
1165 ((u32)addr[2] << 16) |
1166 ((u32)addr[3] << 24));
1167 /*
1168 * Some parts put the VMDq setting in the extra RAH bits,
1169 * so save everything except the lower 16 bits that hold part
1170 * of the address and the address valid bit.
1171 */
1172 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1173 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1174 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1175
1176 if (enable_addr != 0)
1177 rar_high |= IXGBE_RAH_AV;
1178
1179 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1180 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1181 } else {
1182 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1183 }
1184
1185 return 0;
1186 }
1187
1188 /**
1189 * ixgbe_clear_rar_generic - Remove Rx address register
1190 * @hw: pointer to hardware structure
1191 * @index: Receive address register to write
1192 *
1193 * Clears an ethernet address from a receive address register.
1194 **/
1195 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1196 {
1197 u32 rar_high;
1198 u32 rar_entries = hw->mac.num_rar_entries;
1199
1200 /* Make sure we are using a valid rar index range */
1201 if (index < rar_entries) {
1202 /*
1203 * Some parts put the VMDq setting in the extra RAH bits,
1204 * so save everything except the lower 16 bits that hold part
1205 * of the address and the address valid bit.
1206 */
1207 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1208 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1209
1210 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1211 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1212 } else {
1213 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1214 }
1215
1216 /* clear VMDq pool/queue selection for this RAR */
1217 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1218
1219 return 0;
1220 }
1221
1222 /**
1223 * ixgbe_enable_rar - Enable Rx address register
1224 * @hw: pointer to hardware structure
1225 * @index: index into the RAR table
1226 *
1227 * Enables the select receive address register.
1228 **/
1229 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1230 {
1231 u32 rar_high;
1232
1233 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1234 rar_high |= IXGBE_RAH_AV;
1235 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1236 }
1237
1238 /**
1239 * ixgbe_disable_rar - Disable Rx address register
1240 * @hw: pointer to hardware structure
1241 * @index: index into the RAR table
1242 *
1243 * Disables the select receive address register.
1244 **/
1245 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1246 {
1247 u32 rar_high;
1248
1249 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1250 rar_high &= (~IXGBE_RAH_AV);
1251 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1252 }
1253
1254 /**
1255 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1256 * @hw: pointer to hardware structure
1257 *
1258 * Places the MAC address in receive address register 0 and clears the rest
1259 * of the receive address registers. Clears the multicast table. Assumes
1260 * the receiver is in reset when the routine is called.
1261 **/
1262 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1263 {
1264 u32 i;
1265 u32 rar_entries = hw->mac.num_rar_entries;
1266
1267 /*
1268 * If the current mac address is valid, assume it is a software override
1269 * to the permanent address.
1270 * Otherwise, use the permanent address from the eeprom.
1271 */
1272 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1273 IXGBE_ERR_INVALID_MAC_ADDR) {
1274 /* Get the MAC address from the RAR0 for later reference */
1275 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1276
1277 hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
1278 hw->mac.addr[0], hw->mac.addr[1],
1279 hw->mac.addr[2]);
1280 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1281 hw->mac.addr[4], hw->mac.addr[5]);
1282 } else {
1283 /* Setup the receive address. */
1284 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1285 hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ",
1286 hw->mac.addr[0], hw->mac.addr[1],
1287 hw->mac.addr[2]);
1288 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1289 hw->mac.addr[4], hw->mac.addr[5]);
1290
1291 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1292 }
1293 hw->addr_ctrl.overflow_promisc = 0;
1294
1295 hw->addr_ctrl.rar_used_count = 1;
1296
1297 /* Zero out the other receive addresses. */
1298 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1299 for (i = 1; i < rar_entries; i++) {
1300 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1301 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1302 }
1303
1304 /* Clear the MTA */
1305 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1306 hw->addr_ctrl.mta_in_use = 0;
1307 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1308
1309 hw_dbg(hw, " Clearing MTA\n");
1310 for (i = 0; i < hw->mac.mcft_size; i++)
1311 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1312
1313 if (hw->mac.ops.init_uta_tables)
1314 hw->mac.ops.init_uta_tables(hw);
1315
1316 return 0;
1317 }
1318
1319 /**
1320 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1321 * @hw: pointer to hardware structure
1322 * @addr: new address
1323 *
1324 * Adds it to unused receive address register or goes into promiscuous mode.
1325 **/
1326 static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
1327 {
1328 u32 rar_entries = hw->mac.num_rar_entries;
1329 u32 rar;
1330
1331 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1332 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1333
1334 /*
1335 * Place this address in the RAR if there is room,
1336 * else put the controller into promiscuous mode
1337 */
1338 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1339 rar = hw->addr_ctrl.rar_used_count -
1340 hw->addr_ctrl.mc_addr_in_rar_count;
1341 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
1342 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
1343 hw->addr_ctrl.rar_used_count++;
1344 } else {
1345 hw->addr_ctrl.overflow_promisc++;
1346 }
1347
1348 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
1349 }
1350
1351 /**
1352 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
1353 * @hw: pointer to hardware structure
1354 * @addr_list: the list of new addresses
1355 * @addr_count: number of addresses
1356 * @next: iterator function to walk the address list
1357 *
1358 * The given list replaces any existing list. Clears the secondary addrs from
1359 * receive address registers. Uses unused receive address registers for the
1360 * first secondary addresses, and falls back to promiscuous mode as needed.
1361 *
1362 * Drivers using secondary unicast addresses must set user_set_promisc when
1363 * manually putting the device into promiscuous mode.
1364 **/
1365 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
1366 u32 addr_count, ixgbe_mc_addr_itr next)
1367 {
1368 u8 *addr;
1369 u32 i;
1370 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1371 u32 uc_addr_in_use;
1372 u32 fctrl;
1373 u32 vmdq;
1374
1375 /*
1376 * Clear accounting of old secondary address list,
1377 * don't count RAR[0]
1378 */
1379 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
1380 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1381 hw->addr_ctrl.overflow_promisc = 0;
1382
1383 /* Zero out the other receive addresses */
1384 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use);
1385 for (i = 1; i <= uc_addr_in_use; i++) {
1386 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1387 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1388 }
1389
1390 /* Add the new addresses */
1391 for (i = 0; i < addr_count; i++) {
1392 hw_dbg(hw, " Adding the secondary addresses:\n");
1393 addr = next(hw, &addr_list, &vmdq);
1394 ixgbe_add_uc_addr(hw, addr, vmdq);
1395 }
1396
1397 if (hw->addr_ctrl.overflow_promisc) {
1398 /* enable promisc if not already in overflow or set by user */
1399 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1400 hw_dbg(hw, " Entering address overflow promisc mode\n");
1401 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1402 fctrl |= IXGBE_FCTRL_UPE;
1403 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1404 }
1405 } else {
1406 /* only disable if set by overflow, not by user */
1407 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1408 hw_dbg(hw, " Leaving address overflow promisc mode\n");
1409 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1410 fctrl &= ~IXGBE_FCTRL_UPE;
1411 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1412 }
1413 }
1414
1415 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
1416 return 0;
1417 }
1418
1419 /**
1420 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1421 * @hw: pointer to hardware structure
1422 * @mc_addr: the multicast address
1423 *
1424 * Extracts the 12 bits, from a multicast address, to determine which
1425 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1426 * incoming rx multicast addresses, to determine the bit-vector to check in
1427 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1428 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1429 * to mc_filter_type.
1430 **/
1431 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1432 {
1433 u32 vector = 0;
1434
1435 switch (hw->mac.mc_filter_type) {
1436 case 0: /* use bits [47:36] of the address */
1437 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1438 break;
1439 case 1: /* use bits [46:35] of the address */
1440 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1441 break;
1442 case 2: /* use bits [45:34] of the address */
1443 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1444 break;
1445 case 3: /* use bits [43:32] of the address */
1446 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1447 break;
1448 default: /* Invalid mc_filter_type */
1449 hw_dbg(hw, "MC filter type param set incorrectly\n");
1450 break;
1451 }
1452
1453 /* vector can only be 12-bits or boundary will be exceeded */
1454 vector &= 0xFFF;
1455 return vector;
1456 }
1457
1458 /**
1459 * ixgbe_set_mta - Set bit-vector in multicast table
1460 * @hw: pointer to hardware structure
1461 * @hash_value: Multicast address hash value
1462 *
1463 * Sets the bit-vector in the multicast table.
1464 **/
1465 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1466 {
1467 u32 vector;
1468 u32 vector_bit;
1469 u32 vector_reg;
1470 u32 mta_reg;
1471
1472 hw->addr_ctrl.mta_in_use++;
1473
1474 vector = ixgbe_mta_vector(hw, mc_addr);
1475 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1476
1477 /*
1478 * The MTA is a register array of 128 32-bit registers. It is treated
1479 * like an array of 4096 bits. We want to set bit
1480 * BitArray[vector_value]. So we figure out what register the bit is
1481 * in, read it, OR in the new bit, then write back the new value. The
1482 * register is determined by the upper 7 bits of the vector value and
1483 * the bit within that register are determined by the lower 5 bits of
1484 * the value.
1485 */
1486 vector_reg = (vector >> 5) & 0x7F;
1487 vector_bit = vector & 0x1F;
1488 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1489 mta_reg |= (1 << vector_bit);
1490 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1491 }
1492
1493 /**
1494 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1495 * @hw: pointer to hardware structure
1496 * @mc_addr_list: the list of new multicast addresses
1497 * @mc_addr_count: number of addresses
1498 * @next: iterator function to walk the multicast address list
1499 *
1500 * The given list replaces any existing list. Clears the MC addrs from receive
1501 * address registers and the multicast table. Uses unused receive address
1502 * registers for the first multicast addresses, and hashes the rest into the
1503 * multicast table.
1504 **/
1505 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
1506 u32 mc_addr_count, ixgbe_mc_addr_itr next)
1507 {
1508 u32 i;
1509 u32 vmdq;
1510
1511 /*
1512 * Set the new number of MC addresses that we are being requested to
1513 * use.
1514 */
1515 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
1516 hw->addr_ctrl.mta_in_use = 0;
1517
1518 /* Clear the MTA */
1519 hw_dbg(hw, " Clearing MTA\n");
1520 for (i = 0; i < hw->mac.mcft_size; i++)
1521 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1522
1523 /* Add the new addresses */
1524 for (i = 0; i < mc_addr_count; i++) {
1525 hw_dbg(hw, " Adding the multicast addresses:\n");
1526 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
1527 }
1528
1529 /* Enable mta */
1530 if (hw->addr_ctrl.mta_in_use > 0)
1531 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1532 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
1533
1534 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
1535 return 0;
1536 }
1537
1538 /**
1539 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1540 * @hw: pointer to hardware structure
1541 *
1542 * Enables multicast address in RAR and the use of the multicast hash table.
1543 **/
1544 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1545 {
1546 u32 i;
1547 u32 rar_entries = hw->mac.num_rar_entries;
1548 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1549
1550 if (a->mc_addr_in_rar_count > 0)
1551 for (i = (rar_entries - a->mc_addr_in_rar_count);
1552 i < rar_entries; i++)
1553 ixgbe_enable_rar(hw, i);
1554
1555 if (a->mta_in_use > 0)
1556 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1557 hw->mac.mc_filter_type);
1558
1559 return 0;
1560 }
1561
1562 /**
1563 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1564 * @hw: pointer to hardware structure
1565 *
1566 * Disables multicast address in RAR and the use of the multicast hash table.
1567 **/
1568 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1569 {
1570 u32 i;
1571 u32 rar_entries = hw->mac.num_rar_entries;
1572 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1573
1574 if (a->mc_addr_in_rar_count > 0)
1575 for (i = (rar_entries - a->mc_addr_in_rar_count);
1576 i < rar_entries; i++)
1577 ixgbe_disable_rar(hw, i);
1578
1579 if (a->mta_in_use > 0)
1580 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1581
1582 return 0;
1583 }
1584
1585 /**
1586 * ixgbe_fc_enable - Enable flow control
1587 * @hw: pointer to hardware structure
1588 * @packetbuf_num: packet buffer number (0-7)
1589 *
1590 * Enable flow control according to the current settings.
1591 **/
1592 s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
1593 {
1594 s32 ret_val = 0;
1595 u32 mflcn_reg;
1596 u32 fccfg_reg;
1597 u32 reg;
1598
1599 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1600 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1601
1602 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1603 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1604
1605 /*
1606 * The possible values of fc.current_mode are:
1607 * 0: Flow control is completely disabled
1608 * 1: Rx flow control is enabled (we can receive pause frames,
1609 * but not send pause frames).
1610 * 2: Tx flow control is enabled (we can send pause frames but
1611 * we do not support receiving pause frames).
1612 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1613 * 4: Priority Flow Control is enabled.
1614 * other: Invalid.
1615 */
1616 switch (hw->fc.current_mode) {
1617 case ixgbe_fc_none:
1618 /* Flow control completely disabled by software override. */
1619 break;
1620 case ixgbe_fc_rx_pause:
1621 /*
1622 * Rx Flow control is enabled and Tx Flow control is
1623 * disabled by software override. Since there really
1624 * isn't a way to advertise that we are capable of RX
1625 * Pause ONLY, we will advertise that we support both
1626 * symmetric and asymmetric Rx PAUSE. Later, we will
1627 * disable the adapter's ability to send PAUSE frames.
1628 */
1629 mflcn_reg |= IXGBE_MFLCN_RFCE;
1630 break;
1631 case ixgbe_fc_tx_pause:
1632 /*
1633 * Tx Flow control is enabled, and Rx Flow control is
1634 * disabled by software override.
1635 */
1636 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1637 break;
1638 case ixgbe_fc_full:
1639 /* Flow control (both Rx and Tx) is enabled by SW override. */
1640 mflcn_reg |= IXGBE_MFLCN_RFCE;
1641 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1642 break;
1643 #ifdef CONFIG_DCB
1644 case ixgbe_fc_pfc:
1645 goto out;
1646 break;
1647 #endif
1648 default:
1649 hw_dbg(hw, "Flow control param set incorrectly\n");
1650 ret_val = -IXGBE_ERR_CONFIG;
1651 goto out;
1652 break;
1653 }
1654
1655 /* Enable 802.3x based flow control settings. */
1656 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1657 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1658
1659 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
1660 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1661 if (hw->fc.send_xon)
1662 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
1663 (hw->fc.low_water | IXGBE_FCRTL_XONE));
1664 else
1665 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
1666 hw->fc.low_water);
1667
1668 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1669 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1670 }
1671
1672 /* Configure pause time (2 TCs per register) */
1673 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
1674 if ((packetbuf_num & 1) == 0)
1675 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1676 else
1677 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1678 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1679
1680 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1681
1682 out:
1683 return ret_val;
1684 }
1685
1686 /**
1687 * ixgbe_fc_autoneg - Configure flow control
1688 * @hw: pointer to hardware structure
1689 *
1690 * Negotiates flow control capabilities with link partner using autoneg and
1691 * applies the results.
1692 **/
1693 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1694 {
1695 s32 ret_val = 0;
1696 u32 i, reg, pcs_anadv_reg, pcs_lpab_reg;
1697
1698 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1699
1700 /*
1701 * The possible values of fc.current_mode are:
1702 * 0: Flow control is completely disabled
1703 * 1: Rx flow control is enabled (we can receive pause frames,
1704 * but not send pause frames).
1705 * 2: Tx flow control is enabled (we can send pause frames but
1706 * we do not support receiving pause frames).
1707 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1708 * 4: Priority Flow Control is enabled.
1709 * other: Invalid.
1710 */
1711 switch (hw->fc.current_mode) {
1712 case ixgbe_fc_none:
1713 /* Flow control completely disabled by software override. */
1714 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1715 break;
1716 case ixgbe_fc_rx_pause:
1717 /*
1718 * Rx Flow control is enabled and Tx Flow control is
1719 * disabled by software override. Since there really
1720 * isn't a way to advertise that we are capable of RX
1721 * Pause ONLY, we will advertise that we support both
1722 * symmetric and asymmetric Rx PAUSE. Later, we will
1723 * disable the adapter's ability to send PAUSE frames.
1724 */
1725 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1726 break;
1727 case ixgbe_fc_tx_pause:
1728 /*
1729 * Tx Flow control is enabled, and Rx Flow control is
1730 * disabled by software override.
1731 */
1732 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1733 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1734 break;
1735 case ixgbe_fc_full:
1736 /* Flow control (both Rx and Tx) is enabled by SW override. */
1737 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1738 break;
1739 #ifdef CONFIG_DCB
1740 case ixgbe_fc_pfc:
1741 goto out;
1742 break;
1743 #endif
1744 default:
1745 hw_dbg(hw, "Flow control param set incorrectly\n");
1746 ret_val = -IXGBE_ERR_CONFIG;
1747 goto out;
1748 break;
1749 }
1750
1751 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
1752 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
1753
1754 /* Set PCS register for autoneg */
1755 /* Enable and restart autoneg */
1756 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
1757
1758 /* Disable AN timeout */
1759 if (hw->fc.strict_ieee)
1760 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
1761
1762 hw_dbg(hw, "Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1763 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
1764
1765 /* See if autonegotiation has succeeded */
1766 hw->mac.autoneg_succeeded = 0;
1767 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1768 msleep(10);
1769 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1770 if ((reg & (IXGBE_PCS1GLSTA_LINK_OK |
1771 IXGBE_PCS1GLSTA_AN_COMPLETE)) ==
1772 (IXGBE_PCS1GLSTA_LINK_OK |
1773 IXGBE_PCS1GLSTA_AN_COMPLETE)) {
1774 if (!(reg & IXGBE_PCS1GLSTA_AN_TIMED_OUT))
1775 hw->mac.autoneg_succeeded = 1;
1776 break;
1777 }
1778 }
1779
1780 if (!hw->mac.autoneg_succeeded) {
1781 /* Autoneg failed to achieve a link, so we turn fc off */
1782 hw->fc.current_mode = ixgbe_fc_none;
1783 hw_dbg(hw, "Flow Control = NONE.\n");
1784 goto out;
1785 }
1786
1787 /*
1788 * Read the AN advertisement and LP ability registers and resolve
1789 * local flow control settings accordingly
1790 */
1791 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1792 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1793 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1794 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1795 /*
1796 * Now we need to check if the user selected Rx ONLY
1797 * of pause frames. In this case, we had to advertise
1798 * FULL flow control because we could not advertise RX
1799 * ONLY. Hence, we must now check to see if we need to
1800 * turn OFF the TRANSMISSION of PAUSE frames.
1801 */
1802 if (hw->fc.requested_mode == ixgbe_fc_full) {
1803 hw->fc.current_mode = ixgbe_fc_full;
1804 hw_dbg(hw, "Flow Control = FULL.\n");
1805 } else {
1806 hw->fc.current_mode = ixgbe_fc_rx_pause;
1807 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1808 }
1809 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1810 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1811 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1812 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1813 hw->fc.current_mode = ixgbe_fc_tx_pause;
1814 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1815 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1816 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1817 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1818 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1819 hw->fc.current_mode = ixgbe_fc_rx_pause;
1820 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1821 } else {
1822 hw->fc.current_mode = ixgbe_fc_none;
1823 hw_dbg(hw, "Flow Control = NONE.\n");
1824 }
1825
1826 out:
1827 return ret_val;
1828 }
1829
1830 /**
1831 * ixgbe_setup_fc_generic - Set up flow control
1832 * @hw: pointer to hardware structure
1833 *
1834 * Sets up flow control.
1835 **/
1836 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1837 {
1838 s32 ret_val = 0;
1839 ixgbe_link_speed speed;
1840 bool link_up;
1841
1842 #ifdef CONFIG_DCB
1843 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1844 hw->fc.current_mode = hw->fc.requested_mode;
1845 goto out;
1846 }
1847
1848 #endif
1849 /* Validate the packetbuf configuration */
1850 if (packetbuf_num < 0 || packetbuf_num > 7) {
1851 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1852 "is 0-7\n", packetbuf_num);
1853 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1854 goto out;
1855 }
1856
1857 /*
1858 * Validate the water mark configuration. Zero water marks are invalid
1859 * because it causes the controller to just blast out fc packets.
1860 */
1861 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
1862 hw_dbg(hw, "Invalid water mark configuration\n");
1863 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1864 goto out;
1865 }
1866
1867 /*
1868 * Validate the requested mode. Strict IEEE mode does not allow
1869 * ixgbe_fc_rx_pause because it will cause testing anomalies.
1870 */
1871 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1872 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
1873 "IEEE mode\n");
1874 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1875 goto out;
1876 }
1877
1878 /*
1879 * 10gig parts do not have a word in the EEPROM to determine the
1880 * default flow control setting, so we explicitly set it to full.
1881 */
1882 if (hw->fc.requested_mode == ixgbe_fc_default)
1883 hw->fc.requested_mode = ixgbe_fc_full;
1884
1885 /*
1886 * Save off the requested flow control mode for use later. Depending
1887 * on the link partner's capabilities, we may or may not use this mode.
1888 */
1889 hw->fc.current_mode = hw->fc.requested_mode;
1890
1891 /* Decide whether to use autoneg or not. */
1892 hw->mac.ops.check_link(hw, &speed, &link_up, false);
1893 if (!hw->fc.disable_fc_autoneg && hw->phy.multispeed_fiber &&
1894 (speed == IXGBE_LINK_SPEED_1GB_FULL))
1895 ret_val = ixgbe_fc_autoneg(hw);
1896
1897 if (ret_val)
1898 goto out;
1899
1900 ret_val = ixgbe_fc_enable(hw, packetbuf_num);
1901
1902 out:
1903 return ret_val;
1904 }
1905
1906 /**
1907 * ixgbe_disable_pcie_master - Disable PCI-express master access
1908 * @hw: pointer to hardware structure
1909 *
1910 * Disables PCI-Express master access and verifies there are no pending
1911 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1912 * bit hasn't caused the master requests to be disabled, else 0
1913 * is returned signifying master requests disabled.
1914 **/
1915 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
1916 {
1917 u32 i;
1918 u32 reg_val;
1919 u32 number_of_queues;
1920 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
1921
1922 /* Disable the receive unit by stopping each queue */
1923 number_of_queues = hw->mac.max_rx_queues;
1924 for (i = 0; i < number_of_queues; i++) {
1925 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1926 if (reg_val & IXGBE_RXDCTL_ENABLE) {
1927 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1928 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1929 }
1930 }
1931
1932 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
1933 reg_val |= IXGBE_CTRL_GIO_DIS;
1934 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
1935
1936 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
1937 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
1938 status = 0;
1939 break;
1940 }
1941 udelay(100);
1942 }
1943
1944 return status;
1945 }
1946
1947
1948 /**
1949 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
1950 * @hw: pointer to hardware structure
1951 * @mask: Mask to specify which semaphore to acquire
1952 *
1953 * Acquires the SWFW semaphore thought the GSSR register for the specified
1954 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1955 **/
1956 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1957 {
1958 u32 gssr;
1959 u32 swmask = mask;
1960 u32 fwmask = mask << 5;
1961 s32 timeout = 200;
1962
1963 while (timeout) {
1964 if (ixgbe_get_eeprom_semaphore(hw))
1965 return -IXGBE_ERR_SWFW_SYNC;
1966
1967 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
1968 if (!(gssr & (fwmask | swmask)))
1969 break;
1970
1971 /*
1972 * Firmware currently using resource (fwmask) or other software
1973 * thread currently using resource (swmask)
1974 */
1975 ixgbe_release_eeprom_semaphore(hw);
1976 msleep(5);
1977 timeout--;
1978 }
1979
1980 if (!timeout) {
1981 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
1982 return -IXGBE_ERR_SWFW_SYNC;
1983 }
1984
1985 gssr |= swmask;
1986 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
1987
1988 ixgbe_release_eeprom_semaphore(hw);
1989 return 0;
1990 }
1991
1992 /**
1993 * ixgbe_release_swfw_sync - Release SWFW semaphore
1994 * @hw: pointer to hardware structure
1995 * @mask: Mask to specify which semaphore to release
1996 *
1997 * Releases the SWFW semaphore thought the GSSR register for the specified
1998 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1999 **/
2000 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2001 {
2002 u32 gssr;
2003 u32 swmask = mask;
2004
2005 ixgbe_get_eeprom_semaphore(hw);
2006
2007 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2008 gssr &= ~swmask;
2009 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2010
2011 ixgbe_release_eeprom_semaphore(hw);
2012 }
2013
2014 /**
2015 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2016 * @hw: pointer to hardware structure
2017 * @regval: register value to write to RXCTRL
2018 *
2019 * Enables the Rx DMA unit
2020 **/
2021 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2022 {
2023 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2024
2025 return 0;
2026 }
2027
2028 /**
2029 * ixgbe_blink_led_start_generic - Blink LED based on index.
2030 * @hw: pointer to hardware structure
2031 * @index: led number to blink
2032 **/
2033 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2034 {
2035 ixgbe_link_speed speed = 0;
2036 bool link_up = 0;
2037 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2038 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2039
2040 /*
2041 * Link must be up to auto-blink the LEDs;
2042 * Force it if link is down.
2043 */
2044 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2045
2046 if (!link_up) {
2047 autoc_reg |= IXGBE_AUTOC_FLU;
2048 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2049 msleep(10);
2050 }
2051
2052 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2053 led_reg |= IXGBE_LED_BLINK(index);
2054 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2055 IXGBE_WRITE_FLUSH(hw);
2056
2057 return 0;
2058 }
2059
2060 /**
2061 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2062 * @hw: pointer to hardware structure
2063 * @index: led number to stop blinking
2064 **/
2065 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2066 {
2067 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2068 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2069
2070 autoc_reg &= ~IXGBE_AUTOC_FLU;
2071 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2072 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2073
2074 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2075 led_reg &= ~IXGBE_LED_BLINK(index);
2076 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2077 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2078 IXGBE_WRITE_FLUSH(hw);
2079
2080 return 0;
2081 }
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