1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31 #include <linux/netdevice.h>
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
37 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
);
38 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
);
39 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
);
40 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
);
41 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
);
42 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
44 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
);
45 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
46 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
47 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
);
49 static void ixgbe_enable_rar(struct ixgbe_hw
*hw
, u32 index
);
50 static void ixgbe_disable_rar(struct ixgbe_hw
*hw
, u32 index
);
51 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
);
52 static void ixgbe_add_uc_addr(struct ixgbe_hw
*hw
, u8
*addr
, u32 vmdq
);
53 static s32
ixgbe_setup_fc(struct ixgbe_hw
*hw
, s32 packetbuf_num
);
56 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
57 * @hw: pointer to hardware structure
59 * Starts the hardware by filling the bus info structure and media type, clears
60 * all on chip counters, initializes receive address registers, multicast
61 * table, VLAN filter table, calls routine to set up link and flow control
62 * settings, and leaves transmit and receive units disabled and uninitialized
64 s32
ixgbe_start_hw_generic(struct ixgbe_hw
*hw
)
68 /* Set the media type */
69 hw
->phy
.media_type
= hw
->mac
.ops
.get_media_type(hw
);
71 /* Identify the PHY */
72 hw
->phy
.ops
.identify(hw
);
74 /* Clear the VLAN filter table */
75 hw
->mac
.ops
.clear_vfta(hw
);
77 /* Clear statistics registers */
78 hw
->mac
.ops
.clear_hw_cntrs(hw
);
80 /* Set No Snoop Disable */
81 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
82 ctrl_ext
|= IXGBE_CTRL_EXT_NS_DIS
;
83 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
84 IXGBE_WRITE_FLUSH(hw
);
86 /* Setup flow control */
87 ixgbe_setup_fc(hw
, 0);
89 /* Clear adapter stopped flag */
90 hw
->adapter_stopped
= false;
96 * ixgbe_init_hw_generic - Generic hardware initialization
97 * @hw: pointer to hardware structure
99 * Initialize the hardware by resetting the hardware, filling the bus info
100 * structure and media type, clears all on chip counters, initializes receive
101 * address registers, multicast table, VLAN filter table, calls routine to set
102 * up link and flow control settings, and leaves transmit and receive units
103 * disabled and uninitialized
105 s32
ixgbe_init_hw_generic(struct ixgbe_hw
*hw
)
109 /* Reset the hardware */
110 status
= hw
->mac
.ops
.reset_hw(hw
);
114 status
= hw
->mac
.ops
.start_hw(hw
);
121 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
122 * @hw: pointer to hardware structure
124 * Clears all hardware statistics counters by reading them from the hardware
125 * Statistics counters are clear on read.
127 s32
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw
*hw
)
131 IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
132 IXGBE_READ_REG(hw
, IXGBE_ILLERRC
);
133 IXGBE_READ_REG(hw
, IXGBE_ERRBC
);
134 IXGBE_READ_REG(hw
, IXGBE_MSPDC
);
135 for (i
= 0; i
< 8; i
++)
136 IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
138 IXGBE_READ_REG(hw
, IXGBE_MLFC
);
139 IXGBE_READ_REG(hw
, IXGBE_MRFC
);
140 IXGBE_READ_REG(hw
, IXGBE_RLEC
);
141 IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
142 IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
143 IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
144 IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
146 for (i
= 0; i
< 8; i
++) {
147 IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
148 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
149 IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
150 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
153 IXGBE_READ_REG(hw
, IXGBE_PRC64
);
154 IXGBE_READ_REG(hw
, IXGBE_PRC127
);
155 IXGBE_READ_REG(hw
, IXGBE_PRC255
);
156 IXGBE_READ_REG(hw
, IXGBE_PRC511
);
157 IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
158 IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
159 IXGBE_READ_REG(hw
, IXGBE_GPRC
);
160 IXGBE_READ_REG(hw
, IXGBE_BPRC
);
161 IXGBE_READ_REG(hw
, IXGBE_MPRC
);
162 IXGBE_READ_REG(hw
, IXGBE_GPTC
);
163 IXGBE_READ_REG(hw
, IXGBE_GORCL
);
164 IXGBE_READ_REG(hw
, IXGBE_GORCH
);
165 IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
166 IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
167 for (i
= 0; i
< 8; i
++)
168 IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
169 IXGBE_READ_REG(hw
, IXGBE_RUC
);
170 IXGBE_READ_REG(hw
, IXGBE_RFC
);
171 IXGBE_READ_REG(hw
, IXGBE_ROC
);
172 IXGBE_READ_REG(hw
, IXGBE_RJC
);
173 IXGBE_READ_REG(hw
, IXGBE_MNGPRC
);
174 IXGBE_READ_REG(hw
, IXGBE_MNGPDC
);
175 IXGBE_READ_REG(hw
, IXGBE_MNGPTC
);
176 IXGBE_READ_REG(hw
, IXGBE_TORL
);
177 IXGBE_READ_REG(hw
, IXGBE_TORH
);
178 IXGBE_READ_REG(hw
, IXGBE_TPR
);
179 IXGBE_READ_REG(hw
, IXGBE_TPT
);
180 IXGBE_READ_REG(hw
, IXGBE_PTC64
);
181 IXGBE_READ_REG(hw
, IXGBE_PTC127
);
182 IXGBE_READ_REG(hw
, IXGBE_PTC255
);
183 IXGBE_READ_REG(hw
, IXGBE_PTC511
);
184 IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
185 IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
186 IXGBE_READ_REG(hw
, IXGBE_MPTC
);
187 IXGBE_READ_REG(hw
, IXGBE_BPTC
);
188 for (i
= 0; i
< 16; i
++) {
189 IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
190 IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
191 IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
192 IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
199 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
200 * @hw: pointer to hardware structure
201 * @pba_num: stores the part number string from the EEPROM
202 * @pba_num_size: part number string buffer length
204 * Reads the part number string from the EEPROM.
206 s32
ixgbe_read_pba_string_generic(struct ixgbe_hw
*hw
, u8
*pba_num
,
215 if (pba_num
== NULL
) {
216 hw_dbg(hw
, "PBA string buffer was null\n");
217 return IXGBE_ERR_INVALID_ARGUMENT
;
220 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM0_PTR
, &data
);
222 hw_dbg(hw
, "NVM Read Error\n");
226 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM1_PTR
, &pba_ptr
);
228 hw_dbg(hw
, "NVM Read Error\n");
233 * if data is not ptr guard the PBA must be in legacy format which
234 * means pba_ptr is actually our second data word for the PBA number
235 * and we can decode it into an ascii string
237 if (data
!= IXGBE_PBANUM_PTR_GUARD
) {
238 hw_dbg(hw
, "NVM PBA number is not stored as string\n");
240 /* we will need 11 characters to store the PBA */
241 if (pba_num_size
< 11) {
242 hw_dbg(hw
, "PBA string buffer too small\n");
243 return IXGBE_ERR_NO_SPACE
;
246 /* extract hex string from data and pba_ptr */
247 pba_num
[0] = (data
>> 12) & 0xF;
248 pba_num
[1] = (data
>> 8) & 0xF;
249 pba_num
[2] = (data
>> 4) & 0xF;
250 pba_num
[3] = data
& 0xF;
251 pba_num
[4] = (pba_ptr
>> 12) & 0xF;
252 pba_num
[5] = (pba_ptr
>> 8) & 0xF;
255 pba_num
[8] = (pba_ptr
>> 4) & 0xF;
256 pba_num
[9] = pba_ptr
& 0xF;
258 /* put a null character on the end of our string */
261 /* switch all the data but the '-' to hex char */
262 for (offset
= 0; offset
< 10; offset
++) {
263 if (pba_num
[offset
] < 0xA)
264 pba_num
[offset
] += '0';
265 else if (pba_num
[offset
] < 0x10)
266 pba_num
[offset
] += 'A' - 0xA;
272 ret_val
= hw
->eeprom
.ops
.read(hw
, pba_ptr
, &length
);
274 hw_dbg(hw
, "NVM Read Error\n");
278 if (length
== 0xFFFF || length
== 0) {
279 hw_dbg(hw
, "NVM PBA number section invalid length\n");
280 return IXGBE_ERR_PBA_SECTION
;
283 /* check if pba_num buffer is big enough */
284 if (pba_num_size
< (((u32
)length
* 2) - 1)) {
285 hw_dbg(hw
, "PBA string buffer too small\n");
286 return IXGBE_ERR_NO_SPACE
;
289 /* trim pba length from start of string */
293 for (offset
= 0; offset
< length
; offset
++) {
294 ret_val
= hw
->eeprom
.ops
.read(hw
, pba_ptr
+ offset
, &data
);
296 hw_dbg(hw
, "NVM Read Error\n");
299 pba_num
[offset
* 2] = (u8
)(data
>> 8);
300 pba_num
[(offset
* 2) + 1] = (u8
)(data
& 0xFF);
302 pba_num
[offset
* 2] = '\0';
308 * ixgbe_get_mac_addr_generic - Generic get MAC address
309 * @hw: pointer to hardware structure
310 * @mac_addr: Adapter MAC address
312 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
313 * A reset of the adapter must be performed prior to calling this function
314 * in order for the MAC address to have been loaded from the EEPROM into RAR0
316 s32
ixgbe_get_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*mac_addr
)
322 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(0));
323 rar_low
= IXGBE_READ_REG(hw
, IXGBE_RAL(0));
325 for (i
= 0; i
< 4; i
++)
326 mac_addr
[i
] = (u8
)(rar_low
>> (i
*8));
328 for (i
= 0; i
< 2; i
++)
329 mac_addr
[i
+4] = (u8
)(rar_high
>> (i
*8));
335 * ixgbe_get_bus_info_generic - Generic set PCI bus info
336 * @hw: pointer to hardware structure
338 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
340 s32
ixgbe_get_bus_info_generic(struct ixgbe_hw
*hw
)
342 struct ixgbe_adapter
*adapter
= hw
->back
;
343 struct ixgbe_mac_info
*mac
= &hw
->mac
;
346 hw
->bus
.type
= ixgbe_bus_type_pci_express
;
348 /* Get the negotiated link width and speed from PCI config space */
349 pci_read_config_word(adapter
->pdev
, IXGBE_PCI_LINK_STATUS
,
352 switch (link_status
& IXGBE_PCI_LINK_WIDTH
) {
353 case IXGBE_PCI_LINK_WIDTH_1
:
354 hw
->bus
.width
= ixgbe_bus_width_pcie_x1
;
356 case IXGBE_PCI_LINK_WIDTH_2
:
357 hw
->bus
.width
= ixgbe_bus_width_pcie_x2
;
359 case IXGBE_PCI_LINK_WIDTH_4
:
360 hw
->bus
.width
= ixgbe_bus_width_pcie_x4
;
362 case IXGBE_PCI_LINK_WIDTH_8
:
363 hw
->bus
.width
= ixgbe_bus_width_pcie_x8
;
366 hw
->bus
.width
= ixgbe_bus_width_unknown
;
370 switch (link_status
& IXGBE_PCI_LINK_SPEED
) {
371 case IXGBE_PCI_LINK_SPEED_2500
:
372 hw
->bus
.speed
= ixgbe_bus_speed_2500
;
374 case IXGBE_PCI_LINK_SPEED_5000
:
375 hw
->bus
.speed
= ixgbe_bus_speed_5000
;
378 hw
->bus
.speed
= ixgbe_bus_speed_unknown
;
382 mac
->ops
.set_lan_id(hw
);
388 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
389 * @hw: pointer to the HW structure
391 * Determines the LAN function id by reading memory-mapped registers
392 * and swaps the port value if requested.
394 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw
*hw
)
396 struct ixgbe_bus_info
*bus
= &hw
->bus
;
399 reg
= IXGBE_READ_REG(hw
, IXGBE_STATUS
);
400 bus
->func
= (reg
& IXGBE_STATUS_LAN_ID
) >> IXGBE_STATUS_LAN_ID_SHIFT
;
401 bus
->lan_id
= bus
->func
;
403 /* check for a port swap */
404 reg
= IXGBE_READ_REG(hw
, IXGBE_FACTPS
);
405 if (reg
& IXGBE_FACTPS_LFS
)
410 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
411 * @hw: pointer to hardware structure
413 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
414 * disables transmit and receive units. The adapter_stopped flag is used by
415 * the shared code and drivers to determine if the adapter is in a stopped
416 * state and should not touch the hardware.
418 s32
ixgbe_stop_adapter_generic(struct ixgbe_hw
*hw
)
420 u32 number_of_queues
;
425 * Set the adapter_stopped flag so other driver functions stop touching
428 hw
->adapter_stopped
= true;
430 /* Disable the receive unit */
431 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
432 reg_val
&= ~(IXGBE_RXCTRL_RXEN
);
433 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, reg_val
);
434 IXGBE_WRITE_FLUSH(hw
);
437 /* Clear interrupt mask to stop from interrupts being generated */
438 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
440 /* Clear any pending interrupts */
441 IXGBE_READ_REG(hw
, IXGBE_EICR
);
443 /* Disable the transmit unit. Each queue must be disabled. */
444 number_of_queues
= hw
->mac
.max_tx_queues
;
445 for (i
= 0; i
< number_of_queues
; i
++) {
446 reg_val
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
447 if (reg_val
& IXGBE_TXDCTL_ENABLE
) {
448 reg_val
&= ~IXGBE_TXDCTL_ENABLE
;
449 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(i
), reg_val
);
454 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
455 * access and verify no pending requests
457 ixgbe_disable_pcie_master(hw
);
463 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
464 * @hw: pointer to hardware structure
465 * @index: led number to turn on
467 s32
ixgbe_led_on_generic(struct ixgbe_hw
*hw
, u32 index
)
469 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
471 /* To turn on the LED, set mode to ON. */
472 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
473 led_reg
|= IXGBE_LED_ON
<< IXGBE_LED_MODE_SHIFT(index
);
474 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
475 IXGBE_WRITE_FLUSH(hw
);
481 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
482 * @hw: pointer to hardware structure
483 * @index: led number to turn off
485 s32
ixgbe_led_off_generic(struct ixgbe_hw
*hw
, u32 index
)
487 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
489 /* To turn off the LED, set mode to OFF. */
490 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
491 led_reg
|= IXGBE_LED_OFF
<< IXGBE_LED_MODE_SHIFT(index
);
492 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
493 IXGBE_WRITE_FLUSH(hw
);
499 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
500 * @hw: pointer to hardware structure
502 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
503 * ixgbe_hw struct in order to set up EEPROM access.
505 s32
ixgbe_init_eeprom_params_generic(struct ixgbe_hw
*hw
)
507 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
511 if (eeprom
->type
== ixgbe_eeprom_uninitialized
) {
512 eeprom
->type
= ixgbe_eeprom_none
;
513 /* Set default semaphore delay to 10ms which is a well
515 eeprom
->semaphore_delay
= 10;
518 * Check for EEPROM present first.
519 * If not present leave as none
521 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
522 if (eec
& IXGBE_EEC_PRES
) {
523 eeprom
->type
= ixgbe_eeprom_spi
;
526 * SPI EEPROM is assumed here. This code would need to
527 * change if a future EEPROM is not SPI.
529 eeprom_size
= (u16
)((eec
& IXGBE_EEC_SIZE
) >>
530 IXGBE_EEC_SIZE_SHIFT
);
531 eeprom
->word_size
= 1 << (eeprom_size
+
532 IXGBE_EEPROM_WORD_SIZE_SHIFT
);
535 if (eec
& IXGBE_EEC_ADDR_SIZE
)
536 eeprom
->address_bits
= 16;
538 eeprom
->address_bits
= 8;
539 hw_dbg(hw
, "Eeprom params: type = %d, size = %d, address bits: "
540 "%d\n", eeprom
->type
, eeprom
->word_size
,
541 eeprom
->address_bits
);
548 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
549 * @hw: pointer to hardware structure
550 * @offset: offset within the EEPROM to be written to
551 * @data: 16 bit word to be written to the EEPROM
553 * If ixgbe_eeprom_update_checksum is not called after this function, the
554 * EEPROM will most likely contain an invalid checksum.
556 s32
ixgbe_write_eeprom_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
559 u8 write_opcode
= IXGBE_EEPROM_WRITE_OPCODE_SPI
;
561 hw
->eeprom
.ops
.init_params(hw
);
563 if (offset
>= hw
->eeprom
.word_size
) {
564 status
= IXGBE_ERR_EEPROM
;
568 /* Prepare the EEPROM for writing */
569 status
= ixgbe_acquire_eeprom(hw
);
572 if (ixgbe_ready_eeprom(hw
) != 0) {
573 ixgbe_release_eeprom(hw
);
574 status
= IXGBE_ERR_EEPROM
;
579 ixgbe_standby_eeprom(hw
);
581 /* Send the WRITE ENABLE command (8 bit opcode ) */
582 ixgbe_shift_out_eeprom_bits(hw
, IXGBE_EEPROM_WREN_OPCODE_SPI
,
583 IXGBE_EEPROM_OPCODE_BITS
);
585 ixgbe_standby_eeprom(hw
);
588 * Some SPI eeproms use the 8th address bit embedded in the
591 if ((hw
->eeprom
.address_bits
== 8) && (offset
>= 128))
592 write_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
594 /* Send the Write command (8-bit opcode + addr) */
595 ixgbe_shift_out_eeprom_bits(hw
, write_opcode
,
596 IXGBE_EEPROM_OPCODE_BITS
);
597 ixgbe_shift_out_eeprom_bits(hw
, (u16
)(offset
*2),
598 hw
->eeprom
.address_bits
);
601 data
= (data
>> 8) | (data
<< 8);
602 ixgbe_shift_out_eeprom_bits(hw
, data
, 16);
603 ixgbe_standby_eeprom(hw
);
605 /* Done with writing - release the EEPROM */
606 ixgbe_release_eeprom(hw
);
614 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
615 * @hw: pointer to hardware structure
616 * @offset: offset within the EEPROM to be read
617 * @data: read 16 bit value from EEPROM
619 * Reads 16 bit value from EEPROM through bit-bang method
621 s32
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
626 u8 read_opcode
= IXGBE_EEPROM_READ_OPCODE_SPI
;
628 hw
->eeprom
.ops
.init_params(hw
);
630 if (offset
>= hw
->eeprom
.word_size
) {
631 status
= IXGBE_ERR_EEPROM
;
635 /* Prepare the EEPROM for reading */
636 status
= ixgbe_acquire_eeprom(hw
);
639 if (ixgbe_ready_eeprom(hw
) != 0) {
640 ixgbe_release_eeprom(hw
);
641 status
= IXGBE_ERR_EEPROM
;
646 ixgbe_standby_eeprom(hw
);
649 * Some SPI eeproms use the 8th address bit embedded in the
652 if ((hw
->eeprom
.address_bits
== 8) && (offset
>= 128))
653 read_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
655 /* Send the READ command (opcode + addr) */
656 ixgbe_shift_out_eeprom_bits(hw
, read_opcode
,
657 IXGBE_EEPROM_OPCODE_BITS
);
658 ixgbe_shift_out_eeprom_bits(hw
, (u16
)(offset
*2),
659 hw
->eeprom
.address_bits
);
662 word_in
= ixgbe_shift_in_eeprom_bits(hw
, 16);
663 *data
= (word_in
>> 8) | (word_in
<< 8);
665 /* End this read operation */
666 ixgbe_release_eeprom(hw
);
674 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
675 * @hw: pointer to hardware structure
676 * @offset: offset of word in the EEPROM to read
677 * @data: word read from the EEPROM
679 * Reads a 16 bit word from the EEPROM using the EERD register.
681 s32
ixgbe_read_eerd_generic(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
)
686 hw
->eeprom
.ops
.init_params(hw
);
688 if (offset
>= hw
->eeprom
.word_size
) {
689 status
= IXGBE_ERR_EEPROM
;
693 eerd
= (offset
<< IXGBE_EEPROM_RW_ADDR_SHIFT
) +
694 IXGBE_EEPROM_RW_REG_START
;
696 IXGBE_WRITE_REG(hw
, IXGBE_EERD
, eerd
);
697 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_READ
);
700 *data
= (IXGBE_READ_REG(hw
, IXGBE_EERD
) >>
701 IXGBE_EEPROM_RW_REG_DATA
);
703 hw_dbg(hw
, "Eeprom read timed out\n");
710 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
711 * @hw: pointer to hardware structure
712 * @ee_reg: EEPROM flag for polling
714 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
715 * read or write is done respectively.
717 s32
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw
*hw
, u32 ee_reg
)
721 s32 status
= IXGBE_ERR_EEPROM
;
723 for (i
= 0; i
< IXGBE_EERD_EEWR_ATTEMPTS
; i
++) {
724 if (ee_reg
== IXGBE_NVM_POLL_READ
)
725 reg
= IXGBE_READ_REG(hw
, IXGBE_EERD
);
727 reg
= IXGBE_READ_REG(hw
, IXGBE_EEWR
);
729 if (reg
& IXGBE_EEPROM_RW_REG_DONE
) {
739 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
740 * @hw: pointer to hardware structure
742 * Prepares EEPROM for access using bit-bang method. This function should
743 * be called before issuing a command to the EEPROM.
745 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
)
751 if (ixgbe_acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) != 0)
752 status
= IXGBE_ERR_SWFW_SYNC
;
755 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
757 /* Request EEPROM Access */
758 eec
|= IXGBE_EEC_REQ
;
759 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
761 for (i
= 0; i
< IXGBE_EEPROM_GRANT_ATTEMPTS
; i
++) {
762 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
763 if (eec
& IXGBE_EEC_GNT
)
768 /* Release if grant not acquired */
769 if (!(eec
& IXGBE_EEC_GNT
)) {
770 eec
&= ~IXGBE_EEC_REQ
;
771 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
772 hw_dbg(hw
, "Could not acquire EEPROM grant\n");
774 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
775 status
= IXGBE_ERR_EEPROM
;
778 /* Setup EEPROM for Read/Write */
780 /* Clear CS and SK */
781 eec
&= ~(IXGBE_EEC_CS
| IXGBE_EEC_SK
);
782 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
783 IXGBE_WRITE_FLUSH(hw
);
791 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
792 * @hw: pointer to hardware structure
794 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
796 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
)
798 s32 status
= IXGBE_ERR_EEPROM
;
803 /* Get SMBI software semaphore between device drivers first */
804 for (i
= 0; i
< timeout
; i
++) {
806 * If the SMBI bit is 0 when we read it, then the bit will be
807 * set and we have the semaphore
809 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
810 if (!(swsm
& IXGBE_SWSM_SMBI
)) {
817 /* Now get the semaphore between SW/FW through the SWESMBI bit */
819 for (i
= 0; i
< timeout
; i
++) {
820 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
822 /* Set the SW EEPROM semaphore bit to request access */
823 swsm
|= IXGBE_SWSM_SWESMBI
;
824 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
827 * If we set the bit successfully then we got the
830 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
831 if (swsm
& IXGBE_SWSM_SWESMBI
)
838 * Release semaphores and return error if SW EEPROM semaphore
839 * was not granted because we don't have access to the EEPROM
842 hw_dbg(hw
, "SWESMBI Software EEPROM semaphore "
844 ixgbe_release_eeprom_semaphore(hw
);
845 status
= IXGBE_ERR_EEPROM
;
848 hw_dbg(hw
, "Software semaphore SMBI between device drivers "
856 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
857 * @hw: pointer to hardware structure
859 * This function clears hardware semaphore bits.
861 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
)
865 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
867 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
868 swsm
&= ~(IXGBE_SWSM_SWESMBI
| IXGBE_SWSM_SMBI
);
869 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
870 IXGBE_WRITE_FLUSH(hw
);
874 * ixgbe_ready_eeprom - Polls for EEPROM ready
875 * @hw: pointer to hardware structure
877 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
)
884 * Read "Status Register" repeatedly until the LSB is cleared. The
885 * EEPROM will signal that the command has been completed by clearing
886 * bit 0 of the internal status register. If it's not cleared within
887 * 5 milliseconds, then error out.
889 for (i
= 0; i
< IXGBE_EEPROM_MAX_RETRY_SPI
; i
+= 5) {
890 ixgbe_shift_out_eeprom_bits(hw
, IXGBE_EEPROM_RDSR_OPCODE_SPI
,
891 IXGBE_EEPROM_OPCODE_BITS
);
892 spi_stat_reg
= (u8
)ixgbe_shift_in_eeprom_bits(hw
, 8);
893 if (!(spi_stat_reg
& IXGBE_EEPROM_STATUS_RDY_SPI
))
897 ixgbe_standby_eeprom(hw
);
901 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
902 * devices (and only 0-5mSec on 5V devices)
904 if (i
>= IXGBE_EEPROM_MAX_RETRY_SPI
) {
905 hw_dbg(hw
, "SPI EEPROM Status error\n");
906 status
= IXGBE_ERR_EEPROM
;
913 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
914 * @hw: pointer to hardware structure
916 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
)
920 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
922 /* Toggle CS to flush commands */
924 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
925 IXGBE_WRITE_FLUSH(hw
);
927 eec
&= ~IXGBE_EEC_CS
;
928 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
929 IXGBE_WRITE_FLUSH(hw
);
934 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
935 * @hw: pointer to hardware structure
936 * @data: data to send to the EEPROM
937 * @count: number of bits to shift out
939 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
946 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
949 * Mask is used to shift "count" bits of "data" out to the EEPROM
950 * one bit at a time. Determine the starting bit based on count
952 mask
= 0x01 << (count
- 1);
954 for (i
= 0; i
< count
; i
++) {
956 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
957 * "1", and then raising and then lowering the clock (the SK
958 * bit controls the clock input to the EEPROM). A "0" is
959 * shifted out to the EEPROM by setting "DI" to "0" and then
960 * raising and then lowering the clock.
965 eec
&= ~IXGBE_EEC_DI
;
967 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
968 IXGBE_WRITE_FLUSH(hw
);
972 ixgbe_raise_eeprom_clk(hw
, &eec
);
973 ixgbe_lower_eeprom_clk(hw
, &eec
);
976 * Shift mask to signify next bit of data to shift in to the
982 /* We leave the "DI" bit set to "0" when we leave this routine. */
983 eec
&= ~IXGBE_EEC_DI
;
984 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
985 IXGBE_WRITE_FLUSH(hw
);
989 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
990 * @hw: pointer to hardware structure
992 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
)
999 * In order to read a register from the EEPROM, we need to shift
1000 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1001 * the clock input to the EEPROM (setting the SK bit), and then reading
1002 * the value of the "DO" bit. During this "shifting in" process the
1003 * "DI" bit should always be clear.
1005 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1007 eec
&= ~(IXGBE_EEC_DO
| IXGBE_EEC_DI
);
1009 for (i
= 0; i
< count
; i
++) {
1011 ixgbe_raise_eeprom_clk(hw
, &eec
);
1013 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1015 eec
&= ~(IXGBE_EEC_DI
);
1016 if (eec
& IXGBE_EEC_DO
)
1019 ixgbe_lower_eeprom_clk(hw
, &eec
);
1026 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1027 * @hw: pointer to hardware structure
1028 * @eec: EEC register's current value
1030 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
1033 * Raise the clock input to the EEPROM
1034 * (setting the SK bit), then delay
1036 *eec
= *eec
| IXGBE_EEC_SK
;
1037 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, *eec
);
1038 IXGBE_WRITE_FLUSH(hw
);
1043 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1044 * @hw: pointer to hardware structure
1045 * @eecd: EECD's current value
1047 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
1050 * Lower the clock input to the EEPROM (clearing the SK bit), then
1053 *eec
= *eec
& ~IXGBE_EEC_SK
;
1054 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, *eec
);
1055 IXGBE_WRITE_FLUSH(hw
);
1060 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1061 * @hw: pointer to hardware structure
1063 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
)
1067 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1069 eec
|= IXGBE_EEC_CS
; /* Pull CS high */
1070 eec
&= ~IXGBE_EEC_SK
; /* Lower SCK */
1072 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1073 IXGBE_WRITE_FLUSH(hw
);
1077 /* Stop requesting EEPROM access */
1078 eec
&= ~IXGBE_EEC_REQ
;
1079 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1081 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
1083 /* Delay before attempt to obtain semaphore again to allow FW access */
1084 msleep(hw
->eeprom
.semaphore_delay
);
1088 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1089 * @hw: pointer to hardware structure
1091 u16
ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
1100 /* Include 0x0-0x3F in the checksum */
1101 for (i
= 0; i
< IXGBE_EEPROM_CHECKSUM
; i
++) {
1102 if (hw
->eeprom
.ops
.read(hw
, i
, &word
) != 0) {
1103 hw_dbg(hw
, "EEPROM read failed\n");
1109 /* Include all data from pointers except for the fw pointer */
1110 for (i
= IXGBE_PCIE_ANALOG_PTR
; i
< IXGBE_FW_PTR
; i
++) {
1111 hw
->eeprom
.ops
.read(hw
, i
, &pointer
);
1113 /* Make sure the pointer seems valid */
1114 if (pointer
!= 0xFFFF && pointer
!= 0) {
1115 hw
->eeprom
.ops
.read(hw
, pointer
, &length
);
1117 if (length
!= 0xFFFF && length
!= 0) {
1118 for (j
= pointer
+1; j
<= pointer
+length
; j
++) {
1119 hw
->eeprom
.ops
.read(hw
, j
, &word
);
1126 checksum
= (u16
)IXGBE_EEPROM_SUM
- checksum
;
1132 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1133 * @hw: pointer to hardware structure
1134 * @checksum_val: calculated checksum
1136 * Performs checksum calculation and validates the EEPROM checksum. If the
1137 * caller does not need checksum_val, the value can be NULL.
1139 s32
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw
*hw
,
1144 u16 read_checksum
= 0;
1147 * Read the first word from the EEPROM. If this times out or fails, do
1148 * not continue or we could be in for a very long wait while every
1151 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1154 checksum
= hw
->eeprom
.ops
.calc_checksum(hw
);
1156 hw
->eeprom
.ops
.read(hw
, IXGBE_EEPROM_CHECKSUM
, &read_checksum
);
1159 * Verify read checksum from EEPROM is the same as
1160 * calculated checksum
1162 if (read_checksum
!= checksum
)
1163 status
= IXGBE_ERR_EEPROM_CHECKSUM
;
1165 /* If the user cares, return the calculated checksum */
1167 *checksum_val
= checksum
;
1169 hw_dbg(hw
, "EEPROM read failed\n");
1176 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1177 * @hw: pointer to hardware structure
1179 s32
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
1185 * Read the first word from the EEPROM. If this times out or fails, do
1186 * not continue or we could be in for a very long wait while every
1189 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1192 checksum
= hw
->eeprom
.ops
.calc_checksum(hw
);
1193 status
= hw
->eeprom
.ops
.write(hw
, IXGBE_EEPROM_CHECKSUM
,
1196 hw_dbg(hw
, "EEPROM read failed\n");
1203 * ixgbe_validate_mac_addr - Validate MAC address
1204 * @mac_addr: pointer to MAC address.
1206 * Tests a MAC address to ensure it is a valid Individual Address
1208 s32
ixgbe_validate_mac_addr(u8
*mac_addr
)
1212 /* Make sure it is not a multicast address */
1213 if (IXGBE_IS_MULTICAST(mac_addr
))
1214 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1215 /* Not a broadcast address */
1216 else if (IXGBE_IS_BROADCAST(mac_addr
))
1217 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1218 /* Reject the zero address */
1219 else if (mac_addr
[0] == 0 && mac_addr
[1] == 0 && mac_addr
[2] == 0 &&
1220 mac_addr
[3] == 0 && mac_addr
[4] == 0 && mac_addr
[5] == 0)
1221 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1227 * ixgbe_set_rar_generic - Set Rx address register
1228 * @hw: pointer to hardware structure
1229 * @index: Receive address register to write
1230 * @addr: Address to put into receive address register
1231 * @vmdq: VMDq "set" or "pool" index
1232 * @enable_addr: set flag that address is active
1234 * Puts an ethernet address into a receive address register.
1236 s32
ixgbe_set_rar_generic(struct ixgbe_hw
*hw
, u32 index
, u8
*addr
, u32 vmdq
,
1239 u32 rar_low
, rar_high
;
1240 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1242 /* Make sure we are using a valid rar index range */
1243 if (index
>= rar_entries
) {
1244 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1245 return IXGBE_ERR_INVALID_ARGUMENT
;
1248 /* setup VMDq pool selection before this RAR gets enabled */
1249 hw
->mac
.ops
.set_vmdq(hw
, index
, vmdq
);
1252 * HW expects these in little endian so we reverse the byte
1253 * order from network order (big endian) to little endian
1255 rar_low
= ((u32
)addr
[0] |
1256 ((u32
)addr
[1] << 8) |
1257 ((u32
)addr
[2] << 16) |
1258 ((u32
)addr
[3] << 24));
1260 * Some parts put the VMDq setting in the extra RAH bits,
1261 * so save everything except the lower 16 bits that hold part
1262 * of the address and the address valid bit.
1264 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1265 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1266 rar_high
|= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1268 if (enable_addr
!= 0)
1269 rar_high
|= IXGBE_RAH_AV
;
1271 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), rar_low
);
1272 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1278 * ixgbe_clear_rar_generic - Remove Rx address register
1279 * @hw: pointer to hardware structure
1280 * @index: Receive address register to write
1282 * Clears an ethernet address from a receive address register.
1284 s32
ixgbe_clear_rar_generic(struct ixgbe_hw
*hw
, u32 index
)
1287 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1289 /* Make sure we are using a valid rar index range */
1290 if (index
>= rar_entries
) {
1291 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1292 return IXGBE_ERR_INVALID_ARGUMENT
;
1296 * Some parts put the VMDq setting in the extra RAH bits,
1297 * so save everything except the lower 16 bits that hold part
1298 * of the address and the address valid bit.
1300 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1301 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1303 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), 0);
1304 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1306 /* clear VMDq pool/queue selection for this RAR */
1307 hw
->mac
.ops
.clear_vmdq(hw
, index
, IXGBE_CLEAR_VMDQ_ALL
);
1313 * ixgbe_enable_rar - Enable Rx address register
1314 * @hw: pointer to hardware structure
1315 * @index: index into the RAR table
1317 * Enables the select receive address register.
1319 static void ixgbe_enable_rar(struct ixgbe_hw
*hw
, u32 index
)
1323 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1324 rar_high
|= IXGBE_RAH_AV
;
1325 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1329 * ixgbe_disable_rar - Disable Rx address register
1330 * @hw: pointer to hardware structure
1331 * @index: index into the RAR table
1333 * Disables the select receive address register.
1335 static void ixgbe_disable_rar(struct ixgbe_hw
*hw
, u32 index
)
1339 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1340 rar_high
&= (~IXGBE_RAH_AV
);
1341 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1345 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1346 * @hw: pointer to hardware structure
1348 * Places the MAC address in receive address register 0 and clears the rest
1349 * of the receive address registers. Clears the multicast table. Assumes
1350 * the receiver is in reset when the routine is called.
1352 s32
ixgbe_init_rx_addrs_generic(struct ixgbe_hw
*hw
)
1355 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1358 * If the current mac address is valid, assume it is a software override
1359 * to the permanent address.
1360 * Otherwise, use the permanent address from the eeprom.
1362 if (ixgbe_validate_mac_addr(hw
->mac
.addr
) ==
1363 IXGBE_ERR_INVALID_MAC_ADDR
) {
1364 /* Get the MAC address from the RAR0 for later reference */
1365 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.addr
);
1367 hw_dbg(hw
, " Keeping Current RAR0 Addr =%pM\n", hw
->mac
.addr
);
1369 /* Setup the receive address. */
1370 hw_dbg(hw
, "Overriding MAC Address in RAR[0]\n");
1371 hw_dbg(hw
, " New MAC Addr =%pM\n", hw
->mac
.addr
);
1373 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
1375 /* clear VMDq pool/queue selection for RAR 0 */
1376 hw
->mac
.ops
.clear_vmdq(hw
, 0, IXGBE_CLEAR_VMDQ_ALL
);
1378 hw
->addr_ctrl
.overflow_promisc
= 0;
1380 hw
->addr_ctrl
.rar_used_count
= 1;
1382 /* Zero out the other receive addresses. */
1383 hw_dbg(hw
, "Clearing RAR[1-%d]\n", rar_entries
- 1);
1384 for (i
= 1; i
< rar_entries
; i
++) {
1385 IXGBE_WRITE_REG(hw
, IXGBE_RAL(i
), 0);
1386 IXGBE_WRITE_REG(hw
, IXGBE_RAH(i
), 0);
1390 hw
->addr_ctrl
.mc_addr_in_rar_count
= 0;
1391 hw
->addr_ctrl
.mta_in_use
= 0;
1392 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
1394 hw_dbg(hw
, " Clearing MTA\n");
1395 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
1396 IXGBE_WRITE_REG(hw
, IXGBE_MTA(i
), 0);
1398 if (hw
->mac
.ops
.init_uta_tables
)
1399 hw
->mac
.ops
.init_uta_tables(hw
);
1405 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1406 * @hw: pointer to hardware structure
1407 * @addr: new address
1409 * Adds it to unused receive address register or goes into promiscuous mode.
1411 static void ixgbe_add_uc_addr(struct ixgbe_hw
*hw
, u8
*addr
, u32 vmdq
)
1413 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1416 hw_dbg(hw
, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1417 addr
[0], addr
[1], addr
[2], addr
[3], addr
[4], addr
[5]);
1420 * Place this address in the RAR if there is room,
1421 * else put the controller into promiscuous mode
1423 if (hw
->addr_ctrl
.rar_used_count
< rar_entries
) {
1424 rar
= hw
->addr_ctrl
.rar_used_count
-
1425 hw
->addr_ctrl
.mc_addr_in_rar_count
;
1426 hw
->mac
.ops
.set_rar(hw
, rar
, addr
, vmdq
, IXGBE_RAH_AV
);
1427 hw_dbg(hw
, "Added a secondary address to RAR[%d]\n", rar
);
1428 hw
->addr_ctrl
.rar_used_count
++;
1430 hw
->addr_ctrl
.overflow_promisc
++;
1433 hw_dbg(hw
, "ixgbe_add_uc_addr Complete\n");
1437 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
1438 * @hw: pointer to hardware structure
1439 * @netdev: pointer to net device structure
1441 * The given list replaces any existing list. Clears the secondary addrs from
1442 * receive address registers. Uses unused receive address registers for the
1443 * first secondary addresses, and falls back to promiscuous mode as needed.
1445 * Drivers using secondary unicast addresses must set user_set_promisc when
1446 * manually putting the device into promiscuous mode.
1448 s32
ixgbe_update_uc_addr_list_generic(struct ixgbe_hw
*hw
,
1449 struct net_device
*netdev
)
1452 u32 old_promisc_setting
= hw
->addr_ctrl
.overflow_promisc
;
1455 struct netdev_hw_addr
*ha
;
1458 * Clear accounting of old secondary address list,
1459 * don't count RAR[0]
1461 uc_addr_in_use
= hw
->addr_ctrl
.rar_used_count
- 1;
1462 hw
->addr_ctrl
.rar_used_count
-= uc_addr_in_use
;
1463 hw
->addr_ctrl
.overflow_promisc
= 0;
1465 /* Zero out the other receive addresses */
1466 hw_dbg(hw
, "Clearing RAR[1-%d]\n", uc_addr_in_use
+ 1);
1467 for (i
= 0; i
< uc_addr_in_use
; i
++) {
1468 IXGBE_WRITE_REG(hw
, IXGBE_RAL(1+i
), 0);
1469 IXGBE_WRITE_REG(hw
, IXGBE_RAH(1+i
), 0);
1472 /* Add the new addresses */
1473 netdev_for_each_uc_addr(ha
, netdev
) {
1474 hw_dbg(hw
, " Adding the secondary addresses:\n");
1475 ixgbe_add_uc_addr(hw
, ha
->addr
, 0);
1478 if (hw
->addr_ctrl
.overflow_promisc
) {
1479 /* enable promisc if not already in overflow or set by user */
1480 if (!old_promisc_setting
&& !hw
->addr_ctrl
.user_set_promisc
) {
1481 hw_dbg(hw
, " Entering address overflow promisc mode\n");
1482 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
1483 fctrl
|= IXGBE_FCTRL_UPE
;
1484 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
1485 hw
->addr_ctrl
.uc_set_promisc
= true;
1488 /* only disable if set by overflow, not by user */
1489 if ((old_promisc_setting
&& hw
->addr_ctrl
.uc_set_promisc
) &&
1490 !(hw
->addr_ctrl
.user_set_promisc
)) {
1491 hw_dbg(hw
, " Leaving address overflow promisc mode\n");
1492 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
1493 fctrl
&= ~IXGBE_FCTRL_UPE
;
1494 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
1495 hw
->addr_ctrl
.uc_set_promisc
= false;
1499 hw_dbg(hw
, "ixgbe_update_uc_addr_list_generic Complete\n");
1504 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1505 * @hw: pointer to hardware structure
1506 * @mc_addr: the multicast address
1508 * Extracts the 12 bits, from a multicast address, to determine which
1509 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1510 * incoming rx multicast addresses, to determine the bit-vector to check in
1511 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1512 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1513 * to mc_filter_type.
1515 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1519 switch (hw
->mac
.mc_filter_type
) {
1520 case 0: /* use bits [47:36] of the address */
1521 vector
= ((mc_addr
[4] >> 4) | (((u16
)mc_addr
[5]) << 4));
1523 case 1: /* use bits [46:35] of the address */
1524 vector
= ((mc_addr
[4] >> 3) | (((u16
)mc_addr
[5]) << 5));
1526 case 2: /* use bits [45:34] of the address */
1527 vector
= ((mc_addr
[4] >> 2) | (((u16
)mc_addr
[5]) << 6));
1529 case 3: /* use bits [43:32] of the address */
1530 vector
= ((mc_addr
[4]) | (((u16
)mc_addr
[5]) << 8));
1532 default: /* Invalid mc_filter_type */
1533 hw_dbg(hw
, "MC filter type param set incorrectly\n");
1537 /* vector can only be 12-bits or boundary will be exceeded */
1543 * ixgbe_set_mta - Set bit-vector in multicast table
1544 * @hw: pointer to hardware structure
1545 * @hash_value: Multicast address hash value
1547 * Sets the bit-vector in the multicast table.
1549 static void ixgbe_set_mta(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1556 hw
->addr_ctrl
.mta_in_use
++;
1558 vector
= ixgbe_mta_vector(hw
, mc_addr
);
1559 hw_dbg(hw
, " bit-vector = 0x%03X\n", vector
);
1562 * The MTA is a register array of 128 32-bit registers. It is treated
1563 * like an array of 4096 bits. We want to set bit
1564 * BitArray[vector_value]. So we figure out what register the bit is
1565 * in, read it, OR in the new bit, then write back the new value. The
1566 * register is determined by the upper 7 bits of the vector value and
1567 * the bit within that register are determined by the lower 5 bits of
1570 vector_reg
= (vector
>> 5) & 0x7F;
1571 vector_bit
= vector
& 0x1F;
1572 mta_reg
= IXGBE_READ_REG(hw
, IXGBE_MTA(vector_reg
));
1573 mta_reg
|= (1 << vector_bit
);
1574 IXGBE_WRITE_REG(hw
, IXGBE_MTA(vector_reg
), mta_reg
);
1578 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1579 * @hw: pointer to hardware structure
1580 * @netdev: pointer to net device structure
1582 * The given list replaces any existing list. Clears the MC addrs from receive
1583 * address registers and the multicast table. Uses unused receive address
1584 * registers for the first multicast addresses, and hashes the rest into the
1587 s32
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw
*hw
,
1588 struct net_device
*netdev
)
1590 struct netdev_hw_addr
*ha
;
1594 * Set the new number of MC addresses that we are being requested to
1597 hw
->addr_ctrl
.num_mc_addrs
= netdev_mc_count(netdev
);
1598 hw
->addr_ctrl
.mta_in_use
= 0;
1601 hw_dbg(hw
, " Clearing MTA\n");
1602 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
1603 IXGBE_WRITE_REG(hw
, IXGBE_MTA(i
), 0);
1605 /* Add the new addresses */
1606 netdev_for_each_mc_addr(ha
, netdev
) {
1607 hw_dbg(hw
, " Adding the multicast addresses:\n");
1608 ixgbe_set_mta(hw
, ha
->addr
);
1612 if (hw
->addr_ctrl
.mta_in_use
> 0)
1613 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
,
1614 IXGBE_MCSTCTRL_MFE
| hw
->mac
.mc_filter_type
);
1616 hw_dbg(hw
, "ixgbe_update_mc_addr_list_generic Complete\n");
1621 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1622 * @hw: pointer to hardware structure
1624 * Enables multicast address in RAR and the use of the multicast hash table.
1626 s32
ixgbe_enable_mc_generic(struct ixgbe_hw
*hw
)
1629 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1630 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
1632 if (a
->mc_addr_in_rar_count
> 0)
1633 for (i
= (rar_entries
- a
->mc_addr_in_rar_count
);
1634 i
< rar_entries
; i
++)
1635 ixgbe_enable_rar(hw
, i
);
1637 if (a
->mta_in_use
> 0)
1638 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, IXGBE_MCSTCTRL_MFE
|
1639 hw
->mac
.mc_filter_type
);
1645 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1646 * @hw: pointer to hardware structure
1648 * Disables multicast address in RAR and the use of the multicast hash table.
1650 s32
ixgbe_disable_mc_generic(struct ixgbe_hw
*hw
)
1653 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1654 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
1656 if (a
->mc_addr_in_rar_count
> 0)
1657 for (i
= (rar_entries
- a
->mc_addr_in_rar_count
);
1658 i
< rar_entries
; i
++)
1659 ixgbe_disable_rar(hw
, i
);
1661 if (a
->mta_in_use
> 0)
1662 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
1668 * ixgbe_fc_enable_generic - Enable flow control
1669 * @hw: pointer to hardware structure
1670 * @packetbuf_num: packet buffer number (0-7)
1672 * Enable flow control according to the current settings.
1674 s32
ixgbe_fc_enable_generic(struct ixgbe_hw
*hw
, s32 packetbuf_num
)
1677 u32 mflcn_reg
, fccfg_reg
;
1683 if (hw
->fc
.requested_mode
== ixgbe_fc_pfc
)
1686 #endif /* CONFIG_DCB */
1687 /* Negotiate the fc mode to use */
1688 ret_val
= ixgbe_fc_autoneg(hw
);
1692 /* Disable any previous flow control settings */
1693 mflcn_reg
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
1694 mflcn_reg
&= ~(IXGBE_MFLCN_RFCE
| IXGBE_MFLCN_RPFCE
);
1696 fccfg_reg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
1697 fccfg_reg
&= ~(IXGBE_FCCFG_TFCE_802_3X
| IXGBE_FCCFG_TFCE_PRIORITY
);
1700 * The possible values of fc.current_mode are:
1701 * 0: Flow control is completely disabled
1702 * 1: Rx flow control is enabled (we can receive pause frames,
1703 * but not send pause frames).
1704 * 2: Tx flow control is enabled (we can send pause frames but
1705 * we do not support receiving pause frames).
1706 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1707 * 4: Priority Flow Control is enabled.
1710 switch (hw
->fc
.current_mode
) {
1713 * Flow control is disabled by software override or autoneg.
1714 * The code below will actually disable it in the HW.
1717 case ixgbe_fc_rx_pause
:
1719 * Rx Flow control is enabled and Tx Flow control is
1720 * disabled by software override. Since there really
1721 * isn't a way to advertise that we are capable of RX
1722 * Pause ONLY, we will advertise that we support both
1723 * symmetric and asymmetric Rx PAUSE. Later, we will
1724 * disable the adapter's ability to send PAUSE frames.
1726 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
1728 case ixgbe_fc_tx_pause
:
1730 * Tx Flow control is enabled, and Rx Flow control is
1731 * disabled by software override.
1733 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
1736 /* Flow control (both Rx and Tx) is enabled by SW override. */
1737 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
1738 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
1744 #endif /* CONFIG_DCB */
1746 hw_dbg(hw
, "Flow control param set incorrectly\n");
1747 ret_val
= IXGBE_ERR_CONFIG
;
1752 /* Set 802.3x based flow control settings. */
1753 mflcn_reg
|= IXGBE_MFLCN_DPF
;
1754 IXGBE_WRITE_REG(hw
, IXGBE_MFLCN
, mflcn_reg
);
1755 IXGBE_WRITE_REG(hw
, IXGBE_FCCFG
, fccfg_reg
);
1757 rx_pba_size
= IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(packetbuf_num
));
1758 rx_pba_size
>>= IXGBE_RXPBSIZE_SHIFT
;
1760 fcrth
= (rx_pba_size
- hw
->fc
.high_water
) << 10;
1761 fcrtl
= (rx_pba_size
- hw
->fc
.low_water
) << 10;
1763 if (hw
->fc
.current_mode
& ixgbe_fc_tx_pause
) {
1764 fcrth
|= IXGBE_FCRTH_FCEN
;
1765 if (hw
->fc
.send_xon
)
1766 fcrtl
|= IXGBE_FCRTL_XONE
;
1769 IXGBE_WRITE_REG(hw
, IXGBE_FCRTH_82599(packetbuf_num
), fcrth
);
1770 IXGBE_WRITE_REG(hw
, IXGBE_FCRTL_82599(packetbuf_num
), fcrtl
);
1772 /* Configure pause time (2 TCs per register) */
1773 reg
= IXGBE_READ_REG(hw
, IXGBE_FCTTV(packetbuf_num
/ 2));
1774 if ((packetbuf_num
& 1) == 0)
1775 reg
= (reg
& 0xFFFF0000) | hw
->fc
.pause_time
;
1777 reg
= (reg
& 0x0000FFFF) | (hw
->fc
.pause_time
<< 16);
1778 IXGBE_WRITE_REG(hw
, IXGBE_FCTTV(packetbuf_num
/ 2), reg
);
1780 IXGBE_WRITE_REG(hw
, IXGBE_FCRTV
, (hw
->fc
.pause_time
>> 1));
1787 * ixgbe_fc_autoneg - Configure flow control
1788 * @hw: pointer to hardware structure
1790 * Compares our advertised flow control capabilities to those advertised by
1791 * our link partner, and determines the proper flow control mode to use.
1793 s32
ixgbe_fc_autoneg(struct ixgbe_hw
*hw
)
1796 ixgbe_link_speed speed
;
1797 u32 pcs_anadv_reg
, pcs_lpab_reg
, linkstat
;
1798 u32 links2
, anlp1_reg
, autoc_reg
, links
;
1802 * AN should have completed when the cable was plugged in.
1803 * Look for reasons to bail out. Bail out if:
1804 * - FC autoneg is disabled, or if
1807 * Since we're being called from an LSC, link is already known to be up.
1808 * So use link_up_wait_to_complete=false.
1810 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
1812 if (hw
->fc
.disable_fc_autoneg
|| (!link_up
)) {
1813 hw
->fc
.fc_was_autonegged
= false;
1814 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1819 * On backplane, bail out if
1820 * - backplane autoneg was not completed, or if
1821 * - we are 82599 and link partner is not AN enabled
1823 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
1824 links
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
1825 if ((links
& IXGBE_LINKS_KX_AN_COMP
) == 0) {
1826 hw
->fc
.fc_was_autonegged
= false;
1827 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1831 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1832 links2
= IXGBE_READ_REG(hw
, IXGBE_LINKS2
);
1833 if ((links2
& IXGBE_LINKS2_AN_SUPPORTED
) == 0) {
1834 hw
->fc
.fc_was_autonegged
= false;
1835 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1842 * On multispeed fiber at 1g, bail out if
1843 * - link is up but AN did not complete, or if
1844 * - link is up and AN completed but timed out
1846 if (hw
->phy
.multispeed_fiber
&& (speed
== IXGBE_LINK_SPEED_1GB_FULL
)) {
1847 linkstat
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLSTA
);
1848 if (((linkstat
& IXGBE_PCS1GLSTA_AN_COMPLETE
) == 0) ||
1849 ((linkstat
& IXGBE_PCS1GLSTA_AN_TIMED_OUT
) == 1)) {
1850 hw
->fc
.fc_was_autonegged
= false;
1851 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1858 * - copper or CX4 adapters
1859 * - fiber adapters running at 10gig
1861 if ((hw
->phy
.media_type
== ixgbe_media_type_copper
) ||
1862 (hw
->phy
.media_type
== ixgbe_media_type_cx4
) ||
1863 ((hw
->phy
.media_type
== ixgbe_media_type_fiber
) &&
1864 (speed
== IXGBE_LINK_SPEED_10GB_FULL
))) {
1865 hw
->fc
.fc_was_autonegged
= false;
1866 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1871 * Read the AN advertisement and LP ability registers and resolve
1872 * local flow control settings accordingly
1874 if ((speed
== IXGBE_LINK_SPEED_1GB_FULL
) &&
1875 (hw
->phy
.media_type
!= ixgbe_media_type_backplane
)) {
1876 pcs_anadv_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
1877 pcs_lpab_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANLP
);
1878 if ((pcs_anadv_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1879 (pcs_lpab_reg
& IXGBE_PCS1GANA_SYM_PAUSE
)) {
1881 * Now we need to check if the user selected Rx ONLY
1882 * of pause frames. In this case, we had to advertise
1883 * FULL flow control because we could not advertise RX
1884 * ONLY. Hence, we must now check to see if we need to
1885 * turn OFF the TRANSMISSION of PAUSE frames.
1887 if (hw
->fc
.requested_mode
== ixgbe_fc_full
) {
1888 hw
->fc
.current_mode
= ixgbe_fc_full
;
1889 hw_dbg(hw
, "Flow Control = FULL.\n");
1891 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1892 hw_dbg(hw
, "Flow Control=RX PAUSE only\n");
1894 } else if (!(pcs_anadv_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1895 (pcs_anadv_reg
& IXGBE_PCS1GANA_ASM_PAUSE
) &&
1896 (pcs_lpab_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1897 (pcs_lpab_reg
& IXGBE_PCS1GANA_ASM_PAUSE
)) {
1898 hw
->fc
.current_mode
= ixgbe_fc_tx_pause
;
1899 hw_dbg(hw
, "Flow Control = TX PAUSE frames only.\n");
1900 } else if ((pcs_anadv_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1901 (pcs_anadv_reg
& IXGBE_PCS1GANA_ASM_PAUSE
) &&
1902 !(pcs_lpab_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1903 (pcs_lpab_reg
& IXGBE_PCS1GANA_ASM_PAUSE
)) {
1904 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1905 hw_dbg(hw
, "Flow Control = RX PAUSE frames only.\n");
1907 hw
->fc
.current_mode
= ixgbe_fc_none
;
1908 hw_dbg(hw
, "Flow Control = NONE.\n");
1912 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
1914 * Read the 10g AN autoc and LP ability registers and resolve
1915 * local flow control settings accordingly
1917 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
1918 anlp1_reg
= IXGBE_READ_REG(hw
, IXGBE_ANLP1
);
1920 if ((autoc_reg
& IXGBE_AUTOC_SYM_PAUSE
) &&
1921 (anlp1_reg
& IXGBE_ANLP1_SYM_PAUSE
)) {
1923 * Now we need to check if the user selected Rx ONLY
1924 * of pause frames. In this case, we had to advertise
1925 * FULL flow control because we could not advertise RX
1926 * ONLY. Hence, we must now check to see if we need to
1927 * turn OFF the TRANSMISSION of PAUSE frames.
1929 if (hw
->fc
.requested_mode
== ixgbe_fc_full
) {
1930 hw
->fc
.current_mode
= ixgbe_fc_full
;
1931 hw_dbg(hw
, "Flow Control = FULL.\n");
1933 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1934 hw_dbg(hw
, "Flow Control=RX PAUSE only\n");
1936 } else if (!(autoc_reg
& IXGBE_AUTOC_SYM_PAUSE
) &&
1937 (autoc_reg
& IXGBE_AUTOC_ASM_PAUSE
) &&
1938 (anlp1_reg
& IXGBE_ANLP1_SYM_PAUSE
) &&
1939 (anlp1_reg
& IXGBE_ANLP1_ASM_PAUSE
)) {
1940 hw
->fc
.current_mode
= ixgbe_fc_tx_pause
;
1941 hw_dbg(hw
, "Flow Control = TX PAUSE frames only.\n");
1942 } else if ((autoc_reg
& IXGBE_AUTOC_SYM_PAUSE
) &&
1943 (autoc_reg
& IXGBE_AUTOC_ASM_PAUSE
) &&
1944 !(anlp1_reg
& IXGBE_ANLP1_SYM_PAUSE
) &&
1945 (anlp1_reg
& IXGBE_ANLP1_ASM_PAUSE
)) {
1946 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1947 hw_dbg(hw
, "Flow Control = RX PAUSE frames only.\n");
1949 hw
->fc
.current_mode
= ixgbe_fc_none
;
1950 hw_dbg(hw
, "Flow Control = NONE.\n");
1953 /* Record that current_mode is the result of a successful autoneg */
1954 hw
->fc
.fc_was_autonegged
= true;
1961 * ixgbe_setup_fc - Set up flow control
1962 * @hw: pointer to hardware structure
1964 * Called at init time to set up flow control.
1966 static s32
ixgbe_setup_fc(struct ixgbe_hw
*hw
, s32 packetbuf_num
)
1972 if (hw
->fc
.requested_mode
== ixgbe_fc_pfc
) {
1973 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1978 /* Validate the packetbuf configuration */
1979 if (packetbuf_num
< 0 || packetbuf_num
> 7) {
1980 hw_dbg(hw
, "Invalid packet buffer number [%d], expected range "
1981 "is 0-7\n", packetbuf_num
);
1982 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
1987 * Validate the water mark configuration. Zero water marks are invalid
1988 * because it causes the controller to just blast out fc packets.
1990 if (!hw
->fc
.low_water
|| !hw
->fc
.high_water
|| !hw
->fc
.pause_time
) {
1991 hw_dbg(hw
, "Invalid water mark configuration\n");
1992 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
1997 * Validate the requested mode. Strict IEEE mode does not allow
1998 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
2000 if (hw
->fc
.strict_ieee
&& hw
->fc
.requested_mode
== ixgbe_fc_rx_pause
) {
2001 hw_dbg(hw
, "ixgbe_fc_rx_pause not valid in strict "
2003 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
2008 * 10gig parts do not have a word in the EEPROM to determine the
2009 * default flow control setting, so we explicitly set it to full.
2011 if (hw
->fc
.requested_mode
== ixgbe_fc_default
)
2012 hw
->fc
.requested_mode
= ixgbe_fc_full
;
2015 * Set up the 1G flow control advertisement registers so the HW will be
2016 * able to do fc autoneg once the cable is plugged in. If we end up
2017 * using 10g instead, this is harmless.
2019 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
2022 * The possible values of fc.requested_mode are:
2023 * 0: Flow control is completely disabled
2024 * 1: Rx flow control is enabled (we can receive pause frames,
2025 * but not send pause frames).
2026 * 2: Tx flow control is enabled (we can send pause frames but
2027 * we do not support receiving pause frames).
2028 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2030 * 4: Priority Flow Control is enabled.
2034 switch (hw
->fc
.requested_mode
) {
2036 /* Flow control completely disabled by software override. */
2037 reg
&= ~(IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
2039 case ixgbe_fc_rx_pause
:
2041 * Rx Flow control is enabled and Tx Flow control is
2042 * disabled by software override. Since there really
2043 * isn't a way to advertise that we are capable of RX
2044 * Pause ONLY, we will advertise that we support both
2045 * symmetric and asymmetric Rx PAUSE. Later, we will
2046 * disable the adapter's ability to send PAUSE frames.
2048 reg
|= (IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
2050 case ixgbe_fc_tx_pause
:
2052 * Tx Flow control is enabled, and Rx Flow control is
2053 * disabled by software override.
2055 reg
|= (IXGBE_PCS1GANA_ASM_PAUSE
);
2056 reg
&= ~(IXGBE_PCS1GANA_SYM_PAUSE
);
2059 /* Flow control (both Rx and Tx) is enabled by SW override. */
2060 reg
|= (IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
2066 #endif /* CONFIG_DCB */
2068 hw_dbg(hw
, "Flow control param set incorrectly\n");
2069 ret_val
= IXGBE_ERR_CONFIG
;
2074 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GANA
, reg
);
2075 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLCTL
);
2077 /* Disable AN timeout */
2078 if (hw
->fc
.strict_ieee
)
2079 reg
&= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN
;
2081 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GLCTL
, reg
);
2082 hw_dbg(hw
, "Set up FC; PCS1GLCTL = 0x%08X\n", reg
);
2085 * Set up the 10G flow control advertisement registers so the HW
2086 * can do fc autoneg once the cable is plugged in. If we end up
2087 * using 1g instead, this is harmless.
2089 reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2092 * The possible values of fc.requested_mode are:
2093 * 0: Flow control is completely disabled
2094 * 1: Rx flow control is enabled (we can receive pause frames,
2095 * but not send pause frames).
2096 * 2: Tx flow control is enabled (we can send pause frames but
2097 * we do not support receiving pause frames).
2098 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2101 switch (hw
->fc
.requested_mode
) {
2103 /* Flow control completely disabled by software override. */
2104 reg
&= ~(IXGBE_AUTOC_SYM_PAUSE
| IXGBE_AUTOC_ASM_PAUSE
);
2106 case ixgbe_fc_rx_pause
:
2108 * Rx Flow control is enabled and Tx Flow control is
2109 * disabled by software override. Since there really
2110 * isn't a way to advertise that we are capable of RX
2111 * Pause ONLY, we will advertise that we support both
2112 * symmetric and asymmetric Rx PAUSE. Later, we will
2113 * disable the adapter's ability to send PAUSE frames.
2115 reg
|= (IXGBE_AUTOC_SYM_PAUSE
| IXGBE_AUTOC_ASM_PAUSE
);
2117 case ixgbe_fc_tx_pause
:
2119 * Tx Flow control is enabled, and Rx Flow control is
2120 * disabled by software override.
2122 reg
|= (IXGBE_AUTOC_ASM_PAUSE
);
2123 reg
&= ~(IXGBE_AUTOC_SYM_PAUSE
);
2126 /* Flow control (both Rx and Tx) is enabled by SW override. */
2127 reg
|= (IXGBE_AUTOC_SYM_PAUSE
| IXGBE_AUTOC_ASM_PAUSE
);
2133 #endif /* CONFIG_DCB */
2135 hw_dbg(hw
, "Flow control param set incorrectly\n");
2136 ret_val
= IXGBE_ERR_CONFIG
;
2141 * AUTOC restart handles negotiation of 1G and 10G. There is
2142 * no need to set the PCS1GCTL register.
2144 reg
|= IXGBE_AUTOC_AN_RESTART
;
2145 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, reg
);
2146 hw_dbg(hw
, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg
);
2153 * ixgbe_disable_pcie_master - Disable PCI-express master access
2154 * @hw: pointer to hardware structure
2156 * Disables PCI-Express master access and verifies there are no pending
2157 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2158 * bit hasn't caused the master requests to be disabled, else 0
2159 * is returned signifying master requests disabled.
2161 s32
ixgbe_disable_pcie_master(struct ixgbe_hw
*hw
)
2163 struct ixgbe_adapter
*adapter
= hw
->back
;
2166 u32 number_of_queues
;
2170 /* Just jump out if bus mastering is already disabled */
2171 if (!(IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_GIO
))
2174 /* Disable the receive unit by stopping each queue */
2175 number_of_queues
= hw
->mac
.max_rx_queues
;
2176 for (i
= 0; i
< number_of_queues
; i
++) {
2177 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
2178 if (reg_val
& IXGBE_RXDCTL_ENABLE
) {
2179 reg_val
&= ~IXGBE_RXDCTL_ENABLE
;
2180 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(i
), reg_val
);
2184 reg_val
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
2185 reg_val
|= IXGBE_CTRL_GIO_DIS
;
2186 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, reg_val
);
2188 for (i
= 0; i
< IXGBE_PCI_MASTER_DISABLE_TIMEOUT
; i
++) {
2189 if (!(IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_GIO
))
2190 goto check_device_status
;
2194 hw_dbg(hw
, "GIO Master Disable bit didn't clear - requesting resets\n");
2195 status
= IXGBE_ERR_MASTER_REQUESTS_PENDING
;
2198 * Before proceeding, make sure that the PCIe block does not have
2199 * transactions pending.
2201 check_device_status
:
2202 for (i
= 0; i
< IXGBE_PCI_MASTER_DISABLE_TIMEOUT
; i
++) {
2203 pci_read_config_word(adapter
->pdev
, IXGBE_PCI_DEVICE_STATUS
,
2205 if (!(dev_status
& IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING
))
2210 if (i
== IXGBE_PCI_MASTER_DISABLE_TIMEOUT
)
2211 hw_dbg(hw
, "PCIe transaction pending bit also did not clear.\n");
2216 * Two consecutive resets are required via CTRL.RST per datasheet
2217 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2218 * of this need. The first reset prevents new master requests from
2219 * being issued by our device. We then must wait 1usec for any
2220 * remaining completions from the PCIe bus to trickle in, and then reset
2221 * again to clear out any effects they may have had on our device.
2223 hw
->mac
.flags
|= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
2231 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2232 * @hw: pointer to hardware structure
2233 * @mask: Mask to specify which semaphore to acquire
2235 * Acquires the SWFW semaphore thought the GSSR register for the specified
2236 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2238 s32
ixgbe_acquire_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
)
2242 u32 fwmask
= mask
<< 5;
2247 * SW EEPROM semaphore bit is used for access to all
2248 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2250 if (ixgbe_get_eeprom_semaphore(hw
))
2251 return IXGBE_ERR_SWFW_SYNC
;
2253 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2254 if (!(gssr
& (fwmask
| swmask
)))
2258 * Firmware currently using resource (fwmask) or other software
2259 * thread currently using resource (swmask)
2261 ixgbe_release_eeprom_semaphore(hw
);
2267 hw_dbg(hw
, "Driver can't access resource, SW_FW_SYNC timeout.\n");
2268 return IXGBE_ERR_SWFW_SYNC
;
2272 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2274 ixgbe_release_eeprom_semaphore(hw
);
2279 * ixgbe_release_swfw_sync - Release SWFW semaphore
2280 * @hw: pointer to hardware structure
2281 * @mask: Mask to specify which semaphore to release
2283 * Releases the SWFW semaphore thought the GSSR register for the specified
2284 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2286 void ixgbe_release_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
)
2291 ixgbe_get_eeprom_semaphore(hw
);
2293 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2295 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2297 ixgbe_release_eeprom_semaphore(hw
);
2301 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2302 * @hw: pointer to hardware structure
2303 * @regval: register value to write to RXCTRL
2305 * Enables the Rx DMA unit
2307 s32
ixgbe_enable_rx_dma_generic(struct ixgbe_hw
*hw
, u32 regval
)
2309 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
2315 * ixgbe_blink_led_start_generic - Blink LED based on index.
2316 * @hw: pointer to hardware structure
2317 * @index: led number to blink
2319 s32
ixgbe_blink_led_start_generic(struct ixgbe_hw
*hw
, u32 index
)
2321 ixgbe_link_speed speed
= 0;
2323 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2324 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2327 * Link must be up to auto-blink the LEDs;
2328 * Force it if link is down.
2330 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
2333 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2334 autoc_reg
|= IXGBE_AUTOC_FLU
;
2335 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
2339 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2340 led_reg
|= IXGBE_LED_BLINK(index
);
2341 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2342 IXGBE_WRITE_FLUSH(hw
);
2348 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2349 * @hw: pointer to hardware structure
2350 * @index: led number to stop blinking
2352 s32
ixgbe_blink_led_stop_generic(struct ixgbe_hw
*hw
, u32 index
)
2354 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2355 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2357 autoc_reg
&= ~IXGBE_AUTOC_FLU
;
2358 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2359 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
2361 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2362 led_reg
&= ~IXGBE_LED_BLINK(index
);
2363 led_reg
|= IXGBE_LED_LINK_ACTIVE
<< IXGBE_LED_MODE_SHIFT(index
);
2364 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2365 IXGBE_WRITE_FLUSH(hw
);
2371 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2372 * @hw: pointer to hardware structure
2373 * @san_mac_offset: SAN MAC address offset
2375 * This function will read the EEPROM location for the SAN MAC address
2376 * pointer, and returns the value at that location. This is used in both
2377 * get and set mac_addr routines.
2379 static s32
ixgbe_get_san_mac_addr_offset(struct ixgbe_hw
*hw
,
2380 u16
*san_mac_offset
)
2383 * First read the EEPROM pointer to see if the MAC addresses are
2386 hw
->eeprom
.ops
.read(hw
, IXGBE_SAN_MAC_ADDR_PTR
, san_mac_offset
);
2392 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2393 * @hw: pointer to hardware structure
2394 * @san_mac_addr: SAN MAC address
2396 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2397 * per-port, so set_lan_id() must be called before reading the addresses.
2398 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2399 * upon for non-SFP connections, so we must call it here.
2401 s32
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*san_mac_addr
)
2403 u16 san_mac_data
, san_mac_offset
;
2407 * First read the EEPROM pointer to see if the MAC addresses are
2408 * available. If they're not, no point in calling set_lan_id() here.
2410 ixgbe_get_san_mac_addr_offset(hw
, &san_mac_offset
);
2412 if ((san_mac_offset
== 0) || (san_mac_offset
== 0xFFFF)) {
2414 * No addresses available in this EEPROM. It's not an
2415 * error though, so just wipe the local address and return.
2417 for (i
= 0; i
< 6; i
++)
2418 san_mac_addr
[i
] = 0xFF;
2420 goto san_mac_addr_out
;
2423 /* make sure we know which port we need to program */
2424 hw
->mac
.ops
.set_lan_id(hw
);
2425 /* apply the port offset to the address offset */
2426 (hw
->bus
.func
) ? (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT1_OFFSET
) :
2427 (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT0_OFFSET
);
2428 for (i
= 0; i
< 3; i
++) {
2429 hw
->eeprom
.ops
.read(hw
, san_mac_offset
, &san_mac_data
);
2430 san_mac_addr
[i
* 2] = (u8
)(san_mac_data
);
2431 san_mac_addr
[i
* 2 + 1] = (u8
)(san_mac_data
>> 8);
2440 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2441 * @hw: pointer to hardware structure
2443 * Read PCIe configuration space, and get the MSI-X vector count from
2444 * the capabilities table.
2446 u32
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw
*hw
)
2448 struct ixgbe_adapter
*adapter
= hw
->back
;
2450 pci_read_config_word(adapter
->pdev
, IXGBE_PCIE_MSIX_82599_CAPS
,
2452 msix_count
&= IXGBE_PCIE_MSIX_TBL_SZ_MASK
;
2454 /* MSI-X count is zero-based in HW, so increment to give proper value */
2461 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2462 * @hw: pointer to hardware struct
2463 * @rar: receive address register index to disassociate
2464 * @vmdq: VMDq pool index to remove from the rar
2466 s32
ixgbe_clear_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2468 u32 mpsar_lo
, mpsar_hi
;
2469 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2471 /* Make sure we are using a valid rar index range */
2472 if (rar
>= rar_entries
) {
2473 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2474 return IXGBE_ERR_INVALID_ARGUMENT
;
2477 mpsar_lo
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2478 mpsar_hi
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2480 if (!mpsar_lo
&& !mpsar_hi
)
2483 if (vmdq
== IXGBE_CLEAR_VMDQ_ALL
) {
2485 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), 0);
2489 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), 0);
2492 } else if (vmdq
< 32) {
2493 mpsar_lo
&= ~(1 << vmdq
);
2494 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar_lo
);
2496 mpsar_hi
&= ~(1 << (vmdq
- 32));
2497 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar_hi
);
2500 /* was that the last pool using this rar? */
2501 if (mpsar_lo
== 0 && mpsar_hi
== 0 && rar
!= 0)
2502 hw
->mac
.ops
.clear_rar(hw
, rar
);
2508 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2509 * @hw: pointer to hardware struct
2510 * @rar: receive address register index to associate with a VMDq index
2511 * @vmdq: VMDq pool index
2513 s32
ixgbe_set_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2516 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2518 /* Make sure we are using a valid rar index range */
2519 if (rar
>= rar_entries
) {
2520 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2521 return IXGBE_ERR_INVALID_ARGUMENT
;
2525 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2527 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar
);
2529 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2530 mpsar
|= 1 << (vmdq
- 32);
2531 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar
);
2537 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2538 * @hw: pointer to hardware structure
2540 s32
ixgbe_init_uta_tables_generic(struct ixgbe_hw
*hw
)
2545 for (i
= 0; i
< 128; i
++)
2546 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), 0);
2552 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2553 * @hw: pointer to hardware structure
2554 * @vlan: VLAN id to write to VLAN filter
2556 * return the VLVF index where this VLAN id should be placed
2559 static s32
ixgbe_find_vlvf_slot(struct ixgbe_hw
*hw
, u32 vlan
)
2562 u32 first_empty_slot
= 0;
2565 /* short cut the special case */
2570 * Search for the vlan id in the VLVF entries. Save off the first empty
2571 * slot found along the way
2573 for (regindex
= 1; regindex
< IXGBE_VLVF_ENTRIES
; regindex
++) {
2574 bits
= IXGBE_READ_REG(hw
, IXGBE_VLVF(regindex
));
2575 if (!bits
&& !(first_empty_slot
))
2576 first_empty_slot
= regindex
;
2577 else if ((bits
& 0x0FFF) == vlan
)
2582 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2583 * in the VLVF. Else use the first empty VLVF register for this
2586 if (regindex
>= IXGBE_VLVF_ENTRIES
) {
2587 if (first_empty_slot
)
2588 regindex
= first_empty_slot
;
2590 hw_dbg(hw
, "No space in VLVF.\n");
2591 regindex
= IXGBE_ERR_NO_SPACE
;
2599 * ixgbe_set_vfta_generic - Set VLAN filter table
2600 * @hw: pointer to hardware structure
2601 * @vlan: VLAN id to write to VLAN filter
2602 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2603 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2605 * Turn on/off specified VLAN in the VLAN filter table.
2607 s32
ixgbe_set_vfta_generic(struct ixgbe_hw
*hw
, u32 vlan
, u32 vind
,
2616 bool vfta_changed
= false;
2619 return IXGBE_ERR_PARAM
;
2622 * this is a 2 part operation - first the VFTA, then the
2623 * VLVF and VLVFB if VT Mode is set
2624 * We don't write the VFTA until we know the VLVF part succeeded.
2628 * The VFTA is a bitstring made up of 128 32-bit registers
2629 * that enable the particular VLAN id, much like the MTA:
2630 * bits[11-5]: which register
2631 * bits[4-0]: which bit in the register
2633 regindex
= (vlan
>> 5) & 0x7F;
2634 bitindex
= vlan
& 0x1F;
2635 targetbit
= (1 << bitindex
);
2636 vfta
= IXGBE_READ_REG(hw
, IXGBE_VFTA(regindex
));
2639 if (!(vfta
& targetbit
)) {
2641 vfta_changed
= true;
2644 if ((vfta
& targetbit
)) {
2646 vfta_changed
= true;
2653 * make sure the vlan is in VLVF
2654 * set the vind bit in the matching VLVFB
2656 * clear the pool bit and possibly the vind
2658 vt
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2659 if (vt
& IXGBE_VT_CTL_VT_ENABLE
) {
2662 vlvf_index
= ixgbe_find_vlvf_slot(hw
, vlan
);
2667 /* set the pool bit */
2669 bits
= IXGBE_READ_REG(hw
,
2670 IXGBE_VLVFB(vlvf_index
*2));
2671 bits
|= (1 << vind
);
2673 IXGBE_VLVFB(vlvf_index
*2),
2676 bits
= IXGBE_READ_REG(hw
,
2677 IXGBE_VLVFB((vlvf_index
*2)+1));
2678 bits
|= (1 << (vind
-32));
2680 IXGBE_VLVFB((vlvf_index
*2)+1),
2684 /* clear the pool bit */
2686 bits
= IXGBE_READ_REG(hw
,
2687 IXGBE_VLVFB(vlvf_index
*2));
2688 bits
&= ~(1 << vind
);
2690 IXGBE_VLVFB(vlvf_index
*2),
2692 bits
|= IXGBE_READ_REG(hw
,
2693 IXGBE_VLVFB((vlvf_index
*2)+1));
2695 bits
= IXGBE_READ_REG(hw
,
2696 IXGBE_VLVFB((vlvf_index
*2)+1));
2697 bits
&= ~(1 << (vind
-32));
2699 IXGBE_VLVFB((vlvf_index
*2)+1),
2701 bits
|= IXGBE_READ_REG(hw
,
2702 IXGBE_VLVFB(vlvf_index
*2));
2707 * If there are still bits set in the VLVFB registers
2708 * for the VLAN ID indicated we need to see if the
2709 * caller is requesting that we clear the VFTA entry bit.
2710 * If the caller has requested that we clear the VFTA
2711 * entry bit but there are still pools/VFs using this VLAN
2712 * ID entry then ignore the request. We're not worried
2713 * about the case where we're turning the VFTA VLAN ID
2714 * entry bit on, only when requested to turn it off as
2715 * there may be multiple pools and/or VFs using the
2716 * VLAN ID entry. In that case we cannot clear the
2717 * VFTA bit until all pools/VFs using that VLAN ID have also
2718 * been cleared. This will be indicated by "bits" being
2722 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
),
2723 (IXGBE_VLVF_VIEN
| vlan
));
2725 /* someone wants to clear the vfta entry
2726 * but some pools/VFs are still using it.
2728 vfta_changed
= false;
2732 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
), 0);
2736 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(regindex
), vfta
);
2742 * ixgbe_clear_vfta_generic - Clear VLAN filter table
2743 * @hw: pointer to hardware structure
2745 * Clears the VLAN filer table, and the VMDq index associated with the filter
2747 s32
ixgbe_clear_vfta_generic(struct ixgbe_hw
*hw
)
2751 for (offset
= 0; offset
< hw
->mac
.vft_size
; offset
++)
2752 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(offset
), 0);
2754 for (offset
= 0; offset
< IXGBE_VLVF_ENTRIES
; offset
++) {
2755 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(offset
), 0);
2756 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB(offset
*2), 0);
2757 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB((offset
*2)+1), 0);
2764 * ixgbe_check_mac_link_generic - Determine link and speed status
2765 * @hw: pointer to hardware structure
2766 * @speed: pointer to link speed
2767 * @link_up: true when link is up
2768 * @link_up_wait_to_complete: bool used to wait for link up or not
2770 * Reads the links register to determine if link is up and the current speed
2772 s32
ixgbe_check_mac_link_generic(struct ixgbe_hw
*hw
, ixgbe_link_speed
*speed
,
2773 bool *link_up
, bool link_up_wait_to_complete
)
2775 u32 links_reg
, links_orig
;
2778 /* clear the old state */
2779 links_orig
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
2781 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
2783 if (links_orig
!= links_reg
) {
2784 hw_dbg(hw
, "LINKS changed from %08X to %08X\n",
2785 links_orig
, links_reg
);
2788 if (link_up_wait_to_complete
) {
2789 for (i
= 0; i
< IXGBE_LINK_UP_TIME
; i
++) {
2790 if (links_reg
& IXGBE_LINKS_UP
) {
2797 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
2800 if (links_reg
& IXGBE_LINKS_UP
)
2806 if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
2807 IXGBE_LINKS_SPEED_10G_82599
)
2808 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
2809 else if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
2810 IXGBE_LINKS_SPEED_1G_82599
)
2811 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
2813 *speed
= IXGBE_LINK_SPEED_100_FULL
;
2815 /* if link is down, zero out the current_mode */
2816 if (*link_up
== false) {
2817 hw
->fc
.current_mode
= ixgbe_fc_none
;
2818 hw
->fc
.fc_was_autonegged
= false;
2825 * ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from
2827 * @hw: pointer to hardware structure
2828 * @wwnn_prefix: the alternative WWNN prefix
2829 * @wwpn_prefix: the alternative WWPN prefix
2831 * This function will read the EEPROM from the alternative SAN MAC address
2832 * block to check the support for the alternative WWNN/WWPN prefix support.
2834 s32
ixgbe_get_wwn_prefix_generic(struct ixgbe_hw
*hw
, u16
*wwnn_prefix
,
2838 u16 alt_san_mac_blk_offset
;
2840 /* clear output first */
2841 *wwnn_prefix
= 0xFFFF;
2842 *wwpn_prefix
= 0xFFFF;
2844 /* check if alternative SAN MAC is supported */
2845 hw
->eeprom
.ops
.read(hw
, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR
,
2846 &alt_san_mac_blk_offset
);
2848 if ((alt_san_mac_blk_offset
== 0) ||
2849 (alt_san_mac_blk_offset
== 0xFFFF))
2850 goto wwn_prefix_out
;
2852 /* check capability in alternative san mac address block */
2853 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET
;
2854 hw
->eeprom
.ops
.read(hw
, offset
, &caps
);
2855 if (!(caps
& IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN
))
2856 goto wwn_prefix_out
;
2858 /* get the corresponding prefix for WWNN/WWPN */
2859 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET
;
2860 hw
->eeprom
.ops
.read(hw
, offset
, wwnn_prefix
);
2862 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET
;
2863 hw
->eeprom
.ops
.read(hw
, offset
, wwpn_prefix
);
2870 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
2871 * @hw: pointer to hardware structure
2872 * @enable: enable or disable switch for anti-spoofing
2873 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
2876 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int pf
)
2879 int pf_target_reg
= pf
>> 3;
2880 int pf_target_shift
= pf
% 8;
2883 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2887 pfvfspoof
= IXGBE_SPOOF_MACAS_MASK
;
2890 * PFVFSPOOF register array is size 8 with 8 bits assigned to
2891 * MAC anti-spoof enables in each register array element.
2893 for (j
= 0; j
< IXGBE_PFVFSPOOF_REG_COUNT
; j
++)
2894 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(j
), pfvfspoof
);
2896 /* If not enabling anti-spoofing then done */
2901 * The PF should be allowed to spoof so that it can support
2902 * emulation mode NICs. Reset the bit assigned to the PF
2904 pfvfspoof
= IXGBE_READ_REG(hw
, IXGBE_PFVFSPOOF(pf_target_reg
));
2905 pfvfspoof
^= (1 << pf_target_shift
);
2906 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(pf_target_reg
), pfvfspoof
);
2910 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
2911 * @hw: pointer to hardware structure
2912 * @enable: enable or disable switch for VLAN anti-spoofing
2913 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
2916 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int vf
)
2918 int vf_target_reg
= vf
>> 3;
2919 int vf_target_shift
= vf
% 8 + IXGBE_SPOOF_VLANAS_SHIFT
;
2922 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2925 pfvfspoof
= IXGBE_READ_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
));
2927 pfvfspoof
|= (1 << vf_target_shift
);
2929 pfvfspoof
&= ~(1 << vf_target_shift
);
2930 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
), pfvfspoof
);