1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name
[] = "ixgbe";
52 static const char ixgbe_driver_string
[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "2.0.84-k2"
56 const char ixgbe_driver_version
[] = DRV_VERSION
;
57 static char ixgbe_copyright
[] = "Copyright (c) 1999-2010 Intel Corporation.";
59 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
60 [board_82598
] = &ixgbe_82598_info
,
61 [board_82599
] = &ixgbe_82599_info
,
64 /* ixgbe_pci_tbl - PCI Device ID Table
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
73 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
75 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
77 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
79 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
111 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_T3_LOM
),
113 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
116 /* required last entry */
119 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
124 static struct notifier_block dca_notifier
= {
125 .notifier_call
= ixgbe_notify_dca
,
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs
;
133 module_param(max_vfs
, uint
, 0);
134 MODULE_PARM_DESC(max_vfs
, "Maximum number of virtual functions to allocate "
135 "per physical function");
136 #endif /* CONFIG_PCI_IOV */
138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_VERSION
);
143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
147 struct ixgbe_hw
*hw
= &adapter
->hw
;
152 #ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter
->pdev
);
157 /* turn off device IOV mode */
158 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
159 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
160 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
161 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
162 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
163 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
165 /* set default pool back to 0 */
166 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
167 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
168 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
170 /* take a breather then clean up driver data */
173 kfree(adapter
->vfinfo
);
174 adapter
->vfinfo
= NULL
;
176 adapter
->num_vfs
= 0;
177 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
180 struct ixgbe_reg_info
{
185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl
[] = {
187 /* General Registers */
188 {IXGBE_CTRL
, "CTRL"},
189 {IXGBE_STATUS
, "STATUS"},
190 {IXGBE_CTRL_EXT
, "CTRL_EXT"},
192 /* Interrupt Registers */
193 {IXGBE_EICR
, "EICR"},
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
213 /* List Terminator */
219 * ixgbe_regdump - register printout routine
221 static void ixgbe_regdump(struct ixgbe_hw
*hw
, struct ixgbe_reg_info
*reginfo
)
227 switch (reginfo
->ofs
) {
228 case IXGBE_SRRCTL(0):
229 for (i
= 0; i
< 64; i
++)
230 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_SRRCTL(i
));
232 case IXGBE_DCA_RXCTRL(0):
233 for (i
= 0; i
< 64; i
++)
234 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
237 for (i
= 0; i
< 64; i
++)
238 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDLEN(i
));
241 for (i
= 0; i
< 64; i
++)
242 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDH(i
));
245 for (i
= 0; i
< 64; i
++)
246 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDT(i
));
248 case IXGBE_RXDCTL(0):
249 for (i
= 0; i
< 64; i
++)
250 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
253 for (i
= 0; i
< 64; i
++)
254 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAL(i
));
257 for (i
= 0; i
< 64; i
++)
258 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAH(i
));
261 for (i
= 0; i
< 64; i
++)
262 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAL(i
));
265 for (i
= 0; i
< 64; i
++)
266 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAH(i
));
269 for (i
= 0; i
< 64; i
++)
270 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDLEN(i
));
273 for (i
= 0; i
< 64; i
++)
274 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDH(i
));
277 for (i
= 0; i
< 64; i
++)
278 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDT(i
));
280 case IXGBE_TXDCTL(0):
281 for (i
= 0; i
< 64; i
++)
282 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
285 printk(KERN_INFO
"%-15s %08x\n", reginfo
->name
,
286 IXGBE_READ_REG(hw
, reginfo
->ofs
));
290 for (i
= 0; i
< 8; i
++) {
291 snprintf(rname
, 16, "%s[%d-%d]", reginfo
->name
, i
*8, i
*8+7);
292 printk(KERN_ERR
"%-15s ", rname
);
293 for (j
= 0; j
< 8; j
++)
294 printk(KERN_CONT
"%08x ", regs
[i
*8+j
]);
295 printk(KERN_CONT
"\n");
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
303 static void ixgbe_dump(struct ixgbe_adapter
*adapter
)
305 struct net_device
*netdev
= adapter
->netdev
;
306 struct ixgbe_hw
*hw
= &adapter
->hw
;
307 struct ixgbe_reg_info
*reginfo
;
309 struct ixgbe_ring
*tx_ring
;
310 struct ixgbe_tx_buffer
*tx_buffer_info
;
311 union ixgbe_adv_tx_desc
*tx_desc
;
312 struct my_u0
{ u64 a
; u64 b
; } *u0
;
313 struct ixgbe_ring
*rx_ring
;
314 union ixgbe_adv_rx_desc
*rx_desc
;
315 struct ixgbe_rx_buffer
*rx_buffer_info
;
319 if (!netif_msg_hw(adapter
))
322 /* Print netdevice Info */
324 dev_info(&adapter
->pdev
->dev
, "Net device Info\n");
325 printk(KERN_INFO
"Device Name state "
326 "trans_start last_rx\n");
327 printk(KERN_INFO
"%-15s %016lX %016lX %016lX\n",
334 /* Print Registers */
335 dev_info(&adapter
->pdev
->dev
, "Register Dump\n");
336 printk(KERN_INFO
" Register Name Value\n");
337 for (reginfo
= (struct ixgbe_reg_info
*)ixgbe_reg_info_tbl
;
338 reginfo
->name
; reginfo
++) {
339 ixgbe_regdump(hw
, reginfo
);
342 /* Print TX Ring Summary */
343 if (!netdev
|| !netif_running(netdev
))
346 dev_info(&adapter
->pdev
->dev
, "TX Rings Summary\n");
347 printk(KERN_INFO
"Queue [NTU] [NTC] [bi(ntc)->dma ] "
348 "leng ntw timestamp\n");
349 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
350 tx_ring
= adapter
->tx_ring
[n
];
352 &tx_ring
->tx_buffer_info
[tx_ring
->next_to_clean
];
353 printk(KERN_INFO
" %5d %5X %5X %016llX %04X %3X %016llX\n",
354 n
, tx_ring
->next_to_use
, tx_ring
->next_to_clean
,
355 (u64
)tx_buffer_info
->dma
,
356 tx_buffer_info
->length
,
357 tx_buffer_info
->next_to_watch
,
358 (u64
)tx_buffer_info
->time_stamp
);
362 if (!netif_msg_tx_done(adapter
))
363 goto rx_ring_summary
;
365 dev_info(&adapter
->pdev
->dev
, "TX Rings Dump\n");
367 /* Transmit Descriptor Formats
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
378 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
379 tx_ring
= adapter
->tx_ring
[n
];
380 printk(KERN_INFO
"------------------------------------\n");
381 printk(KERN_INFO
"TX QUEUE INDEX = %d\n", tx_ring
->queue_index
);
382 printk(KERN_INFO
"------------------------------------\n");
383 printk(KERN_INFO
"T [desc] [address 63:0 ] "
384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
387 for (i
= 0; tx_ring
->desc
&& (i
< tx_ring
->count
); i
++) {
388 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
389 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
390 u0
= (struct my_u0
*)tx_desc
;
391 printk(KERN_INFO
"T [0x%03X] %016llX %016llX %016llX"
392 " %04X %3X %016llX %p", i
,
395 (u64
)tx_buffer_info
->dma
,
396 tx_buffer_info
->length
,
397 tx_buffer_info
->next_to_watch
,
398 (u64
)tx_buffer_info
->time_stamp
,
399 tx_buffer_info
->skb
);
400 if (i
== tx_ring
->next_to_use
&&
401 i
== tx_ring
->next_to_clean
)
402 printk(KERN_CONT
" NTC/U\n");
403 else if (i
== tx_ring
->next_to_use
)
404 printk(KERN_CONT
" NTU\n");
405 else if (i
== tx_ring
->next_to_clean
)
406 printk(KERN_CONT
" NTC\n");
408 printk(KERN_CONT
"\n");
410 if (netif_msg_pktdata(adapter
) &&
411 tx_buffer_info
->dma
!= 0)
412 print_hex_dump(KERN_INFO
, "",
413 DUMP_PREFIX_ADDRESS
, 16, 1,
414 phys_to_virt(tx_buffer_info
->dma
),
415 tx_buffer_info
->length
, true);
419 /* Print RX Rings Summary */
421 dev_info(&adapter
->pdev
->dev
, "RX Rings Summary\n");
422 printk(KERN_INFO
"Queue [NTU] [NTC]\n");
423 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
424 rx_ring
= adapter
->rx_ring
[n
];
425 printk(KERN_INFO
"%5d %5X %5X\n", n
,
426 rx_ring
->next_to_use
, rx_ring
->next_to_clean
);
430 if (!netif_msg_rx_status(adapter
))
433 dev_info(&adapter
->pdev
->dev
, "RX Rings Dump\n");
435 /* Advanced Receive Descriptor (Read) Format
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
444 * Advanced Receive Descriptor (Write-Back) Format
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
455 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
456 rx_ring
= adapter
->rx_ring
[n
];
457 printk(KERN_INFO
"------------------------------------\n");
458 printk(KERN_INFO
"RX QUEUE INDEX = %d\n", rx_ring
->queue_index
);
459 printk(KERN_INFO
"------------------------------------\n");
460 printk(KERN_INFO
"R [desc] [ PktBuf A0] "
461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
463 printk(KERN_INFO
"RWB[desc] [PcsmIpSHl PtRs] "
464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
467 for (i
= 0; i
< rx_ring
->count
; i
++) {
468 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
469 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
470 u0
= (struct my_u0
*)rx_desc
;
471 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
472 if (staterr
& IXGBE_RXD_STAT_DD
) {
473 /* Descriptor Done */
474 printk(KERN_INFO
"RWB[0x%03X] %016llX "
475 "%016llX ---------------- %p", i
,
478 rx_buffer_info
->skb
);
480 printk(KERN_INFO
"R [0x%03X] %016llX "
481 "%016llX %016llX %p", i
,
484 (u64
)rx_buffer_info
->dma
,
485 rx_buffer_info
->skb
);
487 if (netif_msg_pktdata(adapter
)) {
488 print_hex_dump(KERN_INFO
, "",
489 DUMP_PREFIX_ADDRESS
, 16, 1,
490 phys_to_virt(rx_buffer_info
->dma
),
491 rx_ring
->rx_buf_len
, true);
493 if (rx_ring
->rx_buf_len
494 < IXGBE_RXBUFFER_2048
)
495 print_hex_dump(KERN_INFO
, "",
496 DUMP_PREFIX_ADDRESS
, 16, 1,
498 rx_buffer_info
->page_dma
+
499 rx_buffer_info
->page_offset
505 if (i
== rx_ring
->next_to_use
)
506 printk(KERN_CONT
" NTU\n");
507 else if (i
== rx_ring
->next_to_clean
)
508 printk(KERN_CONT
" NTC\n");
510 printk(KERN_CONT
"\n");
519 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
523 /* Let firmware take over control of h/w */
524 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
525 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
526 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
529 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
533 /* Let firmware know the driver has taken over */
534 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
535 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
536 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
547 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
548 u8 queue
, u8 msix_vector
)
551 struct ixgbe_hw
*hw
= &adapter
->hw
;
552 switch (hw
->mac
.type
) {
553 case ixgbe_mac_82598EB
:
554 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
557 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
558 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
559 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
560 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
561 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
563 case ixgbe_mac_82599EB
:
564 if (direction
== -1) {
566 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
567 index
= ((queue
& 1) * 8);
568 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
569 ivar
&= ~(0xFF << index
);
570 ivar
|= (msix_vector
<< index
);
571 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
574 /* tx or rx causes */
575 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
576 index
= ((16 * (queue
& 1)) + (8 * direction
));
577 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
578 ivar
&= ~(0xFF << index
);
579 ivar
|= (msix_vector
<< index
);
580 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
593 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
594 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
595 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
597 mask
= (qmask
& 0xFFFFFFFF);
598 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
599 mask
= (qmask
>> 32);
600 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
604 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter
*adapter
,
605 struct ixgbe_tx_buffer
608 if (tx_buffer_info
->dma
) {
609 if (tx_buffer_info
->mapped_as_page
)
610 dma_unmap_page(&adapter
->pdev
->dev
,
612 tx_buffer_info
->length
,
615 dma_unmap_single(&adapter
->pdev
->dev
,
617 tx_buffer_info
->length
,
619 tx_buffer_info
->dma
= 0;
621 if (tx_buffer_info
->skb
) {
622 dev_kfree_skb_any(tx_buffer_info
->skb
);
623 tx_buffer_info
->skb
= NULL
;
625 tx_buffer_info
->time_stamp
= 0;
626 /* tx_buffer_info must be completely set up in the transmit path */
630 * ixgbe_tx_xon_state - check the tx ring xon state
631 * @adapter: the ixgbe adapter
632 * @tx_ring: the corresponding tx_ring
634 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
635 * corresponding TC of this tx_ring when checking TFCS.
637 * Returns : true if in xon state (currently not paused)
639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter
*adapter
,
640 struct ixgbe_ring
*tx_ring
)
642 u32 txoff
= IXGBE_TFCS_TXOFF
;
644 #ifdef CONFIG_IXGBE_DCB
645 if (adapter
->dcb_cfg
.pfc_mode_enable
) {
647 int reg_idx
= tx_ring
->reg_idx
;
648 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
650 switch (adapter
->hw
.mac
.type
) {
651 case ixgbe_mac_82598EB
:
653 txoff
= IXGBE_TFCS_TXOFF0
;
655 case ixgbe_mac_82599EB
:
657 txoff
= IXGBE_TFCS_TXOFF
;
661 if (tc
== 2) /* TC2, TC3 */
662 tc
+= (reg_idx
- 64) >> 4;
663 else if (tc
== 3) /* TC4, TC5, TC6, TC7 */
664 tc
+= 1 + ((reg_idx
- 96) >> 3);
665 } else if (dcb_i
== 4) {
669 tc
+= (reg_idx
- 64) >> 5;
670 if (tc
== 2) /* TC2, TC3 */
671 tc
+= (reg_idx
- 96) >> 4;
681 return IXGBE_READ_REG(&adapter
->hw
, IXGBE_TFCS
) & txoff
;
684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter
*adapter
,
685 struct ixgbe_ring
*tx_ring
,
688 struct ixgbe_hw
*hw
= &adapter
->hw
;
690 /* Detect a transmit hang in hardware, this serializes the
691 * check with the clearing of time_stamp and movement of eop */
692 adapter
->detect_tx_hung
= false;
693 if (tx_ring
->tx_buffer_info
[eop
].time_stamp
&&
694 time_after(jiffies
, tx_ring
->tx_buffer_info
[eop
].time_stamp
+ HZ
) &&
695 ixgbe_tx_xon_state(adapter
, tx_ring
)) {
696 /* detected Tx unit hang */
697 union ixgbe_adv_tx_desc
*tx_desc
;
698 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
699 e_err(drv
, "Detected Tx Unit Hang\n"
701 " TDH, TDT <%x>, <%x>\n"
702 " next_to_use <%x>\n"
703 " next_to_clean <%x>\n"
704 "tx_buffer_info[next_to_clean]\n"
705 " time_stamp <%lx>\n"
707 tx_ring
->queue_index
,
708 IXGBE_READ_REG(hw
, tx_ring
->head
),
709 IXGBE_READ_REG(hw
, tx_ring
->tail
),
710 tx_ring
->next_to_use
, eop
,
711 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
718 #define IXGBE_MAX_TXD_PWR 14
719 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
721 /* Tx Descriptors needed, worst case */
722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
723 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
725 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
727 static void ixgbe_tx_timeout(struct net_device
*netdev
);
730 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
731 * @q_vector: structure containing interrupt and ring information
732 * @tx_ring: tx ring to clean
734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
735 struct ixgbe_ring
*tx_ring
)
737 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
738 struct net_device
*netdev
= adapter
->netdev
;
739 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
740 struct ixgbe_tx_buffer
*tx_buffer_info
;
741 unsigned int i
, eop
, count
= 0;
742 unsigned int total_bytes
= 0, total_packets
= 0;
744 i
= tx_ring
->next_to_clean
;
745 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
746 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
748 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
749 (count
< tx_ring
->work_limit
)) {
750 bool cleaned
= false;
751 rmb(); /* read buffer_info after eop_desc */
752 for ( ; !cleaned
; count
++) {
754 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
755 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
756 cleaned
= (i
== eop
);
757 skb
= tx_buffer_info
->skb
;
759 if (cleaned
&& skb
) {
760 unsigned int segs
, bytecount
;
761 unsigned int hlen
= skb_headlen(skb
);
763 /* gso_segs is currently only valid for tcp */
764 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
766 /* adjust for FCoE Sequence Offload */
767 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
768 && (skb
->protocol
== htons(ETH_P_FCOE
)) &&
770 hlen
= skb_transport_offset(skb
) +
771 sizeof(struct fc_frame_header
) +
772 sizeof(struct fcoe_crc_eof
);
773 segs
= DIV_ROUND_UP(skb
->len
- hlen
,
774 skb_shinfo(skb
)->gso_size
);
776 #endif /* IXGBE_FCOE */
777 /* multiply data chunks by size of headers */
778 bytecount
= ((segs
- 1) * hlen
) + skb
->len
;
779 total_packets
+= segs
;
780 total_bytes
+= bytecount
;
783 ixgbe_unmap_and_free_tx_resource(adapter
,
786 tx_desc
->wb
.status
= 0;
789 if (i
== tx_ring
->count
)
793 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
794 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
797 tx_ring
->next_to_clean
= i
;
799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
800 if (unlikely(count
&& netif_carrier_ok(netdev
) &&
801 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
806 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
807 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
808 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
809 ++tx_ring
->restart_queue
;
813 if (adapter
->detect_tx_hung
) {
814 if (ixgbe_check_tx_hang(adapter
, tx_ring
, i
)) {
815 /* schedule immediate reset if we believe we hung */
816 e_info(probe
, "tx hang %d detected, resetting "
817 "adapter\n", adapter
->tx_timeout_count
+ 1);
818 ixgbe_tx_timeout(adapter
->netdev
);
822 /* re-arm the interrupt */
823 if (count
>= tx_ring
->work_limit
)
824 ixgbe_irq_rearm_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
826 tx_ring
->total_bytes
+= total_bytes
;
827 tx_ring
->total_packets
+= total_packets
;
828 tx_ring
->stats
.packets
+= total_packets
;
829 tx_ring
->stats
.bytes
+= total_bytes
;
830 return (count
< tx_ring
->work_limit
);
833 #ifdef CONFIG_IXGBE_DCA
834 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
835 struct ixgbe_ring
*rx_ring
)
839 int q
= rx_ring
->reg_idx
;
841 if (rx_ring
->cpu
!= cpu
) {
842 rxctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
));
843 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
844 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
845 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
846 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
847 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
848 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
849 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
851 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
852 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
853 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
854 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
855 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
856 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
), rxctrl
);
862 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
863 struct ixgbe_ring
*tx_ring
)
867 int q
= tx_ring
->reg_idx
;
868 struct ixgbe_hw
*hw
= &adapter
->hw
;
870 if (tx_ring
->cpu
!= cpu
) {
871 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
872 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(q
));
873 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
874 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
875 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
876 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(q
), txctrl
);
877 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
878 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
));
879 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
880 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
881 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
882 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
883 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
), txctrl
);
890 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
894 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
897 /* always use CB2 mode, difference is masked in the CB driver */
898 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
900 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
901 adapter
->tx_ring
[i
]->cpu
= -1;
902 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[i
]);
904 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
905 adapter
->rx_ring
[i
]->cpu
= -1;
906 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[i
]);
910 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
912 struct net_device
*netdev
= dev_get_drvdata(dev
);
913 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
914 unsigned long event
= *(unsigned long *)data
;
917 case DCA_PROVIDER_ADD
:
918 /* if we're already enabled, don't do it again */
919 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
921 if (dca_add_requester(dev
) == 0) {
922 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
923 ixgbe_setup_dca(adapter
);
926 /* Fall Through since DCA is disabled. */
927 case DCA_PROVIDER_REMOVE
:
928 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
929 dca_remove_requester(dev
);
930 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
931 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
939 #endif /* CONFIG_IXGBE_DCA */
941 * ixgbe_receive_skb - Send a completed packet up the stack
942 * @adapter: board private structure
943 * @skb: packet to send up
944 * @status: hardware indication of status of receive
945 * @rx_ring: rx descriptor ring (for a specific queue) to setup
946 * @rx_desc: rx descriptor
948 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
949 struct sk_buff
*skb
, u8 status
,
950 struct ixgbe_ring
*ring
,
951 union ixgbe_adv_rx_desc
*rx_desc
)
953 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
954 struct napi_struct
*napi
= &q_vector
->napi
;
955 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
956 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
958 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
)) {
959 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
960 vlan_gro_receive(napi
, adapter
->vlgrp
, tag
, skb
);
962 napi_gro_receive(napi
, skb
);
964 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
965 vlan_hwaccel_rx(skb
, adapter
->vlgrp
, tag
);
972 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
973 * @adapter: address of board private structure
974 * @status_err: hardware indication of status of receive
975 * @skb: skb currently being received and modified
977 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
978 union ixgbe_adv_rx_desc
*rx_desc
,
981 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
983 skb
->ip_summed
= CHECKSUM_NONE
;
985 /* Rx csum disabled */
986 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
989 /* if IP and error */
990 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
991 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
992 adapter
->hw_csum_rx_error
++;
996 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
999 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
1000 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1003 * 82599 errata, UDP frames with a 0 checksum can be marked as
1006 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
1007 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1010 adapter
->hw_csum_rx_error
++;
1014 /* It must be a TCP or UDP packet with a valid checksum */
1015 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1018 static inline void ixgbe_release_rx_desc(struct ixgbe_hw
*hw
,
1019 struct ixgbe_ring
*rx_ring
, u32 val
)
1022 * Force memory writes to complete before letting h/w
1023 * know there are new descriptors to fetch. (Only
1024 * applicable for weak-ordered memory model archs,
1028 IXGBE_WRITE_REG(hw
, IXGBE_RDT(rx_ring
->reg_idx
), val
);
1032 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033 * @adapter: address of board private structure
1035 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter
*adapter
,
1036 struct ixgbe_ring
*rx_ring
,
1039 struct net_device
*netdev
= adapter
->netdev
;
1040 struct pci_dev
*pdev
= adapter
->pdev
;
1041 union ixgbe_adv_rx_desc
*rx_desc
;
1042 struct ixgbe_rx_buffer
*bi
;
1044 unsigned int bufsz
= rx_ring
->rx_buf_len
;
1046 i
= rx_ring
->next_to_use
;
1047 bi
= &rx_ring
->rx_buffer_info
[i
];
1049 while (cleaned_count
--) {
1050 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
1052 if (!bi
->page_dma
&&
1053 (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)) {
1055 bi
->page
= netdev_alloc_page(netdev
);
1057 adapter
->alloc_rx_page_failed
++;
1060 bi
->page_offset
= 0;
1062 /* use a half page if we're re-using */
1063 bi
->page_offset
^= (PAGE_SIZE
/ 2);
1066 bi
->page_dma
= dma_map_page(&pdev
->dev
, bi
->page
,
1073 struct sk_buff
*skb
= netdev_alloc_skb_ip_align(netdev
,
1078 adapter
->alloc_rx_buff_failed
++;
1081 /* initialize queue mapping */
1082 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
1086 bi
->dma
= dma_map_single(&pdev
->dev
,
1088 rx_ring
->rx_buf_len
,
1091 /* Refresh the desc even if buffer_addrs didn't change because
1092 * each write-back erases this info. */
1093 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1094 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
1095 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
1097 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
1101 if (i
== rx_ring
->count
)
1103 bi
= &rx_ring
->rx_buffer_info
[i
];
1107 if (rx_ring
->next_to_use
!= i
) {
1108 rx_ring
->next_to_use
= i
;
1110 i
= (rx_ring
->count
- 1);
1112 ixgbe_release_rx_desc(&adapter
->hw
, rx_ring
, i
);
1116 static inline u16
ixgbe_get_hdr_info(union ixgbe_adv_rx_desc
*rx_desc
)
1118 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
;
1121 static inline u16
ixgbe_get_pkt_info(union ixgbe_adv_rx_desc
*rx_desc
)
1123 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1126 static inline u32
ixgbe_get_rsc_count(union ixgbe_adv_rx_desc
*rx_desc
)
1128 return (le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
1129 IXGBE_RXDADV_RSCCNT_MASK
) >>
1130 IXGBE_RXDADV_RSCCNT_SHIFT
;
1134 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135 * @skb: pointer to the last skb in the rsc queue
1136 * @count: pointer to number of packets coalesced in this context
1138 * This function changes a queue full of hw rsc buffers into a completed
1139 * packet. It uses the ->prev pointers to find the first packet and then
1140 * turns it into the frag list owner.
1142 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
,
1145 unsigned int frag_list_size
= 0;
1148 struct sk_buff
*prev
= skb
->prev
;
1149 frag_list_size
+= skb
->len
;
1155 skb_shinfo(skb
)->frag_list
= skb
->next
;
1157 skb
->len
+= frag_list_size
;
1158 skb
->data_len
+= frag_list_size
;
1159 skb
->truesize
+= frag_list_size
;
1163 struct ixgbe_rsc_cb
{
1168 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1170 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
1171 struct ixgbe_ring
*rx_ring
,
1172 int *work_done
, int work_to_do
)
1174 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1175 struct net_device
*netdev
= adapter
->netdev
;
1176 struct pci_dev
*pdev
= adapter
->pdev
;
1177 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
1178 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
1179 struct sk_buff
*skb
;
1180 unsigned int i
, rsc_count
= 0;
1183 bool cleaned
= false;
1184 int cleaned_count
= 0;
1185 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1188 #endif /* IXGBE_FCOE */
1190 i
= rx_ring
->next_to_clean
;
1191 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
1192 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1193 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1195 while (staterr
& IXGBE_RXD_STAT_DD
) {
1197 if (*work_done
>= work_to_do
)
1201 rmb(); /* read descriptor and rx_buffer_info after status DD */
1202 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1203 hdr_info
= le16_to_cpu(ixgbe_get_hdr_info(rx_desc
));
1204 len
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
1205 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
1206 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1207 if ((len
> IXGBE_RX_HDR_SIZE
) ||
1208 (upper_len
&& !(hdr_info
& IXGBE_RXDADV_SPH
)))
1209 len
= IXGBE_RX_HDR_SIZE
;
1211 len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1215 skb
= rx_buffer_info
->skb
;
1216 prefetch(skb
->data
);
1217 rx_buffer_info
->skb
= NULL
;
1219 if (rx_buffer_info
->dma
) {
1220 if ((adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
1221 (!(staterr
& IXGBE_RXD_STAT_EOP
)) &&
1224 * When HWRSC is enabled, delay unmapping
1225 * of the first packet. It carries the
1226 * header information, HW may still
1227 * access the header after the writeback.
1228 * Only unmap it when EOP is reached
1230 IXGBE_RSC_CB(skb
)->delay_unmap
= true;
1231 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
1233 dma_unmap_single(&pdev
->dev
,
1234 rx_buffer_info
->dma
,
1235 rx_ring
->rx_buf_len
,
1238 rx_buffer_info
->dma
= 0;
1243 dma_unmap_page(&pdev
->dev
, rx_buffer_info
->page_dma
,
1244 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
1245 rx_buffer_info
->page_dma
= 0;
1246 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1247 rx_buffer_info
->page
,
1248 rx_buffer_info
->page_offset
,
1251 if ((rx_ring
->rx_buf_len
> (PAGE_SIZE
/ 2)) ||
1252 (page_count(rx_buffer_info
->page
) != 1))
1253 rx_buffer_info
->page
= NULL
;
1255 get_page(rx_buffer_info
->page
);
1257 skb
->len
+= upper_len
;
1258 skb
->data_len
+= upper_len
;
1259 skb
->truesize
+= upper_len
;
1263 if (i
== rx_ring
->count
)
1266 next_rxd
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
1270 if (adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)
1271 rsc_count
= ixgbe_get_rsc_count(rx_desc
);
1274 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
1275 IXGBE_RXDADV_NEXTP_SHIFT
;
1276 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
1278 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
1281 if (staterr
& IXGBE_RXD_STAT_EOP
) {
1283 skb
= ixgbe_transform_rsc_queue(skb
, &(rx_ring
->rsc_count
));
1284 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
1285 if (IXGBE_RSC_CB(skb
)->delay_unmap
) {
1286 dma_unmap_single(&pdev
->dev
,
1287 IXGBE_RSC_CB(skb
)->dma
,
1288 rx_ring
->rx_buf_len
,
1290 IXGBE_RSC_CB(skb
)->dma
= 0;
1291 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
1293 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)
1294 rx_ring
->rsc_count
+= skb_shinfo(skb
)->nr_frags
;
1296 rx_ring
->rsc_count
++;
1297 rx_ring
->rsc_flush
++;
1299 rx_ring
->stats
.packets
++;
1300 rx_ring
->stats
.bytes
+= skb
->len
;
1302 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1303 rx_buffer_info
->skb
= next_buffer
->skb
;
1304 rx_buffer_info
->dma
= next_buffer
->dma
;
1305 next_buffer
->skb
= skb
;
1306 next_buffer
->dma
= 0;
1308 skb
->next
= next_buffer
->skb
;
1309 skb
->next
->prev
= skb
;
1311 rx_ring
->non_eop_descs
++;
1315 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
1316 dev_kfree_skb_irq(skb
);
1320 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
1322 /* probably a little skewed due to removing CRC */
1323 total_rx_bytes
+= skb
->len
;
1326 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
1328 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1329 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1330 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
1334 #endif /* IXGBE_FCOE */
1335 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
1338 rx_desc
->wb
.upper
.status_error
= 0;
1340 /* return some buffers to hardware, one at a time is too slow */
1341 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
1342 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
1346 /* use prefetched values */
1348 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1350 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1353 rx_ring
->next_to_clean
= i
;
1354 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
1357 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
1360 /* include DDPed FCoE data */
1361 if (ddp_bytes
> 0) {
1364 mss
= adapter
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1365 sizeof(struct fc_frame_header
) -
1366 sizeof(struct fcoe_crc_eof
);
1369 total_rx_bytes
+= ddp_bytes
;
1370 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1372 #endif /* IXGBE_FCOE */
1374 rx_ring
->total_packets
+= total_rx_packets
;
1375 rx_ring
->total_bytes
+= total_rx_bytes
;
1376 netdev
->stats
.rx_bytes
+= total_rx_bytes
;
1377 netdev
->stats
.rx_packets
+= total_rx_packets
;
1382 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1384 * ixgbe_configure_msix - Configure MSI-X hardware
1385 * @adapter: board private structure
1387 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1390 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1392 struct ixgbe_q_vector
*q_vector
;
1393 int i
, j
, q_vectors
, v_idx
, r_idx
;
1396 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1399 * Populate the IVAR table and set the ITR values to the
1400 * corresponding register.
1402 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1403 q_vector
= adapter
->q_vector
[v_idx
];
1404 /* XXX for_each_set_bit(...) */
1405 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1406 adapter
->num_rx_queues
);
1408 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1409 j
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1410 ixgbe_set_ivar(adapter
, 0, j
, v_idx
);
1411 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1412 adapter
->num_rx_queues
,
1415 r_idx
= find_first_bit(q_vector
->txr_idx
,
1416 adapter
->num_tx_queues
);
1418 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1419 j
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1420 ixgbe_set_ivar(adapter
, 1, j
, v_idx
);
1421 r_idx
= find_next_bit(q_vector
->txr_idx
,
1422 adapter
->num_tx_queues
,
1426 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1428 q_vector
->eitr
= adapter
->tx_eitr_param
;
1429 else if (q_vector
->rxr_count
)
1431 q_vector
->eitr
= adapter
->rx_eitr_param
;
1433 ixgbe_write_eitr(q_vector
);
1436 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
1437 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1439 else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
1440 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1441 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1443 /* set up to autoclear timer, and the vectors */
1444 mask
= IXGBE_EIMS_ENABLE_MASK
;
1445 if (adapter
->num_vfs
)
1446 mask
&= ~(IXGBE_EIMS_OTHER
|
1447 IXGBE_EIMS_MAILBOX
|
1450 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1451 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1454 enum latency_range
{
1458 latency_invalid
= 255
1462 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1463 * @adapter: pointer to adapter
1464 * @eitr: eitr setting (ints per sec) to give last timeslice
1465 * @itr_setting: current throttle rate in ints/second
1466 * @packets: the number of packets during this measurement interval
1467 * @bytes: the number of bytes during this measurement interval
1469 * Stores a new ITR value based on packets and byte
1470 * counts during the last interrupt. The advantage of per interrupt
1471 * computation is faster updates and more accurate ITR for the current
1472 * traffic pattern. Constants in this function were computed
1473 * based on theoretical maximum wire speed and thresholds were set based
1474 * on testing data as well as attempting to minimize response time
1475 * while increasing bulk throughput.
1476 * this functionality is controlled by the InterruptThrottleRate module
1477 * parameter (see ixgbe_param.c)
1479 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1480 u32 eitr
, u8 itr_setting
,
1481 int packets
, int bytes
)
1483 unsigned int retval
= itr_setting
;
1488 goto update_itr_done
;
1491 /* simple throttlerate management
1492 * 0-20MB/s lowest (100000 ints/s)
1493 * 20-100MB/s low (20000 ints/s)
1494 * 100-1249MB/s bulk (8000 ints/s)
1496 /* what was last interrupt timeslice? */
1497 timepassed_us
= 1000000/eitr
;
1498 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1500 switch (itr_setting
) {
1501 case lowest_latency
:
1502 if (bytes_perint
> adapter
->eitr_low
)
1503 retval
= low_latency
;
1506 if (bytes_perint
> adapter
->eitr_high
)
1507 retval
= bulk_latency
;
1508 else if (bytes_perint
<= adapter
->eitr_low
)
1509 retval
= lowest_latency
;
1512 if (bytes_perint
<= adapter
->eitr_high
)
1513 retval
= low_latency
;
1522 * ixgbe_write_eitr - write EITR register in hardware specific way
1523 * @q_vector: structure containing interrupt and ring information
1525 * This function is made to be called by ethtool and by the driver
1526 * when it needs to update EITR registers at runtime. Hardware
1527 * specific quirks/differences are taken care of here.
1529 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1531 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1532 struct ixgbe_hw
*hw
= &adapter
->hw
;
1533 int v_idx
= q_vector
->v_idx
;
1534 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1536 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1537 /* must write high and low 16 bits to reset counter */
1538 itr_reg
|= (itr_reg
<< 16);
1539 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1541 * 82599 can support a value of zero, so allow it for
1542 * max interrupt rate, but there is an errata where it can
1543 * not be zero with RSC
1546 !(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
1550 * set the WDIS bit to not clear the timer bits and cause an
1551 * immediate assertion of the interrupt
1553 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1555 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1558 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1560 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1562 u8 current_itr
, ret_itr
;
1564 struct ixgbe_ring
*rx_ring
, *tx_ring
;
1566 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1567 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1568 tx_ring
= adapter
->tx_ring
[r_idx
];
1569 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1571 tx_ring
->total_packets
,
1572 tx_ring
->total_bytes
);
1573 /* if the result for this queue would decrease interrupt
1574 * rate for this vector then use that result */
1575 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1576 q_vector
->tx_itr
- 1 : ret_itr
);
1577 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1581 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1582 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1583 rx_ring
= adapter
->rx_ring
[r_idx
];
1584 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1586 rx_ring
->total_packets
,
1587 rx_ring
->total_bytes
);
1588 /* if the result for this queue would decrease interrupt
1589 * rate for this vector then use that result */
1590 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1591 q_vector
->rx_itr
- 1 : ret_itr
);
1592 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1596 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1598 switch (current_itr
) {
1599 /* counts and packets in update_itr are dependent on these numbers */
1600 case lowest_latency
:
1604 new_itr
= 20000; /* aka hwitr = ~200 */
1612 if (new_itr
!= q_vector
->eitr
) {
1613 /* do an exponential smoothing */
1614 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1616 /* save the algorithm value here, not the smoothed one */
1617 q_vector
->eitr
= new_itr
;
1619 ixgbe_write_eitr(q_vector
);
1624 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1625 * @work: pointer to work_struct containing our data
1627 static void ixgbe_check_overtemp_task(struct work_struct
*work
)
1629 struct ixgbe_adapter
*adapter
= container_of(work
,
1630 struct ixgbe_adapter
,
1631 check_overtemp_task
);
1632 struct ixgbe_hw
*hw
= &adapter
->hw
;
1633 u32 eicr
= adapter
->interrupt_event
;
1635 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) {
1636 switch (hw
->device_id
) {
1637 case IXGBE_DEV_ID_82599_T3_LOM
: {
1639 bool link_up
= false;
1641 if (hw
->mac
.ops
.check_link
)
1642 hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
1644 if (((eicr
& IXGBE_EICR_GPI_SDP0
) && (!link_up
)) ||
1645 (eicr
& IXGBE_EICR_LSC
))
1646 /* Check if this is due to overtemp */
1647 if (hw
->phy
.ops
.check_overtemp(hw
) == IXGBE_ERR_OVERTEMP
)
1652 if (!(eicr
& IXGBE_EICR_GPI_SDP0
))
1656 e_crit(drv
, "Network adapter has been stopped because it has "
1657 "over heated. Restart the computer. If the problem "
1658 "persists, power off the system and replace the "
1660 /* write to clear the interrupt */
1661 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP0
);
1665 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1667 struct ixgbe_hw
*hw
= &adapter
->hw
;
1669 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1670 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1671 e_crit(probe
, "Fan has stopped, replace the adapter\n");
1672 /* write to clear the interrupt */
1673 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1677 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1679 struct ixgbe_hw
*hw
= &adapter
->hw
;
1681 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1682 /* Clear the interrupt */
1683 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1684 schedule_work(&adapter
->multispeed_fiber_task
);
1685 } else if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1686 /* Clear the interrupt */
1687 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1688 schedule_work(&adapter
->sfp_config_module_task
);
1690 /* Interrupt isn't for us... */
1695 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1697 struct ixgbe_hw
*hw
= &adapter
->hw
;
1700 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1701 adapter
->link_check_timeout
= jiffies
;
1702 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1703 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1704 IXGBE_WRITE_FLUSH(hw
);
1705 schedule_work(&adapter
->watchdog_task
);
1709 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1711 struct net_device
*netdev
= data
;
1712 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1713 struct ixgbe_hw
*hw
= &adapter
->hw
;
1717 * Workaround for Silicon errata. Use clear-by-write instead
1718 * of clear-by-read. Reading with EICS will return the
1719 * interrupt causes without clearing, which later be done
1720 * with the write to EICR.
1722 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1723 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1725 if (eicr
& IXGBE_EICR_LSC
)
1726 ixgbe_check_lsc(adapter
);
1728 if (eicr
& IXGBE_EICR_MAILBOX
)
1729 ixgbe_msg_task(adapter
);
1731 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1732 ixgbe_check_fan_failure(adapter
, eicr
);
1734 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1735 ixgbe_check_sfp_event(adapter
, eicr
);
1736 adapter
->interrupt_event
= eicr
;
1737 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1738 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
)))
1739 schedule_work(&adapter
->check_overtemp_task
);
1741 /* Handle Flow Director Full threshold interrupt */
1742 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1744 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_FLOW_DIR
);
1745 /* Disable transmits before FDIR Re-initialization */
1746 netif_tx_stop_all_queues(netdev
);
1747 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1748 struct ixgbe_ring
*tx_ring
=
1749 adapter
->tx_ring
[i
];
1750 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE
,
1751 &tx_ring
->reinit_state
))
1752 schedule_work(&adapter
->fdir_reinit_task
);
1756 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1757 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1762 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1767 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1768 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1769 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1771 mask
= (qmask
& 0xFFFFFFFF);
1772 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(0), mask
);
1773 mask
= (qmask
>> 32);
1774 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(1), mask
);
1776 /* skip the flush */
1779 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1784 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1785 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1786 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, mask
);
1788 mask
= (qmask
& 0xFFFFFFFF);
1789 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), mask
);
1790 mask
= (qmask
>> 32);
1791 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), mask
);
1793 /* skip the flush */
1796 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1798 struct ixgbe_q_vector
*q_vector
= data
;
1799 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1800 struct ixgbe_ring
*tx_ring
;
1803 if (!q_vector
->txr_count
)
1806 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1807 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1808 tx_ring
= adapter
->tx_ring
[r_idx
];
1809 tx_ring
->total_bytes
= 0;
1810 tx_ring
->total_packets
= 0;
1811 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1815 /* EIAM disabled interrupts (on this vector) for us */
1816 napi_schedule(&q_vector
->napi
);
1822 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1824 * @data: pointer to our q_vector struct for this interrupt vector
1826 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
1828 struct ixgbe_q_vector
*q_vector
= data
;
1829 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1830 struct ixgbe_ring
*rx_ring
;
1834 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1835 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1836 rx_ring
= adapter
->rx_ring
[r_idx
];
1837 rx_ring
->total_bytes
= 0;
1838 rx_ring
->total_packets
= 0;
1839 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1843 if (!q_vector
->rxr_count
)
1846 /* disable interrupts on this vector only */
1847 /* EIAM disabled interrupts (on this vector) for us */
1848 napi_schedule(&q_vector
->napi
);
1853 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
1855 struct ixgbe_q_vector
*q_vector
= data
;
1856 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1857 struct ixgbe_ring
*ring
;
1861 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
1864 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1865 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1866 ring
= adapter
->tx_ring
[r_idx
];
1867 ring
->total_bytes
= 0;
1868 ring
->total_packets
= 0;
1869 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1873 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1874 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1875 ring
= adapter
->rx_ring
[r_idx
];
1876 ring
->total_bytes
= 0;
1877 ring
->total_packets
= 0;
1878 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1882 /* EIAM disabled interrupts (on this vector) for us */
1883 napi_schedule(&q_vector
->napi
);
1889 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1890 * @napi: napi struct with our devices info in it
1891 * @budget: amount of work driver is allowed to do this pass, in packets
1893 * This function is optimized for cleaning one queue only on a single
1896 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
1898 struct ixgbe_q_vector
*q_vector
=
1899 container_of(napi
, struct ixgbe_q_vector
, napi
);
1900 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1901 struct ixgbe_ring
*rx_ring
= NULL
;
1905 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1906 rx_ring
= adapter
->rx_ring
[r_idx
];
1907 #ifdef CONFIG_IXGBE_DCA
1908 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1909 ixgbe_update_rx_dca(adapter
, rx_ring
);
1912 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1914 /* If all Rx work done, exit the polling mode */
1915 if (work_done
< budget
) {
1916 napi_complete(napi
);
1917 if (adapter
->rx_itr_setting
& 1)
1918 ixgbe_set_itr_msix(q_vector
);
1919 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1920 ixgbe_irq_enable_queues(adapter
,
1921 ((u64
)1 << q_vector
->v_idx
));
1928 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1929 * @napi: napi struct with our devices info in it
1930 * @budget: amount of work driver is allowed to do this pass, in packets
1932 * This function will clean more than one rx queue associated with a
1935 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
1937 struct ixgbe_q_vector
*q_vector
=
1938 container_of(napi
, struct ixgbe_q_vector
, napi
);
1939 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1940 struct ixgbe_ring
*ring
= NULL
;
1941 int work_done
= 0, i
;
1943 bool tx_clean_complete
= true;
1945 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1946 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1947 ring
= adapter
->tx_ring
[r_idx
];
1948 #ifdef CONFIG_IXGBE_DCA
1949 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1950 ixgbe_update_tx_dca(adapter
, ring
);
1952 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
1953 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1957 /* attempt to distribute budget to each queue fairly, but don't allow
1958 * the budget to go below 1 because we'll exit polling */
1959 budget
/= (q_vector
->rxr_count
?: 1);
1960 budget
= max(budget
, 1);
1961 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1962 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1963 ring
= adapter
->rx_ring
[r_idx
];
1964 #ifdef CONFIG_IXGBE_DCA
1965 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1966 ixgbe_update_rx_dca(adapter
, ring
);
1968 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
1969 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1973 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1974 ring
= adapter
->rx_ring
[r_idx
];
1975 /* If all Rx work done, exit the polling mode */
1976 if (work_done
< budget
) {
1977 napi_complete(napi
);
1978 if (adapter
->rx_itr_setting
& 1)
1979 ixgbe_set_itr_msix(q_vector
);
1980 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1981 ixgbe_irq_enable_queues(adapter
,
1982 ((u64
)1 << q_vector
->v_idx
));
1990 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1991 * @napi: napi struct with our devices info in it
1992 * @budget: amount of work driver is allowed to do this pass, in packets
1994 * This function is optimized for cleaning one queue only on a single
1997 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
1999 struct ixgbe_q_vector
*q_vector
=
2000 container_of(napi
, struct ixgbe_q_vector
, napi
);
2001 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2002 struct ixgbe_ring
*tx_ring
= NULL
;
2006 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2007 tx_ring
= adapter
->tx_ring
[r_idx
];
2008 #ifdef CONFIG_IXGBE_DCA
2009 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2010 ixgbe_update_tx_dca(adapter
, tx_ring
);
2013 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
2016 /* If all Tx work done, exit the polling mode */
2017 if (work_done
< budget
) {
2018 napi_complete(napi
);
2019 if (adapter
->tx_itr_setting
& 1)
2020 ixgbe_set_itr_msix(q_vector
);
2021 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2022 ixgbe_irq_enable_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
2028 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
2031 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2033 set_bit(r_idx
, q_vector
->rxr_idx
);
2034 q_vector
->rxr_count
++;
2037 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
2040 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2042 set_bit(t_idx
, q_vector
->txr_idx
);
2043 q_vector
->txr_count
++;
2047 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2048 * @adapter: board private structure to initialize
2049 * @vectors: allotted vector count for descriptor rings
2051 * This function maps descriptor rings to the queue-specific vectors
2052 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2053 * one vector per ring/queue, but on a constrained vector budget, we
2054 * group the rings as "efficiently" as possible. You would add new
2055 * mapping configurations in here.
2057 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
,
2061 int rxr_idx
= 0, txr_idx
= 0;
2062 int rxr_remaining
= adapter
->num_rx_queues
;
2063 int txr_remaining
= adapter
->num_tx_queues
;
2068 /* No mapping required if MSI-X is disabled. */
2069 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2073 * The ideal configuration...
2074 * We have enough vectors to map one per queue.
2076 if (vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
2077 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
2078 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
2080 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
2081 map_vector_to_txq(adapter
, v_start
, txr_idx
);
2087 * If we don't have enough vectors for a 1-to-1
2088 * mapping, we'll have to group them so there are
2089 * multiple queues per vector.
2091 /* Re-adjusting *qpv takes care of the remainder. */
2092 for (i
= v_start
; i
< vectors
; i
++) {
2093 rqpv
= DIV_ROUND_UP(rxr_remaining
, vectors
- i
);
2094 for (j
= 0; j
< rqpv
; j
++) {
2095 map_vector_to_rxq(adapter
, i
, rxr_idx
);
2100 for (i
= v_start
; i
< vectors
; i
++) {
2101 tqpv
= DIV_ROUND_UP(txr_remaining
, vectors
- i
);
2102 for (j
= 0; j
< tqpv
; j
++) {
2103 map_vector_to_txq(adapter
, i
, txr_idx
);
2114 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2115 * @adapter: board private structure
2117 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2118 * interrupts from the kernel.
2120 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
2122 struct net_device
*netdev
= adapter
->netdev
;
2123 irqreturn_t (*handler
)(int, void *);
2124 int i
, vector
, q_vectors
, err
;
2127 /* Decrement for Other and TCP Timer vectors */
2128 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2130 /* Map the Tx/Rx rings to the vectors we were allotted. */
2131 err
= ixgbe_map_rings_to_vectors(adapter
, q_vectors
);
2135 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2136 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2137 &ixgbe_msix_clean_many)
2138 for (vector
= 0; vector
< q_vectors
; vector
++) {
2139 handler
= SET_HANDLER(adapter
->q_vector
[vector
]);
2141 if(handler
== &ixgbe_msix_clean_rx
) {
2142 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2143 netdev
->name
, "rx", ri
++);
2145 else if(handler
== &ixgbe_msix_clean_tx
) {
2146 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2147 netdev
->name
, "tx", ti
++);
2150 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2151 netdev
->name
, "TxRx", vector
);
2153 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2154 handler
, 0, adapter
->name
[vector
],
2155 adapter
->q_vector
[vector
]);
2157 e_err(probe
, "request_irq failed for MSIX interrupt "
2158 "Error: %d\n", err
);
2159 goto free_queue_irqs
;
2163 sprintf(adapter
->name
[vector
], "%s:lsc", netdev
->name
);
2164 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2165 ixgbe_msix_lsc
, 0, adapter
->name
[vector
], netdev
);
2167 e_err(probe
, "request_irq for msix_lsc failed: %d\n", err
);
2168 goto free_queue_irqs
;
2174 for (i
= vector
- 1; i
>= 0; i
--)
2175 free_irq(adapter
->msix_entries
[--vector
].vector
,
2176 adapter
->q_vector
[i
]);
2177 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2178 pci_disable_msix(adapter
->pdev
);
2179 kfree(adapter
->msix_entries
);
2180 adapter
->msix_entries
= NULL
;
2185 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
2187 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2189 u32 new_itr
= q_vector
->eitr
;
2190 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[0];
2191 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[0];
2193 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2195 tx_ring
->total_packets
,
2196 tx_ring
->total_bytes
);
2197 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2199 rx_ring
->total_packets
,
2200 rx_ring
->total_bytes
);
2202 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
2204 switch (current_itr
) {
2205 /* counts and packets in update_itr are dependent on these numbers */
2206 case lowest_latency
:
2210 new_itr
= 20000; /* aka hwitr = ~200 */
2219 if (new_itr
!= q_vector
->eitr
) {
2220 /* do an exponential smoothing */
2221 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
2223 /* save the algorithm value here, not the smoothed one */
2224 q_vector
->eitr
= new_itr
;
2226 ixgbe_write_eitr(q_vector
);
2231 * ixgbe_irq_enable - Enable default interrupt generation settings
2232 * @adapter: board private structure
2234 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
)
2238 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
2239 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
2240 mask
|= IXGBE_EIMS_GPI_SDP0
;
2241 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
2242 mask
|= IXGBE_EIMS_GPI_SDP1
;
2243 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
2244 mask
|= IXGBE_EIMS_ECC
;
2245 mask
|= IXGBE_EIMS_GPI_SDP1
;
2246 mask
|= IXGBE_EIMS_GPI_SDP2
;
2247 if (adapter
->num_vfs
)
2248 mask
|= IXGBE_EIMS_MAILBOX
;
2250 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
2251 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
2252 mask
|= IXGBE_EIMS_FLOW_DIR
;
2254 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
2255 ixgbe_irq_enable_queues(adapter
, ~0);
2256 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2258 if (adapter
->num_vfs
> 32) {
2259 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
2260 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
2265 * ixgbe_intr - legacy mode Interrupt Handler
2266 * @irq: interrupt number
2267 * @data: pointer to a network interface device structure
2269 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
2271 struct net_device
*netdev
= data
;
2272 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2273 struct ixgbe_hw
*hw
= &adapter
->hw
;
2274 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2278 * Workaround for silicon errata. Mask the interrupts
2279 * before the read of EICR.
2281 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
2283 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2284 * therefore no explict interrupt disable is necessary */
2285 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
2287 /* shared interrupt alert!
2288 * make sure interrupts are enabled because the read will
2289 * have disabled interrupts due to EIAM */
2290 ixgbe_irq_enable(adapter
);
2291 return IRQ_NONE
; /* Not our interrupt */
2294 if (eicr
& IXGBE_EICR_LSC
)
2295 ixgbe_check_lsc(adapter
);
2297 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2298 ixgbe_check_sfp_event(adapter
, eicr
);
2300 ixgbe_check_fan_failure(adapter
, eicr
);
2301 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
2302 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
)))
2303 schedule_work(&adapter
->check_overtemp_task
);
2305 if (napi_schedule_prep(&(q_vector
->napi
))) {
2306 adapter
->tx_ring
[0]->total_packets
= 0;
2307 adapter
->tx_ring
[0]->total_bytes
= 0;
2308 adapter
->rx_ring
[0]->total_packets
= 0;
2309 adapter
->rx_ring
[0]->total_bytes
= 0;
2310 /* would disable interrupts here but EIAM disabled it */
2311 __napi_schedule(&(q_vector
->napi
));
2317 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
2319 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2321 for (i
= 0; i
< q_vectors
; i
++) {
2322 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
2323 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
2324 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
2325 q_vector
->rxr_count
= 0;
2326 q_vector
->txr_count
= 0;
2331 * ixgbe_request_irq - initialize interrupts
2332 * @adapter: board private structure
2334 * Attempts to configure interrupts using the best available
2335 * capabilities of the hardware and kernel.
2337 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
2339 struct net_device
*netdev
= adapter
->netdev
;
2342 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2343 err
= ixgbe_request_msix_irqs(adapter
);
2344 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
2345 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
2346 netdev
->name
, netdev
);
2348 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
2349 netdev
->name
, netdev
);
2353 e_err(probe
, "request_irq failed, Error %d\n", err
);
2358 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
2360 struct net_device
*netdev
= adapter
->netdev
;
2362 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2365 q_vectors
= adapter
->num_msix_vectors
;
2368 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
2371 for (; i
>= 0; i
--) {
2372 free_irq(adapter
->msix_entries
[i
].vector
,
2373 adapter
->q_vector
[i
]);
2376 ixgbe_reset_q_vectors(adapter
);
2378 free_irq(adapter
->pdev
->irq
, netdev
);
2383 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2384 * @adapter: board private structure
2386 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
2388 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2389 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2391 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2392 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2393 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2394 if (adapter
->num_vfs
> 32)
2395 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
2397 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2398 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2400 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2401 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2403 synchronize_irq(adapter
->pdev
->irq
);
2408 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2411 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2413 struct ixgbe_hw
*hw
= &adapter
->hw
;
2415 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2416 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2418 ixgbe_set_ivar(adapter
, 0, 0, 0);
2419 ixgbe_set_ivar(adapter
, 1, 0, 0);
2421 map_vector_to_rxq(adapter
, 0, 0);
2422 map_vector_to_txq(adapter
, 0, 0);
2424 e_info(hw
, "Legacy interrupt IVAR setup done\n");
2428 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2429 * @adapter: board private structure
2430 * @ring: structure containing ring specific data
2432 * Configure the Tx descriptor ring after a reset.
2434 static void ixgbe_configure_tx_ring(struct ixgbe_adapter
*adapter
,
2435 struct ixgbe_ring
*ring
)
2437 struct ixgbe_hw
*hw
= &adapter
->hw
;
2438 u64 tdba
= ring
->dma
;
2439 u16 reg_idx
= ring
->reg_idx
;
2441 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(reg_idx
),
2442 (tdba
& DMA_BIT_MASK(32)));
2443 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(reg_idx
), (tdba
>> 32));
2444 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(reg_idx
),
2445 ring
->count
* sizeof(union ixgbe_adv_tx_desc
));
2446 IXGBE_WRITE_REG(hw
, IXGBE_TDH(reg_idx
), 0);
2447 IXGBE_WRITE_REG(hw
, IXGBE_TDT(reg_idx
), 0);
2448 ring
->head
= IXGBE_TDH(reg_idx
);
2449 ring
->tail
= IXGBE_TDT(reg_idx
);
2453 static void ixgbe_setup_mtqc(struct ixgbe_adapter
*adapter
)
2455 struct ixgbe_hw
*hw
= &adapter
->hw
;
2459 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2462 /* disable the arbiter while setting MTQC */
2463 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2464 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2465 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2467 /* set transmit pool layout */
2468 mask
= (IXGBE_FLAG_SRIOV_ENABLED
| IXGBE_FLAG_DCB_ENABLED
);
2469 switch (adapter
->flags
& mask
) {
2471 case (IXGBE_FLAG_SRIOV_ENABLED
):
2472 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2473 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2476 case (IXGBE_FLAG_DCB_ENABLED
):
2477 /* We enable 8 traffic classes, DCB only */
2478 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2479 (IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
));
2483 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2487 /* re-enable the arbiter */
2488 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2489 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2493 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2494 * @adapter: board private structure
2496 * Configure the Tx unit of the MAC after a reset.
2498 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2502 /* Setup the HW Tx Head and Tail descriptor pointers */
2503 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2504 ixgbe_configure_tx_ring(adapter
, adapter
->tx_ring
[i
]);
2506 ixgbe_setup_mtqc(adapter
);
2509 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2511 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2512 struct ixgbe_ring
*rx_ring
)
2516 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2518 index
= rx_ring
->reg_idx
;
2519 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2521 mask
= (unsigned long) feature
[RING_F_RSS
].mask
;
2522 index
= index
& mask
;
2524 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(index
));
2526 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2527 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2529 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2530 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2532 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2533 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2534 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2536 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2538 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2540 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2541 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2542 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2545 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(index
), srrctl
);
2548 static void ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2550 struct ixgbe_hw
*hw
= &adapter
->hw
;
2551 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2552 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2553 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2554 u32 mrqc
= 0, reta
= 0;
2559 /* Fill out hash function seeds */
2560 for (i
= 0; i
< 10; i
++)
2561 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2563 /* Fill out redirection table */
2564 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2565 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2567 /* reta = 4-byte sliding window of
2568 * 0x00..(indices-1)(indices-1)00..etc. */
2569 reta
= (reta
<< 8) | (j
* 0x11);
2571 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2574 /* Disable indicating checksum in descriptor, enables RSS hash */
2575 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2576 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2577 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2579 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
2580 mask
= adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
;
2582 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2583 #ifdef CONFIG_IXGBE_DCB
2584 | IXGBE_FLAG_DCB_ENABLED
2586 | IXGBE_FLAG_SRIOV_ENABLED
2590 case (IXGBE_FLAG_RSS_ENABLED
):
2591 mrqc
= IXGBE_MRQC_RSSEN
;
2593 case (IXGBE_FLAG_SRIOV_ENABLED
):
2594 mrqc
= IXGBE_MRQC_VMDQEN
;
2596 #ifdef CONFIG_IXGBE_DCB
2597 case (IXGBE_FLAG_DCB_ENABLED
):
2598 mrqc
= IXGBE_MRQC_RT8TCEN
;
2600 #endif /* CONFIG_IXGBE_DCB */
2605 /* Perform hash on these packet types */
2606 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2607 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2608 | IXGBE_MRQC_RSS_FIELD_IPV6
2609 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
;
2611 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2615 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2616 * @adapter: address of board private structure
2617 * @index: index of ring to set
2619 static void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
, int index
)
2621 struct ixgbe_ring
*rx_ring
;
2622 struct ixgbe_hw
*hw
= &adapter
->hw
;
2627 rx_ring
= adapter
->rx_ring
[index
];
2628 j
= rx_ring
->reg_idx
;
2629 rx_buf_len
= rx_ring
->rx_buf_len
;
2630 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(j
));
2631 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2633 * we must limit the number of descriptors so that the
2634 * total size of max desc * buf_len is not greater
2637 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2638 #if (MAX_SKB_FRAGS > 16)
2639 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2640 #elif (MAX_SKB_FRAGS > 8)
2641 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2642 #elif (MAX_SKB_FRAGS > 4)
2643 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2645 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2648 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2649 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2650 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2651 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2653 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2655 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(j
), rscctrl
);
2658 static void ixgbe_configure_rx_ring(struct ixgbe_adapter
*adapter
,
2659 struct ixgbe_ring
*ring
)
2661 struct ixgbe_hw
*hw
= &adapter
->hw
;
2662 u64 rdba
= ring
->dma
;
2663 u16 reg_idx
= ring
->reg_idx
;
2665 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(reg_idx
), (rdba
& DMA_BIT_MASK(32)));
2666 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(reg_idx
), (rdba
>> 32));
2667 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(reg_idx
),
2668 ring
->count
* sizeof(union ixgbe_adv_rx_desc
));
2669 IXGBE_WRITE_REG(hw
, IXGBE_RDH(reg_idx
), 0);
2670 IXGBE_WRITE_REG(hw
, IXGBE_RDT(reg_idx
), 0);
2671 ring
->head
= IXGBE_RDH(reg_idx
);
2672 ring
->tail
= IXGBE_RDT(reg_idx
);
2675 static void ixgbe_setup_psrtype(struct ixgbe_adapter
*adapter
)
2677 struct ixgbe_hw
*hw
= &adapter
->hw
;
2680 /* PSRTYPE must be initialized in non 82598 adapters */
2681 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
2682 IXGBE_PSRTYPE_UDPHDR
|
2683 IXGBE_PSRTYPE_IPV4HDR
|
2684 IXGBE_PSRTYPE_L2HDR
|
2685 IXGBE_PSRTYPE_IPV6HDR
;
2687 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2690 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)
2691 psrtype
|= (adapter
->num_rx_queues_per_pool
<< 29);
2693 for (p
= 0; p
< adapter
->num_rx_pools
; p
++)
2694 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(adapter
->num_vfs
+ p
),
2698 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter
*adapter
)
2700 struct ixgbe_hw
*hw
= &adapter
->hw
;
2701 struct net_device
*netdev
= adapter
->netdev
;
2702 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2704 struct ixgbe_ring
*rx_ring
;
2708 /* Decide whether to use packet split mode or not */
2709 /* Do not use packet split if we're in SR-IOV Mode */
2710 if (!adapter
->num_vfs
)
2711 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
2713 /* Set the RX buffer length according to the mode */
2714 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
2715 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
2717 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
2718 (netdev
->mtu
<= ETH_DATA_LEN
))
2719 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
2721 rx_buf_len
= ALIGN(max_frame
+ VLAN_HLEN
, 1024);
2725 /* adjust max frame to be able to do baby jumbo for FCoE */
2726 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
2727 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
2728 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2730 #endif /* IXGBE_FCOE */
2731 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
2732 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
2733 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
2734 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
2736 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
2739 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2740 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2741 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2742 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
2745 * Setup the HW Rx Head and Tail Descriptor Pointers and
2746 * the Base and Length of the Rx Descriptor Ring
2748 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2749 rx_ring
= adapter
->rx_ring
[i
];
2750 rx_ring
->rx_buf_len
= rx_buf_len
;
2752 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
2753 rx_ring
->flags
|= IXGBE_RING_RX_PS_ENABLED
;
2755 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2758 if (netdev
->features
& NETIF_F_FCOE_MTU
)
2760 struct ixgbe_ring_feature
*f
;
2761 f
= &adapter
->ring_feature
[RING_F_FCOE
];
2762 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
2763 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2764 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
2765 rx_ring
->rx_buf_len
=
2766 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2769 #endif /* IXGBE_FCOE */
2775 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2776 * @adapter: board private structure
2778 * Configure the Rx unit of the MAC after a reset.
2780 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
2782 struct ixgbe_hw
*hw
= &adapter
->hw
;
2783 struct ixgbe_ring
*rx_ring
;
2789 /* disable receives while setting up the descriptors */
2790 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2791 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
2793 ixgbe_setup_psrtype(adapter
);
2795 /* set_rx_buffer_len must be called before ring initialization */
2796 ixgbe_set_rx_buffer_len(adapter
);
2799 * Setup the HW Rx Head and Tail Descriptor Pointers and
2800 * the Base and Length of the Rx Descriptor Ring
2802 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2803 rx_ring
= adapter
->rx_ring
[i
];
2804 ixgbe_configure_rx_ring(adapter
, rx_ring
);
2805 ixgbe_configure_srrctl(adapter
, rx_ring
);
2808 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2810 * For VMDq support of different descriptor types or
2811 * buffer sizes through the use of multiple SRRCTL
2812 * registers, RDRXCTL.MVMEN must be set to 1
2814 * also, the manual doesn't mention it clearly but DCA hints
2815 * will only use queue 0's tags unless this bit is set. Side
2816 * effects of setting this bit are only that SRRCTL must be
2817 * fully programmed [0..15]
2819 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2820 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
2821 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2824 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2826 u32 reg_offset
, vf_shift
;
2827 u32 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2828 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
2829 | IXGBE_VT_CTL_REPLEN
;
2830 vt_reg_bits
|= (adapter
->num_vfs
<<
2831 IXGBE_VT_CTL_POOL_SHIFT
);
2832 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
2833 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, 0);
2835 vf_shift
= adapter
->num_vfs
% 32;
2836 reg_offset
= adapter
->num_vfs
/ 32;
2837 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(0), 0);
2838 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(1), 0);
2839 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(0), 0);
2840 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(1), 0);
2841 /* Enable only the PF's pool for Tx/Rx */
2842 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
2843 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
2844 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2847 /* Program MRQC for the distribution of queues */
2848 ixgbe_setup_mrqc(adapter
);
2850 if (adapter
->num_vfs
) {
2851 /* Map PF MAC address in RAR Entry 0 to first pool
2853 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
2855 /* Set up VF register offsets for selected VT Mode, i.e.
2856 * 64 VFs for SR-IOV */
2857 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
2858 gcr_ext
|= IXGBE_GCR_EXT_SRIOV
;
2859 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
2862 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2863 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2864 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
2865 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
2866 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2869 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
2870 /* Enable 82599 HW-RSC */
2871 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2872 ixgbe_configure_rscctl(adapter
, i
);
2874 /* Disable RSC for ACK packets */
2875 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
2876 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
2880 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
2882 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2883 struct ixgbe_hw
*hw
= &adapter
->hw
;
2884 int pool_ndx
= adapter
->num_vfs
;
2886 /* add VID to filter table */
2887 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
2890 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
2892 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2893 struct ixgbe_hw
*hw
= &adapter
->hw
;
2894 int pool_ndx
= adapter
->num_vfs
;
2896 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2897 ixgbe_irq_disable(adapter
);
2899 vlan_group_set_device(adapter
->vlgrp
, vid
, NULL
);
2901 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2902 ixgbe_irq_enable(adapter
);
2904 /* remove VID from filter table */
2905 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
2909 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2910 * @adapter: driver data
2912 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
2914 struct ixgbe_hw
*hw
= &adapter
->hw
;
2915 u32 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2918 switch (hw
->mac
.type
) {
2919 case ixgbe_mac_82598EB
:
2920 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
2921 #ifdef CONFIG_IXGBE_DCB
2922 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
2923 vlnctrl
&= ~IXGBE_VLNCTRL_VME
;
2925 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2926 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2928 case ixgbe_mac_82599EB
:
2929 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
2930 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2931 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2932 #ifdef CONFIG_IXGBE_DCB
2933 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
2936 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2937 j
= adapter
->rx_ring
[i
]->reg_idx
;
2938 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2939 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
2940 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2949 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2950 * @adapter: driver data
2952 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
2954 struct ixgbe_hw
*hw
= &adapter
->hw
;
2955 u32 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2958 switch (hw
->mac
.type
) {
2959 case ixgbe_mac_82598EB
:
2960 vlnctrl
|= IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
;
2961 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2962 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2964 case ixgbe_mac_82599EB
:
2965 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2966 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2967 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2968 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2969 j
= adapter
->rx_ring
[i
]->reg_idx
;
2970 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2971 vlnctrl
|= IXGBE_RXDCTL_VME
;
2972 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2980 static void ixgbe_vlan_rx_register(struct net_device
*netdev
,
2981 struct vlan_group
*grp
)
2983 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2985 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2986 ixgbe_irq_disable(adapter
);
2987 adapter
->vlgrp
= grp
;
2990 * For a DCB driver, always enable VLAN tag stripping so we can
2991 * still receive traffic from a DCB-enabled host even if we're
2994 ixgbe_vlan_filter_enable(adapter
);
2996 ixgbe_vlan_rx_add_vid(netdev
, 0);
2998 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2999 ixgbe_irq_enable(adapter
);
3002 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
3004 ixgbe_vlan_rx_register(adapter
->netdev
, adapter
->vlgrp
);
3006 if (adapter
->vlgrp
) {
3008 for (vid
= 0; vid
< VLAN_GROUP_ARRAY_LEN
; vid
++) {
3009 if (!vlan_group_get_device(adapter
->vlgrp
, vid
))
3011 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
3017 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3018 * @netdev: network interface device structure
3020 * Writes unicast address list to the RAR table.
3021 * Returns: -ENOMEM on failure/insufficient address space
3022 * 0 on no addresses written
3023 * X on writing X addresses to the RAR table
3025 static int ixgbe_write_uc_addr_list(struct net_device
*netdev
)
3027 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3028 struct ixgbe_hw
*hw
= &adapter
->hw
;
3029 unsigned int vfn
= adapter
->num_vfs
;
3030 unsigned int rar_entries
= hw
->mac
.num_rar_entries
- (vfn
+ 1);
3033 /* return ENOMEM indicating insufficient memory for addresses */
3034 if (netdev_uc_count(netdev
) > rar_entries
)
3037 if (!netdev_uc_empty(netdev
) && rar_entries
) {
3038 struct netdev_hw_addr
*ha
;
3039 /* return error if we do not support writing to RAR table */
3040 if (!hw
->mac
.ops
.set_rar
)
3043 netdev_for_each_uc_addr(ha
, netdev
) {
3046 hw
->mac
.ops
.set_rar(hw
, rar_entries
--, ha
->addr
,
3051 /* write the addresses in reverse order to avoid write combining */
3052 for (; rar_entries
> 0 ; rar_entries
--)
3053 hw
->mac
.ops
.clear_rar(hw
, rar_entries
);
3059 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3060 * @netdev: network interface device structure
3062 * The set_rx_method entry point is called whenever the unicast/multicast
3063 * address list or the network interface flags are updated. This routine is
3064 * responsible for configuring the hardware for proper unicast, multicast and
3067 void ixgbe_set_rx_mode(struct net_device
*netdev
)
3069 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3070 struct ixgbe_hw
*hw
= &adapter
->hw
;
3071 u32 fctrl
, vmolr
= IXGBE_VMOLR_BAM
| IXGBE_VMOLR_AUPE
;
3074 /* Check for Promiscuous and All Multicast modes */
3076 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
3078 /* set all bits that we expect to always be set */
3079 fctrl
|= IXGBE_FCTRL_BAM
;
3080 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
3081 fctrl
|= IXGBE_FCTRL_PMCF
;
3083 /* clear the bits we are changing the status of */
3084 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3086 if (netdev
->flags
& IFF_PROMISC
) {
3087 hw
->addr_ctrl
.user_set_promisc
= true;
3088 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3089 vmolr
|= (IXGBE_VMOLR_ROPE
| IXGBE_VMOLR_MPE
);
3090 /* don't hardware filter vlans in promisc mode */
3091 ixgbe_vlan_filter_disable(adapter
);
3093 if (netdev
->flags
& IFF_ALLMULTI
) {
3094 fctrl
|= IXGBE_FCTRL_MPE
;
3095 vmolr
|= IXGBE_VMOLR_MPE
;
3098 * Write addresses to the MTA, if the attempt fails
3099 * then we should just turn on promiscous mode so
3100 * that we can at least receive multicast traffic
3102 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
3103 vmolr
|= IXGBE_VMOLR_ROMPE
;
3105 ixgbe_vlan_filter_enable(adapter
);
3106 hw
->addr_ctrl
.user_set_promisc
= false;
3108 * Write addresses to available RAR registers, if there is not
3109 * sufficient space to store all the addresses then enable
3110 * unicast promiscous mode
3112 count
= ixgbe_write_uc_addr_list(netdev
);
3114 fctrl
|= IXGBE_FCTRL_UPE
;
3115 vmolr
|= IXGBE_VMOLR_ROPE
;
3119 if (adapter
->num_vfs
) {
3120 ixgbe_restore_vf_multicasts(adapter
);
3121 vmolr
|= IXGBE_READ_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
)) &
3122 ~(IXGBE_VMOLR_MPE
| IXGBE_VMOLR_ROMPE
|
3124 IXGBE_WRITE_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
), vmolr
);
3127 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
3130 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
3133 struct ixgbe_q_vector
*q_vector
;
3134 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3136 /* legacy and MSI only use one vector */
3137 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3140 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3141 struct napi_struct
*napi
;
3142 q_vector
= adapter
->q_vector
[q_idx
];
3143 napi
= &q_vector
->napi
;
3144 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3145 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
3146 if (q_vector
->txr_count
== 1)
3147 napi
->poll
= &ixgbe_clean_txonly
;
3148 else if (q_vector
->rxr_count
== 1)
3149 napi
->poll
= &ixgbe_clean_rxonly
;
3157 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
3160 struct ixgbe_q_vector
*q_vector
;
3161 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3163 /* legacy and MSI only use one vector */
3164 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3167 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3168 q_vector
= adapter
->q_vector
[q_idx
];
3169 napi_disable(&q_vector
->napi
);
3173 #ifdef CONFIG_IXGBE_DCB
3175 * ixgbe_configure_dcb - Configure DCB hardware
3176 * @adapter: ixgbe adapter struct
3178 * This is called by the driver on open to configure the DCB hardware.
3179 * This is also called by the gennetlink interface when reconfiguring
3182 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
3184 struct ixgbe_hw
*hw
= &adapter
->hw
;
3188 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)) {
3189 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3190 netif_set_gso_max_size(adapter
->netdev
, 65536);
3194 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3195 netif_set_gso_max_size(adapter
->netdev
, 32768);
3197 ixgbe_dcb_check_config(&adapter
->dcb_cfg
);
3198 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_TX_CONFIG
);
3199 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_RX_CONFIG
);
3201 /* reconfigure the hardware */
3202 ixgbe_dcb_hw_config(&adapter
->hw
, &adapter
->dcb_cfg
);
3204 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3205 j
= adapter
->tx_ring
[i
]->reg_idx
;
3206 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3207 /* PThresh workaround for Tx hang with DFP enabled. */
3209 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
3211 /* Enable VLAN tag insert/strip */
3212 ixgbe_vlan_filter_enable(adapter
);
3214 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
3218 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
3220 struct net_device
*netdev
= adapter
->netdev
;
3221 struct ixgbe_hw
*hw
= &adapter
->hw
;
3224 ixgbe_set_rx_mode(netdev
);
3226 ixgbe_restore_vlan(adapter
);
3227 #ifdef CONFIG_IXGBE_DCB
3228 ixgbe_configure_dcb(adapter
);
3232 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
3233 ixgbe_configure_fcoe(adapter
);
3235 #endif /* IXGBE_FCOE */
3236 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
3237 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3238 adapter
->tx_ring
[i
]->atr_sample_rate
=
3239 adapter
->atr_sample_rate
;
3240 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
3241 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
3242 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
3245 ixgbe_configure_tx(adapter
);
3246 ixgbe_configure_rx(adapter
);
3247 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3248 ixgbe_alloc_rx_buffers(adapter
, adapter
->rx_ring
[i
],
3249 (adapter
->rx_ring
[i
]->count
- 1));
3252 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
3254 switch (hw
->phy
.type
) {
3255 case ixgbe_phy_sfp_avago
:
3256 case ixgbe_phy_sfp_ftl
:
3257 case ixgbe_phy_sfp_intel
:
3258 case ixgbe_phy_sfp_unknown
:
3259 case ixgbe_phy_sfp_passive_tyco
:
3260 case ixgbe_phy_sfp_passive_unknown
:
3261 case ixgbe_phy_sfp_active_unknown
:
3262 case ixgbe_phy_sfp_ftl_active
:
3270 * ixgbe_sfp_link_config - set up SFP+ link
3271 * @adapter: pointer to private adapter struct
3273 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
3275 struct ixgbe_hw
*hw
= &adapter
->hw
;
3277 if (hw
->phy
.multispeed_fiber
) {
3279 * In multispeed fiber setups, the device may not have
3280 * had a physical connection when the driver loaded.
3281 * If that's the case, the initial link configuration
3282 * couldn't get the MAC into 10G or 1G mode, so we'll
3283 * never have a link status change interrupt fire.
3284 * We need to try and force an autonegotiation
3285 * session, then bring up link.
3287 hw
->mac
.ops
.setup_sfp(hw
);
3288 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
3289 schedule_work(&adapter
->multispeed_fiber_task
);
3292 * Direct Attach Cu and non-multispeed fiber modules
3293 * still need to be configured properly prior to
3296 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
3297 schedule_work(&adapter
->sfp_config_module_task
);
3302 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3303 * @hw: pointer to private hardware struct
3305 * Returns 0 on success, negative on failure
3307 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
3310 bool negotiation
, link_up
= false;
3311 u32 ret
= IXGBE_ERR_LINK_SETUP
;
3313 if (hw
->mac
.ops
.check_link
)
3314 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
3319 if (hw
->mac
.ops
.get_link_capabilities
)
3320 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
3324 if (hw
->mac
.ops
.setup_link
)
3325 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
3330 #define IXGBE_MAX_RX_DESC_POLL 10
3331 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
3334 int j
= adapter
->rx_ring
[rxr
]->reg_idx
;
3337 for (k
= 0; k
< IXGBE_MAX_RX_DESC_POLL
; k
++) {
3338 if (IXGBE_READ_REG(&adapter
->hw
,
3339 IXGBE_RXDCTL(j
)) & IXGBE_RXDCTL_ENABLE
)
3344 if (k
>= IXGBE_MAX_RX_DESC_POLL
) {
3345 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not set within "
3346 "the polling period\n", rxr
);
3348 ixgbe_release_rx_desc(&adapter
->hw
, adapter
->rx_ring
[rxr
],
3349 (adapter
->rx_ring
[rxr
]->count
- 1));
3352 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
3354 struct ixgbe_hw
*hw
= &adapter
->hw
;
3356 int num_rx_rings
= adapter
->num_rx_queues
;
3363 ixgbe_get_hw_control(adapter
);
3365 if ((adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) ||
3366 (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
)) {
3367 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3368 gpie
= (IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_EIAME
|
3369 IXGBE_GPIE_PBA_SUPPORT
| IXGBE_GPIE_OCD
);
3374 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
3375 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
3376 gpie
|= IXGBE_GPIE_VTMODE_64
;
3378 /* XXX: to interrupt immediately for EICS writes, enable this */
3379 /* gpie |= IXGBE_GPIE_EIMEN; */
3380 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3383 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3385 * use EIAM to auto-mask when MSI-X interrupt is asserted
3386 * this saves a register write for every interrupt
3388 switch (hw
->mac
.type
) {
3389 case ixgbe_mac_82598EB
:
3390 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3393 case ixgbe_mac_82599EB
:
3394 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3395 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3399 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3400 * specifically only auto mask tx and rx interrupts */
3401 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3404 /* Enable Thermal over heat sensor interrupt */
3405 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) {
3406 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
3407 gpie
|= IXGBE_SDP0_GPIEN
;
3408 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3411 /* Enable fan failure interrupt if media type is copper */
3412 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3413 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
3414 gpie
|= IXGBE_SDP1_GPIEN
;
3415 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3418 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3419 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
3420 gpie
|= IXGBE_SDP1_GPIEN
;
3421 gpie
|= IXGBE_SDP2_GPIEN
;
3422 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3425 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3426 /* DMATXCTL.EN must be set after all Tx queue config is done */
3427 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
3428 dmatxctl
|= IXGBE_DMATXCTL_TE
;
3429 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
3431 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3432 j
= adapter
->tx_ring
[i
]->reg_idx
;
3433 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3434 if (adapter
->rx_itr_setting
== 0) {
3435 /* cannot set wthresh when itr==0 */
3436 txdctl
&= ~0x007F0000;
3438 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3439 txdctl
|= (8 << 16);
3441 txdctl
|= IXGBE_TXDCTL_ENABLE
;
3442 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
3443 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3445 /* poll for Tx Enable ready */
3448 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3449 } while (--wait_loop
&&
3450 !(txdctl
& IXGBE_TXDCTL_ENABLE
));
3452 e_err(drv
, "Could not enable Tx Queue %d\n", j
);
3456 for (i
= 0; i
< num_rx_rings
; i
++) {
3457 j
= adapter
->rx_ring
[i
]->reg_idx
;
3458 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3459 /* enable PTHRESH=32 descriptors (half the internal cache)
3460 * and HTHRESH=0 descriptors (to minimize latency on fetch),
3461 * this also removes a pesky rx_no_buffer_count increment */
3463 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
3464 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), rxdctl
);
3465 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3466 ixgbe_rx_desc_queue_enable(adapter
, i
);
3468 /* enable all receives */
3469 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3470 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3471 rxdctl
|= (IXGBE_RXCTRL_DMBYPS
| IXGBE_RXCTRL_RXEN
);
3473 rxdctl
|= IXGBE_RXCTRL_RXEN
;
3474 hw
->mac
.ops
.enable_rx_dma(hw
, rxdctl
);
3476 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3477 ixgbe_configure_msix(adapter
);
3479 ixgbe_configure_msi_and_legacy(adapter
);
3481 /* enable the optics */
3482 if (hw
->phy
.multispeed_fiber
)
3483 hw
->mac
.ops
.enable_tx_laser(hw
);
3485 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3486 ixgbe_napi_enable_all(adapter
);
3488 /* clear any pending interrupts, may auto mask */
3489 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3491 ixgbe_irq_enable(adapter
);
3494 * If this adapter has a fan, check to see if we had a failure
3495 * before we enabled the interrupt.
3497 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3498 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3499 if (esdp
& IXGBE_ESDP_SDP1
)
3500 e_crit(drv
, "Fan has stopped, replace the adapter\n");
3504 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3505 * arrived before interrupts were enabled but after probe. Such
3506 * devices wouldn't have their type identified yet. We need to
3507 * kick off the SFP+ module setup first, then try to bring up link.
3508 * If we're not hot-pluggable SFP+, we just need to configure link
3511 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
3512 err
= hw
->phy
.ops
.identify(hw
);
3513 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
3515 * Take the device down and schedule the sfp tasklet
3516 * which will unregister_netdev and log it.
3518 ixgbe_down(adapter
);
3519 schedule_work(&adapter
->sfp_config_module_task
);
3524 if (ixgbe_is_sfp(hw
)) {
3525 ixgbe_sfp_link_config(adapter
);
3527 err
= ixgbe_non_sfp_link_config(hw
);
3529 e_err(probe
, "link_config FAILED %d\n", err
);
3532 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3533 set_bit(__IXGBE_FDIR_INIT_DONE
,
3534 &(adapter
->tx_ring
[i
]->reinit_state
));
3536 /* enable transmits */
3537 netif_tx_start_all_queues(adapter
->netdev
);
3539 /* bring the link up in the watchdog, this could race with our first
3540 * link up interrupt but shouldn't be a problem */
3541 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3542 adapter
->link_check_timeout
= jiffies
;
3543 mod_timer(&adapter
->watchdog_timer
, jiffies
);
3545 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3546 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3547 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3548 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3553 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3555 WARN_ON(in_interrupt());
3556 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3558 ixgbe_down(adapter
);
3560 * If SR-IOV enabled then wait a bit before bringing the adapter
3561 * back up to give the VFs time to respond to the reset. The
3562 * two second wait is based upon the watchdog timer cycle in
3565 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3568 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3571 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3573 /* hardware has been reset, we need to reload some things */
3574 ixgbe_configure(adapter
);
3576 return ixgbe_up_complete(adapter
);
3579 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3581 struct ixgbe_hw
*hw
= &adapter
->hw
;
3584 err
= hw
->mac
.ops
.init_hw(hw
);
3587 case IXGBE_ERR_SFP_NOT_PRESENT
:
3589 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3590 e_dev_err("master disable timed out\n");
3592 case IXGBE_ERR_EEPROM_VERSION
:
3593 /* We are running on a pre-production device, log a warning */
3594 e_dev_warn("This device is a pre-production adapter/LOM. "
3595 "Please be aware there may be issuesassociated with "
3596 "your hardware. If you are experiencing problems "
3597 "please contact your Intel or hardware "
3598 "representative who provided you with this "
3602 e_dev_err("Hardware Error: %d\n", err
);
3605 /* reprogram the RAR[0] in case user changed it. */
3606 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3611 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3612 * @adapter: board private structure
3613 * @rx_ring: ring to free buffers from
3615 static void ixgbe_clean_rx_ring(struct ixgbe_adapter
*adapter
,
3616 struct ixgbe_ring
*rx_ring
)
3618 struct pci_dev
*pdev
= adapter
->pdev
;
3622 /* Free all the Rx ring sk_buffs */
3624 for (i
= 0; i
< rx_ring
->count
; i
++) {
3625 struct ixgbe_rx_buffer
*rx_buffer_info
;
3627 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3628 if (rx_buffer_info
->dma
) {
3629 dma_unmap_single(&pdev
->dev
, rx_buffer_info
->dma
,
3630 rx_ring
->rx_buf_len
,
3632 rx_buffer_info
->dma
= 0;
3634 if (rx_buffer_info
->skb
) {
3635 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3636 rx_buffer_info
->skb
= NULL
;
3638 struct sk_buff
*this = skb
;
3639 if (IXGBE_RSC_CB(this)->delay_unmap
) {
3640 dma_unmap_single(&pdev
->dev
,
3641 IXGBE_RSC_CB(this)->dma
,
3642 rx_ring
->rx_buf_len
,
3644 IXGBE_RSC_CB(this)->dma
= 0;
3645 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
3648 dev_kfree_skb(this);
3651 if (!rx_buffer_info
->page
)
3653 if (rx_buffer_info
->page_dma
) {
3654 dma_unmap_page(&pdev
->dev
, rx_buffer_info
->page_dma
,
3655 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
3656 rx_buffer_info
->page_dma
= 0;
3658 put_page(rx_buffer_info
->page
);
3659 rx_buffer_info
->page
= NULL
;
3660 rx_buffer_info
->page_offset
= 0;
3663 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3664 memset(rx_ring
->rx_buffer_info
, 0, size
);
3666 /* Zero out the descriptor ring */
3667 memset(rx_ring
->desc
, 0, rx_ring
->size
);
3669 rx_ring
->next_to_clean
= 0;
3670 rx_ring
->next_to_use
= 0;
3673 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->head
);
3675 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
3679 * ixgbe_clean_tx_ring - Free Tx Buffers
3680 * @adapter: board private structure
3681 * @tx_ring: ring to be cleaned
3683 static void ixgbe_clean_tx_ring(struct ixgbe_adapter
*adapter
,
3684 struct ixgbe_ring
*tx_ring
)
3686 struct ixgbe_tx_buffer
*tx_buffer_info
;
3690 /* Free all the Tx ring sk_buffs */
3692 for (i
= 0; i
< tx_ring
->count
; i
++) {
3693 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
3694 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
3697 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3698 memset(tx_ring
->tx_buffer_info
, 0, size
);
3700 /* Zero out the descriptor ring */
3701 memset(tx_ring
->desc
, 0, tx_ring
->size
);
3703 tx_ring
->next_to_use
= 0;
3704 tx_ring
->next_to_clean
= 0;
3707 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->head
);
3709 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
3713 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3714 * @adapter: board private structure
3716 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
3720 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3721 ixgbe_clean_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3725 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3726 * @adapter: board private structure
3728 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
3732 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3733 ixgbe_clean_tx_ring(adapter
, adapter
->tx_ring
[i
]);
3736 void ixgbe_down(struct ixgbe_adapter
*adapter
)
3738 struct net_device
*netdev
= adapter
->netdev
;
3739 struct ixgbe_hw
*hw
= &adapter
->hw
;
3744 /* signal that we are down to the interrupt handler */
3745 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3747 /* disable receive for all VFs and wait one second */
3748 if (adapter
->num_vfs
) {
3749 /* ping all the active vfs to let them know we are going down */
3750 ixgbe_ping_all_vfs(adapter
);
3752 /* Disable all VFTE/VFRE TX/RX */
3753 ixgbe_disable_tx_rx(adapter
);
3755 /* Mark all the VFs as inactive */
3756 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
3757 adapter
->vfinfo
[i
].clear_to_send
= 0;
3760 /* disable receives */
3761 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3762 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3764 IXGBE_WRITE_FLUSH(hw
);
3767 netif_tx_stop_all_queues(netdev
);
3769 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3770 del_timer_sync(&adapter
->sfp_timer
);
3771 del_timer_sync(&adapter
->watchdog_timer
);
3772 cancel_work_sync(&adapter
->watchdog_task
);
3774 netif_carrier_off(netdev
);
3775 netif_tx_disable(netdev
);
3777 ixgbe_irq_disable(adapter
);
3779 ixgbe_napi_disable_all(adapter
);
3781 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3782 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3783 cancel_work_sync(&adapter
->fdir_reinit_task
);
3785 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
3786 cancel_work_sync(&adapter
->check_overtemp_task
);
3788 /* disable transmits in the hardware now that interrupts are off */
3789 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3790 j
= adapter
->tx_ring
[i
]->reg_idx
;
3791 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3792 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
),
3793 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
3795 /* Disable the Tx DMA engine on 82599 */
3796 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3797 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
3798 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
3799 ~IXGBE_DMATXCTL_TE
));
3801 /* power down the optics */
3802 if (hw
->phy
.multispeed_fiber
)
3803 hw
->mac
.ops
.disable_tx_laser(hw
);
3805 /* clear n-tuple filters that are cached */
3806 ethtool_ntuple_flush(netdev
);
3808 if (!pci_channel_offline(adapter
->pdev
))
3809 ixgbe_reset(adapter
);
3810 ixgbe_clean_all_tx_rings(adapter
);
3811 ixgbe_clean_all_rx_rings(adapter
);
3813 #ifdef CONFIG_IXGBE_DCA
3814 /* since we reset the hardware DCA settings were cleared */
3815 ixgbe_setup_dca(adapter
);
3820 * ixgbe_poll - NAPI Rx polling callback
3821 * @napi: structure for representing this polling device
3822 * @budget: how many packets driver is allowed to clean
3824 * This function is used for legacy and MSI, NAPI mode
3826 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
3828 struct ixgbe_q_vector
*q_vector
=
3829 container_of(napi
, struct ixgbe_q_vector
, napi
);
3830 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
3831 int tx_clean_complete
, work_done
= 0;
3833 #ifdef CONFIG_IXGBE_DCA
3834 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
3835 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[0]);
3836 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[0]);
3840 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
3841 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
3843 if (!tx_clean_complete
)
3846 /* If budget not fully consumed, exit the polling mode */
3847 if (work_done
< budget
) {
3848 napi_complete(napi
);
3849 if (adapter
->rx_itr_setting
& 1)
3850 ixgbe_set_itr(adapter
);
3851 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3852 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
3858 * ixgbe_tx_timeout - Respond to a Tx Hang
3859 * @netdev: network interface device structure
3861 static void ixgbe_tx_timeout(struct net_device
*netdev
)
3863 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3865 /* Do the reset outside of interrupt context */
3866 schedule_work(&adapter
->reset_task
);
3869 static void ixgbe_reset_task(struct work_struct
*work
)
3871 struct ixgbe_adapter
*adapter
;
3872 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
3874 /* If we're already down or resetting, just bail */
3875 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
3876 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
3879 adapter
->tx_timeout_count
++;
3881 ixgbe_dump(adapter
);
3882 netdev_err(adapter
->netdev
, "Reset adapter\n");
3883 ixgbe_reinit_locked(adapter
);
3886 #ifdef CONFIG_IXGBE_DCB
3887 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
3890 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
3892 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
3896 adapter
->num_rx_queues
= f
->indices
;
3897 adapter
->num_tx_queues
= f
->indices
;
3905 * ixgbe_set_rss_queues: Allocate queues for RSS
3906 * @adapter: board private structure to initialize
3908 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3909 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3912 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
3915 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
3917 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3919 adapter
->num_rx_queues
= f
->indices
;
3920 adapter
->num_tx_queues
= f
->indices
;
3930 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3931 * @adapter: board private structure to initialize
3933 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3934 * to the original CPU that initiated the Tx session. This runs in addition
3935 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3936 * Rx load across CPUs using RSS.
3939 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
3942 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
3944 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
3947 /* Flow Director must have RSS enabled */
3948 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
3949 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3950 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
3951 adapter
->num_tx_queues
= f_fdir
->indices
;
3952 adapter
->num_rx_queues
= f_fdir
->indices
;
3955 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
3956 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
3963 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3964 * @adapter: board private structure to initialize
3966 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3967 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3968 * rx queues out of the max number of rx queues, instead, it is used as the
3969 * index of the first rx queue used by FCoE.
3972 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
3975 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3977 f
->indices
= min((int)num_online_cpus(), f
->indices
);
3978 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3979 adapter
->num_rx_queues
= 1;
3980 adapter
->num_tx_queues
= 1;
3981 #ifdef CONFIG_IXGBE_DCB
3982 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3983 e_info(probe
, "FCoE enabled with DCB\n");
3984 ixgbe_set_dcb_queues(adapter
);
3987 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3988 e_info(probe
, "FCoE enabled with RSS\n");
3989 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3990 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
3991 ixgbe_set_fdir_queues(adapter
);
3993 ixgbe_set_rss_queues(adapter
);
3995 /* adding FCoE rx rings to the end */
3996 f
->mask
= adapter
->num_rx_queues
;
3997 adapter
->num_rx_queues
+= f
->indices
;
3998 adapter
->num_tx_queues
+= f
->indices
;
4006 #endif /* IXGBE_FCOE */
4008 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4009 * @adapter: board private structure to initialize
4011 * IOV doesn't actually use anything, so just NAK the
4012 * request for now and let the other queue routines
4013 * figure out what to do.
4015 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
4021 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4022 * @adapter: board private structure to initialize
4024 * This is the top level queue allocation routine. The order here is very
4025 * important, starting with the "most" number of features turned on at once,
4026 * and ending with the smallest set of features. This way large combinations
4027 * can be allocated if they're turned on, and smaller combinations are the
4028 * fallthrough conditions.
4031 static void ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
4033 /* Start with base case */
4034 adapter
->num_rx_queues
= 1;
4035 adapter
->num_tx_queues
= 1;
4036 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
4037 adapter
->num_rx_queues_per_pool
= 1;
4039 if (ixgbe_set_sriov_queues(adapter
))
4043 if (ixgbe_set_fcoe_queues(adapter
))
4046 #endif /* IXGBE_FCOE */
4047 #ifdef CONFIG_IXGBE_DCB
4048 if (ixgbe_set_dcb_queues(adapter
))
4052 if (ixgbe_set_fdir_queues(adapter
))
4055 if (ixgbe_set_rss_queues(adapter
))
4058 /* fallback to base case */
4059 adapter
->num_rx_queues
= 1;
4060 adapter
->num_tx_queues
= 1;
4063 /* Notify the stack of the (possibly) reduced Tx Queue count. */
4064 netif_set_real_num_tx_queues(adapter
->netdev
, adapter
->num_tx_queues
);
4067 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
4070 int err
, vector_threshold
;
4072 /* We'll want at least 3 (vector_threshold):
4075 * 3) Other (Link Status Change, etc.)
4076 * 4) TCP Timer (optional)
4078 vector_threshold
= MIN_MSIX_COUNT
;
4080 /* The more we get, the more we will assign to Tx/Rx Cleanup
4081 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4082 * Right now, we simply care about how many we'll get; we'll
4083 * set them up later while requesting irq's.
4085 while (vectors
>= vector_threshold
) {
4086 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
4088 if (!err
) /* Success in acquiring all requested vectors. */
4091 vectors
= 0; /* Nasty failure, quit now */
4092 else /* err == number of vectors we should try again with */
4096 if (vectors
< vector_threshold
) {
4097 /* Can't allocate enough MSI-X interrupts? Oh well.
4098 * This just means we'll go with either a single MSI
4099 * vector or fall back to legacy interrupts.
4101 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4102 "Unable to allocate MSI-X interrupts\n");
4103 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4104 kfree(adapter
->msix_entries
);
4105 adapter
->msix_entries
= NULL
;
4107 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
4109 * Adjust for only the vectors we'll use, which is minimum
4110 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4111 * vectors we were allocated.
4113 adapter
->num_msix_vectors
= min(vectors
,
4114 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
4119 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4120 * @adapter: board private structure to initialize
4122 * Cache the descriptor ring offsets for RSS to the assigned rings.
4125 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
4130 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4131 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4132 adapter
->rx_ring
[i
]->reg_idx
= i
;
4133 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4134 adapter
->tx_ring
[i
]->reg_idx
= i
;
4143 #ifdef CONFIG_IXGBE_DCB
4145 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4146 * @adapter: board private structure to initialize
4148 * Cache the descriptor ring offsets for DCB to the assigned rings.
4151 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
4155 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
4157 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4158 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
4159 /* the number of queues is assumed to be symmetric */
4160 for (i
= 0; i
< dcb_i
; i
++) {
4161 adapter
->rx_ring
[i
]->reg_idx
= i
<< 3;
4162 adapter
->tx_ring
[i
]->reg_idx
= i
<< 2;
4165 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
4168 * Tx TC0 starts at: descriptor queue 0
4169 * Tx TC1 starts at: descriptor queue 32
4170 * Tx TC2 starts at: descriptor queue 64
4171 * Tx TC3 starts at: descriptor queue 80
4172 * Tx TC4 starts at: descriptor queue 96
4173 * Tx TC5 starts at: descriptor queue 104
4174 * Tx TC6 starts at: descriptor queue 112
4175 * Tx TC7 starts at: descriptor queue 120
4177 * Rx TC0-TC7 are offset by 16 queues each
4179 for (i
= 0; i
< 3; i
++) {
4180 adapter
->tx_ring
[i
]->reg_idx
= i
<< 5;
4181 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4183 for ( ; i
< 5; i
++) {
4184 adapter
->tx_ring
[i
]->reg_idx
=
4186 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4188 for ( ; i
< dcb_i
; i
++) {
4189 adapter
->tx_ring
[i
]->reg_idx
=
4191 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4195 } else if (dcb_i
== 4) {
4197 * Tx TC0 starts at: descriptor queue 0
4198 * Tx TC1 starts at: descriptor queue 64
4199 * Tx TC2 starts at: descriptor queue 96
4200 * Tx TC3 starts at: descriptor queue 112
4202 * Rx TC0-TC3 are offset by 32 queues each
4204 adapter
->tx_ring
[0]->reg_idx
= 0;
4205 adapter
->tx_ring
[1]->reg_idx
= 64;
4206 adapter
->tx_ring
[2]->reg_idx
= 96;
4207 adapter
->tx_ring
[3]->reg_idx
= 112;
4208 for (i
= 0 ; i
< dcb_i
; i
++)
4209 adapter
->rx_ring
[i
]->reg_idx
= i
<< 5;
4227 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4228 * @adapter: board private structure to initialize
4230 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4233 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
4238 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4239 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4240 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
4241 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4242 adapter
->rx_ring
[i
]->reg_idx
= i
;
4243 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4244 adapter
->tx_ring
[i
]->reg_idx
= i
;
4253 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4254 * @adapter: board private structure to initialize
4256 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4259 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
4261 int i
, fcoe_rx_i
= 0, fcoe_tx_i
= 0;
4263 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4265 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4266 #ifdef CONFIG_IXGBE_DCB
4267 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4268 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
4270 ixgbe_cache_ring_dcb(adapter
);
4271 /* find out queues in TC for FCoE */
4272 fcoe_rx_i
= adapter
->rx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4273 fcoe_tx_i
= adapter
->tx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4275 * In 82599, the number of Tx queues for each traffic
4276 * class for both 8-TC and 4-TC modes are:
4277 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4278 * 8 TCs: 32 32 16 16 8 8 8 8
4279 * 4 TCs: 64 64 32 32
4280 * We have max 8 queues for FCoE, where 8 the is
4281 * FCoE redirection table size. If TC for FCoE is
4282 * less than or equal to TC3, we have enough queues
4283 * to add max of 8 queues for FCoE, so we start FCoE
4284 * tx descriptor from the next one, i.e., reg_idx + 1.
4285 * If TC for FCoE is above TC3, implying 8 TC mode,
4286 * and we need 8 for FCoE, we have to take all queues
4287 * in that traffic class for FCoE.
4289 if ((f
->indices
== IXGBE_FCRETA_SIZE
) && (fcoe
->tc
> 3))
4292 #endif /* CONFIG_IXGBE_DCB */
4293 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4294 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4295 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4296 ixgbe_cache_ring_fdir(adapter
);
4298 ixgbe_cache_ring_rss(adapter
);
4300 fcoe_rx_i
= f
->mask
;
4301 fcoe_tx_i
= f
->mask
;
4303 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
4304 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
4305 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
4312 #endif /* IXGBE_FCOE */
4314 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4315 * @adapter: board private structure to initialize
4317 * SR-IOV doesn't use any descriptor rings but changes the default if
4318 * no other mapping is used.
4321 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
4323 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4324 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4325 if (adapter
->num_vfs
)
4332 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4333 * @adapter: board private structure to initialize
4335 * Once we know the feature-set enabled for the device, we'll cache
4336 * the register offset the descriptor ring is assigned to.
4338 * Note, the order the various feature calls is important. It must start with
4339 * the "most" features enabled at the same time, then trickle down to the
4340 * least amount of features turned on at once.
4342 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
4344 /* start with default case */
4345 adapter
->rx_ring
[0]->reg_idx
= 0;
4346 adapter
->tx_ring
[0]->reg_idx
= 0;
4348 if (ixgbe_cache_ring_sriov(adapter
))
4352 if (ixgbe_cache_ring_fcoe(adapter
))
4355 #endif /* IXGBE_FCOE */
4356 #ifdef CONFIG_IXGBE_DCB
4357 if (ixgbe_cache_ring_dcb(adapter
))
4361 if (ixgbe_cache_ring_fdir(adapter
))
4364 if (ixgbe_cache_ring_rss(adapter
))
4369 * ixgbe_alloc_queues - Allocate memory for all rings
4370 * @adapter: board private structure to initialize
4372 * We allocate one ring per queue at run-time since we don't know the
4373 * number of queues at compile-time. The polling_netdev array is
4374 * intended for Multiqueue, but should work fine with a single queue.
4376 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
4379 int orig_node
= adapter
->node
;
4381 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4382 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
4383 if (orig_node
== -1) {
4384 int cur_node
= next_online_node(adapter
->node
);
4385 if (cur_node
== MAX_NUMNODES
)
4386 cur_node
= first_online_node
;
4387 adapter
->node
= cur_node
;
4389 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
4392 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
4394 goto err_tx_ring_allocation
;
4395 ring
->count
= adapter
->tx_ring_count
;
4396 ring
->queue_index
= i
;
4397 ring
->numa_node
= adapter
->node
;
4399 adapter
->tx_ring
[i
] = ring
;
4402 /* Restore the adapter's original node */
4403 adapter
->node
= orig_node
;
4405 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4406 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
4407 if (orig_node
== -1) {
4408 int cur_node
= next_online_node(adapter
->node
);
4409 if (cur_node
== MAX_NUMNODES
)
4410 cur_node
= first_online_node
;
4411 adapter
->node
= cur_node
;
4413 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
4416 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
4418 goto err_rx_ring_allocation
;
4419 ring
->count
= adapter
->rx_ring_count
;
4420 ring
->queue_index
= i
;
4421 ring
->numa_node
= adapter
->node
;
4423 adapter
->rx_ring
[i
] = ring
;
4426 /* Restore the adapter's original node */
4427 adapter
->node
= orig_node
;
4429 ixgbe_cache_ring_register(adapter
);
4433 err_rx_ring_allocation
:
4434 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4435 kfree(adapter
->tx_ring
[i
]);
4436 err_tx_ring_allocation
:
4441 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4442 * @adapter: board private structure to initialize
4444 * Attempt to configure the interrupts using the best available
4445 * capabilities of the hardware and the kernel.
4447 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
4449 struct ixgbe_hw
*hw
= &adapter
->hw
;
4451 int vector
, v_budget
;
4454 * It's easy to be greedy for MSI-X vectors, but it really
4455 * doesn't do us much good if we have a lot more vectors
4456 * than CPU's. So let's be conservative and only ask for
4457 * (roughly) the same number of vectors as there are CPU's.
4459 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
4460 (int)num_online_cpus()) + NON_Q_VECTORS
;
4463 * At the same time, hardware can only support a maximum of
4464 * hw.mac->max_msix_vectors vectors. With features
4465 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4466 * descriptor queues supported by our device. Thus, we cap it off in
4467 * those rare cases where the cpu count also exceeds our vector limit.
4469 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
4471 /* A failure in MSI-X entry allocation isn't fatal, but it does
4472 * mean we disable MSI-X capabilities of the adapter. */
4473 adapter
->msix_entries
= kcalloc(v_budget
,
4474 sizeof(struct msix_entry
), GFP_KERNEL
);
4475 if (adapter
->msix_entries
) {
4476 for (vector
= 0; vector
< v_budget
; vector
++)
4477 adapter
->msix_entries
[vector
].entry
= vector
;
4479 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4481 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4485 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4486 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4487 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4488 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4489 adapter
->atr_sample_rate
= 0;
4490 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4491 ixgbe_disable_sriov(adapter
);
4493 ixgbe_set_num_queues(adapter
);
4495 err
= pci_enable_msi(adapter
->pdev
);
4497 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4499 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4500 "Unable to allocate MSI interrupt, "
4501 "falling back to legacy. Error: %d\n", err
);
4511 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4512 * @adapter: board private structure to initialize
4514 * We allocate one q_vector per queue interrupt. If allocation fails we
4517 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4519 int q_idx
, num_q_vectors
;
4520 struct ixgbe_q_vector
*q_vector
;
4522 int (*poll
)(struct napi_struct
*, int);
4524 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4525 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4526 napi_vectors
= adapter
->num_rx_queues
;
4527 poll
= &ixgbe_clean_rxtx_many
;
4534 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4535 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4536 GFP_KERNEL
, adapter
->node
);
4538 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4542 q_vector
->adapter
= adapter
;
4543 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
4544 q_vector
->eitr
= adapter
->tx_eitr_param
;
4546 q_vector
->eitr
= adapter
->rx_eitr_param
;
4547 q_vector
->v_idx
= q_idx
;
4548 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
4549 adapter
->q_vector
[q_idx
] = q_vector
;
4557 q_vector
= adapter
->q_vector
[q_idx
];
4558 netif_napi_del(&q_vector
->napi
);
4560 adapter
->q_vector
[q_idx
] = NULL
;
4566 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4567 * @adapter: board private structure to initialize
4569 * This function frees the memory allocated to the q_vectors. In addition if
4570 * NAPI is enabled it will delete any references to the NAPI struct prior
4571 * to freeing the q_vector.
4573 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4575 int q_idx
, num_q_vectors
;
4577 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4578 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4582 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4583 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4584 adapter
->q_vector
[q_idx
] = NULL
;
4585 netif_napi_del(&q_vector
->napi
);
4590 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4592 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4593 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4594 pci_disable_msix(adapter
->pdev
);
4595 kfree(adapter
->msix_entries
);
4596 adapter
->msix_entries
= NULL
;
4597 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4598 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4599 pci_disable_msi(adapter
->pdev
);
4604 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4605 * @adapter: board private structure to initialize
4607 * We determine which interrupt scheme to use based on...
4608 * - Kernel support (MSI, MSI-X)
4609 * - which can be user-defined (via MODULE_PARAM)
4610 * - Hardware queue count (num_*_queues)
4611 * - defined by miscellaneous hardware support/features (RSS, etc.)
4613 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4617 /* Number of supported queues */
4618 ixgbe_set_num_queues(adapter
);
4620 err
= ixgbe_set_interrupt_capability(adapter
);
4622 e_dev_err("Unable to setup interrupt capabilities\n");
4623 goto err_set_interrupt
;
4626 err
= ixgbe_alloc_q_vectors(adapter
);
4628 e_dev_err("Unable to allocate memory for queue vectors\n");
4629 goto err_alloc_q_vectors
;
4632 err
= ixgbe_alloc_queues(adapter
);
4634 e_dev_err("Unable to allocate memory for queues\n");
4635 goto err_alloc_queues
;
4638 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4639 (adapter
->num_rx_queues
> 1) ? "Enabled" : "Disabled",
4640 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
4642 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4647 ixgbe_free_q_vectors(adapter
);
4648 err_alloc_q_vectors
:
4649 ixgbe_reset_interrupt_capability(adapter
);
4655 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4656 * @adapter: board private structure to clear interrupt scheme on
4658 * We go through and clear interrupt specific resources and reset the structure
4659 * to pre-load conditions
4661 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4665 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4666 kfree(adapter
->tx_ring
[i
]);
4667 adapter
->tx_ring
[i
] = NULL
;
4669 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4670 kfree(adapter
->rx_ring
[i
]);
4671 adapter
->rx_ring
[i
] = NULL
;
4674 ixgbe_free_q_vectors(adapter
);
4675 ixgbe_reset_interrupt_capability(adapter
);
4679 * ixgbe_sfp_timer - worker thread to find a missing module
4680 * @data: pointer to our adapter struct
4682 static void ixgbe_sfp_timer(unsigned long data
)
4684 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4687 * Do the sfp_timer outside of interrupt context due to the
4688 * delays that sfp+ detection requires
4690 schedule_work(&adapter
->sfp_task
);
4694 * ixgbe_sfp_task - worker thread to find a missing module
4695 * @work: pointer to work_struct containing our data
4697 static void ixgbe_sfp_task(struct work_struct
*work
)
4699 struct ixgbe_adapter
*adapter
= container_of(work
,
4700 struct ixgbe_adapter
,
4702 struct ixgbe_hw
*hw
= &adapter
->hw
;
4704 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
4705 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
4706 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
4707 if (ret
== IXGBE_ERR_SFP_NOT_PRESENT
)
4709 ret
= hw
->phy
.ops
.reset(hw
);
4710 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4711 e_dev_err("failed to initialize because an unsupported "
4712 "SFP+ module type was detected.\n");
4713 e_dev_err("Reload the driver after installing a "
4714 "supported module.\n");
4715 unregister_netdev(adapter
->netdev
);
4717 e_info(probe
, "detected SFP+: %d\n", hw
->phy
.sfp_type
);
4719 /* don't need this routine any more */
4720 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
4724 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
4725 mod_timer(&adapter
->sfp_timer
,
4726 round_jiffies(jiffies
+ (2 * HZ
)));
4730 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4731 * @adapter: board private structure to initialize
4733 * ixgbe_sw_init initializes the Adapter private data structure.
4734 * Fields are initialized based on PCI device information and
4735 * OS network device settings (MTU size).
4737 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
4739 struct ixgbe_hw
*hw
= &adapter
->hw
;
4740 struct pci_dev
*pdev
= adapter
->pdev
;
4741 struct net_device
*dev
= adapter
->netdev
;
4743 #ifdef CONFIG_IXGBE_DCB
4745 struct tc_configuration
*tc
;
4748 /* PCI config space info */
4750 hw
->vendor_id
= pdev
->vendor
;
4751 hw
->device_id
= pdev
->device
;
4752 hw
->revision_id
= pdev
->revision
;
4753 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
4754 hw
->subsystem_device_id
= pdev
->subsystem_device
;
4756 /* Set capability flags */
4757 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
4758 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
4759 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
4760 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
4761 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
4762 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
4763 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
4764 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
4765 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4766 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
4767 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
4768 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
4769 if (hw
->device_id
== IXGBE_DEV_ID_82599_T3_LOM
)
4770 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
;
4771 if (dev
->features
& NETIF_F_NTUPLE
) {
4772 /* Flow Director perfect filter enabled */
4773 adapter
->flags
|= IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4774 adapter
->atr_sample_rate
= 0;
4775 spin_lock_init(&adapter
->fdir_perfect_lock
);
4777 /* Flow Director hash filters enabled */
4778 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4779 adapter
->atr_sample_rate
= 20;
4781 adapter
->ring_feature
[RING_F_FDIR
].indices
=
4782 IXGBE_MAX_FDIR_INDICES
;
4783 adapter
->fdir_pballoc
= 0;
4785 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
4786 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
4787 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
4788 #ifdef CONFIG_IXGBE_DCB
4789 /* Default traffic class to use for FCoE */
4790 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
4791 adapter
->fcoe
.up
= IXGBE_FCOE_DEFTC
;
4793 #endif /* IXGBE_FCOE */
4796 #ifdef CONFIG_IXGBE_DCB
4797 /* Configure DCB traffic classes */
4798 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
4799 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
4800 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
4801 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4802 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
4803 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4804 tc
->dcb_pfc
= pfc_disabled
;
4806 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
4807 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
4808 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
4809 adapter
->dcb_cfg
.pfc_mode_enable
= false;
4810 adapter
->dcb_cfg
.round_robin_enable
= false;
4811 adapter
->dcb_set_bitmap
= 0x00;
4812 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
4813 adapter
->ring_feature
[RING_F_DCB
].indices
);
4817 /* default flow control settings */
4818 hw
->fc
.requested_mode
= ixgbe_fc_full
;
4819 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
4821 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
4823 hw
->fc
.high_water
= IXGBE_DEFAULT_FCRTH
;
4824 hw
->fc
.low_water
= IXGBE_DEFAULT_FCRTL
;
4825 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
4826 hw
->fc
.send_xon
= true;
4827 hw
->fc
.disable_fc_autoneg
= false;
4829 /* enable itr by default in dynamic mode */
4830 adapter
->rx_itr_setting
= 1;
4831 adapter
->rx_eitr_param
= 20000;
4832 adapter
->tx_itr_setting
= 1;
4833 adapter
->tx_eitr_param
= 10000;
4835 /* set defaults for eitr in MegaBytes */
4836 adapter
->eitr_low
= 10;
4837 adapter
->eitr_high
= 20;
4839 /* set default ring sizes */
4840 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
4841 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
4843 /* initialize eeprom parameters */
4844 if (ixgbe_init_eeprom_params_generic(hw
)) {
4845 e_dev_err("EEPROM initialization failed\n");
4849 /* enable rx csum by default */
4850 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
4852 /* get assigned NUMA node */
4853 adapter
->node
= dev_to_node(&pdev
->dev
);
4855 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4861 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4862 * @adapter: board private structure
4863 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4865 * Return 0 on success, negative on failure
4867 int ixgbe_setup_tx_resources(struct ixgbe_adapter
*adapter
,
4868 struct ixgbe_ring
*tx_ring
)
4870 struct pci_dev
*pdev
= adapter
->pdev
;
4873 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4874 tx_ring
->tx_buffer_info
= vmalloc_node(size
, tx_ring
->numa_node
);
4875 if (!tx_ring
->tx_buffer_info
)
4876 tx_ring
->tx_buffer_info
= vmalloc(size
);
4877 if (!tx_ring
->tx_buffer_info
)
4879 memset(tx_ring
->tx_buffer_info
, 0, size
);
4881 /* round up to nearest 4K */
4882 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
4883 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
4885 tx_ring
->desc
= dma_alloc_coherent(&pdev
->dev
, tx_ring
->size
,
4886 &tx_ring
->dma
, GFP_KERNEL
);
4890 tx_ring
->next_to_use
= 0;
4891 tx_ring
->next_to_clean
= 0;
4892 tx_ring
->work_limit
= tx_ring
->count
;
4896 vfree(tx_ring
->tx_buffer_info
);
4897 tx_ring
->tx_buffer_info
= NULL
;
4898 e_err(probe
, "Unable to allocate memory for the Tx descriptor ring\n");
4903 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4904 * @adapter: board private structure
4906 * If this function returns with an error, then it's possible one or
4907 * more of the rings is populated (while the rest are not). It is the
4908 * callers duty to clean those orphaned rings.
4910 * Return 0 on success, negative on failure
4912 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
4916 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4917 err
= ixgbe_setup_tx_resources(adapter
, adapter
->tx_ring
[i
]);
4920 e_err(probe
, "Allocation for Tx Queue %u failed\n", i
);
4928 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4929 * @adapter: board private structure
4930 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4932 * Returns 0 on success, negative on failure
4934 int ixgbe_setup_rx_resources(struct ixgbe_adapter
*adapter
,
4935 struct ixgbe_ring
*rx_ring
)
4937 struct pci_dev
*pdev
= adapter
->pdev
;
4940 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
4941 rx_ring
->rx_buffer_info
= vmalloc_node(size
, adapter
->node
);
4942 if (!rx_ring
->rx_buffer_info
)
4943 rx_ring
->rx_buffer_info
= vmalloc(size
);
4944 if (!rx_ring
->rx_buffer_info
) {
4945 e_err(probe
, "vmalloc allocation failed for the Rx "
4946 "descriptor ring\n");
4949 memset(rx_ring
->rx_buffer_info
, 0, size
);
4951 /* Round up to nearest 4K */
4952 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
4953 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
4955 rx_ring
->desc
= dma_alloc_coherent(&pdev
->dev
, rx_ring
->size
,
4956 &rx_ring
->dma
, GFP_KERNEL
);
4958 if (!rx_ring
->desc
) {
4959 e_err(probe
, "Memory allocation failed for the Rx "
4960 "descriptor ring\n");
4961 vfree(rx_ring
->rx_buffer_info
);
4965 rx_ring
->next_to_clean
= 0;
4966 rx_ring
->next_to_use
= 0;
4975 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4976 * @adapter: board private structure
4978 * If this function returns with an error, then it's possible one or
4979 * more of the rings is populated (while the rest are not). It is the
4980 * callers duty to clean those orphaned rings.
4982 * Return 0 on success, negative on failure
4985 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
4989 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4990 err
= ixgbe_setup_rx_resources(adapter
, adapter
->rx_ring
[i
]);
4993 e_err(probe
, "Allocation for Rx Queue %u failed\n", i
);
5001 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5002 * @adapter: board private structure
5003 * @tx_ring: Tx descriptor ring for a specific queue
5005 * Free all transmit software resources
5007 void ixgbe_free_tx_resources(struct ixgbe_adapter
*adapter
,
5008 struct ixgbe_ring
*tx_ring
)
5010 struct pci_dev
*pdev
= adapter
->pdev
;
5012 ixgbe_clean_tx_ring(adapter
, tx_ring
);
5014 vfree(tx_ring
->tx_buffer_info
);
5015 tx_ring
->tx_buffer_info
= NULL
;
5017 dma_free_coherent(&pdev
->dev
, tx_ring
->size
, tx_ring
->desc
,
5020 tx_ring
->desc
= NULL
;
5024 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5025 * @adapter: board private structure
5027 * Free all transmit software resources
5029 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
5033 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5034 if (adapter
->tx_ring
[i
]->desc
)
5035 ixgbe_free_tx_resources(adapter
, adapter
->tx_ring
[i
]);
5039 * ixgbe_free_rx_resources - Free Rx Resources
5040 * @adapter: board private structure
5041 * @rx_ring: ring to clean the resources from
5043 * Free all receive software resources
5045 void ixgbe_free_rx_resources(struct ixgbe_adapter
*adapter
,
5046 struct ixgbe_ring
*rx_ring
)
5048 struct pci_dev
*pdev
= adapter
->pdev
;
5050 ixgbe_clean_rx_ring(adapter
, rx_ring
);
5052 vfree(rx_ring
->rx_buffer_info
);
5053 rx_ring
->rx_buffer_info
= NULL
;
5055 dma_free_coherent(&pdev
->dev
, rx_ring
->size
, rx_ring
->desc
,
5058 rx_ring
->desc
= NULL
;
5062 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5063 * @adapter: board private structure
5065 * Free all receive software resources
5067 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
5071 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5072 if (adapter
->rx_ring
[i
]->desc
)
5073 ixgbe_free_rx_resources(adapter
, adapter
->rx_ring
[i
]);
5077 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5078 * @netdev: network interface device structure
5079 * @new_mtu: new value for maximum frame size
5081 * Returns 0 on success, negative on failure
5083 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
5085 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5086 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5088 /* MTU < 68 is an error and causes problems on some kernels */
5089 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
5092 e_info(probe
, "changing MTU from %d to %d\n", netdev
->mtu
, new_mtu
);
5093 /* must set new MTU before calling down or up */
5094 netdev
->mtu
= new_mtu
;
5096 if (netif_running(netdev
))
5097 ixgbe_reinit_locked(adapter
);
5103 * ixgbe_open - Called when a network interface is made active
5104 * @netdev: network interface device structure
5106 * Returns 0 on success, negative value on failure
5108 * The open entry point is called when a network interface is made
5109 * active by the system (IFF_UP). At this point all resources needed
5110 * for transmit and receive operations are allocated, the interrupt
5111 * handler is registered with the OS, the watchdog timer is started,
5112 * and the stack is notified that the interface is ready.
5114 static int ixgbe_open(struct net_device
*netdev
)
5116 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5119 /* disallow open during test */
5120 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
5123 netif_carrier_off(netdev
);
5125 /* allocate transmit descriptors */
5126 err
= ixgbe_setup_all_tx_resources(adapter
);
5130 /* allocate receive descriptors */
5131 err
= ixgbe_setup_all_rx_resources(adapter
);
5135 ixgbe_configure(adapter
);
5137 err
= ixgbe_request_irq(adapter
);
5141 err
= ixgbe_up_complete(adapter
);
5145 netif_tx_start_all_queues(netdev
);
5150 ixgbe_release_hw_control(adapter
);
5151 ixgbe_free_irq(adapter
);
5154 ixgbe_free_all_rx_resources(adapter
);
5156 ixgbe_free_all_tx_resources(adapter
);
5157 ixgbe_reset(adapter
);
5163 * ixgbe_close - Disables a network interface
5164 * @netdev: network interface device structure
5166 * Returns 0, this is not allowed to fail
5168 * The close entry point is called when an interface is de-activated
5169 * by the OS. The hardware is still under the drivers control, but
5170 * needs to be disabled. A global MAC reset is issued to stop the
5171 * hardware, and all transmit and receive resources are freed.
5173 static int ixgbe_close(struct net_device
*netdev
)
5175 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5177 ixgbe_down(adapter
);
5178 ixgbe_free_irq(adapter
);
5180 ixgbe_free_all_tx_resources(adapter
);
5181 ixgbe_free_all_rx_resources(adapter
);
5183 ixgbe_release_hw_control(adapter
);
5189 static int ixgbe_resume(struct pci_dev
*pdev
)
5191 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5192 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5195 pci_set_power_state(pdev
, PCI_D0
);
5196 pci_restore_state(pdev
);
5198 * pci_restore_state clears dev->state_saved so call
5199 * pci_save_state to restore it.
5201 pci_save_state(pdev
);
5203 err
= pci_enable_device_mem(pdev
);
5205 e_dev_err("Cannot enable PCI device from suspend\n");
5208 pci_set_master(pdev
);
5210 pci_wake_from_d3(pdev
, false);
5212 err
= ixgbe_init_interrupt_scheme(adapter
);
5214 e_dev_err("Cannot initialize interrupts for device\n");
5218 ixgbe_reset(adapter
);
5220 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5222 if (netif_running(netdev
)) {
5223 err
= ixgbe_open(adapter
->netdev
);
5228 netif_device_attach(netdev
);
5232 #endif /* CONFIG_PM */
5234 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5236 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5237 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5238 struct ixgbe_hw
*hw
= &adapter
->hw
;
5240 u32 wufc
= adapter
->wol
;
5245 netif_device_detach(netdev
);
5247 if (netif_running(netdev
)) {
5248 ixgbe_down(adapter
);
5249 ixgbe_free_irq(adapter
);
5250 ixgbe_free_all_tx_resources(adapter
);
5251 ixgbe_free_all_rx_resources(adapter
);
5255 retval
= pci_save_state(pdev
);
5261 ixgbe_set_rx_mode(netdev
);
5263 /* turn on all-multi mode if wake on multicast is enabled */
5264 if (wufc
& IXGBE_WUFC_MC
) {
5265 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5266 fctrl
|= IXGBE_FCTRL_MPE
;
5267 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
5270 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
5271 ctrl
|= IXGBE_CTRL_GIO_DIS
;
5272 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
5274 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
5276 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
5277 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
5280 if (wufc
&& hw
->mac
.type
== ixgbe_mac_82599EB
)
5281 pci_wake_from_d3(pdev
, true);
5283 pci_wake_from_d3(pdev
, false);
5285 *enable_wake
= !!wufc
;
5287 ixgbe_clear_interrupt_scheme(adapter
);
5289 ixgbe_release_hw_control(adapter
);
5291 pci_disable_device(pdev
);
5297 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5302 retval
= __ixgbe_shutdown(pdev
, &wake
);
5307 pci_prepare_to_sleep(pdev
);
5309 pci_wake_from_d3(pdev
, false);
5310 pci_set_power_state(pdev
, PCI_D3hot
);
5315 #endif /* CONFIG_PM */
5317 static void ixgbe_shutdown(struct pci_dev
*pdev
)
5321 __ixgbe_shutdown(pdev
, &wake
);
5323 if (system_state
== SYSTEM_POWER_OFF
) {
5324 pci_wake_from_d3(pdev
, wake
);
5325 pci_set_power_state(pdev
, PCI_D3hot
);
5330 * ixgbe_update_stats - Update the board statistics counters.
5331 * @adapter: board private structure
5333 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
5335 struct net_device
*netdev
= adapter
->netdev
;
5336 struct ixgbe_hw
*hw
= &adapter
->hw
;
5338 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
5339 u64 non_eop_descs
= 0, restart_queue
= 0;
5341 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5342 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5345 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
5348 for (i
= 0; i
< 16; i
++)
5349 adapter
->hw_rx_no_dma_resources
+=
5350 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5351 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5352 rsc_count
+= adapter
->rx_ring
[i
]->rsc_count
;
5353 rsc_flush
+= adapter
->rx_ring
[i
]->rsc_flush
;
5355 adapter
->rsc_total_count
= rsc_count
;
5356 adapter
->rsc_total_flush
= rsc_flush
;
5359 /* gather some stats to the adapter struct that are per queue */
5360 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5361 restart_queue
+= adapter
->tx_ring
[i
]->restart_queue
;
5362 adapter
->restart_queue
= restart_queue
;
5364 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5365 non_eop_descs
+= adapter
->rx_ring
[i
]->non_eop_descs
;
5366 adapter
->non_eop_descs
= non_eop_descs
;
5368 adapter
->stats
.crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
5369 for (i
= 0; i
< 8; i
++) {
5370 /* for packet buffers not used, the register should read 0 */
5371 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
5373 adapter
->stats
.mpc
[i
] += mpc
;
5374 total_mpc
+= adapter
->stats
.mpc
[i
];
5375 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5376 adapter
->stats
.rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
5377 adapter
->stats
.qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
5378 adapter
->stats
.qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
5379 adapter
->stats
.qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
5380 adapter
->stats
.qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
5381 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5382 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
5383 IXGBE_PXONRXCNT(i
));
5384 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
5385 IXGBE_PXOFFRXCNT(i
));
5386 adapter
->stats
.qprdc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5388 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
5390 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
5393 adapter
->stats
.pxontxc
[i
] += IXGBE_READ_REG(hw
,
5395 adapter
->stats
.pxofftxc
[i
] += IXGBE_READ_REG(hw
,
5398 adapter
->stats
.gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
5399 /* work around hardware counting issue */
5400 adapter
->stats
.gprc
-= missed_rx
;
5402 /* 82598 hardware only has a 32 bit counter in the high register */
5403 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5405 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
5406 tmp
= IXGBE_READ_REG(hw
, IXGBE_GORCH
) & 0xF; /* 4 high bits of GORC */
5407 adapter
->stats
.gorc
+= (tmp
<< 32);
5408 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
5409 tmp
= IXGBE_READ_REG(hw
, IXGBE_GOTCH
) & 0xF; /* 4 high bits of GOTC */
5410 adapter
->stats
.gotc
+= (tmp
<< 32);
5411 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
5412 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
5413 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
5414 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
5415 adapter
->stats
.fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
5416 adapter
->stats
.fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
5418 adapter
->stats
.fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
5419 adapter
->stats
.fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
5420 adapter
->stats
.fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
5421 adapter
->stats
.fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
5422 adapter
->stats
.fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
5423 adapter
->stats
.fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
5424 #endif /* IXGBE_FCOE */
5426 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
5427 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
5428 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
5429 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
5430 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
5432 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
5433 adapter
->stats
.bprc
+= bprc
;
5434 adapter
->stats
.mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
5435 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5436 adapter
->stats
.mprc
-= bprc
;
5437 adapter
->stats
.roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
5438 adapter
->stats
.prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
5439 adapter
->stats
.prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
5440 adapter
->stats
.prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
5441 adapter
->stats
.prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
5442 adapter
->stats
.prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
5443 adapter
->stats
.prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
5444 adapter
->stats
.rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
5445 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
5446 adapter
->stats
.lxontxc
+= lxon
;
5447 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
5448 adapter
->stats
.lxofftxc
+= lxoff
;
5449 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5450 adapter
->stats
.gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
5451 adapter
->stats
.mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
5453 * 82598 errata - tx of flow control packets is included in tx counters
5455 xon_off_tot
= lxon
+ lxoff
;
5456 adapter
->stats
.gptc
-= xon_off_tot
;
5457 adapter
->stats
.mptc
-= xon_off_tot
;
5458 adapter
->stats
.gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
5459 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5460 adapter
->stats
.rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
5461 adapter
->stats
.rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
5462 adapter
->stats
.tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
5463 adapter
->stats
.ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
5464 adapter
->stats
.ptc64
-= xon_off_tot
;
5465 adapter
->stats
.ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
5466 adapter
->stats
.ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
5467 adapter
->stats
.ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
5468 adapter
->stats
.ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
5469 adapter
->stats
.ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
5470 adapter
->stats
.bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
5472 /* Fill out the OS statistics structure */
5473 netdev
->stats
.multicast
= adapter
->stats
.mprc
;
5476 netdev
->stats
.rx_errors
= adapter
->stats
.crcerrs
+
5477 adapter
->stats
.rlec
;
5478 netdev
->stats
.rx_dropped
= 0;
5479 netdev
->stats
.rx_length_errors
= adapter
->stats
.rlec
;
5480 netdev
->stats
.rx_crc_errors
= adapter
->stats
.crcerrs
;
5481 netdev
->stats
.rx_missed_errors
= total_mpc
;
5485 * ixgbe_watchdog - Timer Call-back
5486 * @data: pointer to adapter cast into an unsigned long
5488 static void ixgbe_watchdog(unsigned long data
)
5490 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
5491 struct ixgbe_hw
*hw
= &adapter
->hw
;
5496 * Do the watchdog outside of interrupt context due to the lovely
5497 * delays that some of the newer hardware requires
5500 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5501 goto watchdog_short_circuit
;
5503 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5505 * for legacy and MSI interrupts don't set any bits
5506 * that are enabled for EIAM, because this operation
5507 * would set *both* EIMS and EICS for any bit in EIAM
5509 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5510 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5511 goto watchdog_reschedule
;
5514 /* get one bit for every active tx/rx interrupt vector */
5515 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5516 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5517 if (qv
->rxr_count
|| qv
->txr_count
)
5518 eics
|= ((u64
)1 << i
);
5521 /* Cause software interrupt to ensure rx rings are cleaned */
5522 ixgbe_irq_rearm_queues(adapter
, eics
);
5524 watchdog_reschedule
:
5525 /* Reset the timer */
5526 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
5528 watchdog_short_circuit
:
5529 schedule_work(&adapter
->watchdog_task
);
5533 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5534 * @work: pointer to work_struct containing our data
5536 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
5538 struct ixgbe_adapter
*adapter
= container_of(work
,
5539 struct ixgbe_adapter
,
5540 multispeed_fiber_task
);
5541 struct ixgbe_hw
*hw
= &adapter
->hw
;
5545 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
5546 autoneg
= hw
->phy
.autoneg_advertised
;
5547 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
5548 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
5549 hw
->mac
.autotry_restart
= false;
5550 if (hw
->mac
.ops
.setup_link
)
5551 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
5552 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
5553 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
5557 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5558 * @work: pointer to work_struct containing our data
5560 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
5562 struct ixgbe_adapter
*adapter
= container_of(work
,
5563 struct ixgbe_adapter
,
5564 sfp_config_module_task
);
5565 struct ixgbe_hw
*hw
= &adapter
->hw
;
5568 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
5570 /* Time for electrical oscillations to settle down */
5572 err
= hw
->phy
.ops
.identify_sfp(hw
);
5574 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5575 e_dev_err("failed to initialize because an unsupported SFP+ "
5576 "module type was detected.\n");
5577 e_dev_err("Reload the driver after installing a supported "
5579 unregister_netdev(adapter
->netdev
);
5582 hw
->mac
.ops
.setup_sfp(hw
);
5584 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
5585 /* This will also work for DA Twinax connections */
5586 schedule_work(&adapter
->multispeed_fiber_task
);
5587 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
5591 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5592 * @work: pointer to work_struct containing our data
5594 static void ixgbe_fdir_reinit_task(struct work_struct
*work
)
5596 struct ixgbe_adapter
*adapter
= container_of(work
,
5597 struct ixgbe_adapter
,
5599 struct ixgbe_hw
*hw
= &adapter
->hw
;
5602 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5603 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5604 set_bit(__IXGBE_FDIR_INIT_DONE
,
5605 &(adapter
->tx_ring
[i
]->reinit_state
));
5607 e_err(probe
, "failed to finish FDIR re-initialization, "
5608 "ignored adding FDIR ATR filters\n");
5610 /* Done FDIR Re-initialization, enable transmits */
5611 netif_tx_start_all_queues(adapter
->netdev
);
5614 static DEFINE_MUTEX(ixgbe_watchdog_lock
);
5617 * ixgbe_watchdog_task - worker thread to bring link up
5618 * @work: pointer to work_struct containing our data
5620 static void ixgbe_watchdog_task(struct work_struct
*work
)
5622 struct ixgbe_adapter
*adapter
= container_of(work
,
5623 struct ixgbe_adapter
,
5625 struct net_device
*netdev
= adapter
->netdev
;
5626 struct ixgbe_hw
*hw
= &adapter
->hw
;
5630 struct ixgbe_ring
*tx_ring
;
5631 int some_tx_pending
= 0;
5633 mutex_lock(&ixgbe_watchdog_lock
);
5635 link_up
= adapter
->link_up
;
5636 link_speed
= adapter
->link_speed
;
5638 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
5639 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5642 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5643 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5644 hw
->mac
.ops
.fc_enable(hw
, i
);
5646 hw
->mac
.ops
.fc_enable(hw
, 0);
5649 hw
->mac
.ops
.fc_enable(hw
, 0);
5654 time_after(jiffies
, (adapter
->link_check_timeout
+
5655 IXGBE_TRY_LINK_TIMEOUT
))) {
5656 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5657 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
5659 adapter
->link_up
= link_up
;
5660 adapter
->link_speed
= link_speed
;
5664 if (!netif_carrier_ok(netdev
)) {
5665 bool flow_rx
, flow_tx
;
5667 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5668 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
5669 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
5670 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
5671 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
5673 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5674 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
5675 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
5676 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
5679 e_info(drv
, "NIC Link is Up %s, Flow Control: %s\n",
5680 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
5682 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
5683 "1 Gbps" : "unknown speed")),
5684 ((flow_rx
&& flow_tx
) ? "RX/TX" :
5686 (flow_tx
? "TX" : "None"))));
5688 netif_carrier_on(netdev
);
5690 /* Force detection of hung controller */
5691 adapter
->detect_tx_hung
= true;
5694 adapter
->link_up
= false;
5695 adapter
->link_speed
= 0;
5696 if (netif_carrier_ok(netdev
)) {
5697 e_info(drv
, "NIC Link is Down\n");
5698 netif_carrier_off(netdev
);
5702 if (!netif_carrier_ok(netdev
)) {
5703 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5704 tx_ring
= adapter
->tx_ring
[i
];
5705 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
5706 some_tx_pending
= 1;
5711 if (some_tx_pending
) {
5712 /* We've lost link, so the controller stops DMA,
5713 * but we've got queued Tx work that's never going
5714 * to get done, so reset controller to flush Tx.
5715 * (Do the reset outside of interrupt context).
5717 schedule_work(&adapter
->reset_task
);
5721 ixgbe_update_stats(adapter
);
5722 mutex_unlock(&ixgbe_watchdog_lock
);
5725 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
5726 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
5727 u32 tx_flags
, u8
*hdr_len
)
5729 struct ixgbe_adv_tx_context_desc
*context_desc
;
5732 struct ixgbe_tx_buffer
*tx_buffer_info
;
5733 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
5734 u32 mss_l4len_idx
, l4len
;
5736 if (skb_is_gso(skb
)) {
5737 if (skb_header_cloned(skb
)) {
5738 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
5742 l4len
= tcp_hdrlen(skb
);
5745 if (skb
->protocol
== htons(ETH_P_IP
)) {
5746 struct iphdr
*iph
= ip_hdr(skb
);
5749 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5753 } else if (skb_is_gso_v6(skb
)) {
5754 ipv6_hdr(skb
)->payload_len
= 0;
5755 tcp_hdr(skb
)->check
=
5756 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
5757 &ipv6_hdr(skb
)->daddr
,
5761 i
= tx_ring
->next_to_use
;
5763 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5764 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5766 /* VLAN MACLEN IPLEN */
5767 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5769 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5770 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
5771 IXGBE_ADVTXD_MACLEN_SHIFT
);
5772 *hdr_len
+= skb_network_offset(skb
);
5774 (skb_transport_header(skb
) - skb_network_header(skb
));
5776 (skb_transport_header(skb
) - skb_network_header(skb
));
5777 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5778 context_desc
->seqnum_seed
= 0;
5780 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5781 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
5782 IXGBE_ADVTXD_DTYP_CTXT
);
5784 if (skb
->protocol
== htons(ETH_P_IP
))
5785 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5786 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5787 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5791 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
5792 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
5793 /* use index 1 for TSO */
5794 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5795 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
5797 tx_buffer_info
->time_stamp
= jiffies
;
5798 tx_buffer_info
->next_to_watch
= i
;
5801 if (i
== tx_ring
->count
)
5803 tx_ring
->next_to_use
= i
;
5810 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
5811 struct ixgbe_ring
*tx_ring
,
5812 struct sk_buff
*skb
, u32 tx_flags
)
5814 struct ixgbe_adv_tx_context_desc
*context_desc
;
5816 struct ixgbe_tx_buffer
*tx_buffer_info
;
5817 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
5819 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
5820 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
5821 i
= tx_ring
->next_to_use
;
5822 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5823 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5825 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5827 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5828 vlan_macip_lens
|= (skb_network_offset(skb
) <<
5829 IXGBE_ADVTXD_MACLEN_SHIFT
);
5830 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5831 vlan_macip_lens
|= (skb_transport_header(skb
) -
5832 skb_network_header(skb
));
5834 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5835 context_desc
->seqnum_seed
= 0;
5837 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
5838 IXGBE_ADVTXD_DTYP_CTXT
);
5840 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5843 if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
)) {
5844 const struct vlan_ethhdr
*vhdr
=
5845 (const struct vlan_ethhdr
*)skb
->data
;
5847 protocol
= vhdr
->h_vlan_encapsulated_proto
;
5849 protocol
= skb
->protocol
;
5853 case cpu_to_be16(ETH_P_IP
):
5854 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5855 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
5857 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5858 else if (ip_hdr(skb
)->protocol
== IPPROTO_SCTP
)
5860 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5862 case cpu_to_be16(ETH_P_IPV6
):
5863 /* XXX what about other V6 headers?? */
5864 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
5866 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5867 else if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_SCTP
)
5869 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5872 if (unlikely(net_ratelimit())) {
5873 e_warn(probe
, "partial checksum "
5881 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5882 /* use index zero for tx checksum offload */
5883 context_desc
->mss_l4len_idx
= 0;
5885 tx_buffer_info
->time_stamp
= jiffies
;
5886 tx_buffer_info
->next_to_watch
= i
;
5889 if (i
== tx_ring
->count
)
5891 tx_ring
->next_to_use
= i
;
5899 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
5900 struct ixgbe_ring
*tx_ring
,
5901 struct sk_buff
*skb
, u32 tx_flags
,
5904 struct pci_dev
*pdev
= adapter
->pdev
;
5905 struct ixgbe_tx_buffer
*tx_buffer_info
;
5907 unsigned int total
= skb
->len
;
5908 unsigned int offset
= 0, size
, count
= 0, i
;
5909 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
5912 i
= tx_ring
->next_to_use
;
5914 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
5915 /* excluding fcoe_crc_eof for FCoE */
5916 total
-= sizeof(struct fcoe_crc_eof
);
5918 len
= min(skb_headlen(skb
), total
);
5920 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5921 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5923 tx_buffer_info
->length
= size
;
5924 tx_buffer_info
->mapped_as_page
= false;
5925 tx_buffer_info
->dma
= dma_map_single(&pdev
->dev
,
5927 size
, DMA_TO_DEVICE
);
5928 if (dma_mapping_error(&pdev
->dev
, tx_buffer_info
->dma
))
5930 tx_buffer_info
->time_stamp
= jiffies
;
5931 tx_buffer_info
->next_to_watch
= i
;
5940 if (i
== tx_ring
->count
)
5945 for (f
= 0; f
< nr_frags
; f
++) {
5946 struct skb_frag_struct
*frag
;
5948 frag
= &skb_shinfo(skb
)->frags
[f
];
5949 len
= min((unsigned int)frag
->size
, total
);
5950 offset
= frag
->page_offset
;
5954 if (i
== tx_ring
->count
)
5957 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5958 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5960 tx_buffer_info
->length
= size
;
5961 tx_buffer_info
->dma
= dma_map_page(&adapter
->pdev
->dev
,
5965 tx_buffer_info
->mapped_as_page
= true;
5966 if (dma_mapping_error(&pdev
->dev
, tx_buffer_info
->dma
))
5968 tx_buffer_info
->time_stamp
= jiffies
;
5969 tx_buffer_info
->next_to_watch
= i
;
5980 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
5981 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
5986 e_dev_err("TX DMA map failed\n");
5988 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5989 tx_buffer_info
->dma
= 0;
5990 tx_buffer_info
->time_stamp
= 0;
5991 tx_buffer_info
->next_to_watch
= 0;
5995 /* clear timestamp and dma mappings for remaining portion of packet */
5998 i
+= tx_ring
->count
;
6000 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6001 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
6007 static void ixgbe_tx_queue(struct ixgbe_adapter
*adapter
,
6008 struct ixgbe_ring
*tx_ring
,
6009 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
6011 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
6012 struct ixgbe_tx_buffer
*tx_buffer_info
;
6013 u32 olinfo_status
= 0, cmd_type_len
= 0;
6015 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
6017 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
6019 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
6021 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6022 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
6024 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
6025 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6027 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6028 IXGBE_ADVTXD_POPTS_SHIFT
;
6030 /* use index 1 context for tso */
6031 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6032 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
6033 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
6034 IXGBE_ADVTXD_POPTS_SHIFT
;
6036 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
6037 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6038 IXGBE_ADVTXD_POPTS_SHIFT
;
6040 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6041 olinfo_status
|= IXGBE_ADVTXD_CC
;
6042 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6043 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6044 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6047 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
6049 i
= tx_ring
->next_to_use
;
6051 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6052 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
6053 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
6054 tx_desc
->read
.cmd_type_len
=
6055 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
6056 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
6058 if (i
== tx_ring
->count
)
6062 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
6065 * Force memory writes to complete before letting h/w
6066 * know there are new descriptors to fetch. (Only
6067 * applicable for weak-ordered memory model archs,
6072 tx_ring
->next_to_use
= i
;
6073 writel(i
, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
6076 static void ixgbe_atr(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
6077 int queue
, u32 tx_flags
)
6079 struct ixgbe_atr_input atr_input
;
6081 struct iphdr
*iph
= ip_hdr(skb
);
6082 struct ethhdr
*eth
= (struct ethhdr
*)skb
->data
;
6083 u16 vlan_id
, src_port
, dst_port
, flex_bytes
;
6084 u32 src_ipv4_addr
, dst_ipv4_addr
;
6087 /* Right now, we support IPv4 only */
6088 if (skb
->protocol
!= htons(ETH_P_IP
))
6090 /* check if we're UDP or TCP */
6091 if (iph
->protocol
== IPPROTO_TCP
) {
6093 src_port
= th
->source
;
6094 dst_port
= th
->dest
;
6095 l4type
|= IXGBE_ATR_L4TYPE_TCP
;
6096 /* l4type IPv4 type is 0, no need to assign */
6098 /* Unsupported L4 header, just bail here */
6102 memset(&atr_input
, 0, sizeof(struct ixgbe_atr_input
));
6104 vlan_id
= (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
) >>
6105 IXGBE_TX_FLAGS_VLAN_SHIFT
;
6106 src_ipv4_addr
= iph
->saddr
;
6107 dst_ipv4_addr
= iph
->daddr
;
6108 flex_bytes
= eth
->h_proto
;
6110 ixgbe_atr_set_vlan_id_82599(&atr_input
, vlan_id
);
6111 ixgbe_atr_set_src_port_82599(&atr_input
, dst_port
);
6112 ixgbe_atr_set_dst_port_82599(&atr_input
, src_port
);
6113 ixgbe_atr_set_flex_byte_82599(&atr_input
, flex_bytes
);
6114 ixgbe_atr_set_l4type_82599(&atr_input
, l4type
);
6115 /* src and dst are inverted, think how the receiver sees them */
6116 ixgbe_atr_set_src_ipv4_82599(&atr_input
, dst_ipv4_addr
);
6117 ixgbe_atr_set_dst_ipv4_82599(&atr_input
, src_ipv4_addr
);
6119 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6120 ixgbe_fdir_add_signature_filter_82599(&adapter
->hw
, &atr_input
, queue
);
6123 static int __ixgbe_maybe_stop_tx(struct net_device
*netdev
,
6124 struct ixgbe_ring
*tx_ring
, int size
)
6126 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
6127 /* Herbert's original patch had:
6128 * smp_mb__after_netif_stop_queue();
6129 * but since that doesn't exist yet, just open code it. */
6132 /* We need to check again in a case another CPU has just
6133 * made room available. */
6134 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
6137 /* A reprieve! - use start_queue because it doesn't call schedule */
6138 netif_start_subqueue(netdev
, tx_ring
->queue_index
);
6139 ++tx_ring
->restart_queue
;
6143 static int ixgbe_maybe_stop_tx(struct net_device
*netdev
,
6144 struct ixgbe_ring
*tx_ring
, int size
)
6146 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
6148 return __ixgbe_maybe_stop_tx(netdev
, tx_ring
, size
);
6151 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
6153 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6154 int txq
= smp_processor_id();
6157 if ((skb
->protocol
== htons(ETH_P_FCOE
)) ||
6158 (skb
->protocol
== htons(ETH_P_FIP
))) {
6159 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
6160 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
6161 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
6163 #ifdef CONFIG_IXGBE_DCB
6164 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6165 txq
= adapter
->fcoe
.up
;
6172 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
6173 while (unlikely(txq
>= dev
->real_num_tx_queues
))
6174 txq
-= dev
->real_num_tx_queues
;
6178 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6179 if (skb
->priority
== TC_PRIO_CONTROL
)
6180 txq
= adapter
->ring_feature
[RING_F_DCB
].indices
-1;
6182 txq
= (skb
->vlan_tci
& IXGBE_TX_FLAGS_VLAN_PRIO_MASK
)
6187 return skb_tx_hash(dev
, skb
);
6190 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
,
6191 struct net_device
*netdev
)
6193 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6194 struct ixgbe_ring
*tx_ring
;
6195 struct netdev_queue
*txq
;
6197 unsigned int tx_flags
= 0;
6203 if (adapter
->vlgrp
&& vlan_tx_tag_present(skb
)) {
6204 tx_flags
|= vlan_tx_tag_get(skb
);
6205 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6206 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
6207 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6209 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6210 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6211 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
&&
6212 skb
->priority
!= TC_PRIO_CONTROL
) {
6213 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6214 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6215 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6218 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
6221 /* for FCoE with DCB, we force the priority to what
6222 * was specified by the switch */
6223 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
&&
6224 (skb
->protocol
== htons(ETH_P_FCOE
) ||
6225 skb
->protocol
== htons(ETH_P_FIP
))) {
6226 #ifdef CONFIG_IXGBE_DCB
6227 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6228 tx_flags
&= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6229 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6230 tx_flags
|= ((adapter
->fcoe
.up
<< 13)
6231 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6234 /* flag for FCoE offloads */
6235 if (skb
->protocol
== htons(ETH_P_FCOE
))
6236 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
6240 /* four things can cause us to need a context descriptor */
6241 if (skb_is_gso(skb
) ||
6242 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
6243 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
6244 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
6247 count
+= TXD_USE_COUNT(skb_headlen(skb
));
6248 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
6249 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
6251 if (ixgbe_maybe_stop_tx(netdev
, tx_ring
, count
)) {
6253 return NETDEV_TX_BUSY
;
6256 first
= tx_ring
->next_to_use
;
6257 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6259 /* setup tx offload for FCoE */
6260 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6262 dev_kfree_skb_any(skb
);
6263 return NETDEV_TX_OK
;
6266 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
6267 #endif /* IXGBE_FCOE */
6269 if (skb
->protocol
== htons(ETH_P_IP
))
6270 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
6271 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6273 dev_kfree_skb_any(skb
);
6274 return NETDEV_TX_OK
;
6278 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
6279 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
) &&
6280 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
6281 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
6284 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
);
6286 /* add the ATR filter if ATR is on */
6287 if (tx_ring
->atr_sample_rate
) {
6288 ++tx_ring
->atr_count
;
6289 if ((tx_ring
->atr_count
>= tx_ring
->atr_sample_rate
) &&
6290 test_bit(__IXGBE_FDIR_INIT_DONE
,
6291 &tx_ring
->reinit_state
)) {
6292 ixgbe_atr(adapter
, skb
, tx_ring
->queue_index
,
6294 tx_ring
->atr_count
= 0;
6297 txq
= netdev_get_tx_queue(netdev
, tx_ring
->queue_index
);
6298 txq
->tx_bytes
+= skb
->len
;
6300 ixgbe_tx_queue(adapter
, tx_ring
, tx_flags
, count
, skb
->len
,
6302 ixgbe_maybe_stop_tx(netdev
, tx_ring
, DESC_NEEDED
);
6305 dev_kfree_skb_any(skb
);
6306 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
6307 tx_ring
->next_to_use
= first
;
6310 return NETDEV_TX_OK
;
6314 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6315 * @netdev: network interface device structure
6316 * @p: pointer to an address structure
6318 * Returns 0 on success, negative on failure
6320 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
6322 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6323 struct ixgbe_hw
*hw
= &adapter
->hw
;
6324 struct sockaddr
*addr
= p
;
6326 if (!is_valid_ether_addr(addr
->sa_data
))
6327 return -EADDRNOTAVAIL
;
6329 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
6330 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
6332 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
6339 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
6341 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6342 struct ixgbe_hw
*hw
= &adapter
->hw
;
6346 if (prtad
!= hw
->phy
.mdio
.prtad
)
6348 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
6354 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
6355 u16 addr
, u16 value
)
6357 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6358 struct ixgbe_hw
*hw
= &adapter
->hw
;
6360 if (prtad
!= hw
->phy
.mdio
.prtad
)
6362 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
6365 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
6367 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6369 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
6373 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6375 * @netdev: network interface device structure
6377 * Returns non-zero on failure
6379 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
6382 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6383 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6385 if (is_valid_ether_addr(mac
->san_addr
)) {
6387 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6394 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6396 * @netdev: network interface device structure
6398 * Returns non-zero on failure
6400 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
6403 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6404 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6406 if (is_valid_ether_addr(mac
->san_addr
)) {
6408 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6414 #ifdef CONFIG_NET_POLL_CONTROLLER
6416 * Polling 'interrupt' - used by things like netconsole to send skbs
6417 * without having to re-enable interrupts. It's not called while
6418 * the interrupt routine is executing.
6420 static void ixgbe_netpoll(struct net_device
*netdev
)
6422 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6425 /* if interface is down do nothing */
6426 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6429 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
6430 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
6431 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
6432 for (i
= 0; i
< num_q_vectors
; i
++) {
6433 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
6434 ixgbe_msix_clean_many(0, q_vector
);
6437 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
6439 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
6443 static const struct net_device_ops ixgbe_netdev_ops
= {
6444 .ndo_open
= ixgbe_open
,
6445 .ndo_stop
= ixgbe_close
,
6446 .ndo_start_xmit
= ixgbe_xmit_frame
,
6447 .ndo_select_queue
= ixgbe_select_queue
,
6448 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
6449 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
6450 .ndo_validate_addr
= eth_validate_addr
,
6451 .ndo_set_mac_address
= ixgbe_set_mac
,
6452 .ndo_change_mtu
= ixgbe_change_mtu
,
6453 .ndo_tx_timeout
= ixgbe_tx_timeout
,
6454 .ndo_vlan_rx_register
= ixgbe_vlan_rx_register
,
6455 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
6456 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
6457 .ndo_do_ioctl
= ixgbe_ioctl
,
6458 .ndo_set_vf_mac
= ixgbe_ndo_set_vf_mac
,
6459 .ndo_set_vf_vlan
= ixgbe_ndo_set_vf_vlan
,
6460 .ndo_set_vf_tx_rate
= ixgbe_ndo_set_vf_bw
,
6461 .ndo_get_vf_config
= ixgbe_ndo_get_vf_config
,
6462 #ifdef CONFIG_NET_POLL_CONTROLLER
6463 .ndo_poll_controller
= ixgbe_netpoll
,
6466 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
6467 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
6468 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
6469 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
6470 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
6471 #endif /* IXGBE_FCOE */
6474 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
6475 const struct ixgbe_info
*ii
)
6477 #ifdef CONFIG_PCI_IOV
6478 struct ixgbe_hw
*hw
= &adapter
->hw
;
6481 if (hw
->mac
.type
!= ixgbe_mac_82599EB
|| !max_vfs
)
6484 /* The 82599 supports up to 64 VFs per physical function
6485 * but this implementation limits allocation to 63 so that
6486 * basic networking resources are still available to the
6489 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
6490 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
6491 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
6493 e_err(probe
, "Failed to enable PCI sriov: %d\n", err
);
6496 /* If call to enable VFs succeeded then allocate memory
6497 * for per VF control structures.
6500 kcalloc(adapter
->num_vfs
,
6501 sizeof(struct vf_data_storage
), GFP_KERNEL
);
6502 if (adapter
->vfinfo
) {
6503 /* Now that we're sure SR-IOV is enabled
6504 * and memory allocated set up the mailbox parameters
6506 ixgbe_init_mbx_params_pf(hw
);
6507 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
6508 sizeof(hw
->mbx
.ops
));
6510 /* Disable RSC when in SR-IOV mode */
6511 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
6512 IXGBE_FLAG2_RSC_ENABLED
);
6517 e_err(probe
, "Unable to allocate memory for VF Data Storage - "
6518 "SRIOV disabled\n");
6519 pci_disable_sriov(adapter
->pdev
);
6522 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
6523 adapter
->num_vfs
= 0;
6524 #endif /* CONFIG_PCI_IOV */
6528 * ixgbe_probe - Device Initialization Routine
6529 * @pdev: PCI device information struct
6530 * @ent: entry in ixgbe_pci_tbl
6532 * Returns 0 on success, negative on failure
6534 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6535 * The OS initialization, configuring of the adapter private structure,
6536 * and a hardware reset occur.
6538 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
6539 const struct pci_device_id
*ent
)
6541 struct net_device
*netdev
;
6542 struct ixgbe_adapter
*adapter
= NULL
;
6543 struct ixgbe_hw
*hw
;
6544 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
6545 static int cards_found
;
6546 int i
, err
, pci_using_dac
;
6547 unsigned int indices
= num_possible_cpus();
6553 /* Catch broken hardware that put the wrong VF device ID in
6554 * the PCIe SR-IOV capability.
6556 if (pdev
->is_virtfn
) {
6557 WARN(1, KERN_ERR
"%s (%hx:%hx) should not be a VF!\n",
6558 pci_name(pdev
), pdev
->vendor
, pdev
->device
);
6562 err
= pci_enable_device_mem(pdev
);
6566 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
6567 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
6570 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
6572 err
= dma_set_coherent_mask(&pdev
->dev
,
6576 "No usable DMA configuration, aborting\n");
6583 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
6584 IORESOURCE_MEM
), ixgbe_driver_name
);
6587 "pci_request_selected_regions failed 0x%x\n", err
);
6591 pci_enable_pcie_error_reporting(pdev
);
6593 pci_set_master(pdev
);
6594 pci_save_state(pdev
);
6596 if (ii
->mac
== ixgbe_mac_82598EB
)
6597 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
6599 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
6601 indices
= max_t(unsigned int, indices
, IXGBE_MAX_DCB_INDICES
);
6603 indices
+= min_t(unsigned int, num_possible_cpus(),
6604 IXGBE_MAX_FCOE_INDICES
);
6606 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
6609 goto err_alloc_etherdev
;
6612 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
6614 pci_set_drvdata(pdev
, netdev
);
6615 adapter
= netdev_priv(netdev
);
6617 adapter
->netdev
= netdev
;
6618 adapter
->pdev
= pdev
;
6621 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
6623 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
6624 pci_resource_len(pdev
, 0));
6630 for (i
= 1; i
<= 5; i
++) {
6631 if (pci_resource_len(pdev
, i
) == 0)
6635 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
6636 ixgbe_set_ethtool_ops(netdev
);
6637 netdev
->watchdog_timeo
= 5 * HZ
;
6638 strcpy(netdev
->name
, pci_name(pdev
));
6640 adapter
->bd_number
= cards_found
;
6643 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
6644 hw
->mac
.type
= ii
->mac
;
6647 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
6648 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
6649 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6650 if (!(eec
& (1 << 8)))
6651 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
6654 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
6655 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
6656 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6657 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
6658 hw
->phy
.mdio
.mmds
= 0;
6659 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
6660 hw
->phy
.mdio
.dev
= netdev
;
6661 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
6662 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
6664 /* set up this timer and work struct before calling get_invariants
6665 * which might start the timer
6667 init_timer(&adapter
->sfp_timer
);
6668 adapter
->sfp_timer
.function
= &ixgbe_sfp_timer
;
6669 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
6671 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
6673 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6674 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
6676 /* a new SFP+ module arrival, called from GPI SDP2 context */
6677 INIT_WORK(&adapter
->sfp_config_module_task
,
6678 ixgbe_sfp_config_module_task
);
6680 ii
->get_invariants(hw
);
6682 /* setup the private structure */
6683 err
= ixgbe_sw_init(adapter
);
6687 /* Make it possible the adapter to be woken up via WOL */
6688 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6689 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6692 * If there is a fan on this device and it has failed log the
6695 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
6696 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
6697 if (esdp
& IXGBE_ESDP_SDP1
)
6698 e_crit(probe
, "Fan has stopped, replace the adapter\n");
6701 /* reset_hw fills in the perm_addr as well */
6702 hw
->phy
.reset_if_overtemp
= true;
6703 err
= hw
->mac
.ops
.reset_hw(hw
);
6704 hw
->phy
.reset_if_overtemp
= false;
6705 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
6706 hw
->mac
.type
== ixgbe_mac_82598EB
) {
6708 * Start a kernel thread to watch for a module to arrive.
6709 * Only do this for 82598, since 82599 will generate
6710 * interrupts on module arrival.
6712 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6713 mod_timer(&adapter
->sfp_timer
,
6714 round_jiffies(jiffies
+ (2 * HZ
)));
6716 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
6717 e_dev_err("failed to initialize because an unsupported SFP+ "
6718 "module type was detected.\n");
6719 e_dev_err("Reload the driver after installing a supported "
6723 e_dev_err("HW Init failed: %d\n", err
);
6727 ixgbe_probe_vf(adapter
, ii
);
6729 netdev
->features
= NETIF_F_SG
|
6731 NETIF_F_HW_VLAN_TX
|
6732 NETIF_F_HW_VLAN_RX
|
6733 NETIF_F_HW_VLAN_FILTER
;
6735 netdev
->features
|= NETIF_F_IPV6_CSUM
;
6736 netdev
->features
|= NETIF_F_TSO
;
6737 netdev
->features
|= NETIF_F_TSO6
;
6738 netdev
->features
|= NETIF_F_GRO
;
6740 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6741 netdev
->features
|= NETIF_F_SCTP_CSUM
;
6743 netdev
->vlan_features
|= NETIF_F_TSO
;
6744 netdev
->vlan_features
|= NETIF_F_TSO6
;
6745 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
6746 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
6747 netdev
->vlan_features
|= NETIF_F_SG
;
6749 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6750 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
6751 IXGBE_FLAG_DCB_ENABLED
);
6752 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
6753 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
6755 #ifdef CONFIG_IXGBE_DCB
6756 netdev
->dcbnl_ops
= &dcbnl_ops
;
6760 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
6761 if (hw
->mac
.ops
.get_device_caps
) {
6762 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
6763 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
6764 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
6767 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
6768 netdev
->vlan_features
|= NETIF_F_FCOE_CRC
;
6769 netdev
->vlan_features
|= NETIF_F_FSO
;
6770 netdev
->vlan_features
|= NETIF_F_FCOE_MTU
;
6772 #endif /* IXGBE_FCOE */
6774 netdev
->features
|= NETIF_F_HIGHDMA
;
6776 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
6777 netdev
->features
|= NETIF_F_LRO
;
6779 /* make sure the EEPROM is good */
6780 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
6781 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6786 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6787 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6789 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
6790 e_dev_err("invalid MAC address\n");
6795 /* power down the optics */
6796 if (hw
->phy
.multispeed_fiber
)
6797 hw
->mac
.ops
.disable_tx_laser(hw
);
6799 init_timer(&adapter
->watchdog_timer
);
6800 adapter
->watchdog_timer
.function
= &ixgbe_watchdog
;
6801 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
6803 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
6804 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
6806 err
= ixgbe_init_interrupt_scheme(adapter
);
6810 switch (pdev
->device
) {
6811 case IXGBE_DEV_ID_82599_KX4
:
6812 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
6813 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
6819 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
6821 /* pick up the PCI bus settings for reporting later */
6822 hw
->mac
.ops
.get_bus_info(hw
);
6824 /* print bus type/speed/width info */
6825 e_dev_info("(PCI Express:%s:%s) %pM\n",
6826 ((hw
->bus
.speed
== ixgbe_bus_speed_5000
) ? "5.0Gb/s":
6827 (hw
->bus
.speed
== ixgbe_bus_speed_2500
) ? "2.5Gb/s":"Unknown"),
6828 ((hw
->bus
.width
== ixgbe_bus_width_pcie_x8
) ? "Width x8" :
6829 (hw
->bus
.width
== ixgbe_bus_width_pcie_x4
) ? "Width x4" :
6830 (hw
->bus
.width
== ixgbe_bus_width_pcie_x1
) ? "Width x1" :
6833 ixgbe_read_pba_num_generic(hw
, &part_num
);
6834 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
6835 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6836 "PBA No: %06x-%03x\n",
6837 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
6838 (part_num
>> 8), (part_num
& 0xff));
6840 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6841 hw
->mac
.type
, hw
->phy
.type
,
6842 (part_num
>> 8), (part_num
& 0xff));
6844 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
6845 e_dev_warn("PCI-Express bandwidth available for this card is "
6846 "not sufficient for optimal performance.\n");
6847 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6851 /* save off EEPROM version number */
6852 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
6854 /* reset the hardware with the new settings */
6855 err
= hw
->mac
.ops
.start_hw(hw
);
6857 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
6858 /* We are running on a pre-production device, log a warning */
6859 e_dev_warn("This device is a pre-production adapter/LOM. "
6860 "Please be aware there may be issues associated "
6861 "with your hardware. If you are experiencing "
6862 "problems please contact your Intel or hardware "
6863 "representative who provided you with this "
6866 strcpy(netdev
->name
, "eth%d");
6867 err
= register_netdev(netdev
);
6871 /* carrier off reporting is important to ethtool even BEFORE open */
6872 netif_carrier_off(netdev
);
6874 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6875 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6876 INIT_WORK(&adapter
->fdir_reinit_task
, ixgbe_fdir_reinit_task
);
6878 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
6879 INIT_WORK(&adapter
->check_overtemp_task
, ixgbe_check_overtemp_task
);
6880 #ifdef CONFIG_IXGBE_DCA
6881 if (dca_add_requester(&pdev
->dev
) == 0) {
6882 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
6883 ixgbe_setup_dca(adapter
);
6886 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
6887 e_info(probe
, "IOV is enabled with %d VFs\n", adapter
->num_vfs
);
6888 for (i
= 0; i
< adapter
->num_vfs
; i
++)
6889 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
6892 /* add san mac addr to netdev */
6893 ixgbe_add_sanmac_netdev(netdev
);
6895 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
6900 ixgbe_release_hw_control(adapter
);
6901 ixgbe_clear_interrupt_scheme(adapter
);
6904 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6905 ixgbe_disable_sriov(adapter
);
6906 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6907 del_timer_sync(&adapter
->sfp_timer
);
6908 cancel_work_sync(&adapter
->sfp_task
);
6909 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6910 cancel_work_sync(&adapter
->sfp_config_module_task
);
6911 iounmap(hw
->hw_addr
);
6913 free_netdev(netdev
);
6915 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6919 pci_disable_device(pdev
);
6924 * ixgbe_remove - Device Removal Routine
6925 * @pdev: PCI device information struct
6927 * ixgbe_remove is called by the PCI subsystem to alert the driver
6928 * that it should release a PCI device. The could be caused by a
6929 * Hot-Plug event, or because the driver is going to be removed from
6932 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
6934 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6935 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6937 set_bit(__IXGBE_DOWN
, &adapter
->state
);
6938 /* clear the module not found bit to make sure the worker won't
6941 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6942 del_timer_sync(&adapter
->watchdog_timer
);
6944 del_timer_sync(&adapter
->sfp_timer
);
6945 cancel_work_sync(&adapter
->watchdog_task
);
6946 cancel_work_sync(&adapter
->sfp_task
);
6947 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6948 cancel_work_sync(&adapter
->sfp_config_module_task
);
6949 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6950 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6951 cancel_work_sync(&adapter
->fdir_reinit_task
);
6952 flush_scheduled_work();
6954 #ifdef CONFIG_IXGBE_DCA
6955 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
6956 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
6957 dca_remove_requester(&pdev
->dev
);
6958 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
6963 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
6964 ixgbe_cleanup_fcoe(adapter
);
6966 #endif /* IXGBE_FCOE */
6968 /* remove the added san mac */
6969 ixgbe_del_sanmac_netdev(netdev
);
6971 if (netdev
->reg_state
== NETREG_REGISTERED
)
6972 unregister_netdev(netdev
);
6974 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6975 ixgbe_disable_sriov(adapter
);
6977 ixgbe_clear_interrupt_scheme(adapter
);
6979 ixgbe_release_hw_control(adapter
);
6981 iounmap(adapter
->hw
.hw_addr
);
6982 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6985 e_dev_info("complete\n");
6987 free_netdev(netdev
);
6989 pci_disable_pcie_error_reporting(pdev
);
6991 pci_disable_device(pdev
);
6995 * ixgbe_io_error_detected - called when PCI error is detected
6996 * @pdev: Pointer to PCI device
6997 * @state: The current pci connection state
6999 * This function is called after a PCI bus error affecting
7000 * this device has been detected.
7002 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
7003 pci_channel_state_t state
)
7005 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7006 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7008 netif_device_detach(netdev
);
7010 if (state
== pci_channel_io_perm_failure
)
7011 return PCI_ERS_RESULT_DISCONNECT
;
7013 if (netif_running(netdev
))
7014 ixgbe_down(adapter
);
7015 pci_disable_device(pdev
);
7017 /* Request a slot reset. */
7018 return PCI_ERS_RESULT_NEED_RESET
;
7022 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7023 * @pdev: Pointer to PCI device
7025 * Restart the card from scratch, as if from a cold-boot.
7027 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
7029 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7030 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7031 pci_ers_result_t result
;
7034 if (pci_enable_device_mem(pdev
)) {
7035 e_err(probe
, "Cannot re-enable PCI device after reset.\n");
7036 result
= PCI_ERS_RESULT_DISCONNECT
;
7038 pci_set_master(pdev
);
7039 pci_restore_state(pdev
);
7040 pci_save_state(pdev
);
7042 pci_wake_from_d3(pdev
, false);
7044 ixgbe_reset(adapter
);
7045 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7046 result
= PCI_ERS_RESULT_RECOVERED
;
7049 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7051 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7052 "failed 0x%0x\n", err
);
7053 /* non-fatal, continue */
7060 * ixgbe_io_resume - called when traffic can start flowing again.
7061 * @pdev: Pointer to PCI device
7063 * This callback is called when the error recovery driver tells us that
7064 * its OK to resume normal operation.
7066 static void ixgbe_io_resume(struct pci_dev
*pdev
)
7068 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7069 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7071 if (netif_running(netdev
)) {
7072 if (ixgbe_up(adapter
)) {
7073 e_info(probe
, "ixgbe_up failed after reset\n");
7078 netif_device_attach(netdev
);
7081 static struct pci_error_handlers ixgbe_err_handler
= {
7082 .error_detected
= ixgbe_io_error_detected
,
7083 .slot_reset
= ixgbe_io_slot_reset
,
7084 .resume
= ixgbe_io_resume
,
7087 static struct pci_driver ixgbe_driver
= {
7088 .name
= ixgbe_driver_name
,
7089 .id_table
= ixgbe_pci_tbl
,
7090 .probe
= ixgbe_probe
,
7091 .remove
= __devexit_p(ixgbe_remove
),
7093 .suspend
= ixgbe_suspend
,
7094 .resume
= ixgbe_resume
,
7096 .shutdown
= ixgbe_shutdown
,
7097 .err_handler
= &ixgbe_err_handler
7101 * ixgbe_init_module - Driver Registration Routine
7103 * ixgbe_init_module is the first routine called when the driver is
7104 * loaded. All it does is register with the PCI subsystem.
7106 static int __init
ixgbe_init_module(void)
7109 pr_info("%s - version %s\n", ixgbe_driver_string
,
7110 ixgbe_driver_version
);
7111 pr_info("%s\n", ixgbe_copyright
);
7113 #ifdef CONFIG_IXGBE_DCA
7114 dca_register_notify(&dca_notifier
);
7117 ret
= pci_register_driver(&ixgbe_driver
);
7121 module_init(ixgbe_init_module
);
7124 * ixgbe_exit_module - Driver Exit Cleanup Routine
7126 * ixgbe_exit_module is called just before the driver is removed
7129 static void __exit
ixgbe_exit_module(void)
7131 #ifdef CONFIG_IXGBE_DCA
7132 dca_unregister_notify(&dca_notifier
);
7134 pci_unregister_driver(&ixgbe_driver
);
7137 #ifdef CONFIG_IXGBE_DCA
7138 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
7143 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
7144 __ixgbe_notify_dca
);
7146 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
7149 #endif /* CONFIG_IXGBE_DCA */
7152 * ixgbe_get_hw_dev return device
7153 * used by hardware layer to print debugging information
7155 struct net_device
*ixgbe_get_hw_dev(struct ixgbe_hw
*hw
)
7157 struct ixgbe_adapter
*adapter
= hw
->back
;
7158 return adapter
->netdev
;
7161 module_exit(ixgbe_exit_module
);