]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/net/ixgbe/ixgbe_main.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'stable/for-jens' of git://git.kernel.org/pub/scm/linux/kernel/git/konra...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if_vlan.h>
46 #include <linux/prefetch.h>
47 #include <scsi/fc/fc_fcoe.h>
48
49 #include "ixgbe.h"
50 #include "ixgbe_common.h"
51 #include "ixgbe_dcb_82599.h"
52 #include "ixgbe_sriov.h"
53
54 char ixgbe_driver_name[] = "ixgbe";
55 static const char ixgbe_driver_string[] =
56 "Intel(R) 10 Gigabit PCI Express Network Driver";
57 #define MAJ 3
58 #define MIN 4
59 #define BUILD 8
60 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
61 __stringify(BUILD) "-k"
62 const char ixgbe_driver_version[] = DRV_VERSION;
63 static const char ixgbe_copyright[] =
64 "Copyright (c) 1999-2011 Intel Corporation.";
65
66 static const struct ixgbe_info *ixgbe_info_tbl[] = {
67 [board_82598] = &ixgbe_82598_info,
68 [board_82599] = &ixgbe_82599_info,
69 [board_X540] = &ixgbe_X540_info,
70 };
71
72 /* ixgbe_pci_tbl - PCI Device ID Table
73 *
74 * Wildcard entries (PCI_ANY_ID) should come last
75 * Last entry must be all 0s
76 *
77 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
78 * Class, Class Mask, private data (not used) }
79 */
80 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
84 board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
92 board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
98 board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
100 board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
102 board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
104 board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
106 board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
108 board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
110 board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
112 board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
114 board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
116 board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
118 board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
120 board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
122 board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
124 board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
126 board_82599 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
128 board_X540 },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
130 board_82599 },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
132 board_82599 },
133
134 /* required last entry */
135 {0, }
136 };
137 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
138
139 #ifdef CONFIG_IXGBE_DCA
140 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
141 void *p);
142 static struct notifier_block dca_notifier = {
143 .notifier_call = ixgbe_notify_dca,
144 .next = NULL,
145 .priority = 0
146 };
147 #endif
148
149 #ifdef CONFIG_PCI_IOV
150 static unsigned int max_vfs;
151 module_param(max_vfs, uint, 0);
152 MODULE_PARM_DESC(max_vfs,
153 "Maximum number of virtual functions to allocate per physical function");
154 #endif /* CONFIG_PCI_IOV */
155
156 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
157 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
158 MODULE_LICENSE("GPL");
159 MODULE_VERSION(DRV_VERSION);
160
161 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
162
163 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
164 {
165 struct ixgbe_hw *hw = &adapter->hw;
166 u32 gcr;
167 u32 gpie;
168 u32 vmdctl;
169
170 #ifdef CONFIG_PCI_IOV
171 /* disable iov and allow time for transactions to clear */
172 pci_disable_sriov(adapter->pdev);
173 #endif
174
175 /* turn off device IOV mode */
176 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
177 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
178 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
179 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
180 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
181 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
182
183 /* set default pool back to 0 */
184 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
185 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
186 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
187
188 /* take a breather then clean up driver data */
189 msleep(100);
190
191 kfree(adapter->vfinfo);
192 adapter->vfinfo = NULL;
193
194 adapter->num_vfs = 0;
195 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
196 }
197
198 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
199 {
200 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
202 schedule_work(&adapter->service_task);
203 }
204
205 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
206 {
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
208
209 /* flush memory to make sure state is correct before next watchog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
212 }
213
214 struct ixgbe_reg_info {
215 u32 ofs;
216 char *name;
217 };
218
219 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
220
221 /* General Registers */
222 {IXGBE_CTRL, "CTRL"},
223 {IXGBE_STATUS, "STATUS"},
224 {IXGBE_CTRL_EXT, "CTRL_EXT"},
225
226 /* Interrupt Registers */
227 {IXGBE_EICR, "EICR"},
228
229 /* RX Registers */
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
238
239 /* TX Registers */
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
246
247 /* List Terminator */
248 {}
249 };
250
251
252 /*
253 * ixgbe_regdump - register printout routine
254 */
255 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
256 {
257 int i = 0, j = 0;
258 char rname[16];
259 u32 regs[64];
260
261 switch (reginfo->ofs) {
262 case IXGBE_SRRCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
265 break;
266 case IXGBE_DCA_RXCTRL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
269 break;
270 case IXGBE_RDLEN(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
273 break;
274 case IXGBE_RDH(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
277 break;
278 case IXGBE_RDT(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
281 break;
282 case IXGBE_RXDCTL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
285 break;
286 case IXGBE_RDBAL(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
289 break;
290 case IXGBE_RDBAH(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
293 break;
294 case IXGBE_TDBAL(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
297 break;
298 case IXGBE_TDBAH(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
301 break;
302 case IXGBE_TDLEN(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
305 break;
306 case IXGBE_TDH(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
309 break;
310 case IXGBE_TDT(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
313 break;
314 case IXGBE_TXDCTL(0):
315 for (i = 0; i < 64; i++)
316 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
317 break;
318 default:
319 pr_info("%-15s %08x\n", reginfo->name,
320 IXGBE_READ_REG(hw, reginfo->ofs));
321 return;
322 }
323
324 for (i = 0; i < 8; i++) {
325 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
326 pr_err("%-15s", rname);
327 for (j = 0; j < 8; j++)
328 pr_cont(" %08x", regs[i*8+j]);
329 pr_cont("\n");
330 }
331
332 }
333
334 /*
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
336 */
337 static void ixgbe_dump(struct ixgbe_adapter *adapter)
338 {
339 struct net_device *netdev = adapter->netdev;
340 struct ixgbe_hw *hw = &adapter->hw;
341 struct ixgbe_reg_info *reginfo;
342 int n = 0;
343 struct ixgbe_ring *tx_ring;
344 struct ixgbe_tx_buffer *tx_buffer_info;
345 union ixgbe_adv_tx_desc *tx_desc;
346 struct my_u0 { u64 a; u64 b; } *u0;
347 struct ixgbe_ring *rx_ring;
348 union ixgbe_adv_rx_desc *rx_desc;
349 struct ixgbe_rx_buffer *rx_buffer_info;
350 u32 staterr;
351 int i = 0;
352
353 if (!netif_msg_hw(adapter))
354 return;
355
356 /* Print netdevice Info */
357 if (netdev) {
358 dev_info(&adapter->pdev->dev, "Net device Info\n");
359 pr_info("Device Name state "
360 "trans_start last_rx\n");
361 pr_info("%-15s %016lX %016lX %016lX\n",
362 netdev->name,
363 netdev->state,
364 netdev->trans_start,
365 netdev->last_rx);
366 }
367
368 /* Print Registers */
369 dev_info(&adapter->pdev->dev, "Register Dump\n");
370 pr_info(" Register Name Value\n");
371 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
372 reginfo->name; reginfo++) {
373 ixgbe_regdump(hw, reginfo);
374 }
375
376 /* Print TX Ring Summary */
377 if (!netdev || !netif_running(netdev))
378 goto exit;
379
380 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
381 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
382 for (n = 0; n < adapter->num_tx_queues; n++) {
383 tx_ring = adapter->tx_ring[n];
384 tx_buffer_info =
385 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
386 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
387 n, tx_ring->next_to_use, tx_ring->next_to_clean,
388 (u64)tx_buffer_info->dma,
389 tx_buffer_info->length,
390 tx_buffer_info->next_to_watch,
391 (u64)tx_buffer_info->time_stamp);
392 }
393
394 /* Print TX Rings */
395 if (!netif_msg_tx_done(adapter))
396 goto rx_ring_summary;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
399
400 /* Transmit Descriptor Formats
401 *
402 * Advanced Transmit Descriptor
403 * +--------------------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +--------------------------------------------------------------+
406 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
407 * +--------------------------------------------------------------+
408 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
409 */
410
411 for (n = 0; n < adapter->num_tx_queues; n++) {
412 tx_ring = adapter->tx_ring[n];
413 pr_info("------------------------------------\n");
414 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
415 pr_info("------------------------------------\n");
416 pr_info("T [desc] [address 63:0 ] "
417 "[PlPOIdStDDt Ln] [bi->dma ] "
418 "leng ntw timestamp bi->skb\n");
419
420 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
421 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
422 tx_buffer_info = &tx_ring->tx_buffer_info[i];
423 u0 = (struct my_u0 *)tx_desc;
424 pr_info("T [0x%03X] %016llX %016llX %016llX"
425 " %04X %3X %016llX %p", i,
426 le64_to_cpu(u0->a),
427 le64_to_cpu(u0->b),
428 (u64)tx_buffer_info->dma,
429 tx_buffer_info->length,
430 tx_buffer_info->next_to_watch,
431 (u64)tx_buffer_info->time_stamp,
432 tx_buffer_info->skb);
433 if (i == tx_ring->next_to_use &&
434 i == tx_ring->next_to_clean)
435 pr_cont(" NTC/U\n");
436 else if (i == tx_ring->next_to_use)
437 pr_cont(" NTU\n");
438 else if (i == tx_ring->next_to_clean)
439 pr_cont(" NTC\n");
440 else
441 pr_cont("\n");
442
443 if (netif_msg_pktdata(adapter) &&
444 tx_buffer_info->dma != 0)
445 print_hex_dump(KERN_INFO, "",
446 DUMP_PREFIX_ADDRESS, 16, 1,
447 phys_to_virt(tx_buffer_info->dma),
448 tx_buffer_info->length, true);
449 }
450 }
451
452 /* Print RX Rings Summary */
453 rx_ring_summary:
454 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
455 pr_info("Queue [NTU] [NTC]\n");
456 for (n = 0; n < adapter->num_rx_queues; n++) {
457 rx_ring = adapter->rx_ring[n];
458 pr_info("%5d %5X %5X\n",
459 n, rx_ring->next_to_use, rx_ring->next_to_clean);
460 }
461
462 /* Print RX Rings */
463 if (!netif_msg_rx_status(adapter))
464 goto exit;
465
466 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
467
468 /* Advanced Receive Descriptor (Read) Format
469 * 63 1 0
470 * +-----------------------------------------------------+
471 * 0 | Packet Buffer Address [63:1] |A0/NSE|
472 * +----------------------------------------------+------+
473 * 8 | Header Buffer Address [63:1] | DD |
474 * +-----------------------------------------------------+
475 *
476 *
477 * Advanced Receive Descriptor (Write-Back) Format
478 *
479 * 63 48 47 32 31 30 21 20 16 15 4 3 0
480 * +------------------------------------------------------+
481 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
482 * | Checksum Ident | | | | Type | Type |
483 * +------------------------------------------------------+
484 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
485 * +------------------------------------------------------+
486 * 63 48 47 32 31 20 19 0
487 */
488 for (n = 0; n < adapter->num_rx_queues; n++) {
489 rx_ring = adapter->rx_ring[n];
490 pr_info("------------------------------------\n");
491 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
492 pr_info("------------------------------------\n");
493 pr_info("R [desc] [ PktBuf A0] "
494 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
495 "<-- Adv Rx Read format\n");
496 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
497 "[vl er S cks ln] ---------------- [bi->skb] "
498 "<-- Adv Rx Write-Back format\n");
499
500 for (i = 0; i < rx_ring->count; i++) {
501 rx_buffer_info = &rx_ring->rx_buffer_info[i];
502 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
503 u0 = (struct my_u0 *)rx_desc;
504 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
505 if (staterr & IXGBE_RXD_STAT_DD) {
506 /* Descriptor Done */
507 pr_info("RWB[0x%03X] %016llX "
508 "%016llX ---------------- %p", i,
509 le64_to_cpu(u0->a),
510 le64_to_cpu(u0->b),
511 rx_buffer_info->skb);
512 } else {
513 pr_info("R [0x%03X] %016llX "
514 "%016llX %016llX %p", i,
515 le64_to_cpu(u0->a),
516 le64_to_cpu(u0->b),
517 (u64)rx_buffer_info->dma,
518 rx_buffer_info->skb);
519
520 if (netif_msg_pktdata(adapter)) {
521 print_hex_dump(KERN_INFO, "",
522 DUMP_PREFIX_ADDRESS, 16, 1,
523 phys_to_virt(rx_buffer_info->dma),
524 rx_ring->rx_buf_len, true);
525
526 if (rx_ring->rx_buf_len
527 < IXGBE_RXBUFFER_2048)
528 print_hex_dump(KERN_INFO, "",
529 DUMP_PREFIX_ADDRESS, 16, 1,
530 phys_to_virt(
531 rx_buffer_info->page_dma +
532 rx_buffer_info->page_offset
533 ),
534 PAGE_SIZE/2, true);
535 }
536 }
537
538 if (i == rx_ring->next_to_use)
539 pr_cont(" NTU\n");
540 else if (i == rx_ring->next_to_clean)
541 pr_cont(" NTC\n");
542 else
543 pr_cont("\n");
544
545 }
546 }
547
548 exit:
549 return;
550 }
551
552 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
553 {
554 u32 ctrl_ext;
555
556 /* Let firmware take over control of h/w */
557 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
558 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
559 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
560 }
561
562 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
563 {
564 u32 ctrl_ext;
565
566 /* Let firmware know the driver has taken over */
567 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
569 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
570 }
571
572 /*
573 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
574 * @adapter: pointer to adapter struct
575 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
576 * @queue: queue to map the corresponding interrupt to
577 * @msix_vector: the vector to map to the corresponding queue
578 *
579 */
580 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
581 u8 queue, u8 msix_vector)
582 {
583 u32 ivar, index;
584 struct ixgbe_hw *hw = &adapter->hw;
585 switch (hw->mac.type) {
586 case ixgbe_mac_82598EB:
587 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
588 if (direction == -1)
589 direction = 0;
590 index = (((direction * 64) + queue) >> 2) & 0x1F;
591 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
592 ivar &= ~(0xFF << (8 * (queue & 0x3)));
593 ivar |= (msix_vector << (8 * (queue & 0x3)));
594 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
595 break;
596 case ixgbe_mac_82599EB:
597 case ixgbe_mac_X540:
598 if (direction == -1) {
599 /* other causes */
600 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
601 index = ((queue & 1) * 8);
602 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
603 ivar &= ~(0xFF << index);
604 ivar |= (msix_vector << index);
605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
606 break;
607 } else {
608 /* tx or rx causes */
609 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
610 index = ((16 * (queue & 1)) + (8 * direction));
611 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
612 ivar &= ~(0xFF << index);
613 ivar |= (msix_vector << index);
614 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
615 break;
616 }
617 default:
618 break;
619 }
620 }
621
622 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
623 u64 qmask)
624 {
625 u32 mask;
626
627 switch (adapter->hw.mac.type) {
628 case ixgbe_mac_82598EB:
629 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
631 break;
632 case ixgbe_mac_82599EB:
633 case ixgbe_mac_X540:
634 mask = (qmask & 0xFFFFFFFF);
635 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
636 mask = (qmask >> 32);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
638 break;
639 default:
640 break;
641 }
642 }
643
644 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
645 struct ixgbe_tx_buffer *tx_buffer_info)
646 {
647 if (tx_buffer_info->dma) {
648 if (tx_buffer_info->mapped_as_page)
649 dma_unmap_page(tx_ring->dev,
650 tx_buffer_info->dma,
651 tx_buffer_info->length,
652 DMA_TO_DEVICE);
653 else
654 dma_unmap_single(tx_ring->dev,
655 tx_buffer_info->dma,
656 tx_buffer_info->length,
657 DMA_TO_DEVICE);
658 tx_buffer_info->dma = 0;
659 }
660 if (tx_buffer_info->skb) {
661 dev_kfree_skb_any(tx_buffer_info->skb);
662 tx_buffer_info->skb = NULL;
663 }
664 tx_buffer_info->time_stamp = 0;
665 /* tx_buffer_info must be completely set up in the transmit path */
666 }
667
668 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
669 {
670 struct ixgbe_hw *hw = &adapter->hw;
671 struct ixgbe_hw_stats *hwstats = &adapter->stats;
672 u32 data = 0;
673 u32 xoff[8] = {0};
674 int i;
675
676 if ((hw->fc.current_mode == ixgbe_fc_full) ||
677 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
678 switch (hw->mac.type) {
679 case ixgbe_mac_82598EB:
680 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
681 break;
682 default:
683 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
684 }
685 hwstats->lxoffrxc += data;
686
687 /* refill credits (no tx hang) if we received xoff */
688 if (!data)
689 return;
690
691 for (i = 0; i < adapter->num_tx_queues; i++)
692 clear_bit(__IXGBE_HANG_CHECK_ARMED,
693 &adapter->tx_ring[i]->state);
694 return;
695 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
696 return;
697
698 /* update stats for each tc, only valid with PFC enabled */
699 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
700 switch (hw->mac.type) {
701 case ixgbe_mac_82598EB:
702 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
703 break;
704 default:
705 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
706 }
707 hwstats->pxoffrxc[i] += xoff[i];
708 }
709
710 /* disarm tx queues that have received xoff frames */
711 for (i = 0; i < adapter->num_tx_queues; i++) {
712 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
713 u8 tc = tx_ring->dcb_tc;
714
715 if (xoff[tc])
716 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
717 }
718 }
719
720 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
721 {
722 return ring->tx_stats.completed;
723 }
724
725 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
726 {
727 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
728 struct ixgbe_hw *hw = &adapter->hw;
729
730 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
731 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
732
733 if (head != tail)
734 return (head < tail) ?
735 tail - head : (tail + ring->count - head);
736
737 return 0;
738 }
739
740 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
741 {
742 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
743 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
744 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
745 bool ret = false;
746
747 clear_check_for_tx_hang(tx_ring);
748
749 /*
750 * Check for a hung queue, but be thorough. This verifies
751 * that a transmit has been completed since the previous
752 * check AND there is at least one packet pending. The
753 * ARMED bit is set to indicate a potential hang. The
754 * bit is cleared if a pause frame is received to remove
755 * false hang detection due to PFC or 802.3x frames. By
756 * requiring this to fail twice we avoid races with
757 * pfc clearing the ARMED bit and conditions where we
758 * run the check_tx_hang logic with a transmit completion
759 * pending but without time to complete it yet.
760 */
761 if ((tx_done_old == tx_done) && tx_pending) {
762 /* make sure it is true for two checks in a row */
763 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
764 &tx_ring->state);
765 } else {
766 /* update completed stats and continue */
767 tx_ring->tx_stats.tx_done_old = tx_done;
768 /* reset the countdown */
769 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
770 }
771
772 return ret;
773 }
774
775 /**
776 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
777 * @adapter: driver private struct
778 **/
779 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
780 {
781
782 /* Do the reset outside of interrupt context */
783 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
784 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
785 ixgbe_service_event_schedule(adapter);
786 }
787 }
788
789 /**
790 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
791 * @q_vector: structure containing interrupt and ring information
792 * @tx_ring: tx ring to clean
793 **/
794 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
795 struct ixgbe_ring *tx_ring)
796 {
797 struct ixgbe_adapter *adapter = q_vector->adapter;
798 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
799 struct ixgbe_tx_buffer *tx_buffer_info;
800 unsigned int total_bytes = 0, total_packets = 0;
801 u16 i, eop, count = 0;
802
803 i = tx_ring->next_to_clean;
804 eop = tx_ring->tx_buffer_info[i].next_to_watch;
805 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
806
807 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
808 (count < q_vector->tx.work_limit)) {
809 bool cleaned = false;
810 rmb(); /* read buffer_info after eop_desc */
811 for ( ; !cleaned; count++) {
812 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
813 tx_buffer_info = &tx_ring->tx_buffer_info[i];
814
815 tx_desc->wb.status = 0;
816 cleaned = (i == eop);
817
818 i++;
819 if (i == tx_ring->count)
820 i = 0;
821
822 if (cleaned && tx_buffer_info->skb) {
823 total_bytes += tx_buffer_info->bytecount;
824 total_packets += tx_buffer_info->gso_segs;
825 }
826
827 ixgbe_unmap_and_free_tx_resource(tx_ring,
828 tx_buffer_info);
829 }
830
831 tx_ring->tx_stats.completed++;
832 eop = tx_ring->tx_buffer_info[i].next_to_watch;
833 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
834 }
835
836 tx_ring->next_to_clean = i;
837 tx_ring->stats.bytes += total_bytes;
838 tx_ring->stats.packets += total_packets;
839 u64_stats_update_begin(&tx_ring->syncp);
840 q_vector->tx.total_bytes += total_bytes;
841 q_vector->tx.total_packets += total_packets;
842 u64_stats_update_end(&tx_ring->syncp);
843
844 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
845 /* schedule immediate reset if we believe we hung */
846 struct ixgbe_hw *hw = &adapter->hw;
847 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
848 e_err(drv, "Detected Tx Unit Hang\n"
849 " Tx Queue <%d>\n"
850 " TDH, TDT <%x>, <%x>\n"
851 " next_to_use <%x>\n"
852 " next_to_clean <%x>\n"
853 "tx_buffer_info[next_to_clean]\n"
854 " time_stamp <%lx>\n"
855 " jiffies <%lx>\n",
856 tx_ring->queue_index,
857 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
858 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
859 tx_ring->next_to_use, eop,
860 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
861
862 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
863
864 e_info(probe,
865 "tx hang %d detected on queue %d, resetting adapter\n",
866 adapter->tx_timeout_count + 1, tx_ring->queue_index);
867
868 /* schedule immediate reset if we believe we hung */
869 ixgbe_tx_timeout_reset(adapter);
870
871 /* the adapter is about to reset, no point in enabling stuff */
872 return true;
873 }
874
875 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
876 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
877 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
878 /* Make sure that anybody stopping the queue after this
879 * sees the new next_to_clean.
880 */
881 smp_mb();
882 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
883 !test_bit(__IXGBE_DOWN, &adapter->state)) {
884 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
885 ++tx_ring->tx_stats.restart_queue;
886 }
887 }
888
889 return count < q_vector->tx.work_limit;
890 }
891
892 #ifdef CONFIG_IXGBE_DCA
893 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
894 struct ixgbe_ring *rx_ring,
895 int cpu)
896 {
897 struct ixgbe_hw *hw = &adapter->hw;
898 u32 rxctrl;
899 u8 reg_idx = rx_ring->reg_idx;
900
901 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
902 switch (hw->mac.type) {
903 case ixgbe_mac_82598EB:
904 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
905 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
906 break;
907 case ixgbe_mac_82599EB:
908 case ixgbe_mac_X540:
909 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
910 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
911 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
912 break;
913 default:
914 break;
915 }
916 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
917 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
918 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
919 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
920 }
921
922 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
923 struct ixgbe_ring *tx_ring,
924 int cpu)
925 {
926 struct ixgbe_hw *hw = &adapter->hw;
927 u32 txctrl;
928 u8 reg_idx = tx_ring->reg_idx;
929
930 switch (hw->mac.type) {
931 case ixgbe_mac_82598EB:
932 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
933 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
934 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
935 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
936 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
937 break;
938 case ixgbe_mac_82599EB:
939 case ixgbe_mac_X540:
940 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
941 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
942 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
943 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
944 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
945 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
946 break;
947 default:
948 break;
949 }
950 }
951
952 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
953 {
954 struct ixgbe_adapter *adapter = q_vector->adapter;
955 int cpu = get_cpu();
956 long r_idx;
957 int i;
958
959 if (q_vector->cpu == cpu)
960 goto out_no_update;
961
962 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
963 for (i = 0; i < q_vector->tx.count; i++) {
964 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
965 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
966 r_idx + 1);
967 }
968
969 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
970 for (i = 0; i < q_vector->rx.count; i++) {
971 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
972 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
973 r_idx + 1);
974 }
975
976 q_vector->cpu = cpu;
977 out_no_update:
978 put_cpu();
979 }
980
981 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
982 {
983 int num_q_vectors;
984 int i;
985
986 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
987 return;
988
989 /* always use CB2 mode, difference is masked in the CB driver */
990 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
991
992 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
993 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
994 else
995 num_q_vectors = 1;
996
997 for (i = 0; i < num_q_vectors; i++) {
998 adapter->q_vector[i]->cpu = -1;
999 ixgbe_update_dca(adapter->q_vector[i]);
1000 }
1001 }
1002
1003 static int __ixgbe_notify_dca(struct device *dev, void *data)
1004 {
1005 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1006 unsigned long event = *(unsigned long *)data;
1007
1008 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1009 return 0;
1010
1011 switch (event) {
1012 case DCA_PROVIDER_ADD:
1013 /* if we're already enabled, don't do it again */
1014 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1015 break;
1016 if (dca_add_requester(dev) == 0) {
1017 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1018 ixgbe_setup_dca(adapter);
1019 break;
1020 }
1021 /* Fall Through since DCA is disabled. */
1022 case DCA_PROVIDER_REMOVE:
1023 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1024 dca_remove_requester(dev);
1025 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1026 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1027 }
1028 break;
1029 }
1030
1031 return 0;
1032 }
1033 #endif /* CONFIG_IXGBE_DCA */
1034
1035 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1036 struct sk_buff *skb)
1037 {
1038 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1039 }
1040
1041 /**
1042 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1043 * @adapter: address of board private structure
1044 * @rx_desc: advanced rx descriptor
1045 *
1046 * Returns : true if it is FCoE pkt
1047 */
1048 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1049 union ixgbe_adv_rx_desc *rx_desc)
1050 {
1051 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1052
1053 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1054 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1055 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1056 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1057 }
1058
1059 /**
1060 * ixgbe_receive_skb - Send a completed packet up the stack
1061 * @adapter: board private structure
1062 * @skb: packet to send up
1063 * @status: hardware indication of status of receive
1064 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1065 * @rx_desc: rx descriptor
1066 **/
1067 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1068 struct sk_buff *skb, u8 status,
1069 struct ixgbe_ring *ring,
1070 union ixgbe_adv_rx_desc *rx_desc)
1071 {
1072 struct ixgbe_adapter *adapter = q_vector->adapter;
1073 struct napi_struct *napi = &q_vector->napi;
1074 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1075 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1076
1077 if (is_vlan && (tag & VLAN_VID_MASK))
1078 __vlan_hwaccel_put_tag(skb, tag);
1079
1080 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1081 napi_gro_receive(napi, skb);
1082 else
1083 netif_rx(skb);
1084 }
1085
1086 /**
1087 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1088 * @adapter: address of board private structure
1089 * @status_err: hardware indication of status of receive
1090 * @skb: skb currently being received and modified
1091 * @status_err: status error value of last descriptor in packet
1092 **/
1093 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1094 union ixgbe_adv_rx_desc *rx_desc,
1095 struct sk_buff *skb,
1096 u32 status_err)
1097 {
1098 skb->ip_summed = CHECKSUM_NONE;
1099
1100 /* Rx csum disabled */
1101 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1102 return;
1103
1104 /* if IP and error */
1105 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1106 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1107 adapter->hw_csum_rx_error++;
1108 return;
1109 }
1110
1111 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1112 return;
1113
1114 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1115 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1116
1117 /*
1118 * 82599 errata, UDP frames with a 0 checksum can be marked as
1119 * checksum errors.
1120 */
1121 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1122 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1123 return;
1124
1125 adapter->hw_csum_rx_error++;
1126 return;
1127 }
1128
1129 /* It must be a TCP or UDP packet with a valid checksum */
1130 skb->ip_summed = CHECKSUM_UNNECESSARY;
1131 }
1132
1133 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1134 {
1135 /*
1136 * Force memory writes to complete before letting h/w
1137 * know there are new descriptors to fetch. (Only
1138 * applicable for weak-ordered memory model archs,
1139 * such as IA-64).
1140 */
1141 wmb();
1142 writel(val, rx_ring->tail);
1143 }
1144
1145 /**
1146 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1147 * @rx_ring: ring to place buffers on
1148 * @cleaned_count: number of buffers to replace
1149 **/
1150 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1151 {
1152 union ixgbe_adv_rx_desc *rx_desc;
1153 struct ixgbe_rx_buffer *bi;
1154 struct sk_buff *skb;
1155 u16 i = rx_ring->next_to_use;
1156
1157 /* do nothing if no valid netdev defined */
1158 if (!rx_ring->netdev)
1159 return;
1160
1161 while (cleaned_count--) {
1162 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1163 bi = &rx_ring->rx_buffer_info[i];
1164 skb = bi->skb;
1165
1166 if (!skb) {
1167 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1168 rx_ring->rx_buf_len);
1169 if (!skb) {
1170 rx_ring->rx_stats.alloc_rx_buff_failed++;
1171 goto no_buffers;
1172 }
1173 /* initialize queue mapping */
1174 skb_record_rx_queue(skb, rx_ring->queue_index);
1175 bi->skb = skb;
1176 }
1177
1178 if (!bi->dma) {
1179 bi->dma = dma_map_single(rx_ring->dev,
1180 skb->data,
1181 rx_ring->rx_buf_len,
1182 DMA_FROM_DEVICE);
1183 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1184 rx_ring->rx_stats.alloc_rx_buff_failed++;
1185 bi->dma = 0;
1186 goto no_buffers;
1187 }
1188 }
1189
1190 if (ring_is_ps_enabled(rx_ring)) {
1191 if (!bi->page) {
1192 bi->page = netdev_alloc_page(rx_ring->netdev);
1193 if (!bi->page) {
1194 rx_ring->rx_stats.alloc_rx_page_failed++;
1195 goto no_buffers;
1196 }
1197 }
1198
1199 if (!bi->page_dma) {
1200 /* use a half page if we're re-using */
1201 bi->page_offset ^= PAGE_SIZE / 2;
1202 bi->page_dma = dma_map_page(rx_ring->dev,
1203 bi->page,
1204 bi->page_offset,
1205 PAGE_SIZE / 2,
1206 DMA_FROM_DEVICE);
1207 if (dma_mapping_error(rx_ring->dev,
1208 bi->page_dma)) {
1209 rx_ring->rx_stats.alloc_rx_page_failed++;
1210 bi->page_dma = 0;
1211 goto no_buffers;
1212 }
1213 }
1214
1215 /* Refresh the desc even if buffer_addrs didn't change
1216 * because each write-back erases this info. */
1217 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1218 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1219 } else {
1220 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1221 rx_desc->read.hdr_addr = 0;
1222 }
1223
1224 i++;
1225 if (i == rx_ring->count)
1226 i = 0;
1227 }
1228
1229 no_buffers:
1230 if (rx_ring->next_to_use != i) {
1231 rx_ring->next_to_use = i;
1232 ixgbe_release_rx_desc(rx_ring, i);
1233 }
1234 }
1235
1236 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1237 {
1238 /* HW will not DMA in data larger than the given buffer, even if it
1239 * parses the (NFS, of course) header to be larger. In that case, it
1240 * fills the header buffer and spills the rest into the page.
1241 */
1242 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1243 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1244 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1245 if (hlen > IXGBE_RX_HDR_SIZE)
1246 hlen = IXGBE_RX_HDR_SIZE;
1247 return hlen;
1248 }
1249
1250 /**
1251 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1252 * @skb: pointer to the last skb in the rsc queue
1253 *
1254 * This function changes a queue full of hw rsc buffers into a completed
1255 * packet. It uses the ->prev pointers to find the first packet and then
1256 * turns it into the frag list owner.
1257 **/
1258 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1259 {
1260 unsigned int frag_list_size = 0;
1261 unsigned int skb_cnt = 1;
1262
1263 while (skb->prev) {
1264 struct sk_buff *prev = skb->prev;
1265 frag_list_size += skb->len;
1266 skb->prev = NULL;
1267 skb = prev;
1268 skb_cnt++;
1269 }
1270
1271 skb_shinfo(skb)->frag_list = skb->next;
1272 skb->next = NULL;
1273 skb->len += frag_list_size;
1274 skb->data_len += frag_list_size;
1275 skb->truesize += frag_list_size;
1276 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1277
1278 return skb;
1279 }
1280
1281 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1282 {
1283 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1284 IXGBE_RXDADV_RSCCNT_MASK);
1285 }
1286
1287 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1288 struct ixgbe_ring *rx_ring,
1289 int *work_done, int work_to_do)
1290 {
1291 struct ixgbe_adapter *adapter = q_vector->adapter;
1292 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1293 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1294 struct sk_buff *skb;
1295 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1296 const int current_node = numa_node_id();
1297 #ifdef IXGBE_FCOE
1298 int ddp_bytes = 0;
1299 #endif /* IXGBE_FCOE */
1300 u32 staterr;
1301 u16 i;
1302 u16 cleaned_count = 0;
1303 bool pkt_is_rsc = false;
1304
1305 i = rx_ring->next_to_clean;
1306 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1307 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1308
1309 while (staterr & IXGBE_RXD_STAT_DD) {
1310 u32 upper_len = 0;
1311
1312 rmb(); /* read descriptor and rx_buffer_info after status DD */
1313
1314 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1315
1316 skb = rx_buffer_info->skb;
1317 rx_buffer_info->skb = NULL;
1318 prefetch(skb->data);
1319
1320 if (ring_is_rsc_enabled(rx_ring))
1321 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1322
1323 /* if this is a skb from previous receive DMA will be 0 */
1324 if (rx_buffer_info->dma) {
1325 u16 hlen;
1326 if (pkt_is_rsc &&
1327 !(staterr & IXGBE_RXD_STAT_EOP) &&
1328 !skb->prev) {
1329 /*
1330 * When HWRSC is enabled, delay unmapping
1331 * of the first packet. It carries the
1332 * header information, HW may still
1333 * access the header after the writeback.
1334 * Only unmap it when EOP is reached
1335 */
1336 IXGBE_RSC_CB(skb)->delay_unmap = true;
1337 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1338 } else {
1339 dma_unmap_single(rx_ring->dev,
1340 rx_buffer_info->dma,
1341 rx_ring->rx_buf_len,
1342 DMA_FROM_DEVICE);
1343 }
1344 rx_buffer_info->dma = 0;
1345
1346 if (ring_is_ps_enabled(rx_ring)) {
1347 hlen = ixgbe_get_hlen(rx_desc);
1348 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1349 } else {
1350 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1351 }
1352
1353 skb_put(skb, hlen);
1354 } else {
1355 /* assume packet split since header is unmapped */
1356 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1357 }
1358
1359 if (upper_len) {
1360 dma_unmap_page(rx_ring->dev,
1361 rx_buffer_info->page_dma,
1362 PAGE_SIZE / 2,
1363 DMA_FROM_DEVICE);
1364 rx_buffer_info->page_dma = 0;
1365 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1366 rx_buffer_info->page,
1367 rx_buffer_info->page_offset,
1368 upper_len);
1369
1370 if ((page_count(rx_buffer_info->page) == 1) &&
1371 (page_to_nid(rx_buffer_info->page) == current_node))
1372 get_page(rx_buffer_info->page);
1373 else
1374 rx_buffer_info->page = NULL;
1375
1376 skb->len += upper_len;
1377 skb->data_len += upper_len;
1378 skb->truesize += upper_len;
1379 }
1380
1381 i++;
1382 if (i == rx_ring->count)
1383 i = 0;
1384
1385 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1386 prefetch(next_rxd);
1387 cleaned_count++;
1388
1389 if (pkt_is_rsc) {
1390 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1391 IXGBE_RXDADV_NEXTP_SHIFT;
1392 next_buffer = &rx_ring->rx_buffer_info[nextp];
1393 } else {
1394 next_buffer = &rx_ring->rx_buffer_info[i];
1395 }
1396
1397 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1398 if (ring_is_ps_enabled(rx_ring)) {
1399 rx_buffer_info->skb = next_buffer->skb;
1400 rx_buffer_info->dma = next_buffer->dma;
1401 next_buffer->skb = skb;
1402 next_buffer->dma = 0;
1403 } else {
1404 skb->next = next_buffer->skb;
1405 skb->next->prev = skb;
1406 }
1407 rx_ring->rx_stats.non_eop_descs++;
1408 goto next_desc;
1409 }
1410
1411 if (skb->prev) {
1412 skb = ixgbe_transform_rsc_queue(skb);
1413 /* if we got here without RSC the packet is invalid */
1414 if (!pkt_is_rsc) {
1415 __pskb_trim(skb, 0);
1416 rx_buffer_info->skb = skb;
1417 goto next_desc;
1418 }
1419 }
1420
1421 if (ring_is_rsc_enabled(rx_ring)) {
1422 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1423 dma_unmap_single(rx_ring->dev,
1424 IXGBE_RSC_CB(skb)->dma,
1425 rx_ring->rx_buf_len,
1426 DMA_FROM_DEVICE);
1427 IXGBE_RSC_CB(skb)->dma = 0;
1428 IXGBE_RSC_CB(skb)->delay_unmap = false;
1429 }
1430 }
1431 if (pkt_is_rsc) {
1432 if (ring_is_ps_enabled(rx_ring))
1433 rx_ring->rx_stats.rsc_count +=
1434 skb_shinfo(skb)->nr_frags;
1435 else
1436 rx_ring->rx_stats.rsc_count +=
1437 IXGBE_RSC_CB(skb)->skb_cnt;
1438 rx_ring->rx_stats.rsc_flush++;
1439 }
1440
1441 /* ERR_MASK will only have valid bits if EOP set */
1442 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1443 dev_kfree_skb_any(skb);
1444 goto next_desc;
1445 }
1446
1447 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1448 if (adapter->netdev->features & NETIF_F_RXHASH)
1449 ixgbe_rx_hash(rx_desc, skb);
1450
1451 /* probably a little skewed due to removing CRC */
1452 total_rx_bytes += skb->len;
1453 total_rx_packets++;
1454
1455 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1456 #ifdef IXGBE_FCOE
1457 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1458 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1459 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1460 staterr);
1461 if (!ddp_bytes)
1462 goto next_desc;
1463 }
1464 #endif /* IXGBE_FCOE */
1465 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1466
1467 next_desc:
1468 rx_desc->wb.upper.status_error = 0;
1469
1470 (*work_done)++;
1471 if (*work_done >= work_to_do)
1472 break;
1473
1474 /* return some buffers to hardware, one at a time is too slow */
1475 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1476 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1477 cleaned_count = 0;
1478 }
1479
1480 /* use prefetched values */
1481 rx_desc = next_rxd;
1482 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1483 }
1484
1485 rx_ring->next_to_clean = i;
1486 cleaned_count = ixgbe_desc_unused(rx_ring);
1487
1488 if (cleaned_count)
1489 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1490
1491 #ifdef IXGBE_FCOE
1492 /* include DDPed FCoE data */
1493 if (ddp_bytes > 0) {
1494 unsigned int mss;
1495
1496 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1497 sizeof(struct fc_frame_header) -
1498 sizeof(struct fcoe_crc_eof);
1499 if (mss > 512)
1500 mss &= ~511;
1501 total_rx_bytes += ddp_bytes;
1502 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1503 }
1504 #endif /* IXGBE_FCOE */
1505
1506 u64_stats_update_begin(&rx_ring->syncp);
1507 rx_ring->stats.packets += total_rx_packets;
1508 rx_ring->stats.bytes += total_rx_bytes;
1509 u64_stats_update_end(&rx_ring->syncp);
1510 q_vector->rx.total_packets += total_rx_packets;
1511 q_vector->rx.total_bytes += total_rx_bytes;
1512 }
1513
1514 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1515 /**
1516 * ixgbe_configure_msix - Configure MSI-X hardware
1517 * @adapter: board private structure
1518 *
1519 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1520 * interrupts.
1521 **/
1522 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1523 {
1524 struct ixgbe_q_vector *q_vector;
1525 int i, q_vectors, v_idx, r_idx;
1526 u32 mask;
1527
1528 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1529
1530 /*
1531 * Populate the IVAR table and set the ITR values to the
1532 * corresponding register.
1533 */
1534 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1535 q_vector = adapter->q_vector[v_idx];
1536 /* XXX for_each_set_bit(...) */
1537 r_idx = find_first_bit(q_vector->rx.idx,
1538 adapter->num_rx_queues);
1539
1540 for (i = 0; i < q_vector->rx.count; i++) {
1541 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1542 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1543 r_idx = find_next_bit(q_vector->rx.idx,
1544 adapter->num_rx_queues,
1545 r_idx + 1);
1546 }
1547 r_idx = find_first_bit(q_vector->tx.idx,
1548 adapter->num_tx_queues);
1549
1550 for (i = 0; i < q_vector->tx.count; i++) {
1551 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1552 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1553 r_idx = find_next_bit(q_vector->tx.idx,
1554 adapter->num_tx_queues,
1555 r_idx + 1);
1556 }
1557
1558 if (q_vector->tx.count && !q_vector->rx.count)
1559 /* tx only */
1560 q_vector->eitr = adapter->tx_eitr_param;
1561 else if (q_vector->rx.count)
1562 /* rx or mixed */
1563 q_vector->eitr = adapter->rx_eitr_param;
1564
1565 ixgbe_write_eitr(q_vector);
1566 /* If ATR is enabled, set interrupt affinity */
1567 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
1568 /*
1569 * Allocate the affinity_hint cpumask, assign the mask
1570 * for this vector, and set our affinity_hint for
1571 * this irq.
1572 */
1573 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1574 GFP_KERNEL))
1575 return;
1576 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1577 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1578 q_vector->affinity_mask);
1579 }
1580 }
1581
1582 switch (adapter->hw.mac.type) {
1583 case ixgbe_mac_82598EB:
1584 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1585 v_idx);
1586 break;
1587 case ixgbe_mac_82599EB:
1588 case ixgbe_mac_X540:
1589 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1590 break;
1591
1592 default:
1593 break;
1594 }
1595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1596
1597 /* set up to autoclear timer, and the vectors */
1598 mask = IXGBE_EIMS_ENABLE_MASK;
1599 if (adapter->num_vfs)
1600 mask &= ~(IXGBE_EIMS_OTHER |
1601 IXGBE_EIMS_MAILBOX |
1602 IXGBE_EIMS_LSC);
1603 else
1604 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1606 }
1607
1608 enum latency_range {
1609 lowest_latency = 0,
1610 low_latency = 1,
1611 bulk_latency = 2,
1612 latency_invalid = 255
1613 };
1614
1615 /**
1616 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1617 * @q_vector: structure containing interrupt and ring information
1618 * @ring_container: structure containing ring performance data
1619 *
1620 * Stores a new ITR value based on packets and byte
1621 * counts during the last interrupt. The advantage of per interrupt
1622 * computation is faster updates and more accurate ITR for the current
1623 * traffic pattern. Constants in this function were computed
1624 * based on theoretical maximum wire speed and thresholds were set based
1625 * on testing data as well as attempting to minimize response time
1626 * while increasing bulk throughput.
1627 * this functionality is controlled by the InterruptThrottleRate module
1628 * parameter (see ixgbe_param.c)
1629 **/
1630 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1631 struct ixgbe_ring_container *ring_container)
1632 {
1633 u64 bytes_perint;
1634 struct ixgbe_adapter *adapter = q_vector->adapter;
1635 int bytes = ring_container->total_bytes;
1636 int packets = ring_container->total_packets;
1637 u32 timepassed_us;
1638 u8 itr_setting = ring_container->itr;
1639
1640 if (packets == 0)
1641 return;
1642
1643 /* simple throttlerate management
1644 * 0-20MB/s lowest (100000 ints/s)
1645 * 20-100MB/s low (20000 ints/s)
1646 * 100-1249MB/s bulk (8000 ints/s)
1647 */
1648 /* what was last interrupt timeslice? */
1649 timepassed_us = 1000000/q_vector->eitr;
1650 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1651
1652 switch (itr_setting) {
1653 case lowest_latency:
1654 if (bytes_perint > adapter->eitr_low)
1655 itr_setting = low_latency;
1656 break;
1657 case low_latency:
1658 if (bytes_perint > adapter->eitr_high)
1659 itr_setting = bulk_latency;
1660 else if (bytes_perint <= adapter->eitr_low)
1661 itr_setting = lowest_latency;
1662 break;
1663 case bulk_latency:
1664 if (bytes_perint <= adapter->eitr_high)
1665 itr_setting = low_latency;
1666 break;
1667 }
1668
1669 /* clear work counters since we have the values we need */
1670 ring_container->total_bytes = 0;
1671 ring_container->total_packets = 0;
1672
1673 /* write updated itr to ring container */
1674 ring_container->itr = itr_setting;
1675 }
1676
1677 /**
1678 * ixgbe_write_eitr - write EITR register in hardware specific way
1679 * @q_vector: structure containing interrupt and ring information
1680 *
1681 * This function is made to be called by ethtool and by the driver
1682 * when it needs to update EITR registers at runtime. Hardware
1683 * specific quirks/differences are taken care of here.
1684 */
1685 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1686 {
1687 struct ixgbe_adapter *adapter = q_vector->adapter;
1688 struct ixgbe_hw *hw = &adapter->hw;
1689 int v_idx = q_vector->v_idx;
1690 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1691
1692 switch (adapter->hw.mac.type) {
1693 case ixgbe_mac_82598EB:
1694 /* must write high and low 16 bits to reset counter */
1695 itr_reg |= (itr_reg << 16);
1696 break;
1697 case ixgbe_mac_82599EB:
1698 case ixgbe_mac_X540:
1699 /*
1700 * 82599 and X540 can support a value of zero, so allow it for
1701 * max interrupt rate, but there is an errata where it can
1702 * not be zero with RSC
1703 */
1704 if (itr_reg == 8 &&
1705 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1706 itr_reg = 0;
1707
1708 /*
1709 * set the WDIS bit to not clear the timer bits and cause an
1710 * immediate assertion of the interrupt
1711 */
1712 itr_reg |= IXGBE_EITR_CNT_WDIS;
1713 break;
1714 default:
1715 break;
1716 }
1717 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1718 }
1719
1720 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1721 {
1722 u32 new_itr = q_vector->eitr;
1723 u8 current_itr;
1724
1725 ixgbe_update_itr(q_vector, &q_vector->tx);
1726 ixgbe_update_itr(q_vector, &q_vector->rx);
1727
1728 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1729
1730 switch (current_itr) {
1731 /* counts and packets in update_itr are dependent on these numbers */
1732 case lowest_latency:
1733 new_itr = 100000;
1734 break;
1735 case low_latency:
1736 new_itr = 20000; /* aka hwitr = ~200 */
1737 break;
1738 case bulk_latency:
1739 new_itr = 8000;
1740 break;
1741 default:
1742 break;
1743 }
1744
1745 if (new_itr != q_vector->eitr) {
1746 /* do an exponential smoothing */
1747 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1748
1749 /* save the algorithm value here */
1750 q_vector->eitr = new_itr;
1751
1752 ixgbe_write_eitr(q_vector);
1753 }
1754 }
1755
1756 /**
1757 * ixgbe_check_overtemp_subtask - check for over tempurature
1758 * @adapter: pointer to adapter
1759 **/
1760 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1761 {
1762 struct ixgbe_hw *hw = &adapter->hw;
1763 u32 eicr = adapter->interrupt_event;
1764
1765 if (test_bit(__IXGBE_DOWN, &adapter->state))
1766 return;
1767
1768 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1769 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1770 return;
1771
1772 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1773
1774 switch (hw->device_id) {
1775 case IXGBE_DEV_ID_82599_T3_LOM:
1776 /*
1777 * Since the warning interrupt is for both ports
1778 * we don't have to check if:
1779 * - This interrupt wasn't for our port.
1780 * - We may have missed the interrupt so always have to
1781 * check if we got a LSC
1782 */
1783 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1784 !(eicr & IXGBE_EICR_LSC))
1785 return;
1786
1787 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1788 u32 autoneg;
1789 bool link_up = false;
1790
1791 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1792
1793 if (link_up)
1794 return;
1795 }
1796
1797 /* Check if this is not due to overtemp */
1798 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1799 return;
1800
1801 break;
1802 default:
1803 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1804 return;
1805 break;
1806 }
1807 e_crit(drv,
1808 "Network adapter has been stopped because it has over heated. "
1809 "Restart the computer. If the problem persists, "
1810 "power off the system and replace the adapter\n");
1811
1812 adapter->interrupt_event = 0;
1813 }
1814
1815 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1816 {
1817 struct ixgbe_hw *hw = &adapter->hw;
1818
1819 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1820 (eicr & IXGBE_EICR_GPI_SDP1)) {
1821 e_crit(probe, "Fan has stopped, replace the adapter\n");
1822 /* write to clear the interrupt */
1823 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1824 }
1825 }
1826
1827 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1828 {
1829 struct ixgbe_hw *hw = &adapter->hw;
1830
1831 if (eicr & IXGBE_EICR_GPI_SDP2) {
1832 /* Clear the interrupt */
1833 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1834 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1835 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1836 ixgbe_service_event_schedule(adapter);
1837 }
1838 }
1839
1840 if (eicr & IXGBE_EICR_GPI_SDP1) {
1841 /* Clear the interrupt */
1842 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1843 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1844 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1845 ixgbe_service_event_schedule(adapter);
1846 }
1847 }
1848 }
1849
1850 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1851 {
1852 struct ixgbe_hw *hw = &adapter->hw;
1853
1854 adapter->lsc_int++;
1855 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1856 adapter->link_check_timeout = jiffies;
1857 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1858 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1859 IXGBE_WRITE_FLUSH(hw);
1860 ixgbe_service_event_schedule(adapter);
1861 }
1862 }
1863
1864 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1865 {
1866 struct ixgbe_adapter *adapter = data;
1867 struct ixgbe_hw *hw = &adapter->hw;
1868 u32 eicr;
1869
1870 /*
1871 * Workaround for Silicon errata. Use clear-by-write instead
1872 * of clear-by-read. Reading with EICS will return the
1873 * interrupt causes without clearing, which later be done
1874 * with the write to EICR.
1875 */
1876 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1877 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1878
1879 if (eicr & IXGBE_EICR_LSC)
1880 ixgbe_check_lsc(adapter);
1881
1882 if (eicr & IXGBE_EICR_MAILBOX)
1883 ixgbe_msg_task(adapter);
1884
1885 switch (hw->mac.type) {
1886 case ixgbe_mac_82599EB:
1887 case ixgbe_mac_X540:
1888 /* Handle Flow Director Full threshold interrupt */
1889 if (eicr & IXGBE_EICR_FLOW_DIR) {
1890 int reinit_count = 0;
1891 int i;
1892 for (i = 0; i < adapter->num_tx_queues; i++) {
1893 struct ixgbe_ring *ring = adapter->tx_ring[i];
1894 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1895 &ring->state))
1896 reinit_count++;
1897 }
1898 if (reinit_count) {
1899 /* no more flow director interrupts until after init */
1900 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1901 eicr &= ~IXGBE_EICR_FLOW_DIR;
1902 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1903 ixgbe_service_event_schedule(adapter);
1904 }
1905 }
1906 ixgbe_check_sfp_event(adapter, eicr);
1907 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1908 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1909 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1910 adapter->interrupt_event = eicr;
1911 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1912 ixgbe_service_event_schedule(adapter);
1913 }
1914 }
1915 break;
1916 default:
1917 break;
1918 }
1919
1920 ixgbe_check_fan_failure(adapter, eicr);
1921
1922 /* re-enable the original interrupt state, no lsc, no queues */
1923 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1924 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1925 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1926
1927 return IRQ_HANDLED;
1928 }
1929
1930 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1931 u64 qmask)
1932 {
1933 u32 mask;
1934 struct ixgbe_hw *hw = &adapter->hw;
1935
1936 switch (hw->mac.type) {
1937 case ixgbe_mac_82598EB:
1938 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1939 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1940 break;
1941 case ixgbe_mac_82599EB:
1942 case ixgbe_mac_X540:
1943 mask = (qmask & 0xFFFFFFFF);
1944 if (mask)
1945 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1946 mask = (qmask >> 32);
1947 if (mask)
1948 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1949 break;
1950 default:
1951 break;
1952 }
1953 /* skip the flush */
1954 }
1955
1956 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1957 u64 qmask)
1958 {
1959 u32 mask;
1960 struct ixgbe_hw *hw = &adapter->hw;
1961
1962 switch (hw->mac.type) {
1963 case ixgbe_mac_82598EB:
1964 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1965 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1966 break;
1967 case ixgbe_mac_82599EB:
1968 case ixgbe_mac_X540:
1969 mask = (qmask & 0xFFFFFFFF);
1970 if (mask)
1971 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1972 mask = (qmask >> 32);
1973 if (mask)
1974 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1975 break;
1976 default:
1977 break;
1978 }
1979 /* skip the flush */
1980 }
1981
1982 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1983 {
1984 struct ixgbe_q_vector *q_vector = data;
1985 struct ixgbe_adapter *adapter = q_vector->adapter;
1986 struct ixgbe_ring *tx_ring;
1987 int i, r_idx;
1988
1989 if (!q_vector->tx.count)
1990 return IRQ_HANDLED;
1991
1992 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
1993 for (i = 0; i < q_vector->tx.count; i++) {
1994 tx_ring = adapter->tx_ring[r_idx];
1995 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
1996 r_idx + 1);
1997 }
1998
1999 /* EIAM disabled interrupts (on this vector) for us */
2000 napi_schedule(&q_vector->napi);
2001
2002 return IRQ_HANDLED;
2003 }
2004
2005 /**
2006 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2007 * @irq: unused
2008 * @data: pointer to our q_vector struct for this interrupt vector
2009 **/
2010 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2011 {
2012 struct ixgbe_q_vector *q_vector = data;
2013 struct ixgbe_adapter *adapter = q_vector->adapter;
2014 struct ixgbe_ring *rx_ring;
2015 int r_idx;
2016 int i;
2017
2018 #ifdef CONFIG_IXGBE_DCA
2019 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2020 ixgbe_update_dca(q_vector);
2021 #endif
2022
2023 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2024 for (i = 0; i < q_vector->rx.count; i++) {
2025 rx_ring = adapter->rx_ring[r_idx];
2026 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2027 r_idx + 1);
2028 }
2029
2030 if (!q_vector->rx.count)
2031 return IRQ_HANDLED;
2032
2033 /* EIAM disabled interrupts (on this vector) for us */
2034 napi_schedule(&q_vector->napi);
2035
2036 return IRQ_HANDLED;
2037 }
2038
2039 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2040 {
2041 struct ixgbe_q_vector *q_vector = data;
2042 struct ixgbe_adapter *adapter = q_vector->adapter;
2043 struct ixgbe_ring *ring;
2044 int r_idx;
2045 int i;
2046
2047 if (!q_vector->tx.count && !q_vector->rx.count)
2048 return IRQ_HANDLED;
2049
2050 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2051 for (i = 0; i < q_vector->tx.count; i++) {
2052 ring = adapter->tx_ring[r_idx];
2053 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2054 r_idx + 1);
2055 }
2056
2057 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2058 for (i = 0; i < q_vector->rx.count; i++) {
2059 ring = adapter->rx_ring[r_idx];
2060 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2061 r_idx + 1);
2062 }
2063
2064 /* EIAM disabled interrupts (on this vector) for us */
2065 napi_schedule(&q_vector->napi);
2066
2067 return IRQ_HANDLED;
2068 }
2069
2070 /**
2071 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2072 * @napi: napi struct with our devices info in it
2073 * @budget: amount of work driver is allowed to do this pass, in packets
2074 *
2075 * This function is optimized for cleaning one queue only on a single
2076 * q_vector!!!
2077 **/
2078 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2079 {
2080 struct ixgbe_q_vector *q_vector =
2081 container_of(napi, struct ixgbe_q_vector, napi);
2082 struct ixgbe_adapter *adapter = q_vector->adapter;
2083 struct ixgbe_ring *rx_ring = NULL;
2084 int work_done = 0;
2085 long r_idx;
2086
2087 #ifdef CONFIG_IXGBE_DCA
2088 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2089 ixgbe_update_dca(q_vector);
2090 #endif
2091
2092 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2093 rx_ring = adapter->rx_ring[r_idx];
2094
2095 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2096
2097 /* If all Rx work done, exit the polling mode */
2098 if (work_done < budget) {
2099 napi_complete(napi);
2100 if (adapter->rx_itr_setting & 1)
2101 ixgbe_set_itr(q_vector);
2102 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2103 ixgbe_irq_enable_queues(adapter,
2104 ((u64)1 << q_vector->v_idx));
2105 }
2106
2107 return work_done;
2108 }
2109
2110 /**
2111 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2112 * @napi: napi struct with our devices info in it
2113 * @budget: amount of work driver is allowed to do this pass, in packets
2114 *
2115 * This function will clean more than one rx queue associated with a
2116 * q_vector.
2117 **/
2118 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2119 {
2120 struct ixgbe_q_vector *q_vector =
2121 container_of(napi, struct ixgbe_q_vector, napi);
2122 struct ixgbe_adapter *adapter = q_vector->adapter;
2123 struct ixgbe_ring *ring = NULL;
2124 int work_done = 0, i;
2125 long r_idx;
2126 bool tx_clean_complete = true;
2127
2128 #ifdef CONFIG_IXGBE_DCA
2129 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2130 ixgbe_update_dca(q_vector);
2131 #endif
2132
2133 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2134 for (i = 0; i < q_vector->tx.count; i++) {
2135 ring = adapter->tx_ring[r_idx];
2136 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2137 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2138 r_idx + 1);
2139 }
2140
2141 /* attempt to distribute budget to each queue fairly, but don't allow
2142 * the budget to go below 1 because we'll exit polling */
2143 budget /= (q_vector->rx.count ?: 1);
2144 budget = max(budget, 1);
2145 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2146 for (i = 0; i < q_vector->rx.count; i++) {
2147 ring = adapter->rx_ring[r_idx];
2148 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2149 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2150 r_idx + 1);
2151 }
2152
2153 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2154 ring = adapter->rx_ring[r_idx];
2155 /* If all Rx work done, exit the polling mode */
2156 if (work_done < budget) {
2157 napi_complete(napi);
2158 if (adapter->rx_itr_setting & 1)
2159 ixgbe_set_itr(q_vector);
2160 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2161 ixgbe_irq_enable_queues(adapter,
2162 ((u64)1 << q_vector->v_idx));
2163 return 0;
2164 }
2165
2166 return work_done;
2167 }
2168
2169 /**
2170 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2171 * @napi: napi struct with our devices info in it
2172 * @budget: amount of work driver is allowed to do this pass, in packets
2173 *
2174 * This function is optimized for cleaning one queue only on a single
2175 * q_vector!!!
2176 **/
2177 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2178 {
2179 struct ixgbe_q_vector *q_vector =
2180 container_of(napi, struct ixgbe_q_vector, napi);
2181 struct ixgbe_adapter *adapter = q_vector->adapter;
2182 struct ixgbe_ring *tx_ring = NULL;
2183 int work_done = 0;
2184 long r_idx;
2185
2186 #ifdef CONFIG_IXGBE_DCA
2187 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2188 ixgbe_update_dca(q_vector);
2189 #endif
2190
2191 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2192 tx_ring = adapter->tx_ring[r_idx];
2193
2194 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2195 work_done = budget;
2196
2197 /* If all Tx work done, exit the polling mode */
2198 if (work_done < budget) {
2199 napi_complete(napi);
2200 if (adapter->tx_itr_setting & 1)
2201 ixgbe_set_itr(q_vector);
2202 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2203 ixgbe_irq_enable_queues(adapter,
2204 ((u64)1 << q_vector->v_idx));
2205 }
2206
2207 return work_done;
2208 }
2209
2210 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2211 int r_idx)
2212 {
2213 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2214 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2215
2216 set_bit(r_idx, q_vector->rx.idx);
2217 q_vector->rx.count++;
2218 rx_ring->q_vector = q_vector;
2219 }
2220
2221 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2222 int t_idx)
2223 {
2224 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2225 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2226
2227 set_bit(t_idx, q_vector->tx.idx);
2228 q_vector->tx.count++;
2229 tx_ring->q_vector = q_vector;
2230 q_vector->tx.work_limit = a->tx_work_limit;
2231 }
2232
2233 /**
2234 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2235 * @adapter: board private structure to initialize
2236 *
2237 * This function maps descriptor rings to the queue-specific vectors
2238 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2239 * one vector per ring/queue, but on a constrained vector budget, we
2240 * group the rings as "efficiently" as possible. You would add new
2241 * mapping configurations in here.
2242 **/
2243 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2244 {
2245 int q_vectors;
2246 int v_start = 0;
2247 int rxr_idx = 0, txr_idx = 0;
2248 int rxr_remaining = adapter->num_rx_queues;
2249 int txr_remaining = adapter->num_tx_queues;
2250 int i, j;
2251 int rqpv, tqpv;
2252 int err = 0;
2253
2254 /* No mapping required if MSI-X is disabled. */
2255 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2256 goto out;
2257
2258 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2259
2260 /*
2261 * The ideal configuration...
2262 * We have enough vectors to map one per queue.
2263 */
2264 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2265 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2266 map_vector_to_rxq(adapter, v_start, rxr_idx);
2267
2268 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2269 map_vector_to_txq(adapter, v_start, txr_idx);
2270
2271 goto out;
2272 }
2273
2274 /*
2275 * If we don't have enough vectors for a 1-to-1
2276 * mapping, we'll have to group them so there are
2277 * multiple queues per vector.
2278 */
2279 /* Re-adjusting *qpv takes care of the remainder. */
2280 for (i = v_start; i < q_vectors; i++) {
2281 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2282 for (j = 0; j < rqpv; j++) {
2283 map_vector_to_rxq(adapter, i, rxr_idx);
2284 rxr_idx++;
2285 rxr_remaining--;
2286 }
2287 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2288 for (j = 0; j < tqpv; j++) {
2289 map_vector_to_txq(adapter, i, txr_idx);
2290 txr_idx++;
2291 txr_remaining--;
2292 }
2293 }
2294 out:
2295 return err;
2296 }
2297
2298 /**
2299 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2300 * @adapter: board private structure
2301 *
2302 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2303 * interrupts from the kernel.
2304 **/
2305 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2306 {
2307 struct net_device *netdev = adapter->netdev;
2308 irqreturn_t (*handler)(int, void *);
2309 int i, vector, q_vectors, err;
2310 int ri = 0, ti = 0;
2311
2312 /* Decrement for Other and TCP Timer vectors */
2313 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2314
2315 err = ixgbe_map_rings_to_vectors(adapter);
2316 if (err)
2317 return err;
2318
2319 #define SET_HANDLER(_v) (((_v)->rx.count && (_v)->tx.count) \
2320 ? &ixgbe_msix_clean_many : \
2321 (_v)->rx.count ? &ixgbe_msix_clean_rx : \
2322 (_v)->tx.count ? &ixgbe_msix_clean_tx : \
2323 NULL)
2324 for (vector = 0; vector < q_vectors; vector++) {
2325 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2326 handler = SET_HANDLER(q_vector);
2327
2328 if (handler == &ixgbe_msix_clean_rx) {
2329 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2330 "%s-%s-%d", netdev->name, "rx", ri++);
2331 } else if (handler == &ixgbe_msix_clean_tx) {
2332 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2333 "%s-%s-%d", netdev->name, "tx", ti++);
2334 } else if (handler == &ixgbe_msix_clean_many) {
2335 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2336 "%s-%s-%d", netdev->name, "TxRx", ri++);
2337 ti++;
2338 } else {
2339 /* skip this unused q_vector */
2340 continue;
2341 }
2342 err = request_irq(adapter->msix_entries[vector].vector,
2343 handler, 0, q_vector->name,
2344 q_vector);
2345 if (err) {
2346 e_err(probe, "request_irq failed for MSIX interrupt "
2347 "Error: %d\n", err);
2348 goto free_queue_irqs;
2349 }
2350 }
2351
2352 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2353 err = request_irq(adapter->msix_entries[vector].vector,
2354 ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
2355 if (err) {
2356 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2357 goto free_queue_irqs;
2358 }
2359
2360 return 0;
2361
2362 free_queue_irqs:
2363 for (i = vector - 1; i >= 0; i--)
2364 free_irq(adapter->msix_entries[--vector].vector,
2365 adapter->q_vector[i]);
2366 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2367 pci_disable_msix(adapter->pdev);
2368 kfree(adapter->msix_entries);
2369 adapter->msix_entries = NULL;
2370 return err;
2371 }
2372
2373 /**
2374 * ixgbe_irq_enable - Enable default interrupt generation settings
2375 * @adapter: board private structure
2376 **/
2377 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2378 bool flush)
2379 {
2380 u32 mask;
2381
2382 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2383 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2384 mask |= IXGBE_EIMS_GPI_SDP0;
2385 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2386 mask |= IXGBE_EIMS_GPI_SDP1;
2387 switch (adapter->hw.mac.type) {
2388 case ixgbe_mac_82599EB:
2389 case ixgbe_mac_X540:
2390 mask |= IXGBE_EIMS_ECC;
2391 mask |= IXGBE_EIMS_GPI_SDP1;
2392 mask |= IXGBE_EIMS_GPI_SDP2;
2393 if (adapter->num_vfs)
2394 mask |= IXGBE_EIMS_MAILBOX;
2395 break;
2396 default:
2397 break;
2398 }
2399 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2400 mask |= IXGBE_EIMS_FLOW_DIR;
2401
2402 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2403 if (queues)
2404 ixgbe_irq_enable_queues(adapter, ~0);
2405 if (flush)
2406 IXGBE_WRITE_FLUSH(&adapter->hw);
2407
2408 if (adapter->num_vfs > 32) {
2409 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2410 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2411 }
2412 }
2413
2414 /**
2415 * ixgbe_intr - legacy mode Interrupt Handler
2416 * @irq: interrupt number
2417 * @data: pointer to a network interface device structure
2418 **/
2419 static irqreturn_t ixgbe_intr(int irq, void *data)
2420 {
2421 struct ixgbe_adapter *adapter = data;
2422 struct ixgbe_hw *hw = &adapter->hw;
2423 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2424 u32 eicr;
2425
2426 /*
2427 * Workaround for silicon errata on 82598. Mask the interrupts
2428 * before the read of EICR.
2429 */
2430 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2431
2432 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2433 * therefore no explict interrupt disable is necessary */
2434 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2435 if (!eicr) {
2436 /*
2437 * shared interrupt alert!
2438 * make sure interrupts are enabled because the read will
2439 * have disabled interrupts due to EIAM
2440 * finish the workaround of silicon errata on 82598. Unmask
2441 * the interrupt that we masked before the EICR read.
2442 */
2443 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2444 ixgbe_irq_enable(adapter, true, true);
2445 return IRQ_NONE; /* Not our interrupt */
2446 }
2447
2448 if (eicr & IXGBE_EICR_LSC)
2449 ixgbe_check_lsc(adapter);
2450
2451 switch (hw->mac.type) {
2452 case ixgbe_mac_82599EB:
2453 ixgbe_check_sfp_event(adapter, eicr);
2454 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2455 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2456 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2457 adapter->interrupt_event = eicr;
2458 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2459 ixgbe_service_event_schedule(adapter);
2460 }
2461 }
2462 break;
2463 default:
2464 break;
2465 }
2466
2467 ixgbe_check_fan_failure(adapter, eicr);
2468
2469 if (napi_schedule_prep(&(q_vector->napi))) {
2470 /* would disable interrupts here but EIAM disabled it */
2471 __napi_schedule(&(q_vector->napi));
2472 }
2473
2474 /*
2475 * re-enable link(maybe) and non-queue interrupts, no flush.
2476 * ixgbe_poll will re-enable the queue interrupts
2477 */
2478
2479 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2480 ixgbe_irq_enable(adapter, false, false);
2481
2482 return IRQ_HANDLED;
2483 }
2484
2485 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2486 {
2487 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2488
2489 for (i = 0; i < q_vectors; i++) {
2490 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2491 bitmap_zero(q_vector->rx.idx, MAX_RX_QUEUES);
2492 bitmap_zero(q_vector->tx.idx, MAX_TX_QUEUES);
2493 q_vector->rx.count = 0;
2494 q_vector->tx.count = 0;
2495 }
2496 }
2497
2498 /**
2499 * ixgbe_request_irq - initialize interrupts
2500 * @adapter: board private structure
2501 *
2502 * Attempts to configure interrupts using the best available
2503 * capabilities of the hardware and kernel.
2504 **/
2505 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2506 {
2507 struct net_device *netdev = adapter->netdev;
2508 int err;
2509
2510 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2511 err = ixgbe_request_msix_irqs(adapter);
2512 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2513 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2514 netdev->name, adapter);
2515 } else {
2516 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2517 netdev->name, adapter);
2518 }
2519
2520 if (err)
2521 e_err(probe, "request_irq failed, Error %d\n", err);
2522
2523 return err;
2524 }
2525
2526 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2527 {
2528 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2529 int i, q_vectors;
2530
2531 q_vectors = adapter->num_msix_vectors;
2532
2533 i = q_vectors - 1;
2534 free_irq(adapter->msix_entries[i].vector, adapter);
2535
2536 i--;
2537 for (; i >= 0; i--) {
2538 /* free only the irqs that were actually requested */
2539 if (!adapter->q_vector[i]->rx.count &&
2540 !adapter->q_vector[i]->tx.count)
2541 continue;
2542
2543 free_irq(adapter->msix_entries[i].vector,
2544 adapter->q_vector[i]);
2545 }
2546
2547 ixgbe_reset_q_vectors(adapter);
2548 } else {
2549 free_irq(adapter->pdev->irq, adapter);
2550 }
2551 }
2552
2553 /**
2554 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2555 * @adapter: board private structure
2556 **/
2557 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2558 {
2559 switch (adapter->hw.mac.type) {
2560 case ixgbe_mac_82598EB:
2561 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2562 break;
2563 case ixgbe_mac_82599EB:
2564 case ixgbe_mac_X540:
2565 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2566 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2568 if (adapter->num_vfs > 32)
2569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2570 break;
2571 default:
2572 break;
2573 }
2574 IXGBE_WRITE_FLUSH(&adapter->hw);
2575 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2576 int i;
2577 for (i = 0; i < adapter->num_msix_vectors; i++)
2578 synchronize_irq(adapter->msix_entries[i].vector);
2579 } else {
2580 synchronize_irq(adapter->pdev->irq);
2581 }
2582 }
2583
2584 /**
2585 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2586 *
2587 **/
2588 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2589 {
2590 struct ixgbe_hw *hw = &adapter->hw;
2591
2592 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2593 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2594
2595 ixgbe_set_ivar(adapter, 0, 0, 0);
2596 ixgbe_set_ivar(adapter, 1, 0, 0);
2597
2598 map_vector_to_rxq(adapter, 0, 0);
2599 map_vector_to_txq(adapter, 0, 0);
2600
2601 e_info(hw, "Legacy interrupt IVAR setup done\n");
2602 }
2603
2604 /**
2605 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2606 * @adapter: board private structure
2607 * @ring: structure containing ring specific data
2608 *
2609 * Configure the Tx descriptor ring after a reset.
2610 **/
2611 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2612 struct ixgbe_ring *ring)
2613 {
2614 struct ixgbe_hw *hw = &adapter->hw;
2615 u64 tdba = ring->dma;
2616 int wait_loop = 10;
2617 u32 txdctl;
2618 u8 reg_idx = ring->reg_idx;
2619
2620 /* disable queue to avoid issues while updating state */
2621 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2622 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2623 txdctl & ~IXGBE_TXDCTL_ENABLE);
2624 IXGBE_WRITE_FLUSH(hw);
2625
2626 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2627 (tdba & DMA_BIT_MASK(32)));
2628 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2629 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2630 ring->count * sizeof(union ixgbe_adv_tx_desc));
2631 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2632 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2633 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2634
2635 /* configure fetching thresholds */
2636 if (adapter->rx_itr_setting == 0) {
2637 /* cannot set wthresh when itr==0 */
2638 txdctl &= ~0x007F0000;
2639 } else {
2640 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2641 txdctl |= (8 << 16);
2642 }
2643 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2644 /* PThresh workaround for Tx hang with DFP enabled. */
2645 txdctl |= 32;
2646 }
2647
2648 /* reinitialize flowdirector state */
2649 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2650 adapter->atr_sample_rate) {
2651 ring->atr_sample_rate = adapter->atr_sample_rate;
2652 ring->atr_count = 0;
2653 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2654 } else {
2655 ring->atr_sample_rate = 0;
2656 }
2657
2658 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2659
2660 /* enable queue */
2661 txdctl |= IXGBE_TXDCTL_ENABLE;
2662 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2663
2664 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2665 if (hw->mac.type == ixgbe_mac_82598EB &&
2666 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2667 return;
2668
2669 /* poll to verify queue is enabled */
2670 do {
2671 usleep_range(1000, 2000);
2672 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2673 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2674 if (!wait_loop)
2675 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2676 }
2677
2678 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2679 {
2680 struct ixgbe_hw *hw = &adapter->hw;
2681 u32 rttdcs;
2682 u32 reg;
2683 u8 tcs = netdev_get_num_tc(adapter->netdev);
2684
2685 if (hw->mac.type == ixgbe_mac_82598EB)
2686 return;
2687
2688 /* disable the arbiter while setting MTQC */
2689 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2690 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2691 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2692
2693 /* set transmit pool layout */
2694 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2695 case (IXGBE_FLAG_SRIOV_ENABLED):
2696 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2697 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2698 break;
2699 default:
2700 if (!tcs)
2701 reg = IXGBE_MTQC_64Q_1PB;
2702 else if (tcs <= 4)
2703 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2704 else
2705 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2706
2707 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2708
2709 /* Enable Security TX Buffer IFG for multiple pb */
2710 if (tcs) {
2711 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2712 reg |= IXGBE_SECTX_DCB;
2713 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2714 }
2715 break;
2716 }
2717
2718 /* re-enable the arbiter */
2719 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2720 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2721 }
2722
2723 /**
2724 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2725 * @adapter: board private structure
2726 *
2727 * Configure the Tx unit of the MAC after a reset.
2728 **/
2729 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2730 {
2731 struct ixgbe_hw *hw = &adapter->hw;
2732 u32 dmatxctl;
2733 u32 i;
2734
2735 ixgbe_setup_mtqc(adapter);
2736
2737 if (hw->mac.type != ixgbe_mac_82598EB) {
2738 /* DMATXCTL.EN must be before Tx queues are enabled */
2739 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2740 dmatxctl |= IXGBE_DMATXCTL_TE;
2741 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2742 }
2743
2744 /* Setup the HW Tx Head and Tail descriptor pointers */
2745 for (i = 0; i < adapter->num_tx_queues; i++)
2746 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2747 }
2748
2749 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2750
2751 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2752 struct ixgbe_ring *rx_ring)
2753 {
2754 u32 srrctl;
2755 u8 reg_idx = rx_ring->reg_idx;
2756
2757 switch (adapter->hw.mac.type) {
2758 case ixgbe_mac_82598EB: {
2759 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2760 const int mask = feature[RING_F_RSS].mask;
2761 reg_idx = reg_idx & mask;
2762 }
2763 break;
2764 case ixgbe_mac_82599EB:
2765 case ixgbe_mac_X540:
2766 default:
2767 break;
2768 }
2769
2770 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2771
2772 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2773 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2774 if (adapter->num_vfs)
2775 srrctl |= IXGBE_SRRCTL_DROP_EN;
2776
2777 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2778 IXGBE_SRRCTL_BSIZEHDR_MASK;
2779
2780 if (ring_is_ps_enabled(rx_ring)) {
2781 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2782 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2783 #else
2784 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2785 #endif
2786 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2787 } else {
2788 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2789 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2790 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2791 }
2792
2793 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2794 }
2795
2796 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2797 {
2798 struct ixgbe_hw *hw = &adapter->hw;
2799 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2800 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2801 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2802 u32 mrqc = 0, reta = 0;
2803 u32 rxcsum;
2804 int i, j;
2805 u8 tcs = netdev_get_num_tc(adapter->netdev);
2806 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2807
2808 if (tcs)
2809 maxq = min(maxq, adapter->num_tx_queues / tcs);
2810
2811 /* Fill out hash function seeds */
2812 for (i = 0; i < 10; i++)
2813 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2814
2815 /* Fill out redirection table */
2816 for (i = 0, j = 0; i < 128; i++, j++) {
2817 if (j == maxq)
2818 j = 0;
2819 /* reta = 4-byte sliding window of
2820 * 0x00..(indices-1)(indices-1)00..etc. */
2821 reta = (reta << 8) | (j * 0x11);
2822 if ((i & 3) == 3)
2823 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2824 }
2825
2826 /* Disable indicating checksum in descriptor, enables RSS hash */
2827 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2828 rxcsum |= IXGBE_RXCSUM_PCSD;
2829 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2830
2831 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2832 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2833 mrqc = IXGBE_MRQC_RSSEN;
2834 } else {
2835 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2836 | IXGBE_FLAG_SRIOV_ENABLED);
2837
2838 switch (mask) {
2839 case (IXGBE_FLAG_RSS_ENABLED):
2840 if (!tcs)
2841 mrqc = IXGBE_MRQC_RSSEN;
2842 else if (tcs <= 4)
2843 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2844 else
2845 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2846 break;
2847 case (IXGBE_FLAG_SRIOV_ENABLED):
2848 mrqc = IXGBE_MRQC_VMDQEN;
2849 break;
2850 default:
2851 break;
2852 }
2853 }
2854
2855 /* Perform hash on these packet types */
2856 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2857 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2858 | IXGBE_MRQC_RSS_FIELD_IPV6
2859 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2860
2861 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2862 }
2863
2864 /**
2865 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2866 * @adapter: address of board private structure
2867 * @index: index of ring to set
2868 **/
2869 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2870 struct ixgbe_ring *ring)
2871 {
2872 struct ixgbe_hw *hw = &adapter->hw;
2873 u32 rscctrl;
2874 int rx_buf_len;
2875 u8 reg_idx = ring->reg_idx;
2876
2877 if (!ring_is_rsc_enabled(ring))
2878 return;
2879
2880 rx_buf_len = ring->rx_buf_len;
2881 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2882 rscctrl |= IXGBE_RSCCTL_RSCEN;
2883 /*
2884 * we must limit the number of descriptors so that the
2885 * total size of max desc * buf_len is not greater
2886 * than 65535
2887 */
2888 if (ring_is_ps_enabled(ring)) {
2889 #if (MAX_SKB_FRAGS > 16)
2890 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2891 #elif (MAX_SKB_FRAGS > 8)
2892 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2893 #elif (MAX_SKB_FRAGS > 4)
2894 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2895 #else
2896 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2897 #endif
2898 } else {
2899 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2900 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2901 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2902 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2903 else
2904 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2905 }
2906 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2907 }
2908
2909 /**
2910 * ixgbe_set_uta - Set unicast filter table address
2911 * @adapter: board private structure
2912 *
2913 * The unicast table address is a register array of 32-bit registers.
2914 * The table is meant to be used in a way similar to how the MTA is used
2915 * however due to certain limitations in the hardware it is necessary to
2916 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2917 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2918 **/
2919 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2920 {
2921 struct ixgbe_hw *hw = &adapter->hw;
2922 int i;
2923
2924 /* The UTA table only exists on 82599 hardware and newer */
2925 if (hw->mac.type < ixgbe_mac_82599EB)
2926 return;
2927
2928 /* we only need to do this if VMDq is enabled */
2929 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2930 return;
2931
2932 for (i = 0; i < 128; i++)
2933 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2934 }
2935
2936 #define IXGBE_MAX_RX_DESC_POLL 10
2937 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2938 struct ixgbe_ring *ring)
2939 {
2940 struct ixgbe_hw *hw = &adapter->hw;
2941 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2942 u32 rxdctl;
2943 u8 reg_idx = ring->reg_idx;
2944
2945 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2946 if (hw->mac.type == ixgbe_mac_82598EB &&
2947 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2948 return;
2949
2950 do {
2951 usleep_range(1000, 2000);
2952 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2953 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2954
2955 if (!wait_loop) {
2956 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2957 "the polling period\n", reg_idx);
2958 }
2959 }
2960
2961 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2962 struct ixgbe_ring *ring)
2963 {
2964 struct ixgbe_hw *hw = &adapter->hw;
2965 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2966 u32 rxdctl;
2967 u8 reg_idx = ring->reg_idx;
2968
2969 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2970 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2971
2972 /* write value back with RXDCTL.ENABLE bit cleared */
2973 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2974
2975 if (hw->mac.type == ixgbe_mac_82598EB &&
2976 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2977 return;
2978
2979 /* the hardware may take up to 100us to really disable the rx queue */
2980 do {
2981 udelay(10);
2982 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2983 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2984
2985 if (!wait_loop) {
2986 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2987 "the polling period\n", reg_idx);
2988 }
2989 }
2990
2991 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2992 struct ixgbe_ring *ring)
2993 {
2994 struct ixgbe_hw *hw = &adapter->hw;
2995 u64 rdba = ring->dma;
2996 u32 rxdctl;
2997 u8 reg_idx = ring->reg_idx;
2998
2999 /* disable queue to avoid issues while updating state */
3000 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3001 ixgbe_disable_rx_queue(adapter, ring);
3002
3003 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3004 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3005 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3006 ring->count * sizeof(union ixgbe_adv_rx_desc));
3007 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3008 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3009 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3010
3011 ixgbe_configure_srrctl(adapter, ring);
3012 ixgbe_configure_rscctl(adapter, ring);
3013
3014 /* If operating in IOV mode set RLPML for X540 */
3015 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3016 hw->mac.type == ixgbe_mac_X540) {
3017 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3018 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3019 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3020 }
3021
3022 if (hw->mac.type == ixgbe_mac_82598EB) {
3023 /*
3024 * enable cache line friendly hardware writes:
3025 * PTHRESH=32 descriptors (half the internal cache),
3026 * this also removes ugly rx_no_buffer_count increment
3027 * HTHRESH=4 descriptors (to minimize latency on fetch)
3028 * WTHRESH=8 burst writeback up to two cache lines
3029 */
3030 rxdctl &= ~0x3FFFFF;
3031 rxdctl |= 0x080420;
3032 }
3033
3034 /* enable receive descriptor ring */
3035 rxdctl |= IXGBE_RXDCTL_ENABLE;
3036 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3037
3038 ixgbe_rx_desc_queue_enable(adapter, ring);
3039 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3040 }
3041
3042 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3043 {
3044 struct ixgbe_hw *hw = &adapter->hw;
3045 int p;
3046
3047 /* PSRTYPE must be initialized in non 82598 adapters */
3048 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3049 IXGBE_PSRTYPE_UDPHDR |
3050 IXGBE_PSRTYPE_IPV4HDR |
3051 IXGBE_PSRTYPE_L2HDR |
3052 IXGBE_PSRTYPE_IPV6HDR;
3053
3054 if (hw->mac.type == ixgbe_mac_82598EB)
3055 return;
3056
3057 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3058 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3059
3060 for (p = 0; p < adapter->num_rx_pools; p++)
3061 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3062 psrtype);
3063 }
3064
3065 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3066 {
3067 struct ixgbe_hw *hw = &adapter->hw;
3068 u32 gcr_ext;
3069 u32 vt_reg_bits;
3070 u32 reg_offset, vf_shift;
3071 u32 vmdctl;
3072
3073 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3074 return;
3075
3076 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3077 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3078 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3079 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3080
3081 vf_shift = adapter->num_vfs % 32;
3082 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3083
3084 /* Enable only the PF's pool for Tx/Rx */
3085 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3086 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3087 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3088 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3089 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3090
3091 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3092 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3093
3094 /*
3095 * Set up VF register offsets for selected VT Mode,
3096 * i.e. 32 or 64 VFs for SR-IOV
3097 */
3098 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3099 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3100 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3101 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3102
3103 /* enable Tx loopback for VF/PF communication */
3104 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3105 /* Enable MAC Anti-Spoofing */
3106 hw->mac.ops.set_mac_anti_spoofing(hw,
3107 (adapter->antispoofing_enabled =
3108 (adapter->num_vfs != 0)),
3109 adapter->num_vfs);
3110 }
3111
3112 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3113 {
3114 struct ixgbe_hw *hw = &adapter->hw;
3115 struct net_device *netdev = adapter->netdev;
3116 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3117 int rx_buf_len;
3118 struct ixgbe_ring *rx_ring;
3119 int i;
3120 u32 mhadd, hlreg0;
3121
3122 /* Decide whether to use packet split mode or not */
3123 /* On by default */
3124 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3125
3126 /* Do not use packet split if we're in SR-IOV Mode */
3127 if (adapter->num_vfs)
3128 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3129
3130 /* Disable packet split due to 82599 erratum #45 */
3131 if (hw->mac.type == ixgbe_mac_82599EB)
3132 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3133
3134 /* Set the RX buffer length according to the mode */
3135 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3136 rx_buf_len = IXGBE_RX_HDR_SIZE;
3137 } else {
3138 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3139 (netdev->mtu <= ETH_DATA_LEN))
3140 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3141 else
3142 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3143 }
3144
3145 #ifdef IXGBE_FCOE
3146 /* adjust max frame to be able to do baby jumbo for FCoE */
3147 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3148 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3149 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3150
3151 #endif /* IXGBE_FCOE */
3152 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3153 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3154 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3155 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3156
3157 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3158 }
3159
3160 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3161 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3162 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3163 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3164
3165 /*
3166 * Setup the HW Rx Head and Tail Descriptor Pointers and
3167 * the Base and Length of the Rx Descriptor Ring
3168 */
3169 for (i = 0; i < adapter->num_rx_queues; i++) {
3170 rx_ring = adapter->rx_ring[i];
3171 rx_ring->rx_buf_len = rx_buf_len;
3172
3173 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3174 set_ring_ps_enabled(rx_ring);
3175 else
3176 clear_ring_ps_enabled(rx_ring);
3177
3178 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3179 set_ring_rsc_enabled(rx_ring);
3180 else
3181 clear_ring_rsc_enabled(rx_ring);
3182
3183 #ifdef IXGBE_FCOE
3184 if (netdev->features & NETIF_F_FCOE_MTU) {
3185 struct ixgbe_ring_feature *f;
3186 f = &adapter->ring_feature[RING_F_FCOE];
3187 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3188 clear_ring_ps_enabled(rx_ring);
3189 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3190 rx_ring->rx_buf_len =
3191 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3192 } else if (!ring_is_rsc_enabled(rx_ring) &&
3193 !ring_is_ps_enabled(rx_ring)) {
3194 rx_ring->rx_buf_len =
3195 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3196 }
3197 }
3198 #endif /* IXGBE_FCOE */
3199 }
3200 }
3201
3202 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3203 {
3204 struct ixgbe_hw *hw = &adapter->hw;
3205 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3206
3207 switch (hw->mac.type) {
3208 case ixgbe_mac_82598EB:
3209 /*
3210 * For VMDq support of different descriptor types or
3211 * buffer sizes through the use of multiple SRRCTL
3212 * registers, RDRXCTL.MVMEN must be set to 1
3213 *
3214 * also, the manual doesn't mention it clearly but DCA hints
3215 * will only use queue 0's tags unless this bit is set. Side
3216 * effects of setting this bit are only that SRRCTL must be
3217 * fully programmed [0..15]
3218 */
3219 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3220 break;
3221 case ixgbe_mac_82599EB:
3222 case ixgbe_mac_X540:
3223 /* Disable RSC for ACK packets */
3224 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3225 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3226 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3227 /* hardware requires some bits to be set by default */
3228 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3229 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3230 break;
3231 default:
3232 /* We should do nothing since we don't know this hardware */
3233 return;
3234 }
3235
3236 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3237 }
3238
3239 /**
3240 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3241 * @adapter: board private structure
3242 *
3243 * Configure the Rx unit of the MAC after a reset.
3244 **/
3245 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3246 {
3247 struct ixgbe_hw *hw = &adapter->hw;
3248 int i;
3249 u32 rxctrl;
3250
3251 /* disable receives while setting up the descriptors */
3252 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3253 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3254
3255 ixgbe_setup_psrtype(adapter);
3256 ixgbe_setup_rdrxctl(adapter);
3257
3258 /* Program registers for the distribution of queues */
3259 ixgbe_setup_mrqc(adapter);
3260
3261 ixgbe_set_uta(adapter);
3262
3263 /* set_rx_buffer_len must be called before ring initialization */
3264 ixgbe_set_rx_buffer_len(adapter);
3265
3266 /*
3267 * Setup the HW Rx Head and Tail Descriptor Pointers and
3268 * the Base and Length of the Rx Descriptor Ring
3269 */
3270 for (i = 0; i < adapter->num_rx_queues; i++)
3271 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3272
3273 /* disable drop enable for 82598 parts */
3274 if (hw->mac.type == ixgbe_mac_82598EB)
3275 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3276
3277 /* enable all receives */
3278 rxctrl |= IXGBE_RXCTRL_RXEN;
3279 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3280 }
3281
3282 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3283 {
3284 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3285 struct ixgbe_hw *hw = &adapter->hw;
3286 int pool_ndx = adapter->num_vfs;
3287
3288 /* add VID to filter table */
3289 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3290 set_bit(vid, adapter->active_vlans);
3291 }
3292
3293 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3294 {
3295 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3296 struct ixgbe_hw *hw = &adapter->hw;
3297 int pool_ndx = adapter->num_vfs;
3298
3299 /* remove VID from filter table */
3300 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3301 clear_bit(vid, adapter->active_vlans);
3302 }
3303
3304 /**
3305 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3306 * @adapter: driver data
3307 */
3308 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3309 {
3310 struct ixgbe_hw *hw = &adapter->hw;
3311 u32 vlnctrl;
3312
3313 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3314 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3315 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3316 }
3317
3318 /**
3319 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3320 * @adapter: driver data
3321 */
3322 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3323 {
3324 struct ixgbe_hw *hw = &adapter->hw;
3325 u32 vlnctrl;
3326
3327 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3328 vlnctrl |= IXGBE_VLNCTRL_VFE;
3329 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3330 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3331 }
3332
3333 /**
3334 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3335 * @adapter: driver data
3336 */
3337 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3338 {
3339 struct ixgbe_hw *hw = &adapter->hw;
3340 u32 vlnctrl;
3341 int i, j;
3342
3343 switch (hw->mac.type) {
3344 case ixgbe_mac_82598EB:
3345 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3346 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3347 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3348 break;
3349 case ixgbe_mac_82599EB:
3350 case ixgbe_mac_X540:
3351 for (i = 0; i < adapter->num_rx_queues; i++) {
3352 j = adapter->rx_ring[i]->reg_idx;
3353 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3354 vlnctrl &= ~IXGBE_RXDCTL_VME;
3355 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3356 }
3357 break;
3358 default:
3359 break;
3360 }
3361 }
3362
3363 /**
3364 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3365 * @adapter: driver data
3366 */
3367 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3368 {
3369 struct ixgbe_hw *hw = &adapter->hw;
3370 u32 vlnctrl;
3371 int i, j;
3372
3373 switch (hw->mac.type) {
3374 case ixgbe_mac_82598EB:
3375 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3376 vlnctrl |= IXGBE_VLNCTRL_VME;
3377 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3378 break;
3379 case ixgbe_mac_82599EB:
3380 case ixgbe_mac_X540:
3381 for (i = 0; i < adapter->num_rx_queues; i++) {
3382 j = adapter->rx_ring[i]->reg_idx;
3383 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3384 vlnctrl |= IXGBE_RXDCTL_VME;
3385 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3386 }
3387 break;
3388 default:
3389 break;
3390 }
3391 }
3392
3393 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3394 {
3395 u16 vid;
3396
3397 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3398
3399 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3400 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3401 }
3402
3403 /**
3404 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3405 * @netdev: network interface device structure
3406 *
3407 * Writes unicast address list to the RAR table.
3408 * Returns: -ENOMEM on failure/insufficient address space
3409 * 0 on no addresses written
3410 * X on writing X addresses to the RAR table
3411 **/
3412 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3413 {
3414 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3415 struct ixgbe_hw *hw = &adapter->hw;
3416 unsigned int vfn = adapter->num_vfs;
3417 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3418 int count = 0;
3419
3420 /* return ENOMEM indicating insufficient memory for addresses */
3421 if (netdev_uc_count(netdev) > rar_entries)
3422 return -ENOMEM;
3423
3424 if (!netdev_uc_empty(netdev) && rar_entries) {
3425 struct netdev_hw_addr *ha;
3426 /* return error if we do not support writing to RAR table */
3427 if (!hw->mac.ops.set_rar)
3428 return -ENOMEM;
3429
3430 netdev_for_each_uc_addr(ha, netdev) {
3431 if (!rar_entries)
3432 break;
3433 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3434 vfn, IXGBE_RAH_AV);
3435 count++;
3436 }
3437 }
3438 /* write the addresses in reverse order to avoid write combining */
3439 for (; rar_entries > 0 ; rar_entries--)
3440 hw->mac.ops.clear_rar(hw, rar_entries);
3441
3442 return count;
3443 }
3444
3445 /**
3446 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3447 * @netdev: network interface device structure
3448 *
3449 * The set_rx_method entry point is called whenever the unicast/multicast
3450 * address list or the network interface flags are updated. This routine is
3451 * responsible for configuring the hardware for proper unicast, multicast and
3452 * promiscuous mode.
3453 **/
3454 void ixgbe_set_rx_mode(struct net_device *netdev)
3455 {
3456 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3457 struct ixgbe_hw *hw = &adapter->hw;
3458 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3459 int count;
3460
3461 /* Check for Promiscuous and All Multicast modes */
3462
3463 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3464
3465 /* set all bits that we expect to always be set */
3466 fctrl |= IXGBE_FCTRL_BAM;
3467 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3468 fctrl |= IXGBE_FCTRL_PMCF;
3469
3470 /* clear the bits we are changing the status of */
3471 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3472
3473 if (netdev->flags & IFF_PROMISC) {
3474 hw->addr_ctrl.user_set_promisc = true;
3475 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3476 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3477 /* don't hardware filter vlans in promisc mode */
3478 ixgbe_vlan_filter_disable(adapter);
3479 } else {
3480 if (netdev->flags & IFF_ALLMULTI) {
3481 fctrl |= IXGBE_FCTRL_MPE;
3482 vmolr |= IXGBE_VMOLR_MPE;
3483 } else {
3484 /*
3485 * Write addresses to the MTA, if the attempt fails
3486 * then we should just turn on promiscuous mode so
3487 * that we can at least receive multicast traffic
3488 */
3489 hw->mac.ops.update_mc_addr_list(hw, netdev);
3490 vmolr |= IXGBE_VMOLR_ROMPE;
3491 }
3492 ixgbe_vlan_filter_enable(adapter);
3493 hw->addr_ctrl.user_set_promisc = false;
3494 /*
3495 * Write addresses to available RAR registers, if there is not
3496 * sufficient space to store all the addresses then enable
3497 * unicast promiscuous mode
3498 */
3499 count = ixgbe_write_uc_addr_list(netdev);
3500 if (count < 0) {
3501 fctrl |= IXGBE_FCTRL_UPE;
3502 vmolr |= IXGBE_VMOLR_ROPE;
3503 }
3504 }
3505
3506 if (adapter->num_vfs) {
3507 ixgbe_restore_vf_multicasts(adapter);
3508 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3509 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3510 IXGBE_VMOLR_ROPE);
3511 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3512 }
3513
3514 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3515
3516 if (netdev->features & NETIF_F_HW_VLAN_RX)
3517 ixgbe_vlan_strip_enable(adapter);
3518 else
3519 ixgbe_vlan_strip_disable(adapter);
3520 }
3521
3522 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3523 {
3524 int q_idx;
3525 struct ixgbe_q_vector *q_vector;
3526 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3527
3528 /* legacy and MSI only use one vector */
3529 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3530 q_vectors = 1;
3531
3532 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3533 struct napi_struct *napi;
3534 q_vector = adapter->q_vector[q_idx];
3535 napi = &q_vector->napi;
3536 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3537 if (!q_vector->rx.count || !q_vector->tx.count) {
3538 if (q_vector->tx.count == 1)
3539 napi->poll = &ixgbe_clean_txonly;
3540 else if (q_vector->rx.count == 1)
3541 napi->poll = &ixgbe_clean_rxonly;
3542 }
3543 }
3544
3545 napi_enable(napi);
3546 }
3547 }
3548
3549 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3550 {
3551 int q_idx;
3552 struct ixgbe_q_vector *q_vector;
3553 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3554
3555 /* legacy and MSI only use one vector */
3556 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3557 q_vectors = 1;
3558
3559 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3560 q_vector = adapter->q_vector[q_idx];
3561 napi_disable(&q_vector->napi);
3562 }
3563 }
3564
3565 #ifdef CONFIG_IXGBE_DCB
3566 /*
3567 * ixgbe_configure_dcb - Configure DCB hardware
3568 * @adapter: ixgbe adapter struct
3569 *
3570 * This is called by the driver on open to configure the DCB hardware.
3571 * This is also called by the gennetlink interface when reconfiguring
3572 * the DCB state.
3573 */
3574 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3575 {
3576 struct ixgbe_hw *hw = &adapter->hw;
3577 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3578
3579 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3580 if (hw->mac.type == ixgbe_mac_82598EB)
3581 netif_set_gso_max_size(adapter->netdev, 65536);
3582 return;
3583 }
3584
3585 if (hw->mac.type == ixgbe_mac_82598EB)
3586 netif_set_gso_max_size(adapter->netdev, 32768);
3587
3588
3589 /* Enable VLAN tag insert/strip */
3590 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3591
3592 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3593
3594 /* reconfigure the hardware */
3595 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3596 #ifdef CONFIG_FCOE
3597 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3598 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3599 #endif
3600 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3601 DCB_TX_CONFIG);
3602 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3603 DCB_RX_CONFIG);
3604 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3605 } else {
3606 struct net_device *dev = adapter->netdev;
3607
3608 if (adapter->ixgbe_ieee_ets)
3609 dev->dcbnl_ops->ieee_setets(dev,
3610 adapter->ixgbe_ieee_ets);
3611 if (adapter->ixgbe_ieee_pfc)
3612 dev->dcbnl_ops->ieee_setpfc(dev,
3613 adapter->ixgbe_ieee_pfc);
3614 }
3615
3616 /* Enable RSS Hash per TC */
3617 if (hw->mac.type != ixgbe_mac_82598EB) {
3618 int i;
3619 u32 reg = 0;
3620
3621 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3622 u8 msb = 0;
3623 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3624
3625 while (cnt >>= 1)
3626 msb++;
3627
3628 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3629 }
3630 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3631 }
3632 }
3633
3634 #endif
3635
3636 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3637 {
3638 int hdrm = 0;
3639 int num_tc = netdev_get_num_tc(adapter->netdev);
3640 struct ixgbe_hw *hw = &adapter->hw;
3641
3642 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3643 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3644 hdrm = 64 << adapter->fdir_pballoc;
3645
3646 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3647 }
3648
3649 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3650 {
3651 struct ixgbe_hw *hw = &adapter->hw;
3652 struct hlist_node *node, *node2;
3653 struct ixgbe_fdir_filter *filter;
3654
3655 spin_lock(&adapter->fdir_perfect_lock);
3656
3657 if (!hlist_empty(&adapter->fdir_filter_list))
3658 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3659
3660 hlist_for_each_entry_safe(filter, node, node2,
3661 &adapter->fdir_filter_list, fdir_node) {
3662 ixgbe_fdir_write_perfect_filter_82599(hw,
3663 &filter->filter,
3664 filter->sw_idx,
3665 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3666 IXGBE_FDIR_DROP_QUEUE :
3667 adapter->rx_ring[filter->action]->reg_idx);
3668 }
3669
3670 spin_unlock(&adapter->fdir_perfect_lock);
3671 }
3672
3673 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3674 {
3675 struct net_device *netdev = adapter->netdev;
3676 struct ixgbe_hw *hw = &adapter->hw;
3677 int i;
3678
3679 ixgbe_configure_pb(adapter);
3680 #ifdef CONFIG_IXGBE_DCB
3681 ixgbe_configure_dcb(adapter);
3682 #endif
3683
3684 ixgbe_set_rx_mode(netdev);
3685 ixgbe_restore_vlan(adapter);
3686
3687 #ifdef IXGBE_FCOE
3688 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3689 ixgbe_configure_fcoe(adapter);
3690
3691 #endif /* IXGBE_FCOE */
3692 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3693 for (i = 0; i < adapter->num_tx_queues; i++)
3694 adapter->tx_ring[i]->atr_sample_rate =
3695 adapter->atr_sample_rate;
3696 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3697 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3698 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3699 adapter->fdir_pballoc);
3700 ixgbe_fdir_filter_restore(adapter);
3701 }
3702 ixgbe_configure_virtualization(adapter);
3703
3704 ixgbe_configure_tx(adapter);
3705 ixgbe_configure_rx(adapter);
3706 }
3707
3708 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3709 {
3710 switch (hw->phy.type) {
3711 case ixgbe_phy_sfp_avago:
3712 case ixgbe_phy_sfp_ftl:
3713 case ixgbe_phy_sfp_intel:
3714 case ixgbe_phy_sfp_unknown:
3715 case ixgbe_phy_sfp_passive_tyco:
3716 case ixgbe_phy_sfp_passive_unknown:
3717 case ixgbe_phy_sfp_active_unknown:
3718 case ixgbe_phy_sfp_ftl_active:
3719 return true;
3720 default:
3721 return false;
3722 }
3723 }
3724
3725 /**
3726 * ixgbe_sfp_link_config - set up SFP+ link
3727 * @adapter: pointer to private adapter struct
3728 **/
3729 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3730 {
3731 /*
3732 * We are assuming the worst case scenerio here, and that
3733 * is that an SFP was inserted/removed after the reset
3734 * but before SFP detection was enabled. As such the best
3735 * solution is to just start searching as soon as we start
3736 */
3737 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3738 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3739
3740 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3741 }
3742
3743 /**
3744 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3745 * @hw: pointer to private hardware struct
3746 *
3747 * Returns 0 on success, negative on failure
3748 **/
3749 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3750 {
3751 u32 autoneg;
3752 bool negotiation, link_up = false;
3753 u32 ret = IXGBE_ERR_LINK_SETUP;
3754
3755 if (hw->mac.ops.check_link)
3756 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3757
3758 if (ret)
3759 goto link_cfg_out;
3760
3761 autoneg = hw->phy.autoneg_advertised;
3762 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3763 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3764 &negotiation);
3765 if (ret)
3766 goto link_cfg_out;
3767
3768 if (hw->mac.ops.setup_link)
3769 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3770 link_cfg_out:
3771 return ret;
3772 }
3773
3774 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3775 {
3776 struct ixgbe_hw *hw = &adapter->hw;
3777 u32 gpie = 0;
3778
3779 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3780 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3781 IXGBE_GPIE_OCD;
3782 gpie |= IXGBE_GPIE_EIAME;
3783 /*
3784 * use EIAM to auto-mask when MSI-X interrupt is asserted
3785 * this saves a register write for every interrupt
3786 */
3787 switch (hw->mac.type) {
3788 case ixgbe_mac_82598EB:
3789 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3790 break;
3791 case ixgbe_mac_82599EB:
3792 case ixgbe_mac_X540:
3793 default:
3794 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3795 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3796 break;
3797 }
3798 } else {
3799 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3800 * specifically only auto mask tx and rx interrupts */
3801 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3802 }
3803
3804 /* XXX: to interrupt immediately for EICS writes, enable this */
3805 /* gpie |= IXGBE_GPIE_EIMEN; */
3806
3807 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3808 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3809 gpie |= IXGBE_GPIE_VTMODE_64;
3810 }
3811
3812 /* Enable fan failure interrupt */
3813 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3814 gpie |= IXGBE_SDP1_GPIEN;
3815
3816 if (hw->mac.type == ixgbe_mac_82599EB) {
3817 gpie |= IXGBE_SDP1_GPIEN;
3818 gpie |= IXGBE_SDP2_GPIEN;
3819 }
3820
3821 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3822 }
3823
3824 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3825 {
3826 struct ixgbe_hw *hw = &adapter->hw;
3827 int err;
3828 u32 ctrl_ext;
3829
3830 ixgbe_get_hw_control(adapter);
3831 ixgbe_setup_gpie(adapter);
3832
3833 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3834 ixgbe_configure_msix(adapter);
3835 else
3836 ixgbe_configure_msi_and_legacy(adapter);
3837
3838 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3839 if (hw->mac.ops.enable_tx_laser &&
3840 ((hw->phy.multispeed_fiber) ||
3841 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3842 (hw->mac.type == ixgbe_mac_82599EB))))
3843 hw->mac.ops.enable_tx_laser(hw);
3844
3845 clear_bit(__IXGBE_DOWN, &adapter->state);
3846 ixgbe_napi_enable_all(adapter);
3847
3848 if (ixgbe_is_sfp(hw)) {
3849 ixgbe_sfp_link_config(adapter);
3850 } else {
3851 err = ixgbe_non_sfp_link_config(hw);
3852 if (err)
3853 e_err(probe, "link_config FAILED %d\n", err);
3854 }
3855
3856 /* clear any pending interrupts, may auto mask */
3857 IXGBE_READ_REG(hw, IXGBE_EICR);
3858 ixgbe_irq_enable(adapter, true, true);
3859
3860 /*
3861 * If this adapter has a fan, check to see if we had a failure
3862 * before we enabled the interrupt.
3863 */
3864 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3865 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3866 if (esdp & IXGBE_ESDP_SDP1)
3867 e_crit(drv, "Fan has stopped, replace the adapter\n");
3868 }
3869
3870 /* enable transmits */
3871 netif_tx_start_all_queues(adapter->netdev);
3872
3873 /* bring the link up in the watchdog, this could race with our first
3874 * link up interrupt but shouldn't be a problem */
3875 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3876 adapter->link_check_timeout = jiffies;
3877 mod_timer(&adapter->service_timer, jiffies);
3878
3879 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3880 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3881 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3882 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3883
3884 return 0;
3885 }
3886
3887 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3888 {
3889 WARN_ON(in_interrupt());
3890 /* put off any impending NetWatchDogTimeout */
3891 adapter->netdev->trans_start = jiffies;
3892
3893 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3894 usleep_range(1000, 2000);
3895 ixgbe_down(adapter);
3896 /*
3897 * If SR-IOV enabled then wait a bit before bringing the adapter
3898 * back up to give the VFs time to respond to the reset. The
3899 * two second wait is based upon the watchdog timer cycle in
3900 * the VF driver.
3901 */
3902 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3903 msleep(2000);
3904 ixgbe_up(adapter);
3905 clear_bit(__IXGBE_RESETTING, &adapter->state);
3906 }
3907
3908 int ixgbe_up(struct ixgbe_adapter *adapter)
3909 {
3910 /* hardware has been reset, we need to reload some things */
3911 ixgbe_configure(adapter);
3912
3913 return ixgbe_up_complete(adapter);
3914 }
3915
3916 void ixgbe_reset(struct ixgbe_adapter *adapter)
3917 {
3918 struct ixgbe_hw *hw = &adapter->hw;
3919 int err;
3920
3921 /* lock SFP init bit to prevent race conditions with the watchdog */
3922 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3923 usleep_range(1000, 2000);
3924
3925 /* clear all SFP and link config related flags while holding SFP_INIT */
3926 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3927 IXGBE_FLAG2_SFP_NEEDS_RESET);
3928 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3929
3930 err = hw->mac.ops.init_hw(hw);
3931 switch (err) {
3932 case 0:
3933 case IXGBE_ERR_SFP_NOT_PRESENT:
3934 case IXGBE_ERR_SFP_NOT_SUPPORTED:
3935 break;
3936 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3937 e_dev_err("master disable timed out\n");
3938 break;
3939 case IXGBE_ERR_EEPROM_VERSION:
3940 /* We are running on a pre-production device, log a warning */
3941 e_dev_warn("This device is a pre-production adapter/LOM. "
3942 "Please be aware there may be issuesassociated with "
3943 "your hardware. If you are experiencing problems "
3944 "please contact your Intel or hardware "
3945 "representative who provided you with this "
3946 "hardware.\n");
3947 break;
3948 default:
3949 e_dev_err("Hardware Error: %d\n", err);
3950 }
3951
3952 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3953
3954 /* reprogram the RAR[0] in case user changed it. */
3955 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3956 IXGBE_RAH_AV);
3957 }
3958
3959 /**
3960 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3961 * @rx_ring: ring to free buffers from
3962 **/
3963 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3964 {
3965 struct device *dev = rx_ring->dev;
3966 unsigned long size;
3967 u16 i;
3968
3969 /* ring already cleared, nothing to do */
3970 if (!rx_ring->rx_buffer_info)
3971 return;
3972
3973 /* Free all the Rx ring sk_buffs */
3974 for (i = 0; i < rx_ring->count; i++) {
3975 struct ixgbe_rx_buffer *rx_buffer_info;
3976
3977 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3978 if (rx_buffer_info->dma) {
3979 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3980 rx_ring->rx_buf_len,
3981 DMA_FROM_DEVICE);
3982 rx_buffer_info->dma = 0;
3983 }
3984 if (rx_buffer_info->skb) {
3985 struct sk_buff *skb = rx_buffer_info->skb;
3986 rx_buffer_info->skb = NULL;
3987 do {
3988 struct sk_buff *this = skb;
3989 if (IXGBE_RSC_CB(this)->delay_unmap) {
3990 dma_unmap_single(dev,
3991 IXGBE_RSC_CB(this)->dma,
3992 rx_ring->rx_buf_len,
3993 DMA_FROM_DEVICE);
3994 IXGBE_RSC_CB(this)->dma = 0;
3995 IXGBE_RSC_CB(skb)->delay_unmap = false;
3996 }
3997 skb = skb->prev;
3998 dev_kfree_skb(this);
3999 } while (skb);
4000 }
4001 if (!rx_buffer_info->page)
4002 continue;
4003 if (rx_buffer_info->page_dma) {
4004 dma_unmap_page(dev, rx_buffer_info->page_dma,
4005 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4006 rx_buffer_info->page_dma = 0;
4007 }
4008 put_page(rx_buffer_info->page);
4009 rx_buffer_info->page = NULL;
4010 rx_buffer_info->page_offset = 0;
4011 }
4012
4013 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4014 memset(rx_ring->rx_buffer_info, 0, size);
4015
4016 /* Zero out the descriptor ring */
4017 memset(rx_ring->desc, 0, rx_ring->size);
4018
4019 rx_ring->next_to_clean = 0;
4020 rx_ring->next_to_use = 0;
4021 }
4022
4023 /**
4024 * ixgbe_clean_tx_ring - Free Tx Buffers
4025 * @tx_ring: ring to be cleaned
4026 **/
4027 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4028 {
4029 struct ixgbe_tx_buffer *tx_buffer_info;
4030 unsigned long size;
4031 u16 i;
4032
4033 /* ring already cleared, nothing to do */
4034 if (!tx_ring->tx_buffer_info)
4035 return;
4036
4037 /* Free all the Tx ring sk_buffs */
4038 for (i = 0; i < tx_ring->count; i++) {
4039 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4040 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4041 }
4042
4043 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4044 memset(tx_ring->tx_buffer_info, 0, size);
4045
4046 /* Zero out the descriptor ring */
4047 memset(tx_ring->desc, 0, tx_ring->size);
4048
4049 tx_ring->next_to_use = 0;
4050 tx_ring->next_to_clean = 0;
4051 }
4052
4053 /**
4054 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4055 * @adapter: board private structure
4056 **/
4057 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4058 {
4059 int i;
4060
4061 for (i = 0; i < adapter->num_rx_queues; i++)
4062 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4063 }
4064
4065 /**
4066 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4067 * @adapter: board private structure
4068 **/
4069 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4070 {
4071 int i;
4072
4073 for (i = 0; i < adapter->num_tx_queues; i++)
4074 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4075 }
4076
4077 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4078 {
4079 struct hlist_node *node, *node2;
4080 struct ixgbe_fdir_filter *filter;
4081
4082 spin_lock(&adapter->fdir_perfect_lock);
4083
4084 hlist_for_each_entry_safe(filter, node, node2,
4085 &adapter->fdir_filter_list, fdir_node) {
4086 hlist_del(&filter->fdir_node);
4087 kfree(filter);
4088 }
4089 adapter->fdir_filter_count = 0;
4090
4091 spin_unlock(&adapter->fdir_perfect_lock);
4092 }
4093
4094 void ixgbe_down(struct ixgbe_adapter *adapter)
4095 {
4096 struct net_device *netdev = adapter->netdev;
4097 struct ixgbe_hw *hw = &adapter->hw;
4098 u32 rxctrl;
4099 int i;
4100 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4101
4102 /* signal that we are down to the interrupt handler */
4103 set_bit(__IXGBE_DOWN, &adapter->state);
4104
4105 /* disable receives */
4106 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4107 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4108
4109 /* disable all enabled rx queues */
4110 for (i = 0; i < adapter->num_rx_queues; i++)
4111 /* this call also flushes the previous write */
4112 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4113
4114 usleep_range(10000, 20000);
4115
4116 netif_tx_stop_all_queues(netdev);
4117
4118 /* call carrier off first to avoid false dev_watchdog timeouts */
4119 netif_carrier_off(netdev);
4120 netif_tx_disable(netdev);
4121
4122 ixgbe_irq_disable(adapter);
4123
4124 ixgbe_napi_disable_all(adapter);
4125
4126 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4127 IXGBE_FLAG2_RESET_REQUESTED);
4128 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4129
4130 del_timer_sync(&adapter->service_timer);
4131
4132 /* disable receive for all VFs and wait one second */
4133 if (adapter->num_vfs) {
4134 /* ping all the active vfs to let them know we are going down */
4135 ixgbe_ping_all_vfs(adapter);
4136
4137 /* Disable all VFTE/VFRE TX/RX */
4138 ixgbe_disable_tx_rx(adapter);
4139
4140 /* Mark all the VFs as inactive */
4141 for (i = 0 ; i < adapter->num_vfs; i++)
4142 adapter->vfinfo[i].clear_to_send = 0;
4143 }
4144
4145 /* Cleanup the affinity_hint CPU mask memory and callback */
4146 for (i = 0; i < num_q_vectors; i++) {
4147 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4148 /* clear the affinity_mask in the IRQ descriptor */
4149 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4150 /* release the CPU mask memory */
4151 free_cpumask_var(q_vector->affinity_mask);
4152 }
4153
4154 /* disable transmits in the hardware now that interrupts are off */
4155 for (i = 0; i < adapter->num_tx_queues; i++) {
4156 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4157 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4158 }
4159
4160 /* Disable the Tx DMA engine on 82599 and X540 */
4161 switch (hw->mac.type) {
4162 case ixgbe_mac_82599EB:
4163 case ixgbe_mac_X540:
4164 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4165 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4166 ~IXGBE_DMATXCTL_TE));
4167 break;
4168 default:
4169 break;
4170 }
4171
4172 if (!pci_channel_offline(adapter->pdev))
4173 ixgbe_reset(adapter);
4174
4175 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4176 if (hw->mac.ops.disable_tx_laser &&
4177 ((hw->phy.multispeed_fiber) ||
4178 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4179 (hw->mac.type == ixgbe_mac_82599EB))))
4180 hw->mac.ops.disable_tx_laser(hw);
4181
4182 ixgbe_clean_all_tx_rings(adapter);
4183 ixgbe_clean_all_rx_rings(adapter);
4184
4185 #ifdef CONFIG_IXGBE_DCA
4186 /* since we reset the hardware DCA settings were cleared */
4187 ixgbe_setup_dca(adapter);
4188 #endif
4189 }
4190
4191 /**
4192 * ixgbe_poll - NAPI Rx polling callback
4193 * @napi: structure for representing this polling device
4194 * @budget: how many packets driver is allowed to clean
4195 *
4196 * This function is used for legacy and MSI, NAPI mode
4197 **/
4198 static int ixgbe_poll(struct napi_struct *napi, int budget)
4199 {
4200 struct ixgbe_q_vector *q_vector =
4201 container_of(napi, struct ixgbe_q_vector, napi);
4202 struct ixgbe_adapter *adapter = q_vector->adapter;
4203 int tx_clean_complete, work_done = 0;
4204
4205 #ifdef CONFIG_IXGBE_DCA
4206 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4207 ixgbe_update_dca(q_vector);
4208 #endif
4209
4210 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4211 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4212
4213 if (!tx_clean_complete)
4214 work_done = budget;
4215
4216 /* If budget not fully consumed, exit the polling mode */
4217 if (work_done < budget) {
4218 napi_complete(napi);
4219 if (adapter->rx_itr_setting & 1)
4220 ixgbe_set_itr(q_vector);
4221 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4222 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4223 }
4224 return work_done;
4225 }
4226
4227 /**
4228 * ixgbe_tx_timeout - Respond to a Tx Hang
4229 * @netdev: network interface device structure
4230 **/
4231 static void ixgbe_tx_timeout(struct net_device *netdev)
4232 {
4233 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4234
4235 /* Do the reset outside of interrupt context */
4236 ixgbe_tx_timeout_reset(adapter);
4237 }
4238
4239 /**
4240 * ixgbe_set_rss_queues: Allocate queues for RSS
4241 * @adapter: board private structure to initialize
4242 *
4243 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4244 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4245 *
4246 **/
4247 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4248 {
4249 bool ret = false;
4250 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4251
4252 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4253 f->mask = 0xF;
4254 adapter->num_rx_queues = f->indices;
4255 adapter->num_tx_queues = f->indices;
4256 ret = true;
4257 } else {
4258 ret = false;
4259 }
4260
4261 return ret;
4262 }
4263
4264 /**
4265 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4266 * @adapter: board private structure to initialize
4267 *
4268 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4269 * to the original CPU that initiated the Tx session. This runs in addition
4270 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4271 * Rx load across CPUs using RSS.
4272 *
4273 **/
4274 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4275 {
4276 bool ret = false;
4277 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4278
4279 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4280 f_fdir->mask = 0;
4281
4282 /* Flow Director must have RSS enabled */
4283 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4284 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4285 adapter->num_tx_queues = f_fdir->indices;
4286 adapter->num_rx_queues = f_fdir->indices;
4287 ret = true;
4288 } else {
4289 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4290 }
4291 return ret;
4292 }
4293
4294 #ifdef IXGBE_FCOE
4295 /**
4296 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4297 * @adapter: board private structure to initialize
4298 *
4299 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4300 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4301 * rx queues out of the max number of rx queues, instead, it is used as the
4302 * index of the first rx queue used by FCoE.
4303 *
4304 **/
4305 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4306 {
4307 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4308
4309 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4310 return false;
4311
4312 f->indices = min((int)num_online_cpus(), f->indices);
4313
4314 adapter->num_rx_queues = 1;
4315 adapter->num_tx_queues = 1;
4316
4317 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4318 e_info(probe, "FCoE enabled with RSS\n");
4319 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4320 ixgbe_set_fdir_queues(adapter);
4321 else
4322 ixgbe_set_rss_queues(adapter);
4323 }
4324
4325 /* adding FCoE rx rings to the end */
4326 f->mask = adapter->num_rx_queues;
4327 adapter->num_rx_queues += f->indices;
4328 adapter->num_tx_queues += f->indices;
4329
4330 return true;
4331 }
4332 #endif /* IXGBE_FCOE */
4333
4334 /* Artificial max queue cap per traffic class in DCB mode */
4335 #define DCB_QUEUE_CAP 8
4336
4337 #ifdef CONFIG_IXGBE_DCB
4338 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4339 {
4340 int per_tc_q, q, i, offset = 0;
4341 struct net_device *dev = adapter->netdev;
4342 int tcs = netdev_get_num_tc(dev);
4343
4344 if (!tcs)
4345 return false;
4346
4347 /* Map queue offset and counts onto allocated tx queues */
4348 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4349 q = min((int)num_online_cpus(), per_tc_q);
4350
4351 for (i = 0; i < tcs; i++) {
4352 netdev_set_prio_tc_map(dev, i, i);
4353 netdev_set_tc_queue(dev, i, q, offset);
4354 offset += q;
4355 }
4356
4357 adapter->num_tx_queues = q * tcs;
4358 adapter->num_rx_queues = q * tcs;
4359
4360 #ifdef IXGBE_FCOE
4361 /* FCoE enabled queues require special configuration indexed
4362 * by feature specific indices and mask. Here we map FCoE
4363 * indices onto the DCB queue pairs allowing FCoE to own
4364 * configuration later.
4365 */
4366 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4367 int tc;
4368 struct ixgbe_ring_feature *f =
4369 &adapter->ring_feature[RING_F_FCOE];
4370
4371 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4372 f->indices = dev->tc_to_txq[tc].count;
4373 f->mask = dev->tc_to_txq[tc].offset;
4374 }
4375 #endif
4376
4377 return true;
4378 }
4379 #endif
4380
4381 /**
4382 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4383 * @adapter: board private structure to initialize
4384 *
4385 * IOV doesn't actually use anything, so just NAK the
4386 * request for now and let the other queue routines
4387 * figure out what to do.
4388 */
4389 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4390 {
4391 return false;
4392 }
4393
4394 /*
4395 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4396 * @adapter: board private structure to initialize
4397 *
4398 * This is the top level queue allocation routine. The order here is very
4399 * important, starting with the "most" number of features turned on at once,
4400 * and ending with the smallest set of features. This way large combinations
4401 * can be allocated if they're turned on, and smaller combinations are the
4402 * fallthrough conditions.
4403 *
4404 **/
4405 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4406 {
4407 /* Start with base case */
4408 adapter->num_rx_queues = 1;
4409 adapter->num_tx_queues = 1;
4410 adapter->num_rx_pools = adapter->num_rx_queues;
4411 adapter->num_rx_queues_per_pool = 1;
4412
4413 if (ixgbe_set_sriov_queues(adapter))
4414 goto done;
4415
4416 #ifdef CONFIG_IXGBE_DCB
4417 if (ixgbe_set_dcb_queues(adapter))
4418 goto done;
4419
4420 #endif
4421 #ifdef IXGBE_FCOE
4422 if (ixgbe_set_fcoe_queues(adapter))
4423 goto done;
4424
4425 #endif /* IXGBE_FCOE */
4426 if (ixgbe_set_fdir_queues(adapter))
4427 goto done;
4428
4429 if (ixgbe_set_rss_queues(adapter))
4430 goto done;
4431
4432 /* fallback to base case */
4433 adapter->num_rx_queues = 1;
4434 adapter->num_tx_queues = 1;
4435
4436 done:
4437 /* Notify the stack of the (possibly) reduced queue counts. */
4438 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4439 return netif_set_real_num_rx_queues(adapter->netdev,
4440 adapter->num_rx_queues);
4441 }
4442
4443 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4444 int vectors)
4445 {
4446 int err, vector_threshold;
4447
4448 /* We'll want at least 3 (vector_threshold):
4449 * 1) TxQ[0] Cleanup
4450 * 2) RxQ[0] Cleanup
4451 * 3) Other (Link Status Change, etc.)
4452 * 4) TCP Timer (optional)
4453 */
4454 vector_threshold = MIN_MSIX_COUNT;
4455
4456 /* The more we get, the more we will assign to Tx/Rx Cleanup
4457 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4458 * Right now, we simply care about how many we'll get; we'll
4459 * set them up later while requesting irq's.
4460 */
4461 while (vectors >= vector_threshold) {
4462 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4463 vectors);
4464 if (!err) /* Success in acquiring all requested vectors. */
4465 break;
4466 else if (err < 0)
4467 vectors = 0; /* Nasty failure, quit now */
4468 else /* err == number of vectors we should try again with */
4469 vectors = err;
4470 }
4471
4472 if (vectors < vector_threshold) {
4473 /* Can't allocate enough MSI-X interrupts? Oh well.
4474 * This just means we'll go with either a single MSI
4475 * vector or fall back to legacy interrupts.
4476 */
4477 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4478 "Unable to allocate MSI-X interrupts\n");
4479 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4480 kfree(adapter->msix_entries);
4481 adapter->msix_entries = NULL;
4482 } else {
4483 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4484 /*
4485 * Adjust for only the vectors we'll use, which is minimum
4486 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4487 * vectors we were allocated.
4488 */
4489 adapter->num_msix_vectors = min(vectors,
4490 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4491 }
4492 }
4493
4494 /**
4495 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4496 * @adapter: board private structure to initialize
4497 *
4498 * Cache the descriptor ring offsets for RSS to the assigned rings.
4499 *
4500 **/
4501 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4502 {
4503 int i;
4504
4505 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4506 return false;
4507
4508 for (i = 0; i < adapter->num_rx_queues; i++)
4509 adapter->rx_ring[i]->reg_idx = i;
4510 for (i = 0; i < adapter->num_tx_queues; i++)
4511 adapter->tx_ring[i]->reg_idx = i;
4512
4513 return true;
4514 }
4515
4516 #ifdef CONFIG_IXGBE_DCB
4517
4518 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4519 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4520 unsigned int *tx, unsigned int *rx)
4521 {
4522 struct net_device *dev = adapter->netdev;
4523 struct ixgbe_hw *hw = &adapter->hw;
4524 u8 num_tcs = netdev_get_num_tc(dev);
4525
4526 *tx = 0;
4527 *rx = 0;
4528
4529 switch (hw->mac.type) {
4530 case ixgbe_mac_82598EB:
4531 *tx = tc << 2;
4532 *rx = tc << 3;
4533 break;
4534 case ixgbe_mac_82599EB:
4535 case ixgbe_mac_X540:
4536 if (num_tcs == 8) {
4537 if (tc < 3) {
4538 *tx = tc << 5;
4539 *rx = tc << 4;
4540 } else if (tc < 5) {
4541 *tx = ((tc + 2) << 4);
4542 *rx = tc << 4;
4543 } else if (tc < num_tcs) {
4544 *tx = ((tc + 8) << 3);
4545 *rx = tc << 4;
4546 }
4547 } else if (num_tcs == 4) {
4548 *rx = tc << 5;
4549 switch (tc) {
4550 case 0:
4551 *tx = 0;
4552 break;
4553 case 1:
4554 *tx = 64;
4555 break;
4556 case 2:
4557 *tx = 96;
4558 break;
4559 case 3:
4560 *tx = 112;
4561 break;
4562 default:
4563 break;
4564 }
4565 }
4566 break;
4567 default:
4568 break;
4569 }
4570 }
4571
4572 /**
4573 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4574 * @adapter: board private structure to initialize
4575 *
4576 * Cache the descriptor ring offsets for DCB to the assigned rings.
4577 *
4578 **/
4579 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4580 {
4581 struct net_device *dev = adapter->netdev;
4582 int i, j, k;
4583 u8 num_tcs = netdev_get_num_tc(dev);
4584
4585 if (!num_tcs)
4586 return false;
4587
4588 for (i = 0, k = 0; i < num_tcs; i++) {
4589 unsigned int tx_s, rx_s;
4590 u16 count = dev->tc_to_txq[i].count;
4591
4592 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4593 for (j = 0; j < count; j++, k++) {
4594 adapter->tx_ring[k]->reg_idx = tx_s + j;
4595 adapter->rx_ring[k]->reg_idx = rx_s + j;
4596 adapter->tx_ring[k]->dcb_tc = i;
4597 adapter->rx_ring[k]->dcb_tc = i;
4598 }
4599 }
4600
4601 return true;
4602 }
4603 #endif
4604
4605 /**
4606 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4607 * @adapter: board private structure to initialize
4608 *
4609 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4610 *
4611 **/
4612 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4613 {
4614 int i;
4615 bool ret = false;
4616
4617 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4618 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4619 for (i = 0; i < adapter->num_rx_queues; i++)
4620 adapter->rx_ring[i]->reg_idx = i;
4621 for (i = 0; i < adapter->num_tx_queues; i++)
4622 adapter->tx_ring[i]->reg_idx = i;
4623 ret = true;
4624 }
4625
4626 return ret;
4627 }
4628
4629 #ifdef IXGBE_FCOE
4630 /**
4631 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4632 * @adapter: board private structure to initialize
4633 *
4634 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4635 *
4636 */
4637 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4638 {
4639 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4640 int i;
4641 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4642
4643 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4644 return false;
4645
4646 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4647 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4648 ixgbe_cache_ring_fdir(adapter);
4649 else
4650 ixgbe_cache_ring_rss(adapter);
4651
4652 fcoe_rx_i = f->mask;
4653 fcoe_tx_i = f->mask;
4654 }
4655 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4656 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4657 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4658 }
4659 return true;
4660 }
4661
4662 #endif /* IXGBE_FCOE */
4663 /**
4664 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4665 * @adapter: board private structure to initialize
4666 *
4667 * SR-IOV doesn't use any descriptor rings but changes the default if
4668 * no other mapping is used.
4669 *
4670 */
4671 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4672 {
4673 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4674 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4675 if (adapter->num_vfs)
4676 return true;
4677 else
4678 return false;
4679 }
4680
4681 /**
4682 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4683 * @adapter: board private structure to initialize
4684 *
4685 * Once we know the feature-set enabled for the device, we'll cache
4686 * the register offset the descriptor ring is assigned to.
4687 *
4688 * Note, the order the various feature calls is important. It must start with
4689 * the "most" features enabled at the same time, then trickle down to the
4690 * least amount of features turned on at once.
4691 **/
4692 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4693 {
4694 /* start with default case */
4695 adapter->rx_ring[0]->reg_idx = 0;
4696 adapter->tx_ring[0]->reg_idx = 0;
4697
4698 if (ixgbe_cache_ring_sriov(adapter))
4699 return;
4700
4701 #ifdef CONFIG_IXGBE_DCB
4702 if (ixgbe_cache_ring_dcb(adapter))
4703 return;
4704 #endif
4705
4706 #ifdef IXGBE_FCOE
4707 if (ixgbe_cache_ring_fcoe(adapter))
4708 return;
4709 #endif /* IXGBE_FCOE */
4710
4711 if (ixgbe_cache_ring_fdir(adapter))
4712 return;
4713
4714 if (ixgbe_cache_ring_rss(adapter))
4715 return;
4716 }
4717
4718 /**
4719 * ixgbe_alloc_queues - Allocate memory for all rings
4720 * @adapter: board private structure to initialize
4721 *
4722 * We allocate one ring per queue at run-time since we don't know the
4723 * number of queues at compile-time. The polling_netdev array is
4724 * intended for Multiqueue, but should work fine with a single queue.
4725 **/
4726 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4727 {
4728 int rx = 0, tx = 0, nid = adapter->node;
4729
4730 if (nid < 0 || !node_online(nid))
4731 nid = first_online_node;
4732
4733 for (; tx < adapter->num_tx_queues; tx++) {
4734 struct ixgbe_ring *ring;
4735
4736 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4737 if (!ring)
4738 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4739 if (!ring)
4740 goto err_allocation;
4741 ring->count = adapter->tx_ring_count;
4742 ring->queue_index = tx;
4743 ring->numa_node = nid;
4744 ring->dev = &adapter->pdev->dev;
4745 ring->netdev = adapter->netdev;
4746
4747 adapter->tx_ring[tx] = ring;
4748 }
4749
4750 for (; rx < adapter->num_rx_queues; rx++) {
4751 struct ixgbe_ring *ring;
4752
4753 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4754 if (!ring)
4755 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4756 if (!ring)
4757 goto err_allocation;
4758 ring->count = adapter->rx_ring_count;
4759 ring->queue_index = rx;
4760 ring->numa_node = nid;
4761 ring->dev = &adapter->pdev->dev;
4762 ring->netdev = adapter->netdev;
4763
4764 adapter->rx_ring[rx] = ring;
4765 }
4766
4767 ixgbe_cache_ring_register(adapter);
4768
4769 return 0;
4770
4771 err_allocation:
4772 while (tx)
4773 kfree(adapter->tx_ring[--tx]);
4774
4775 while (rx)
4776 kfree(adapter->rx_ring[--rx]);
4777 return -ENOMEM;
4778 }
4779
4780 /**
4781 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4782 * @adapter: board private structure to initialize
4783 *
4784 * Attempt to configure the interrupts using the best available
4785 * capabilities of the hardware and the kernel.
4786 **/
4787 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4788 {
4789 struct ixgbe_hw *hw = &adapter->hw;
4790 int err = 0;
4791 int vector, v_budget;
4792
4793 /*
4794 * It's easy to be greedy for MSI-X vectors, but it really
4795 * doesn't do us much good if we have a lot more vectors
4796 * than CPU's. So let's be conservative and only ask for
4797 * (roughly) the same number of vectors as there are CPU's.
4798 */
4799 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4800 (int)num_online_cpus()) + NON_Q_VECTORS;
4801
4802 /*
4803 * At the same time, hardware can only support a maximum of
4804 * hw.mac->max_msix_vectors vectors. With features
4805 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4806 * descriptor queues supported by our device. Thus, we cap it off in
4807 * those rare cases where the cpu count also exceeds our vector limit.
4808 */
4809 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4810
4811 /* A failure in MSI-X entry allocation isn't fatal, but it does
4812 * mean we disable MSI-X capabilities of the adapter. */
4813 adapter->msix_entries = kcalloc(v_budget,
4814 sizeof(struct msix_entry), GFP_KERNEL);
4815 if (adapter->msix_entries) {
4816 for (vector = 0; vector < v_budget; vector++)
4817 adapter->msix_entries[vector].entry = vector;
4818
4819 ixgbe_acquire_msix_vectors(adapter, v_budget);
4820
4821 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4822 goto out;
4823 }
4824
4825 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4826 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4827 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4828 e_err(probe,
4829 "ATR is not supported while multiple "
4830 "queues are disabled. Disabling Flow Director\n");
4831 }
4832 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4833 adapter->atr_sample_rate = 0;
4834 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4835 ixgbe_disable_sriov(adapter);
4836
4837 err = ixgbe_set_num_queues(adapter);
4838 if (err)
4839 return err;
4840
4841 err = pci_enable_msi(adapter->pdev);
4842 if (!err) {
4843 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4844 } else {
4845 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4846 "Unable to allocate MSI interrupt, "
4847 "falling back to legacy. Error: %d\n", err);
4848 /* reset err */
4849 err = 0;
4850 }
4851
4852 out:
4853 return err;
4854 }
4855
4856 /**
4857 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4858 * @adapter: board private structure to initialize
4859 *
4860 * We allocate one q_vector per queue interrupt. If allocation fails we
4861 * return -ENOMEM.
4862 **/
4863 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4864 {
4865 int q_idx, num_q_vectors;
4866 struct ixgbe_q_vector *q_vector;
4867 int (*poll)(struct napi_struct *, int);
4868
4869 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4870 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4871 poll = &ixgbe_clean_rxtx_many;
4872 } else {
4873 num_q_vectors = 1;
4874 poll = &ixgbe_poll;
4875 }
4876
4877 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4878 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4879 GFP_KERNEL, adapter->node);
4880 if (!q_vector)
4881 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4882 GFP_KERNEL);
4883 if (!q_vector)
4884 goto err_out;
4885 q_vector->adapter = adapter;
4886 if (q_vector->tx.count && !q_vector->rx.count)
4887 q_vector->eitr = adapter->tx_eitr_param;
4888 else
4889 q_vector->eitr = adapter->rx_eitr_param;
4890 q_vector->v_idx = q_idx;
4891 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4892 adapter->q_vector[q_idx] = q_vector;
4893 }
4894
4895 return 0;
4896
4897 err_out:
4898 while (q_idx) {
4899 q_idx--;
4900 q_vector = adapter->q_vector[q_idx];
4901 netif_napi_del(&q_vector->napi);
4902 kfree(q_vector);
4903 adapter->q_vector[q_idx] = NULL;
4904 }
4905 return -ENOMEM;
4906 }
4907
4908 /**
4909 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4910 * @adapter: board private structure to initialize
4911 *
4912 * This function frees the memory allocated to the q_vectors. In addition if
4913 * NAPI is enabled it will delete any references to the NAPI struct prior
4914 * to freeing the q_vector.
4915 **/
4916 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4917 {
4918 int q_idx, num_q_vectors;
4919
4920 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4921 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4922 else
4923 num_q_vectors = 1;
4924
4925 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4926 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4927 adapter->q_vector[q_idx] = NULL;
4928 netif_napi_del(&q_vector->napi);
4929 kfree(q_vector);
4930 }
4931 }
4932
4933 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4934 {
4935 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4936 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4937 pci_disable_msix(adapter->pdev);
4938 kfree(adapter->msix_entries);
4939 adapter->msix_entries = NULL;
4940 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4941 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4942 pci_disable_msi(adapter->pdev);
4943 }
4944 }
4945
4946 /**
4947 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4948 * @adapter: board private structure to initialize
4949 *
4950 * We determine which interrupt scheme to use based on...
4951 * - Kernel support (MSI, MSI-X)
4952 * - which can be user-defined (via MODULE_PARAM)
4953 * - Hardware queue count (num_*_queues)
4954 * - defined by miscellaneous hardware support/features (RSS, etc.)
4955 **/
4956 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4957 {
4958 int err;
4959
4960 /* Number of supported queues */
4961 err = ixgbe_set_num_queues(adapter);
4962 if (err)
4963 return err;
4964
4965 err = ixgbe_set_interrupt_capability(adapter);
4966 if (err) {
4967 e_dev_err("Unable to setup interrupt capabilities\n");
4968 goto err_set_interrupt;
4969 }
4970
4971 err = ixgbe_alloc_q_vectors(adapter);
4972 if (err) {
4973 e_dev_err("Unable to allocate memory for queue vectors\n");
4974 goto err_alloc_q_vectors;
4975 }
4976
4977 err = ixgbe_alloc_queues(adapter);
4978 if (err) {
4979 e_dev_err("Unable to allocate memory for queues\n");
4980 goto err_alloc_queues;
4981 }
4982
4983 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4984 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4985 adapter->num_rx_queues, adapter->num_tx_queues);
4986
4987 set_bit(__IXGBE_DOWN, &adapter->state);
4988
4989 return 0;
4990
4991 err_alloc_queues:
4992 ixgbe_free_q_vectors(adapter);
4993 err_alloc_q_vectors:
4994 ixgbe_reset_interrupt_capability(adapter);
4995 err_set_interrupt:
4996 return err;
4997 }
4998
4999 /**
5000 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5001 * @adapter: board private structure to clear interrupt scheme on
5002 *
5003 * We go through and clear interrupt specific resources and reset the structure
5004 * to pre-load conditions
5005 **/
5006 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5007 {
5008 int i;
5009
5010 for (i = 0; i < adapter->num_tx_queues; i++) {
5011 kfree(adapter->tx_ring[i]);
5012 adapter->tx_ring[i] = NULL;
5013 }
5014 for (i = 0; i < adapter->num_rx_queues; i++) {
5015 struct ixgbe_ring *ring = adapter->rx_ring[i];
5016
5017 /* ixgbe_get_stats64() might access this ring, we must wait
5018 * a grace period before freeing it.
5019 */
5020 kfree_rcu(ring, rcu);
5021 adapter->rx_ring[i] = NULL;
5022 }
5023
5024 adapter->num_tx_queues = 0;
5025 adapter->num_rx_queues = 0;
5026
5027 ixgbe_free_q_vectors(adapter);
5028 ixgbe_reset_interrupt_capability(adapter);
5029 }
5030
5031 /**
5032 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5033 * @adapter: board private structure to initialize
5034 *
5035 * ixgbe_sw_init initializes the Adapter private data structure.
5036 * Fields are initialized based on PCI device information and
5037 * OS network device settings (MTU size).
5038 **/
5039 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5040 {
5041 struct ixgbe_hw *hw = &adapter->hw;
5042 struct pci_dev *pdev = adapter->pdev;
5043 struct net_device *dev = adapter->netdev;
5044 unsigned int rss;
5045 #ifdef CONFIG_IXGBE_DCB
5046 int j;
5047 struct tc_configuration *tc;
5048 #endif
5049 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5050
5051 /* PCI config space info */
5052
5053 hw->vendor_id = pdev->vendor;
5054 hw->device_id = pdev->device;
5055 hw->revision_id = pdev->revision;
5056 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5057 hw->subsystem_device_id = pdev->subsystem_device;
5058
5059 /* Set capability flags */
5060 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5061 adapter->ring_feature[RING_F_RSS].indices = rss;
5062 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5063 switch (hw->mac.type) {
5064 case ixgbe_mac_82598EB:
5065 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5066 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5067 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5068 break;
5069 case ixgbe_mac_82599EB:
5070 case ixgbe_mac_X540:
5071 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5072 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5073 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5074 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5075 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5076 /* Flow Director hash filters enabled */
5077 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5078 adapter->atr_sample_rate = 20;
5079 adapter->ring_feature[RING_F_FDIR].indices =
5080 IXGBE_MAX_FDIR_INDICES;
5081 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5082 #ifdef IXGBE_FCOE
5083 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5084 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5085 adapter->ring_feature[RING_F_FCOE].indices = 0;
5086 #ifdef CONFIG_IXGBE_DCB
5087 /* Default traffic class to use for FCoE */
5088 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5089 #endif
5090 #endif /* IXGBE_FCOE */
5091 break;
5092 default:
5093 break;
5094 }
5095
5096 /* n-tuple support exists, always init our spinlock */
5097 spin_lock_init(&adapter->fdir_perfect_lock);
5098
5099 #ifdef CONFIG_IXGBE_DCB
5100 /* Configure DCB traffic classes */
5101 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5102 tc = &adapter->dcb_cfg.tc_config[j];
5103 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5104 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5105 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5106 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5107 tc->dcb_pfc = pfc_disabled;
5108 }
5109 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5110 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5111 adapter->dcb_cfg.pfc_mode_enable = false;
5112 adapter->dcb_set_bitmap = 0x00;
5113 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5114 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5115 MAX_TRAFFIC_CLASS);
5116
5117 #endif
5118
5119 /* default flow control settings */
5120 hw->fc.requested_mode = ixgbe_fc_full;
5121 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5122 #ifdef CONFIG_DCB
5123 adapter->last_lfc_mode = hw->fc.current_mode;
5124 #endif
5125 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5126 hw->fc.low_water = FC_LOW_WATER(max_frame);
5127 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5128 hw->fc.send_xon = true;
5129 hw->fc.disable_fc_autoneg = false;
5130
5131 /* enable itr by default in dynamic mode */
5132 adapter->rx_itr_setting = 1;
5133 adapter->rx_eitr_param = 20000;
5134 adapter->tx_itr_setting = 1;
5135 adapter->tx_eitr_param = 10000;
5136
5137 /* set defaults for eitr in MegaBytes */
5138 adapter->eitr_low = 10;
5139 adapter->eitr_high = 20;
5140
5141 /* set default ring sizes */
5142 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5143 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5144
5145 /* set default work limits */
5146 adapter->tx_work_limit = adapter->tx_ring_count;
5147
5148 /* initialize eeprom parameters */
5149 if (ixgbe_init_eeprom_params_generic(hw)) {
5150 e_dev_err("EEPROM initialization failed\n");
5151 return -EIO;
5152 }
5153
5154 /* enable rx csum by default */
5155 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5156
5157 /* get assigned NUMA node */
5158 adapter->node = dev_to_node(&pdev->dev);
5159
5160 set_bit(__IXGBE_DOWN, &adapter->state);
5161
5162 return 0;
5163 }
5164
5165 /**
5166 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5167 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5168 *
5169 * Return 0 on success, negative on failure
5170 **/
5171 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5172 {
5173 struct device *dev = tx_ring->dev;
5174 int size;
5175
5176 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5177 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5178 if (!tx_ring->tx_buffer_info)
5179 tx_ring->tx_buffer_info = vzalloc(size);
5180 if (!tx_ring->tx_buffer_info)
5181 goto err;
5182
5183 /* round up to nearest 4K */
5184 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5185 tx_ring->size = ALIGN(tx_ring->size, 4096);
5186
5187 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5188 &tx_ring->dma, GFP_KERNEL);
5189 if (!tx_ring->desc)
5190 goto err;
5191
5192 tx_ring->next_to_use = 0;
5193 tx_ring->next_to_clean = 0;
5194 return 0;
5195
5196 err:
5197 vfree(tx_ring->tx_buffer_info);
5198 tx_ring->tx_buffer_info = NULL;
5199 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5200 return -ENOMEM;
5201 }
5202
5203 /**
5204 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5205 * @adapter: board private structure
5206 *
5207 * If this function returns with an error, then it's possible one or
5208 * more of the rings is populated (while the rest are not). It is the
5209 * callers duty to clean those orphaned rings.
5210 *
5211 * Return 0 on success, negative on failure
5212 **/
5213 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5214 {
5215 int i, err = 0;
5216
5217 for (i = 0; i < adapter->num_tx_queues; i++) {
5218 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5219 if (!err)
5220 continue;
5221 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5222 break;
5223 }
5224
5225 return err;
5226 }
5227
5228 /**
5229 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5230 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5231 *
5232 * Returns 0 on success, negative on failure
5233 **/
5234 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5235 {
5236 struct device *dev = rx_ring->dev;
5237 int size;
5238
5239 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5240 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5241 if (!rx_ring->rx_buffer_info)
5242 rx_ring->rx_buffer_info = vzalloc(size);
5243 if (!rx_ring->rx_buffer_info)
5244 goto err;
5245
5246 /* Round up to nearest 4K */
5247 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5248 rx_ring->size = ALIGN(rx_ring->size, 4096);
5249
5250 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5251 &rx_ring->dma, GFP_KERNEL);
5252
5253 if (!rx_ring->desc)
5254 goto err;
5255
5256 rx_ring->next_to_clean = 0;
5257 rx_ring->next_to_use = 0;
5258
5259 return 0;
5260 err:
5261 vfree(rx_ring->rx_buffer_info);
5262 rx_ring->rx_buffer_info = NULL;
5263 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5264 return -ENOMEM;
5265 }
5266
5267 /**
5268 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5269 * @adapter: board private structure
5270 *
5271 * If this function returns with an error, then it's possible one or
5272 * more of the rings is populated (while the rest are not). It is the
5273 * callers duty to clean those orphaned rings.
5274 *
5275 * Return 0 on success, negative on failure
5276 **/
5277 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5278 {
5279 int i, err = 0;
5280
5281 for (i = 0; i < adapter->num_rx_queues; i++) {
5282 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5283 if (!err)
5284 continue;
5285 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5286 break;
5287 }
5288
5289 return err;
5290 }
5291
5292 /**
5293 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5294 * @tx_ring: Tx descriptor ring for a specific queue
5295 *
5296 * Free all transmit software resources
5297 **/
5298 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5299 {
5300 ixgbe_clean_tx_ring(tx_ring);
5301
5302 vfree(tx_ring->tx_buffer_info);
5303 tx_ring->tx_buffer_info = NULL;
5304
5305 /* if not set, then don't free */
5306 if (!tx_ring->desc)
5307 return;
5308
5309 dma_free_coherent(tx_ring->dev, tx_ring->size,
5310 tx_ring->desc, tx_ring->dma);
5311
5312 tx_ring->desc = NULL;
5313 }
5314
5315 /**
5316 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5317 * @adapter: board private structure
5318 *
5319 * Free all transmit software resources
5320 **/
5321 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5322 {
5323 int i;
5324
5325 for (i = 0; i < adapter->num_tx_queues; i++)
5326 if (adapter->tx_ring[i]->desc)
5327 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5328 }
5329
5330 /**
5331 * ixgbe_free_rx_resources - Free Rx Resources
5332 * @rx_ring: ring to clean the resources from
5333 *
5334 * Free all receive software resources
5335 **/
5336 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5337 {
5338 ixgbe_clean_rx_ring(rx_ring);
5339
5340 vfree(rx_ring->rx_buffer_info);
5341 rx_ring->rx_buffer_info = NULL;
5342
5343 /* if not set, then don't free */
5344 if (!rx_ring->desc)
5345 return;
5346
5347 dma_free_coherent(rx_ring->dev, rx_ring->size,
5348 rx_ring->desc, rx_ring->dma);
5349
5350 rx_ring->desc = NULL;
5351 }
5352
5353 /**
5354 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5355 * @adapter: board private structure
5356 *
5357 * Free all receive software resources
5358 **/
5359 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5360 {
5361 int i;
5362
5363 for (i = 0; i < adapter->num_rx_queues; i++)
5364 if (adapter->rx_ring[i]->desc)
5365 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5366 }
5367
5368 /**
5369 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5370 * @netdev: network interface device structure
5371 * @new_mtu: new value for maximum frame size
5372 *
5373 * Returns 0 on success, negative on failure
5374 **/
5375 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5376 {
5377 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5378 struct ixgbe_hw *hw = &adapter->hw;
5379 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5380
5381 /* MTU < 68 is an error and causes problems on some kernels */
5382 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5383 hw->mac.type != ixgbe_mac_X540) {
5384 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5385 return -EINVAL;
5386 } else {
5387 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5388 return -EINVAL;
5389 }
5390
5391 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5392 /* must set new MTU before calling down or up */
5393 netdev->mtu = new_mtu;
5394
5395 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5396 hw->fc.low_water = FC_LOW_WATER(max_frame);
5397
5398 if (netif_running(netdev))
5399 ixgbe_reinit_locked(adapter);
5400
5401 return 0;
5402 }
5403
5404 /**
5405 * ixgbe_open - Called when a network interface is made active
5406 * @netdev: network interface device structure
5407 *
5408 * Returns 0 on success, negative value on failure
5409 *
5410 * The open entry point is called when a network interface is made
5411 * active by the system (IFF_UP). At this point all resources needed
5412 * for transmit and receive operations are allocated, the interrupt
5413 * handler is registered with the OS, the watchdog timer is started,
5414 * and the stack is notified that the interface is ready.
5415 **/
5416 static int ixgbe_open(struct net_device *netdev)
5417 {
5418 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5419 int err;
5420
5421 /* disallow open during test */
5422 if (test_bit(__IXGBE_TESTING, &adapter->state))
5423 return -EBUSY;
5424
5425 netif_carrier_off(netdev);
5426
5427 /* allocate transmit descriptors */
5428 err = ixgbe_setup_all_tx_resources(adapter);
5429 if (err)
5430 goto err_setup_tx;
5431
5432 /* allocate receive descriptors */
5433 err = ixgbe_setup_all_rx_resources(adapter);
5434 if (err)
5435 goto err_setup_rx;
5436
5437 ixgbe_configure(adapter);
5438
5439 err = ixgbe_request_irq(adapter);
5440 if (err)
5441 goto err_req_irq;
5442
5443 err = ixgbe_up_complete(adapter);
5444 if (err)
5445 goto err_up;
5446
5447 netif_tx_start_all_queues(netdev);
5448
5449 return 0;
5450
5451 err_up:
5452 ixgbe_release_hw_control(adapter);
5453 ixgbe_free_irq(adapter);
5454 err_req_irq:
5455 err_setup_rx:
5456 ixgbe_free_all_rx_resources(adapter);
5457 err_setup_tx:
5458 ixgbe_free_all_tx_resources(adapter);
5459 ixgbe_reset(adapter);
5460
5461 return err;
5462 }
5463
5464 /**
5465 * ixgbe_close - Disables a network interface
5466 * @netdev: network interface device structure
5467 *
5468 * Returns 0, this is not allowed to fail
5469 *
5470 * The close entry point is called when an interface is de-activated
5471 * by the OS. The hardware is still under the drivers control, but
5472 * needs to be disabled. A global MAC reset is issued to stop the
5473 * hardware, and all transmit and receive resources are freed.
5474 **/
5475 static int ixgbe_close(struct net_device *netdev)
5476 {
5477 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5478
5479 ixgbe_down(adapter);
5480 ixgbe_free_irq(adapter);
5481
5482 ixgbe_fdir_filter_exit(adapter);
5483
5484 ixgbe_free_all_tx_resources(adapter);
5485 ixgbe_free_all_rx_resources(adapter);
5486
5487 ixgbe_release_hw_control(adapter);
5488
5489 return 0;
5490 }
5491
5492 #ifdef CONFIG_PM
5493 static int ixgbe_resume(struct pci_dev *pdev)
5494 {
5495 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5496 struct net_device *netdev = adapter->netdev;
5497 u32 err;
5498
5499 pci_set_power_state(pdev, PCI_D0);
5500 pci_restore_state(pdev);
5501 /*
5502 * pci_restore_state clears dev->state_saved so call
5503 * pci_save_state to restore it.
5504 */
5505 pci_save_state(pdev);
5506
5507 err = pci_enable_device_mem(pdev);
5508 if (err) {
5509 e_dev_err("Cannot enable PCI device from suspend\n");
5510 return err;
5511 }
5512 pci_set_master(pdev);
5513
5514 pci_wake_from_d3(pdev, false);
5515
5516 err = ixgbe_init_interrupt_scheme(adapter);
5517 if (err) {
5518 e_dev_err("Cannot initialize interrupts for device\n");
5519 return err;
5520 }
5521
5522 ixgbe_reset(adapter);
5523
5524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5525
5526 if (netif_running(netdev)) {
5527 err = ixgbe_open(netdev);
5528 if (err)
5529 return err;
5530 }
5531
5532 netif_device_attach(netdev);
5533
5534 return 0;
5535 }
5536 #endif /* CONFIG_PM */
5537
5538 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5539 {
5540 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5541 struct net_device *netdev = adapter->netdev;
5542 struct ixgbe_hw *hw = &adapter->hw;
5543 u32 ctrl, fctrl;
5544 u32 wufc = adapter->wol;
5545 #ifdef CONFIG_PM
5546 int retval = 0;
5547 #endif
5548
5549 netif_device_detach(netdev);
5550
5551 if (netif_running(netdev)) {
5552 ixgbe_down(adapter);
5553 ixgbe_free_irq(adapter);
5554 ixgbe_free_all_tx_resources(adapter);
5555 ixgbe_free_all_rx_resources(adapter);
5556 }
5557
5558 ixgbe_clear_interrupt_scheme(adapter);
5559 #ifdef CONFIG_DCB
5560 kfree(adapter->ixgbe_ieee_pfc);
5561 kfree(adapter->ixgbe_ieee_ets);
5562 #endif
5563
5564 #ifdef CONFIG_PM
5565 retval = pci_save_state(pdev);
5566 if (retval)
5567 return retval;
5568
5569 #endif
5570 if (wufc) {
5571 ixgbe_set_rx_mode(netdev);
5572
5573 /* turn on all-multi mode if wake on multicast is enabled */
5574 if (wufc & IXGBE_WUFC_MC) {
5575 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5576 fctrl |= IXGBE_FCTRL_MPE;
5577 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5578 }
5579
5580 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5581 ctrl |= IXGBE_CTRL_GIO_DIS;
5582 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5583
5584 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5585 } else {
5586 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5587 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5588 }
5589
5590 switch (hw->mac.type) {
5591 case ixgbe_mac_82598EB:
5592 pci_wake_from_d3(pdev, false);
5593 break;
5594 case ixgbe_mac_82599EB:
5595 case ixgbe_mac_X540:
5596 pci_wake_from_d3(pdev, !!wufc);
5597 break;
5598 default:
5599 break;
5600 }
5601
5602 *enable_wake = !!wufc;
5603
5604 ixgbe_release_hw_control(adapter);
5605
5606 pci_disable_device(pdev);
5607
5608 return 0;
5609 }
5610
5611 #ifdef CONFIG_PM
5612 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5613 {
5614 int retval;
5615 bool wake;
5616
5617 retval = __ixgbe_shutdown(pdev, &wake);
5618 if (retval)
5619 return retval;
5620
5621 if (wake) {
5622 pci_prepare_to_sleep(pdev);
5623 } else {
5624 pci_wake_from_d3(pdev, false);
5625 pci_set_power_state(pdev, PCI_D3hot);
5626 }
5627
5628 return 0;
5629 }
5630 #endif /* CONFIG_PM */
5631
5632 static void ixgbe_shutdown(struct pci_dev *pdev)
5633 {
5634 bool wake;
5635
5636 __ixgbe_shutdown(pdev, &wake);
5637
5638 if (system_state == SYSTEM_POWER_OFF) {
5639 pci_wake_from_d3(pdev, wake);
5640 pci_set_power_state(pdev, PCI_D3hot);
5641 }
5642 }
5643
5644 /**
5645 * ixgbe_update_stats - Update the board statistics counters.
5646 * @adapter: board private structure
5647 **/
5648 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5649 {
5650 struct net_device *netdev = adapter->netdev;
5651 struct ixgbe_hw *hw = &adapter->hw;
5652 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5653 u64 total_mpc = 0;
5654 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5655 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5656 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5657 u64 bytes = 0, packets = 0;
5658
5659 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5660 test_bit(__IXGBE_RESETTING, &adapter->state))
5661 return;
5662
5663 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5664 u64 rsc_count = 0;
5665 u64 rsc_flush = 0;
5666 for (i = 0; i < 16; i++)
5667 adapter->hw_rx_no_dma_resources +=
5668 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5669 for (i = 0; i < adapter->num_rx_queues; i++) {
5670 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5671 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5672 }
5673 adapter->rsc_total_count = rsc_count;
5674 adapter->rsc_total_flush = rsc_flush;
5675 }
5676
5677 for (i = 0; i < adapter->num_rx_queues; i++) {
5678 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5679 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5680 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5681 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5682 bytes += rx_ring->stats.bytes;
5683 packets += rx_ring->stats.packets;
5684 }
5685 adapter->non_eop_descs = non_eop_descs;
5686 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5687 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5688 netdev->stats.rx_bytes = bytes;
5689 netdev->stats.rx_packets = packets;
5690
5691 bytes = 0;
5692 packets = 0;
5693 /* gather some stats to the adapter struct that are per queue */
5694 for (i = 0; i < adapter->num_tx_queues; i++) {
5695 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5696 restart_queue += tx_ring->tx_stats.restart_queue;
5697 tx_busy += tx_ring->tx_stats.tx_busy;
5698 bytes += tx_ring->stats.bytes;
5699 packets += tx_ring->stats.packets;
5700 }
5701 adapter->restart_queue = restart_queue;
5702 adapter->tx_busy = tx_busy;
5703 netdev->stats.tx_bytes = bytes;
5704 netdev->stats.tx_packets = packets;
5705
5706 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5707 for (i = 0; i < 8; i++) {
5708 /* for packet buffers not used, the register should read 0 */
5709 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5710 missed_rx += mpc;
5711 hwstats->mpc[i] += mpc;
5712 total_mpc += hwstats->mpc[i];
5713 if (hw->mac.type == ixgbe_mac_82598EB)
5714 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5715 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5716 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5717 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5718 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5719 switch (hw->mac.type) {
5720 case ixgbe_mac_82598EB:
5721 hwstats->pxonrxc[i] +=
5722 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5723 break;
5724 case ixgbe_mac_82599EB:
5725 case ixgbe_mac_X540:
5726 hwstats->pxonrxc[i] +=
5727 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5728 break;
5729 default:
5730 break;
5731 }
5732 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5733 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5734 }
5735 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5736 /* work around hardware counting issue */
5737 hwstats->gprc -= missed_rx;
5738
5739 ixgbe_update_xoff_received(adapter);
5740
5741 /* 82598 hardware only has a 32 bit counter in the high register */
5742 switch (hw->mac.type) {
5743 case ixgbe_mac_82598EB:
5744 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5745 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5746 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5747 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5748 break;
5749 case ixgbe_mac_X540:
5750 /* OS2BMC stats are X540 only*/
5751 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5752 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5753 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5754 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5755 case ixgbe_mac_82599EB:
5756 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5757 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5758 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5759 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5760 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5761 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5762 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5763 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5764 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5765 #ifdef IXGBE_FCOE
5766 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5767 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5768 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5769 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5770 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5771 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5772 #endif /* IXGBE_FCOE */
5773 break;
5774 default:
5775 break;
5776 }
5777 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5778 hwstats->bprc += bprc;
5779 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5780 if (hw->mac.type == ixgbe_mac_82598EB)
5781 hwstats->mprc -= bprc;
5782 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5783 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5784 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5785 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5786 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5787 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5788 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5789 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5790 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5791 hwstats->lxontxc += lxon;
5792 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5793 hwstats->lxofftxc += lxoff;
5794 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5795 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5796 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5797 /*
5798 * 82598 errata - tx of flow control packets is included in tx counters
5799 */
5800 xon_off_tot = lxon + lxoff;
5801 hwstats->gptc -= xon_off_tot;
5802 hwstats->mptc -= xon_off_tot;
5803 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5804 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5805 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5806 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5807 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5808 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5809 hwstats->ptc64 -= xon_off_tot;
5810 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5811 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5812 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5813 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5814 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5815 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5816
5817 /* Fill out the OS statistics structure */
5818 netdev->stats.multicast = hwstats->mprc;
5819
5820 /* Rx Errors */
5821 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5822 netdev->stats.rx_dropped = 0;
5823 netdev->stats.rx_length_errors = hwstats->rlec;
5824 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5825 netdev->stats.rx_missed_errors = total_mpc;
5826 }
5827
5828 /**
5829 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5830 * @adapter - pointer to the device adapter structure
5831 **/
5832 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5833 {
5834 struct ixgbe_hw *hw = &adapter->hw;
5835 int i;
5836
5837 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5838 return;
5839
5840 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5841
5842 /* if interface is down do nothing */
5843 if (test_bit(__IXGBE_DOWN, &adapter->state))
5844 return;
5845
5846 /* do nothing if we are not using signature filters */
5847 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5848 return;
5849
5850 adapter->fdir_overflow++;
5851
5852 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5853 for (i = 0; i < adapter->num_tx_queues; i++)
5854 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5855 &(adapter->tx_ring[i]->state));
5856 /* re-enable flow director interrupts */
5857 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5858 } else {
5859 e_err(probe, "failed to finish FDIR re-initialization, "
5860 "ignored adding FDIR ATR filters\n");
5861 }
5862 }
5863
5864 /**
5865 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5866 * @adapter - pointer to the device adapter structure
5867 *
5868 * This function serves two purposes. First it strobes the interrupt lines
5869 * in order to make certain interrupts are occuring. Secondly it sets the
5870 * bits needed to check for TX hangs. As a result we should immediately
5871 * determine if a hang has occured.
5872 */
5873 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5874 {
5875 struct ixgbe_hw *hw = &adapter->hw;
5876 u64 eics = 0;
5877 int i;
5878
5879 /* If we're down or resetting, just bail */
5880 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5881 test_bit(__IXGBE_RESETTING, &adapter->state))
5882 return;
5883
5884 /* Force detection of hung controller */
5885 if (netif_carrier_ok(adapter->netdev)) {
5886 for (i = 0; i < adapter->num_tx_queues; i++)
5887 set_check_for_tx_hang(adapter->tx_ring[i]);
5888 }
5889
5890 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5891 /*
5892 * for legacy and MSI interrupts don't set any bits
5893 * that are enabled for EIAM, because this operation
5894 * would set *both* EIMS and EICS for any bit in EIAM
5895 */
5896 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5897 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5898 } else {
5899 /* get one bit for every active tx/rx interrupt vector */
5900 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5901 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5902 if (qv->rx.count || qv->tx.count)
5903 eics |= ((u64)1 << i);
5904 }
5905 }
5906
5907 /* Cause software interrupt to ensure rings are cleaned */
5908 ixgbe_irq_rearm_queues(adapter, eics);
5909
5910 }
5911
5912 /**
5913 * ixgbe_watchdog_update_link - update the link status
5914 * @adapter - pointer to the device adapter structure
5915 * @link_speed - pointer to a u32 to store the link_speed
5916 **/
5917 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5918 {
5919 struct ixgbe_hw *hw = &adapter->hw;
5920 u32 link_speed = adapter->link_speed;
5921 bool link_up = adapter->link_up;
5922 int i;
5923
5924 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5925 return;
5926
5927 if (hw->mac.ops.check_link) {
5928 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5929 } else {
5930 /* always assume link is up, if no check link function */
5931 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5932 link_up = true;
5933 }
5934 if (link_up) {
5935 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5936 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5937 hw->mac.ops.fc_enable(hw, i);
5938 } else {
5939 hw->mac.ops.fc_enable(hw, 0);
5940 }
5941 }
5942
5943 if (link_up ||
5944 time_after(jiffies, (adapter->link_check_timeout +
5945 IXGBE_TRY_LINK_TIMEOUT))) {
5946 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5947 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5948 IXGBE_WRITE_FLUSH(hw);
5949 }
5950
5951 adapter->link_up = link_up;
5952 adapter->link_speed = link_speed;
5953 }
5954
5955 /**
5956 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5957 * print link up message
5958 * @adapter - pointer to the device adapter structure
5959 **/
5960 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5961 {
5962 struct net_device *netdev = adapter->netdev;
5963 struct ixgbe_hw *hw = &adapter->hw;
5964 u32 link_speed = adapter->link_speed;
5965 bool flow_rx, flow_tx;
5966
5967 /* only continue if link was previously down */
5968 if (netif_carrier_ok(netdev))
5969 return;
5970
5971 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5972
5973 switch (hw->mac.type) {
5974 case ixgbe_mac_82598EB: {
5975 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5976 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5977 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5978 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5979 }
5980 break;
5981 case ixgbe_mac_X540:
5982 case ixgbe_mac_82599EB: {
5983 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5984 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5985 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5986 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5987 }
5988 break;
5989 default:
5990 flow_tx = false;
5991 flow_rx = false;
5992 break;
5993 }
5994 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5995 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5996 "10 Gbps" :
5997 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5998 "1 Gbps" :
5999 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6000 "100 Mbps" :
6001 "unknown speed"))),
6002 ((flow_rx && flow_tx) ? "RX/TX" :
6003 (flow_rx ? "RX" :
6004 (flow_tx ? "TX" : "None"))));
6005
6006 netif_carrier_on(netdev);
6007 ixgbe_check_vf_rate_limit(adapter);
6008 }
6009
6010 /**
6011 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6012 * print link down message
6013 * @adapter - pointer to the adapter structure
6014 **/
6015 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6016 {
6017 struct net_device *netdev = adapter->netdev;
6018 struct ixgbe_hw *hw = &adapter->hw;
6019
6020 adapter->link_up = false;
6021 adapter->link_speed = 0;
6022
6023 /* only continue if link was up previously */
6024 if (!netif_carrier_ok(netdev))
6025 return;
6026
6027 /* poll for SFP+ cable when link is down */
6028 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6029 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6030
6031 e_info(drv, "NIC Link is Down\n");
6032 netif_carrier_off(netdev);
6033 }
6034
6035 /**
6036 * ixgbe_watchdog_flush_tx - flush queues on link down
6037 * @adapter - pointer to the device adapter structure
6038 **/
6039 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6040 {
6041 int i;
6042 int some_tx_pending = 0;
6043
6044 if (!netif_carrier_ok(adapter->netdev)) {
6045 for (i = 0; i < adapter->num_tx_queues; i++) {
6046 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6047 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6048 some_tx_pending = 1;
6049 break;
6050 }
6051 }
6052
6053 if (some_tx_pending) {
6054 /* We've lost link, so the controller stops DMA,
6055 * but we've got queued Tx work that's never going
6056 * to get done, so reset controller to flush Tx.
6057 * (Do the reset outside of interrupt context).
6058 */
6059 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6060 }
6061 }
6062 }
6063
6064 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6065 {
6066 u32 ssvpc;
6067
6068 /* Do not perform spoof check for 82598 */
6069 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6070 return;
6071
6072 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6073
6074 /*
6075 * ssvpc register is cleared on read, if zero then no
6076 * spoofed packets in the last interval.
6077 */
6078 if (!ssvpc)
6079 return;
6080
6081 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6082 }
6083
6084 /**
6085 * ixgbe_watchdog_subtask - check and bring link up
6086 * @adapter - pointer to the device adapter structure
6087 **/
6088 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6089 {
6090 /* if interface is down do nothing */
6091 if (test_bit(__IXGBE_DOWN, &adapter->state))
6092 return;
6093
6094 ixgbe_watchdog_update_link(adapter);
6095
6096 if (adapter->link_up)
6097 ixgbe_watchdog_link_is_up(adapter);
6098 else
6099 ixgbe_watchdog_link_is_down(adapter);
6100
6101 ixgbe_spoof_check(adapter);
6102 ixgbe_update_stats(adapter);
6103
6104 ixgbe_watchdog_flush_tx(adapter);
6105 }
6106
6107 /**
6108 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6109 * @adapter - the ixgbe adapter structure
6110 **/
6111 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6112 {
6113 struct ixgbe_hw *hw = &adapter->hw;
6114 s32 err;
6115
6116 /* not searching for SFP so there is nothing to do here */
6117 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6118 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6119 return;
6120
6121 /* someone else is in init, wait until next service event */
6122 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6123 return;
6124
6125 err = hw->phy.ops.identify_sfp(hw);
6126 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6127 goto sfp_out;
6128
6129 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6130 /* If no cable is present, then we need to reset
6131 * the next time we find a good cable. */
6132 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6133 }
6134
6135 /* exit on error */
6136 if (err)
6137 goto sfp_out;
6138
6139 /* exit if reset not needed */
6140 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6141 goto sfp_out;
6142
6143 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6144
6145 /*
6146 * A module may be identified correctly, but the EEPROM may not have
6147 * support for that module. setup_sfp() will fail in that case, so
6148 * we should not allow that module to load.
6149 */
6150 if (hw->mac.type == ixgbe_mac_82598EB)
6151 err = hw->phy.ops.reset(hw);
6152 else
6153 err = hw->mac.ops.setup_sfp(hw);
6154
6155 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6156 goto sfp_out;
6157
6158 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6159 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6160
6161 sfp_out:
6162 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6163
6164 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6165 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6166 e_dev_err("failed to initialize because an unsupported "
6167 "SFP+ module type was detected.\n");
6168 e_dev_err("Reload the driver after installing a "
6169 "supported module.\n");
6170 unregister_netdev(adapter->netdev);
6171 }
6172 }
6173
6174 /**
6175 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6176 * @adapter - the ixgbe adapter structure
6177 **/
6178 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6179 {
6180 struct ixgbe_hw *hw = &adapter->hw;
6181 u32 autoneg;
6182 bool negotiation;
6183
6184 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6185 return;
6186
6187 /* someone else is in init, wait until next service event */
6188 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6189 return;
6190
6191 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6192
6193 autoneg = hw->phy.autoneg_advertised;
6194 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6195 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6196 hw->mac.autotry_restart = false;
6197 if (hw->mac.ops.setup_link)
6198 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6199
6200 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6201 adapter->link_check_timeout = jiffies;
6202 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6203 }
6204
6205 /**
6206 * ixgbe_service_timer - Timer Call-back
6207 * @data: pointer to adapter cast into an unsigned long
6208 **/
6209 static void ixgbe_service_timer(unsigned long data)
6210 {
6211 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6212 unsigned long next_event_offset;
6213
6214 /* poll faster when waiting for link */
6215 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6216 next_event_offset = HZ / 10;
6217 else
6218 next_event_offset = HZ * 2;
6219
6220 /* Reset the timer */
6221 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6222
6223 ixgbe_service_event_schedule(adapter);
6224 }
6225
6226 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6227 {
6228 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6229 return;
6230
6231 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6232
6233 /* If we're already down or resetting, just bail */
6234 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6235 test_bit(__IXGBE_RESETTING, &adapter->state))
6236 return;
6237
6238 ixgbe_dump(adapter);
6239 netdev_err(adapter->netdev, "Reset adapter\n");
6240 adapter->tx_timeout_count++;
6241
6242 ixgbe_reinit_locked(adapter);
6243 }
6244
6245 /**
6246 * ixgbe_service_task - manages and runs subtasks
6247 * @work: pointer to work_struct containing our data
6248 **/
6249 static void ixgbe_service_task(struct work_struct *work)
6250 {
6251 struct ixgbe_adapter *adapter = container_of(work,
6252 struct ixgbe_adapter,
6253 service_task);
6254
6255 ixgbe_reset_subtask(adapter);
6256 ixgbe_sfp_detection_subtask(adapter);
6257 ixgbe_sfp_link_config_subtask(adapter);
6258 ixgbe_check_overtemp_subtask(adapter);
6259 ixgbe_watchdog_subtask(adapter);
6260 ixgbe_fdir_reinit_subtask(adapter);
6261 ixgbe_check_hang_subtask(adapter);
6262
6263 ixgbe_service_event_complete(adapter);
6264 }
6265
6266 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6267 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6268 {
6269 struct ixgbe_adv_tx_context_desc *context_desc;
6270 u16 i = tx_ring->next_to_use;
6271
6272 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6273
6274 i++;
6275 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6276
6277 /* set bits to identify this as an advanced context descriptor */
6278 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6279
6280 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6281 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6282 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6283 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6284 }
6285
6286 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6287 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6288 {
6289 int err;
6290 u32 vlan_macip_lens, type_tucmd;
6291 u32 mss_l4len_idx, l4len;
6292
6293 if (!skb_is_gso(skb))
6294 return 0;
6295
6296 if (skb_header_cloned(skb)) {
6297 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6298 if (err)
6299 return err;
6300 }
6301
6302 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6303 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6304
6305 if (protocol == __constant_htons(ETH_P_IP)) {
6306 struct iphdr *iph = ip_hdr(skb);
6307 iph->tot_len = 0;
6308 iph->check = 0;
6309 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6310 iph->daddr, 0,
6311 IPPROTO_TCP,
6312 0);
6313 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6314 } else if (skb_is_gso_v6(skb)) {
6315 ipv6_hdr(skb)->payload_len = 0;
6316 tcp_hdr(skb)->check =
6317 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6318 &ipv6_hdr(skb)->daddr,
6319 0, IPPROTO_TCP, 0);
6320 }
6321
6322 l4len = tcp_hdrlen(skb);
6323 *hdr_len = skb_transport_offset(skb) + l4len;
6324
6325 /* mss_l4len_id: use 1 as index for TSO */
6326 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6327 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6328 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6329
6330 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6331 vlan_macip_lens = skb_network_header_len(skb);
6332 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6333 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6334
6335 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6336 mss_l4len_idx);
6337
6338 return 1;
6339 }
6340
6341 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6342 struct sk_buff *skb, u32 tx_flags,
6343 __be16 protocol)
6344 {
6345 u32 vlan_macip_lens = 0;
6346 u32 mss_l4len_idx = 0;
6347 u32 type_tucmd = 0;
6348
6349 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6350 if (!(tx_flags & IXGBE_TX_FLAGS_VLAN))
6351 return false;
6352 } else {
6353 u8 l4_hdr = 0;
6354 switch (protocol) {
6355 case __constant_htons(ETH_P_IP):
6356 vlan_macip_lens |= skb_network_header_len(skb);
6357 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6358 l4_hdr = ip_hdr(skb)->protocol;
6359 break;
6360 case __constant_htons(ETH_P_IPV6):
6361 vlan_macip_lens |= skb_network_header_len(skb);
6362 l4_hdr = ipv6_hdr(skb)->nexthdr;
6363 break;
6364 default:
6365 if (unlikely(net_ratelimit())) {
6366 dev_warn(tx_ring->dev,
6367 "partial checksum but proto=%x!\n",
6368 skb->protocol);
6369 }
6370 break;
6371 }
6372
6373 switch (l4_hdr) {
6374 case IPPROTO_TCP:
6375 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6376 mss_l4len_idx = tcp_hdrlen(skb) <<
6377 IXGBE_ADVTXD_L4LEN_SHIFT;
6378 break;
6379 case IPPROTO_SCTP:
6380 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6381 mss_l4len_idx = sizeof(struct sctphdr) <<
6382 IXGBE_ADVTXD_L4LEN_SHIFT;
6383 break;
6384 case IPPROTO_UDP:
6385 mss_l4len_idx = sizeof(struct udphdr) <<
6386 IXGBE_ADVTXD_L4LEN_SHIFT;
6387 break;
6388 default:
6389 if (unlikely(net_ratelimit())) {
6390 dev_warn(tx_ring->dev,
6391 "partial checksum but l4 proto=%x!\n",
6392 skb->protocol);
6393 }
6394 break;
6395 }
6396 }
6397
6398 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6399 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6400
6401 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6402 type_tucmd, mss_l4len_idx);
6403
6404 return (skb->ip_summed == CHECKSUM_PARTIAL);
6405 }
6406
6407 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6408 struct ixgbe_ring *tx_ring,
6409 struct sk_buff *skb, u32 tx_flags,
6410 unsigned int first, const u8 hdr_len)
6411 {
6412 struct device *dev = tx_ring->dev;
6413 struct ixgbe_tx_buffer *tx_buffer_info;
6414 unsigned int len;
6415 unsigned int total = skb->len;
6416 unsigned int offset = 0, size, count = 0;
6417 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6418 unsigned int f;
6419 unsigned int bytecount = skb->len;
6420 u16 gso_segs = 1;
6421 u16 i;
6422
6423 i = tx_ring->next_to_use;
6424
6425 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6426 /* excluding fcoe_crc_eof for FCoE */
6427 total -= sizeof(struct fcoe_crc_eof);
6428
6429 len = min(skb_headlen(skb), total);
6430 while (len) {
6431 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6432 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6433
6434 tx_buffer_info->length = size;
6435 tx_buffer_info->mapped_as_page = false;
6436 tx_buffer_info->dma = dma_map_single(dev,
6437 skb->data + offset,
6438 size, DMA_TO_DEVICE);
6439 if (dma_mapping_error(dev, tx_buffer_info->dma))
6440 goto dma_error;
6441 tx_buffer_info->time_stamp = jiffies;
6442 tx_buffer_info->next_to_watch = i;
6443
6444 len -= size;
6445 total -= size;
6446 offset += size;
6447 count++;
6448
6449 if (len) {
6450 i++;
6451 if (i == tx_ring->count)
6452 i = 0;
6453 }
6454 }
6455
6456 for (f = 0; f < nr_frags; f++) {
6457 struct skb_frag_struct *frag;
6458
6459 frag = &skb_shinfo(skb)->frags[f];
6460 len = min((unsigned int)frag->size, total);
6461 offset = frag->page_offset;
6462
6463 while (len) {
6464 i++;
6465 if (i == tx_ring->count)
6466 i = 0;
6467
6468 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6469 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6470
6471 tx_buffer_info->length = size;
6472 tx_buffer_info->dma = dma_map_page(dev,
6473 frag->page,
6474 offset, size,
6475 DMA_TO_DEVICE);
6476 tx_buffer_info->mapped_as_page = true;
6477 if (dma_mapping_error(dev, tx_buffer_info->dma))
6478 goto dma_error;
6479 tx_buffer_info->time_stamp = jiffies;
6480 tx_buffer_info->next_to_watch = i;
6481
6482 len -= size;
6483 total -= size;
6484 offset += size;
6485 count++;
6486 }
6487 if (total == 0)
6488 break;
6489 }
6490
6491 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6492 gso_segs = skb_shinfo(skb)->gso_segs;
6493 #ifdef IXGBE_FCOE
6494 /* adjust for FCoE Sequence Offload */
6495 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6496 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6497 skb_shinfo(skb)->gso_size);
6498 #endif /* IXGBE_FCOE */
6499 bytecount += (gso_segs - 1) * hdr_len;
6500
6501 /* multiply data chunks by size of headers */
6502 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6503 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6504 tx_ring->tx_buffer_info[i].skb = skb;
6505 tx_ring->tx_buffer_info[first].next_to_watch = i;
6506
6507 return count;
6508
6509 dma_error:
6510 e_dev_err("TX DMA map failed\n");
6511
6512 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6513 tx_buffer_info->dma = 0;
6514 tx_buffer_info->time_stamp = 0;
6515 tx_buffer_info->next_to_watch = 0;
6516 if (count)
6517 count--;
6518
6519 /* clear timestamp and dma mappings for remaining portion of packet */
6520 while (count--) {
6521 if (i == 0)
6522 i += tx_ring->count;
6523 i--;
6524 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6525 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6526 }
6527
6528 return 0;
6529 }
6530
6531 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6532 int tx_flags, int count, u32 paylen, u8 hdr_len)
6533 {
6534 union ixgbe_adv_tx_desc *tx_desc = NULL;
6535 struct ixgbe_tx_buffer *tx_buffer_info;
6536 u32 olinfo_status = 0, cmd_type_len = 0;
6537 unsigned int i;
6538 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6539
6540 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6541
6542 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6543
6544 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6545 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6546
6547 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6548 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6549
6550 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6551 IXGBE_ADVTXD_POPTS_SHIFT;
6552
6553 /* use index 1 context for tso */
6554 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6555 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6556 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6557 IXGBE_ADVTXD_POPTS_SHIFT;
6558
6559 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6560 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6561 IXGBE_ADVTXD_POPTS_SHIFT;
6562
6563 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6564 olinfo_status |= IXGBE_ADVTXD_CC;
6565 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6566 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6567 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6568 }
6569
6570 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6571
6572 i = tx_ring->next_to_use;
6573 while (count--) {
6574 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6575 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6576 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6577 tx_desc->read.cmd_type_len =
6578 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6579 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6580 i++;
6581 if (i == tx_ring->count)
6582 i = 0;
6583 }
6584
6585 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6586
6587 /*
6588 * Force memory writes to complete before letting h/w
6589 * know there are new descriptors to fetch. (Only
6590 * applicable for weak-ordered memory model archs,
6591 * such as IA-64).
6592 */
6593 wmb();
6594
6595 tx_ring->next_to_use = i;
6596 writel(i, tx_ring->tail);
6597 }
6598
6599 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6600 u32 tx_flags, __be16 protocol)
6601 {
6602 struct ixgbe_q_vector *q_vector = ring->q_vector;
6603 union ixgbe_atr_hash_dword input = { .dword = 0 };
6604 union ixgbe_atr_hash_dword common = { .dword = 0 };
6605 union {
6606 unsigned char *network;
6607 struct iphdr *ipv4;
6608 struct ipv6hdr *ipv6;
6609 } hdr;
6610 struct tcphdr *th;
6611 __be16 vlan_id;
6612
6613 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6614 if (!q_vector)
6615 return;
6616
6617 /* do nothing if sampling is disabled */
6618 if (!ring->atr_sample_rate)
6619 return;
6620
6621 ring->atr_count++;
6622
6623 /* snag network header to get L4 type and address */
6624 hdr.network = skb_network_header(skb);
6625
6626 /* Currently only IPv4/IPv6 with TCP is supported */
6627 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6628 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6629 (protocol != __constant_htons(ETH_P_IP) ||
6630 hdr.ipv4->protocol != IPPROTO_TCP))
6631 return;
6632
6633 th = tcp_hdr(skb);
6634
6635 /* skip this packet since the socket is closing */
6636 if (th->fin)
6637 return;
6638
6639 /* sample on all syn packets or once every atr sample count */
6640 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6641 return;
6642
6643 /* reset sample count */
6644 ring->atr_count = 0;
6645
6646 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6647
6648 /*
6649 * src and dst are inverted, think how the receiver sees them
6650 *
6651 * The input is broken into two sections, a non-compressed section
6652 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6653 * is XORed together and stored in the compressed dword.
6654 */
6655 input.formatted.vlan_id = vlan_id;
6656
6657 /*
6658 * since src port and flex bytes occupy the same word XOR them together
6659 * and write the value to source port portion of compressed dword
6660 */
6661 if (vlan_id)
6662 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6663 else
6664 common.port.src ^= th->dest ^ protocol;
6665 common.port.dst ^= th->source;
6666
6667 if (protocol == __constant_htons(ETH_P_IP)) {
6668 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6669 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6670 } else {
6671 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6672 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6673 hdr.ipv6->saddr.s6_addr32[1] ^
6674 hdr.ipv6->saddr.s6_addr32[2] ^
6675 hdr.ipv6->saddr.s6_addr32[3] ^
6676 hdr.ipv6->daddr.s6_addr32[0] ^
6677 hdr.ipv6->daddr.s6_addr32[1] ^
6678 hdr.ipv6->daddr.s6_addr32[2] ^
6679 hdr.ipv6->daddr.s6_addr32[3];
6680 }
6681
6682 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6683 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6684 input, common, ring->queue_index);
6685 }
6686
6687 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6688 {
6689 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6690 /* Herbert's original patch had:
6691 * smp_mb__after_netif_stop_queue();
6692 * but since that doesn't exist yet, just open code it. */
6693 smp_mb();
6694
6695 /* We need to check again in a case another CPU has just
6696 * made room available. */
6697 if (likely(ixgbe_desc_unused(tx_ring) < size))
6698 return -EBUSY;
6699
6700 /* A reprieve! - use start_queue because it doesn't call schedule */
6701 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6702 ++tx_ring->tx_stats.restart_queue;
6703 return 0;
6704 }
6705
6706 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6707 {
6708 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6709 return 0;
6710 return __ixgbe_maybe_stop_tx(tx_ring, size);
6711 }
6712
6713 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6714 {
6715 struct ixgbe_adapter *adapter = netdev_priv(dev);
6716 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6717 smp_processor_id();
6718 #ifdef IXGBE_FCOE
6719 __be16 protocol = vlan_get_protocol(skb);
6720
6721 if (((protocol == htons(ETH_P_FCOE)) ||
6722 (protocol == htons(ETH_P_FIP))) &&
6723 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6724 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6725 txq += adapter->ring_feature[RING_F_FCOE].mask;
6726 return txq;
6727 }
6728 #endif
6729
6730 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6731 while (unlikely(txq >= dev->real_num_tx_queues))
6732 txq -= dev->real_num_tx_queues;
6733 return txq;
6734 }
6735
6736 return skb_tx_hash(dev, skb);
6737 }
6738
6739 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6740 struct ixgbe_adapter *adapter,
6741 struct ixgbe_ring *tx_ring)
6742 {
6743 int tso;
6744 u32 tx_flags = 0;
6745 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6746 unsigned short f;
6747 #endif
6748 u16 first;
6749 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6750 __be16 protocol;
6751 u8 hdr_len = 0;
6752
6753 /*
6754 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6755 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6756 * + 2 desc gap to keep tail from touching head,
6757 * + 1 desc for context descriptor,
6758 * otherwise try next time
6759 */
6760 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6761 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6762 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6763 #else
6764 count += skb_shinfo(skb)->nr_frags;
6765 #endif
6766 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6767 tx_ring->tx_stats.tx_busy++;
6768 return NETDEV_TX_BUSY;
6769 }
6770
6771 protocol = vlan_get_protocol(skb);
6772
6773 if (vlan_tx_tag_present(skb)) {
6774 tx_flags |= vlan_tx_tag_get(skb);
6775 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6776 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6777 tx_flags |= tx_ring->dcb_tc << 13;
6778 }
6779 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6780 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6781 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6782 skb->priority != TC_PRIO_CONTROL) {
6783 tx_flags |= tx_ring->dcb_tc << 13;
6784 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6785 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6786 }
6787
6788 #ifdef IXGBE_FCOE
6789 /* for FCoE with DCB, we force the priority to what
6790 * was specified by the switch */
6791 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6792 (protocol == htons(ETH_P_FCOE)))
6793 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6794
6795 #endif
6796 /* record the location of the first descriptor for this packet */
6797 first = tx_ring->next_to_use;
6798
6799 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6800 #ifdef IXGBE_FCOE
6801 /* setup tx offload for FCoE */
6802 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6803 if (tso < 0)
6804 goto out_drop;
6805 else if (tso)
6806 tx_flags |= IXGBE_TX_FLAGS_FSO;
6807 #endif /* IXGBE_FCOE */
6808 } else {
6809 if (protocol == htons(ETH_P_IP))
6810 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6811 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6812 if (tso < 0)
6813 goto out_drop;
6814 else if (tso)
6815 tx_flags |= IXGBE_TX_FLAGS_TSO;
6816 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6817 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6818 }
6819
6820 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6821 if (count) {
6822 /* add the ATR filter if ATR is on */
6823 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6824 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6825 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6826 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6827
6828 } else {
6829 tx_ring->tx_buffer_info[first].time_stamp = 0;
6830 tx_ring->next_to_use = first;
6831 goto out_drop;
6832 }
6833
6834 return NETDEV_TX_OK;
6835
6836 out_drop:
6837 dev_kfree_skb_any(skb);
6838 return NETDEV_TX_OK;
6839 }
6840
6841 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6842 {
6843 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6844 struct ixgbe_ring *tx_ring;
6845
6846 tx_ring = adapter->tx_ring[skb->queue_mapping];
6847 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6848 }
6849
6850 /**
6851 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6852 * @netdev: network interface device structure
6853 * @p: pointer to an address structure
6854 *
6855 * Returns 0 on success, negative on failure
6856 **/
6857 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6858 {
6859 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6860 struct ixgbe_hw *hw = &adapter->hw;
6861 struct sockaddr *addr = p;
6862
6863 if (!is_valid_ether_addr(addr->sa_data))
6864 return -EADDRNOTAVAIL;
6865
6866 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6867 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6868
6869 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6870 IXGBE_RAH_AV);
6871
6872 return 0;
6873 }
6874
6875 static int
6876 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6877 {
6878 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6879 struct ixgbe_hw *hw = &adapter->hw;
6880 u16 value;
6881 int rc;
6882
6883 if (prtad != hw->phy.mdio.prtad)
6884 return -EINVAL;
6885 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6886 if (!rc)
6887 rc = value;
6888 return rc;
6889 }
6890
6891 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6892 u16 addr, u16 value)
6893 {
6894 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6895 struct ixgbe_hw *hw = &adapter->hw;
6896
6897 if (prtad != hw->phy.mdio.prtad)
6898 return -EINVAL;
6899 return hw->phy.ops.write_reg(hw, addr, devad, value);
6900 }
6901
6902 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6903 {
6904 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6905
6906 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6907 }
6908
6909 /**
6910 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6911 * netdev->dev_addrs
6912 * @netdev: network interface device structure
6913 *
6914 * Returns non-zero on failure
6915 **/
6916 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6917 {
6918 int err = 0;
6919 struct ixgbe_adapter *adapter = netdev_priv(dev);
6920 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6921
6922 if (is_valid_ether_addr(mac->san_addr)) {
6923 rtnl_lock();
6924 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6925 rtnl_unlock();
6926 }
6927 return err;
6928 }
6929
6930 /**
6931 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6932 * netdev->dev_addrs
6933 * @netdev: network interface device structure
6934 *
6935 * Returns non-zero on failure
6936 **/
6937 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6938 {
6939 int err = 0;
6940 struct ixgbe_adapter *adapter = netdev_priv(dev);
6941 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6942
6943 if (is_valid_ether_addr(mac->san_addr)) {
6944 rtnl_lock();
6945 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6946 rtnl_unlock();
6947 }
6948 return err;
6949 }
6950
6951 #ifdef CONFIG_NET_POLL_CONTROLLER
6952 /*
6953 * Polling 'interrupt' - used by things like netconsole to send skbs
6954 * without having to re-enable interrupts. It's not called while
6955 * the interrupt routine is executing.
6956 */
6957 static void ixgbe_netpoll(struct net_device *netdev)
6958 {
6959 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6960 int i;
6961
6962 /* if interface is down do nothing */
6963 if (test_bit(__IXGBE_DOWN, &adapter->state))
6964 return;
6965
6966 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6967 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6968 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6969 for (i = 0; i < num_q_vectors; i++) {
6970 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6971 ixgbe_msix_clean_many(0, q_vector);
6972 }
6973 } else {
6974 ixgbe_intr(adapter->pdev->irq, netdev);
6975 }
6976 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6977 }
6978 #endif
6979
6980 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6981 struct rtnl_link_stats64 *stats)
6982 {
6983 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6984 int i;
6985
6986 rcu_read_lock();
6987 for (i = 0; i < adapter->num_rx_queues; i++) {
6988 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6989 u64 bytes, packets;
6990 unsigned int start;
6991
6992 if (ring) {
6993 do {
6994 start = u64_stats_fetch_begin_bh(&ring->syncp);
6995 packets = ring->stats.packets;
6996 bytes = ring->stats.bytes;
6997 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6998 stats->rx_packets += packets;
6999 stats->rx_bytes += bytes;
7000 }
7001 }
7002
7003 for (i = 0; i < adapter->num_tx_queues; i++) {
7004 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7005 u64 bytes, packets;
7006 unsigned int start;
7007
7008 if (ring) {
7009 do {
7010 start = u64_stats_fetch_begin_bh(&ring->syncp);
7011 packets = ring->stats.packets;
7012 bytes = ring->stats.bytes;
7013 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7014 stats->tx_packets += packets;
7015 stats->tx_bytes += bytes;
7016 }
7017 }
7018 rcu_read_unlock();
7019 /* following stats updated by ixgbe_watchdog_task() */
7020 stats->multicast = netdev->stats.multicast;
7021 stats->rx_errors = netdev->stats.rx_errors;
7022 stats->rx_length_errors = netdev->stats.rx_length_errors;
7023 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7024 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7025 return stats;
7026 }
7027
7028 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7029 * #adapter: pointer to ixgbe_adapter
7030 * @tc: number of traffic classes currently enabled
7031 *
7032 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7033 * 802.1Q priority maps to a packet buffer that exists.
7034 */
7035 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7036 {
7037 struct ixgbe_hw *hw = &adapter->hw;
7038 u32 reg, rsave;
7039 int i;
7040
7041 /* 82598 have a static priority to TC mapping that can not
7042 * be changed so no validation is needed.
7043 */
7044 if (hw->mac.type == ixgbe_mac_82598EB)
7045 return;
7046
7047 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7048 rsave = reg;
7049
7050 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7051 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7052
7053 /* If up2tc is out of bounds default to zero */
7054 if (up2tc > tc)
7055 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7056 }
7057
7058 if (reg != rsave)
7059 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7060
7061 return;
7062 }
7063
7064
7065 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7066 * classes.
7067 *
7068 * @netdev: net device to configure
7069 * @tc: number of traffic classes to enable
7070 */
7071 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7072 {
7073 struct ixgbe_adapter *adapter = netdev_priv(dev);
7074 struct ixgbe_hw *hw = &adapter->hw;
7075
7076 /* If DCB is anabled do not remove traffic classes, multiple
7077 * traffic classes are required to implement DCB
7078 */
7079 if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7080 return 0;
7081
7082 /* Hardware supports up to 8 traffic classes */
7083 if (tc > MAX_TRAFFIC_CLASS ||
7084 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7085 return -EINVAL;
7086
7087 /* Hardware has to reinitialize queues and interrupts to
7088 * match packet buffer alignment. Unfortunantly, the
7089 * hardware is not flexible enough to do this dynamically.
7090 */
7091 if (netif_running(dev))
7092 ixgbe_close(dev);
7093 ixgbe_clear_interrupt_scheme(adapter);
7094
7095 if (tc)
7096 netdev_set_num_tc(dev, tc);
7097 else
7098 netdev_reset_tc(dev);
7099
7100 ixgbe_init_interrupt_scheme(adapter);
7101 ixgbe_validate_rtr(adapter, tc);
7102 if (netif_running(dev))
7103 ixgbe_open(dev);
7104
7105 return 0;
7106 }
7107
7108 void ixgbe_do_reset(struct net_device *netdev)
7109 {
7110 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7111
7112 if (netif_running(netdev))
7113 ixgbe_reinit_locked(adapter);
7114 else
7115 ixgbe_reset(adapter);
7116 }
7117
7118 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7119 {
7120 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7121
7122 #ifdef CONFIG_DCB
7123 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7124 data &= ~NETIF_F_HW_VLAN_RX;
7125 #endif
7126
7127 /* return error if RXHASH is being enabled when RSS is not supported */
7128 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7129 data &= ~NETIF_F_RXHASH;
7130
7131 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7132 if (!(data & NETIF_F_RXCSUM))
7133 data &= ~NETIF_F_LRO;
7134
7135 /* Turn off LRO if not RSC capable or invalid ITR settings */
7136 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7137 data &= ~NETIF_F_LRO;
7138 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7139 (adapter->rx_itr_setting != 1 &&
7140 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7141 data &= ~NETIF_F_LRO;
7142 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7143 }
7144
7145 return data;
7146 }
7147
7148 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7149 {
7150 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7151 bool need_reset = false;
7152
7153 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7154 if (!(data & NETIF_F_RXCSUM))
7155 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7156 else
7157 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7158
7159 /* Make sure RSC matches LRO, reset if change */
7160 if (!!(data & NETIF_F_LRO) !=
7161 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7162 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7163 switch (adapter->hw.mac.type) {
7164 case ixgbe_mac_X540:
7165 case ixgbe_mac_82599EB:
7166 need_reset = true;
7167 break;
7168 default:
7169 break;
7170 }
7171 }
7172
7173 /*
7174 * Check if Flow Director n-tuple support was enabled or disabled. If
7175 * the state changed, we need to reset.
7176 */
7177 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7178 /* turn off ATR, enable perfect filters and reset */
7179 if (data & NETIF_F_NTUPLE) {
7180 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7181 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7182 need_reset = true;
7183 }
7184 } else if (!(data & NETIF_F_NTUPLE)) {
7185 /* turn off Flow Director, set ATR and reset */
7186 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7187 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7188 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7189 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7190 need_reset = true;
7191 }
7192
7193 if (need_reset)
7194 ixgbe_do_reset(netdev);
7195
7196 return 0;
7197
7198 }
7199
7200 static const struct net_device_ops ixgbe_netdev_ops = {
7201 .ndo_open = ixgbe_open,
7202 .ndo_stop = ixgbe_close,
7203 .ndo_start_xmit = ixgbe_xmit_frame,
7204 .ndo_select_queue = ixgbe_select_queue,
7205 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7206 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7207 .ndo_validate_addr = eth_validate_addr,
7208 .ndo_set_mac_address = ixgbe_set_mac,
7209 .ndo_change_mtu = ixgbe_change_mtu,
7210 .ndo_tx_timeout = ixgbe_tx_timeout,
7211 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7212 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7213 .ndo_do_ioctl = ixgbe_ioctl,
7214 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7215 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7216 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7217 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7218 .ndo_get_stats64 = ixgbe_get_stats64,
7219 .ndo_setup_tc = ixgbe_setup_tc,
7220 #ifdef CONFIG_NET_POLL_CONTROLLER
7221 .ndo_poll_controller = ixgbe_netpoll,
7222 #endif
7223 #ifdef IXGBE_FCOE
7224 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7225 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7226 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7227 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7228 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7229 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7230 #endif /* IXGBE_FCOE */
7231 .ndo_set_features = ixgbe_set_features,
7232 .ndo_fix_features = ixgbe_fix_features,
7233 };
7234
7235 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7236 const struct ixgbe_info *ii)
7237 {
7238 #ifdef CONFIG_PCI_IOV
7239 struct ixgbe_hw *hw = &adapter->hw;
7240 int err;
7241 int num_vf_macvlans, i;
7242 struct vf_macvlans *mv_list;
7243
7244 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7245 return;
7246
7247 /* The 82599 supports up to 64 VFs per physical function
7248 * but this implementation limits allocation to 63 so that
7249 * basic networking resources are still available to the
7250 * physical function
7251 */
7252 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7253 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7254 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7255 if (err) {
7256 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7257 goto err_novfs;
7258 }
7259
7260 num_vf_macvlans = hw->mac.num_rar_entries -
7261 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7262
7263 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7264 sizeof(struct vf_macvlans),
7265 GFP_KERNEL);
7266 if (mv_list) {
7267 /* Initialize list of VF macvlans */
7268 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7269 for (i = 0; i < num_vf_macvlans; i++) {
7270 mv_list->vf = -1;
7271 mv_list->free = true;
7272 mv_list->rar_entry = hw->mac.num_rar_entries -
7273 (i + adapter->num_vfs + 1);
7274 list_add(&mv_list->l, &adapter->vf_mvs.l);
7275 mv_list++;
7276 }
7277 }
7278
7279 /* If call to enable VFs succeeded then allocate memory
7280 * for per VF control structures.
7281 */
7282 adapter->vfinfo =
7283 kcalloc(adapter->num_vfs,
7284 sizeof(struct vf_data_storage), GFP_KERNEL);
7285 if (adapter->vfinfo) {
7286 /* Now that we're sure SR-IOV is enabled
7287 * and memory allocated set up the mailbox parameters
7288 */
7289 ixgbe_init_mbx_params_pf(hw);
7290 memcpy(&hw->mbx.ops, ii->mbx_ops,
7291 sizeof(hw->mbx.ops));
7292
7293 /* Disable RSC when in SR-IOV mode */
7294 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7295 IXGBE_FLAG2_RSC_ENABLED);
7296 return;
7297 }
7298
7299 /* Oh oh */
7300 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7301 "SRIOV disabled\n");
7302 pci_disable_sriov(adapter->pdev);
7303
7304 err_novfs:
7305 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7306 adapter->num_vfs = 0;
7307 #endif /* CONFIG_PCI_IOV */
7308 }
7309
7310 /**
7311 * ixgbe_probe - Device Initialization Routine
7312 * @pdev: PCI device information struct
7313 * @ent: entry in ixgbe_pci_tbl
7314 *
7315 * Returns 0 on success, negative on failure
7316 *
7317 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7318 * The OS initialization, configuring of the adapter private structure,
7319 * and a hardware reset occur.
7320 **/
7321 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7322 const struct pci_device_id *ent)
7323 {
7324 struct net_device *netdev;
7325 struct ixgbe_adapter *adapter = NULL;
7326 struct ixgbe_hw *hw;
7327 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7328 static int cards_found;
7329 int i, err, pci_using_dac;
7330 u8 part_str[IXGBE_PBANUM_LENGTH];
7331 unsigned int indices = num_possible_cpus();
7332 #ifdef IXGBE_FCOE
7333 u16 device_caps;
7334 #endif
7335 u32 eec;
7336
7337 /* Catch broken hardware that put the wrong VF device ID in
7338 * the PCIe SR-IOV capability.
7339 */
7340 if (pdev->is_virtfn) {
7341 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7342 pci_name(pdev), pdev->vendor, pdev->device);
7343 return -EINVAL;
7344 }
7345
7346 err = pci_enable_device_mem(pdev);
7347 if (err)
7348 return err;
7349
7350 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7351 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7352 pci_using_dac = 1;
7353 } else {
7354 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7355 if (err) {
7356 err = dma_set_coherent_mask(&pdev->dev,
7357 DMA_BIT_MASK(32));
7358 if (err) {
7359 dev_err(&pdev->dev,
7360 "No usable DMA configuration, aborting\n");
7361 goto err_dma;
7362 }
7363 }
7364 pci_using_dac = 0;
7365 }
7366
7367 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7368 IORESOURCE_MEM), ixgbe_driver_name);
7369 if (err) {
7370 dev_err(&pdev->dev,
7371 "pci_request_selected_regions failed 0x%x\n", err);
7372 goto err_pci_reg;
7373 }
7374
7375 pci_enable_pcie_error_reporting(pdev);
7376
7377 pci_set_master(pdev);
7378 pci_save_state(pdev);
7379
7380 #ifdef CONFIG_IXGBE_DCB
7381 indices *= MAX_TRAFFIC_CLASS;
7382 #endif
7383
7384 if (ii->mac == ixgbe_mac_82598EB)
7385 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7386 else
7387 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7388
7389 #ifdef IXGBE_FCOE
7390 indices += min_t(unsigned int, num_possible_cpus(),
7391 IXGBE_MAX_FCOE_INDICES);
7392 #endif
7393 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7394 if (!netdev) {
7395 err = -ENOMEM;
7396 goto err_alloc_etherdev;
7397 }
7398
7399 SET_NETDEV_DEV(netdev, &pdev->dev);
7400
7401 adapter = netdev_priv(netdev);
7402 pci_set_drvdata(pdev, adapter);
7403
7404 adapter->netdev = netdev;
7405 adapter->pdev = pdev;
7406 hw = &adapter->hw;
7407 hw->back = adapter;
7408 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7409
7410 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7411 pci_resource_len(pdev, 0));
7412 if (!hw->hw_addr) {
7413 err = -EIO;
7414 goto err_ioremap;
7415 }
7416
7417 for (i = 1; i <= 5; i++) {
7418 if (pci_resource_len(pdev, i) == 0)
7419 continue;
7420 }
7421
7422 netdev->netdev_ops = &ixgbe_netdev_ops;
7423 ixgbe_set_ethtool_ops(netdev);
7424 netdev->watchdog_timeo = 5 * HZ;
7425 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7426
7427 adapter->bd_number = cards_found;
7428
7429 /* Setup hw api */
7430 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7431 hw->mac.type = ii->mac;
7432
7433 /* EEPROM */
7434 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7435 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7436 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7437 if (!(eec & (1 << 8)))
7438 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7439
7440 /* PHY */
7441 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7442 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7443 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7444 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7445 hw->phy.mdio.mmds = 0;
7446 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7447 hw->phy.mdio.dev = netdev;
7448 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7449 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7450
7451 ii->get_invariants(hw);
7452
7453 /* setup the private structure */
7454 err = ixgbe_sw_init(adapter);
7455 if (err)
7456 goto err_sw_init;
7457
7458 /* Make it possible the adapter to be woken up via WOL */
7459 switch (adapter->hw.mac.type) {
7460 case ixgbe_mac_82599EB:
7461 case ixgbe_mac_X540:
7462 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7463 break;
7464 default:
7465 break;
7466 }
7467
7468 /*
7469 * If there is a fan on this device and it has failed log the
7470 * failure.
7471 */
7472 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7473 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7474 if (esdp & IXGBE_ESDP_SDP1)
7475 e_crit(probe, "Fan has stopped, replace the adapter\n");
7476 }
7477
7478 /* reset_hw fills in the perm_addr as well */
7479 hw->phy.reset_if_overtemp = true;
7480 err = hw->mac.ops.reset_hw(hw);
7481 hw->phy.reset_if_overtemp = false;
7482 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7483 hw->mac.type == ixgbe_mac_82598EB) {
7484 err = 0;
7485 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7486 e_dev_err("failed to load because an unsupported SFP+ "
7487 "module type was detected.\n");
7488 e_dev_err("Reload the driver after installing a supported "
7489 "module.\n");
7490 goto err_sw_init;
7491 } else if (err) {
7492 e_dev_err("HW Init failed: %d\n", err);
7493 goto err_sw_init;
7494 }
7495
7496 ixgbe_probe_vf(adapter, ii);
7497
7498 netdev->features = NETIF_F_SG |
7499 NETIF_F_IP_CSUM |
7500 NETIF_F_IPV6_CSUM |
7501 NETIF_F_HW_VLAN_TX |
7502 NETIF_F_HW_VLAN_RX |
7503 NETIF_F_HW_VLAN_FILTER |
7504 NETIF_F_TSO |
7505 NETIF_F_TSO6 |
7506 NETIF_F_GRO |
7507 NETIF_F_RXHASH |
7508 NETIF_F_RXCSUM;
7509
7510 netdev->hw_features = netdev->features;
7511
7512 switch (adapter->hw.mac.type) {
7513 case ixgbe_mac_82599EB:
7514 case ixgbe_mac_X540:
7515 netdev->features |= NETIF_F_SCTP_CSUM;
7516 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7517 NETIF_F_NTUPLE;
7518 break;
7519 default:
7520 break;
7521 }
7522
7523 netdev->vlan_features |= NETIF_F_TSO;
7524 netdev->vlan_features |= NETIF_F_TSO6;
7525 netdev->vlan_features |= NETIF_F_IP_CSUM;
7526 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7527 netdev->vlan_features |= NETIF_F_SG;
7528
7529 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7530 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7531 IXGBE_FLAG_DCB_ENABLED);
7532
7533 #ifdef CONFIG_IXGBE_DCB
7534 netdev->dcbnl_ops = &dcbnl_ops;
7535 #endif
7536
7537 #ifdef IXGBE_FCOE
7538 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7539 if (hw->mac.ops.get_device_caps) {
7540 hw->mac.ops.get_device_caps(hw, &device_caps);
7541 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7542 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7543 }
7544 }
7545 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7546 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7547 netdev->vlan_features |= NETIF_F_FSO;
7548 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7549 }
7550 #endif /* IXGBE_FCOE */
7551 if (pci_using_dac) {
7552 netdev->features |= NETIF_F_HIGHDMA;
7553 netdev->vlan_features |= NETIF_F_HIGHDMA;
7554 }
7555
7556 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7557 netdev->hw_features |= NETIF_F_LRO;
7558 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7559 netdev->features |= NETIF_F_LRO;
7560
7561 /* make sure the EEPROM is good */
7562 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7563 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7564 err = -EIO;
7565 goto err_eeprom;
7566 }
7567
7568 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7569 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7570
7571 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7572 e_dev_err("invalid MAC address\n");
7573 err = -EIO;
7574 goto err_eeprom;
7575 }
7576
7577 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7578 if (hw->mac.ops.disable_tx_laser &&
7579 ((hw->phy.multispeed_fiber) ||
7580 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7581 (hw->mac.type == ixgbe_mac_82599EB))))
7582 hw->mac.ops.disable_tx_laser(hw);
7583
7584 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7585 (unsigned long) adapter);
7586
7587 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7588 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7589
7590 err = ixgbe_init_interrupt_scheme(adapter);
7591 if (err)
7592 goto err_sw_init;
7593
7594 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7595 netdev->hw_features &= ~NETIF_F_RXHASH;
7596 netdev->features &= ~NETIF_F_RXHASH;
7597 }
7598
7599 switch (pdev->device) {
7600 case IXGBE_DEV_ID_82599_SFP:
7601 /* Only this subdevice supports WOL */
7602 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7603 adapter->wol = IXGBE_WUFC_MAG;
7604 break;
7605 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7606 /* All except this subdevice support WOL */
7607 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7608 adapter->wol = IXGBE_WUFC_MAG;
7609 break;
7610 case IXGBE_DEV_ID_82599_KX4:
7611 adapter->wol = IXGBE_WUFC_MAG;
7612 break;
7613 default:
7614 adapter->wol = 0;
7615 break;
7616 }
7617 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7618
7619 /* pick up the PCI bus settings for reporting later */
7620 hw->mac.ops.get_bus_info(hw);
7621
7622 /* print bus type/speed/width info */
7623 e_dev_info("(PCI Express:%s:%s) %pM\n",
7624 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7625 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7626 "Unknown"),
7627 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7628 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7629 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7630 "Unknown"),
7631 netdev->dev_addr);
7632
7633 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7634 if (err)
7635 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7636 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7637 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7638 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7639 part_str);
7640 else
7641 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7642 hw->mac.type, hw->phy.type, part_str);
7643
7644 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7645 e_dev_warn("PCI-Express bandwidth available for this card is "
7646 "not sufficient for optimal performance.\n");
7647 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7648 "is required.\n");
7649 }
7650
7651 /* save off EEPROM version number */
7652 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7653
7654 /* reset the hardware with the new settings */
7655 err = hw->mac.ops.start_hw(hw);
7656
7657 if (err == IXGBE_ERR_EEPROM_VERSION) {
7658 /* We are running on a pre-production device, log a warning */
7659 e_dev_warn("This device is a pre-production adapter/LOM. "
7660 "Please be aware there may be issues associated "
7661 "with your hardware. If you are experiencing "
7662 "problems please contact your Intel or hardware "
7663 "representative who provided you with this "
7664 "hardware.\n");
7665 }
7666 strcpy(netdev->name, "eth%d");
7667 err = register_netdev(netdev);
7668 if (err)
7669 goto err_register;
7670
7671 /* carrier off reporting is important to ethtool even BEFORE open */
7672 netif_carrier_off(netdev);
7673
7674 #ifdef CONFIG_IXGBE_DCA
7675 if (dca_add_requester(&pdev->dev) == 0) {
7676 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7677 ixgbe_setup_dca(adapter);
7678 }
7679 #endif
7680 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7681 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7682 for (i = 0; i < adapter->num_vfs; i++)
7683 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7684 }
7685
7686 /* Inform firmware of driver version */
7687 if (hw->mac.ops.set_fw_drv_ver)
7688 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7689 FW_CEM_UNUSED_VER);
7690
7691 /* add san mac addr to netdev */
7692 ixgbe_add_sanmac_netdev(netdev);
7693
7694 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7695 cards_found++;
7696 return 0;
7697
7698 err_register:
7699 ixgbe_release_hw_control(adapter);
7700 ixgbe_clear_interrupt_scheme(adapter);
7701 err_sw_init:
7702 err_eeprom:
7703 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7704 ixgbe_disable_sriov(adapter);
7705 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7706 iounmap(hw->hw_addr);
7707 err_ioremap:
7708 free_netdev(netdev);
7709 err_alloc_etherdev:
7710 pci_release_selected_regions(pdev,
7711 pci_select_bars(pdev, IORESOURCE_MEM));
7712 err_pci_reg:
7713 err_dma:
7714 pci_disable_device(pdev);
7715 return err;
7716 }
7717
7718 /**
7719 * ixgbe_remove - Device Removal Routine
7720 * @pdev: PCI device information struct
7721 *
7722 * ixgbe_remove is called by the PCI subsystem to alert the driver
7723 * that it should release a PCI device. The could be caused by a
7724 * Hot-Plug event, or because the driver is going to be removed from
7725 * memory.
7726 **/
7727 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7728 {
7729 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7730 struct net_device *netdev = adapter->netdev;
7731
7732 set_bit(__IXGBE_DOWN, &adapter->state);
7733 cancel_work_sync(&adapter->service_task);
7734
7735 #ifdef CONFIG_IXGBE_DCA
7736 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7737 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7738 dca_remove_requester(&pdev->dev);
7739 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7740 }
7741
7742 #endif
7743 #ifdef IXGBE_FCOE
7744 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7745 ixgbe_cleanup_fcoe(adapter);
7746
7747 #endif /* IXGBE_FCOE */
7748
7749 /* remove the added san mac */
7750 ixgbe_del_sanmac_netdev(netdev);
7751
7752 if (netdev->reg_state == NETREG_REGISTERED)
7753 unregister_netdev(netdev);
7754
7755 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7756 ixgbe_disable_sriov(adapter);
7757
7758 ixgbe_clear_interrupt_scheme(adapter);
7759
7760 ixgbe_release_hw_control(adapter);
7761
7762 iounmap(adapter->hw.hw_addr);
7763 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7764 IORESOURCE_MEM));
7765
7766 e_dev_info("complete\n");
7767
7768 free_netdev(netdev);
7769
7770 pci_disable_pcie_error_reporting(pdev);
7771
7772 pci_disable_device(pdev);
7773 }
7774
7775 /**
7776 * ixgbe_io_error_detected - called when PCI error is detected
7777 * @pdev: Pointer to PCI device
7778 * @state: The current pci connection state
7779 *
7780 * This function is called after a PCI bus error affecting
7781 * this device has been detected.
7782 */
7783 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7784 pci_channel_state_t state)
7785 {
7786 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7787 struct net_device *netdev = adapter->netdev;
7788
7789 netif_device_detach(netdev);
7790
7791 if (state == pci_channel_io_perm_failure)
7792 return PCI_ERS_RESULT_DISCONNECT;
7793
7794 if (netif_running(netdev))
7795 ixgbe_down(adapter);
7796 pci_disable_device(pdev);
7797
7798 /* Request a slot reset. */
7799 return PCI_ERS_RESULT_NEED_RESET;
7800 }
7801
7802 /**
7803 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7804 * @pdev: Pointer to PCI device
7805 *
7806 * Restart the card from scratch, as if from a cold-boot.
7807 */
7808 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7809 {
7810 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7811 pci_ers_result_t result;
7812 int err;
7813
7814 if (pci_enable_device_mem(pdev)) {
7815 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7816 result = PCI_ERS_RESULT_DISCONNECT;
7817 } else {
7818 pci_set_master(pdev);
7819 pci_restore_state(pdev);
7820 pci_save_state(pdev);
7821
7822 pci_wake_from_d3(pdev, false);
7823
7824 ixgbe_reset(adapter);
7825 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7826 result = PCI_ERS_RESULT_RECOVERED;
7827 }
7828
7829 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7830 if (err) {
7831 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7832 "failed 0x%0x\n", err);
7833 /* non-fatal, continue */
7834 }
7835
7836 return result;
7837 }
7838
7839 /**
7840 * ixgbe_io_resume - called when traffic can start flowing again.
7841 * @pdev: Pointer to PCI device
7842 *
7843 * This callback is called when the error recovery driver tells us that
7844 * its OK to resume normal operation.
7845 */
7846 static void ixgbe_io_resume(struct pci_dev *pdev)
7847 {
7848 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7849 struct net_device *netdev = adapter->netdev;
7850
7851 if (netif_running(netdev)) {
7852 if (ixgbe_up(adapter)) {
7853 e_info(probe, "ixgbe_up failed after reset\n");
7854 return;
7855 }
7856 }
7857
7858 netif_device_attach(netdev);
7859 }
7860
7861 static struct pci_error_handlers ixgbe_err_handler = {
7862 .error_detected = ixgbe_io_error_detected,
7863 .slot_reset = ixgbe_io_slot_reset,
7864 .resume = ixgbe_io_resume,
7865 };
7866
7867 static struct pci_driver ixgbe_driver = {
7868 .name = ixgbe_driver_name,
7869 .id_table = ixgbe_pci_tbl,
7870 .probe = ixgbe_probe,
7871 .remove = __devexit_p(ixgbe_remove),
7872 #ifdef CONFIG_PM
7873 .suspend = ixgbe_suspend,
7874 .resume = ixgbe_resume,
7875 #endif
7876 .shutdown = ixgbe_shutdown,
7877 .err_handler = &ixgbe_err_handler
7878 };
7879
7880 /**
7881 * ixgbe_init_module - Driver Registration Routine
7882 *
7883 * ixgbe_init_module is the first routine called when the driver is
7884 * loaded. All it does is register with the PCI subsystem.
7885 **/
7886 static int __init ixgbe_init_module(void)
7887 {
7888 int ret;
7889 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7890 pr_info("%s\n", ixgbe_copyright);
7891
7892 #ifdef CONFIG_IXGBE_DCA
7893 dca_register_notify(&dca_notifier);
7894 #endif
7895
7896 ret = pci_register_driver(&ixgbe_driver);
7897 return ret;
7898 }
7899
7900 module_init(ixgbe_init_module);
7901
7902 /**
7903 * ixgbe_exit_module - Driver Exit Cleanup Routine
7904 *
7905 * ixgbe_exit_module is called just before the driver is removed
7906 * from memory.
7907 **/
7908 static void __exit ixgbe_exit_module(void)
7909 {
7910 #ifdef CONFIG_IXGBE_DCA
7911 dca_unregister_notify(&dca_notifier);
7912 #endif
7913 pci_unregister_driver(&ixgbe_driver);
7914 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7915 }
7916
7917 #ifdef CONFIG_IXGBE_DCA
7918 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7919 void *p)
7920 {
7921 int ret_val;
7922
7923 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7924 __ixgbe_notify_dca);
7925
7926 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7927 }
7928
7929 #endif /* CONFIG_IXGBE_DCA */
7930
7931 module_exit(ixgbe_exit_module);
7932
7933 /* ixgbe_main.c */
ubuntu-bionic-kernel mirror