1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if_vlan.h>
46 #include <linux/prefetch.h>
47 #include <scsi/fc/fc_fcoe.h>
50 #include "ixgbe_common.h"
51 #include "ixgbe_dcb_82599.h"
52 #include "ixgbe_sriov.h"
54 char ixgbe_driver_name
[] = "ixgbe";
55 static const char ixgbe_driver_string
[] =
56 "Intel(R) 10 Gigabit PCI Express Network Driver";
60 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
61 __stringify(BUILD) "-k"
62 const char ixgbe_driver_version
[] = DRV_VERSION
;
63 static const char ixgbe_copyright
[] =
64 "Copyright (c) 1999-2011 Intel Corporation.";
66 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
67 [board_82598
] = &ixgbe_82598_info
,
68 [board_82599
] = &ixgbe_82599_info
,
69 [board_X540
] = &ixgbe_X540_info
,
72 /* ixgbe_pci_tbl - PCI Device ID Table
74 * Wildcard entries (PCI_ANY_ID) should come last
75 * Last entry must be all 0s
77 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
78 * Class, Class Mask, private data (not used) }
80 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
111 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
113 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
115 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
117 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
119 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_BACKPLANE_FCOE
),
121 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_FCOE
),
123 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_T3_LOM
),
125 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
127 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_X540T
),
129 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_SF2
),
131 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_LS
),
134 /* required last entry */
137 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
139 #ifdef CONFIG_IXGBE_DCA
140 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
142 static struct notifier_block dca_notifier
= {
143 .notifier_call
= ixgbe_notify_dca
,
149 #ifdef CONFIG_PCI_IOV
150 static unsigned int max_vfs
;
151 module_param(max_vfs
, uint
, 0);
152 MODULE_PARM_DESC(max_vfs
,
153 "Maximum number of virtual functions to allocate per physical function");
154 #endif /* CONFIG_PCI_IOV */
156 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
157 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
158 MODULE_LICENSE("GPL");
159 MODULE_VERSION(DRV_VERSION
);
161 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
163 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
165 struct ixgbe_hw
*hw
= &adapter
->hw
;
170 #ifdef CONFIG_PCI_IOV
171 /* disable iov and allow time for transactions to clear */
172 pci_disable_sriov(adapter
->pdev
);
175 /* turn off device IOV mode */
176 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
177 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
178 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
179 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
180 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
181 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
183 /* set default pool back to 0 */
184 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
185 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
186 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
188 /* take a breather then clean up driver data */
191 kfree(adapter
->vfinfo
);
192 adapter
->vfinfo
= NULL
;
194 adapter
->num_vfs
= 0;
195 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
198 static void ixgbe_service_event_schedule(struct ixgbe_adapter
*adapter
)
200 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
))
202 schedule_work(&adapter
->service_task
);
205 static void ixgbe_service_event_complete(struct ixgbe_adapter
*adapter
)
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
));
209 /* flush memory to make sure state is correct before next watchog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
);
214 struct ixgbe_reg_info
{
219 static const struct ixgbe_reg_info ixgbe_reg_info_tbl
[] = {
221 /* General Registers */
222 {IXGBE_CTRL
, "CTRL"},
223 {IXGBE_STATUS
, "STATUS"},
224 {IXGBE_CTRL_EXT
, "CTRL_EXT"},
226 /* Interrupt Registers */
227 {IXGBE_EICR
, "EICR"},
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
247 /* List Terminator */
253 * ixgbe_regdump - register printout routine
255 static void ixgbe_regdump(struct ixgbe_hw
*hw
, struct ixgbe_reg_info
*reginfo
)
261 switch (reginfo
->ofs
) {
262 case IXGBE_SRRCTL(0):
263 for (i
= 0; i
< 64; i
++)
264 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_SRRCTL(i
));
266 case IXGBE_DCA_RXCTRL(0):
267 for (i
= 0; i
< 64; i
++)
268 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
271 for (i
= 0; i
< 64; i
++)
272 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDLEN(i
));
275 for (i
= 0; i
< 64; i
++)
276 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDH(i
));
279 for (i
= 0; i
< 64; i
++)
280 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDT(i
));
282 case IXGBE_RXDCTL(0):
283 for (i
= 0; i
< 64; i
++)
284 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
287 for (i
= 0; i
< 64; i
++)
288 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAL(i
));
291 for (i
= 0; i
< 64; i
++)
292 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAH(i
));
295 for (i
= 0; i
< 64; i
++)
296 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAL(i
));
299 for (i
= 0; i
< 64; i
++)
300 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAH(i
));
303 for (i
= 0; i
< 64; i
++)
304 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDLEN(i
));
307 for (i
= 0; i
< 64; i
++)
308 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDH(i
));
311 for (i
= 0; i
< 64; i
++)
312 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDT(i
));
314 case IXGBE_TXDCTL(0):
315 for (i
= 0; i
< 64; i
++)
316 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
319 pr_info("%-15s %08x\n", reginfo
->name
,
320 IXGBE_READ_REG(hw
, reginfo
->ofs
));
324 for (i
= 0; i
< 8; i
++) {
325 snprintf(rname
, 16, "%s[%d-%d]", reginfo
->name
, i
*8, i
*8+7);
326 pr_err("%-15s", rname
);
327 for (j
= 0; j
< 8; j
++)
328 pr_cont(" %08x", regs
[i
*8+j
]);
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
337 static void ixgbe_dump(struct ixgbe_adapter
*adapter
)
339 struct net_device
*netdev
= adapter
->netdev
;
340 struct ixgbe_hw
*hw
= &adapter
->hw
;
341 struct ixgbe_reg_info
*reginfo
;
343 struct ixgbe_ring
*tx_ring
;
344 struct ixgbe_tx_buffer
*tx_buffer_info
;
345 union ixgbe_adv_tx_desc
*tx_desc
;
346 struct my_u0
{ u64 a
; u64 b
; } *u0
;
347 struct ixgbe_ring
*rx_ring
;
348 union ixgbe_adv_rx_desc
*rx_desc
;
349 struct ixgbe_rx_buffer
*rx_buffer_info
;
353 if (!netif_msg_hw(adapter
))
356 /* Print netdevice Info */
358 dev_info(&adapter
->pdev
->dev
, "Net device Info\n");
359 pr_info("Device Name state "
360 "trans_start last_rx\n");
361 pr_info("%-15s %016lX %016lX %016lX\n",
368 /* Print Registers */
369 dev_info(&adapter
->pdev
->dev
, "Register Dump\n");
370 pr_info(" Register Name Value\n");
371 for (reginfo
= (struct ixgbe_reg_info
*)ixgbe_reg_info_tbl
;
372 reginfo
->name
; reginfo
++) {
373 ixgbe_regdump(hw
, reginfo
);
376 /* Print TX Ring Summary */
377 if (!netdev
|| !netif_running(netdev
))
380 dev_info(&adapter
->pdev
->dev
, "TX Rings Summary\n");
381 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
382 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
383 tx_ring
= adapter
->tx_ring
[n
];
385 &tx_ring
->tx_buffer_info
[tx_ring
->next_to_clean
];
386 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
387 n
, tx_ring
->next_to_use
, tx_ring
->next_to_clean
,
388 (u64
)tx_buffer_info
->dma
,
389 tx_buffer_info
->length
,
390 tx_buffer_info
->next_to_watch
,
391 (u64
)tx_buffer_info
->time_stamp
);
395 if (!netif_msg_tx_done(adapter
))
396 goto rx_ring_summary
;
398 dev_info(&adapter
->pdev
->dev
, "TX Rings Dump\n");
400 /* Transmit Descriptor Formats
402 * Advanced Transmit Descriptor
403 * +--------------------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +--------------------------------------------------------------+
406 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
407 * +--------------------------------------------------------------+
408 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
411 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
412 tx_ring
= adapter
->tx_ring
[n
];
413 pr_info("------------------------------------\n");
414 pr_info("TX QUEUE INDEX = %d\n", tx_ring
->queue_index
);
415 pr_info("------------------------------------\n");
416 pr_info("T [desc] [address 63:0 ] "
417 "[PlPOIdStDDt Ln] [bi->dma ] "
418 "leng ntw timestamp bi->skb\n");
420 for (i
= 0; tx_ring
->desc
&& (i
< tx_ring
->count
); i
++) {
421 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
422 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
423 u0
= (struct my_u0
*)tx_desc
;
424 pr_info("T [0x%03X] %016llX %016llX %016llX"
425 " %04X %3X %016llX %p", i
,
428 (u64
)tx_buffer_info
->dma
,
429 tx_buffer_info
->length
,
430 tx_buffer_info
->next_to_watch
,
431 (u64
)tx_buffer_info
->time_stamp
,
432 tx_buffer_info
->skb
);
433 if (i
== tx_ring
->next_to_use
&&
434 i
== tx_ring
->next_to_clean
)
436 else if (i
== tx_ring
->next_to_use
)
438 else if (i
== tx_ring
->next_to_clean
)
443 if (netif_msg_pktdata(adapter
) &&
444 tx_buffer_info
->dma
!= 0)
445 print_hex_dump(KERN_INFO
, "",
446 DUMP_PREFIX_ADDRESS
, 16, 1,
447 phys_to_virt(tx_buffer_info
->dma
),
448 tx_buffer_info
->length
, true);
452 /* Print RX Rings Summary */
454 dev_info(&adapter
->pdev
->dev
, "RX Rings Summary\n");
455 pr_info("Queue [NTU] [NTC]\n");
456 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
457 rx_ring
= adapter
->rx_ring
[n
];
458 pr_info("%5d %5X %5X\n",
459 n
, rx_ring
->next_to_use
, rx_ring
->next_to_clean
);
463 if (!netif_msg_rx_status(adapter
))
466 dev_info(&adapter
->pdev
->dev
, "RX Rings Dump\n");
468 /* Advanced Receive Descriptor (Read) Format
470 * +-----------------------------------------------------+
471 * 0 | Packet Buffer Address [63:1] |A0/NSE|
472 * +----------------------------------------------+------+
473 * 8 | Header Buffer Address [63:1] | DD |
474 * +-----------------------------------------------------+
477 * Advanced Receive Descriptor (Write-Back) Format
479 * 63 48 47 32 31 30 21 20 16 15 4 3 0
480 * +------------------------------------------------------+
481 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
482 * | Checksum Ident | | | | Type | Type |
483 * +------------------------------------------------------+
484 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
485 * +------------------------------------------------------+
486 * 63 48 47 32 31 20 19 0
488 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
489 rx_ring
= adapter
->rx_ring
[n
];
490 pr_info("------------------------------------\n");
491 pr_info("RX QUEUE INDEX = %d\n", rx_ring
->queue_index
);
492 pr_info("------------------------------------\n");
493 pr_info("R [desc] [ PktBuf A0] "
494 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
495 "<-- Adv Rx Read format\n");
496 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
497 "[vl er S cks ln] ---------------- [bi->skb] "
498 "<-- Adv Rx Write-Back format\n");
500 for (i
= 0; i
< rx_ring
->count
; i
++) {
501 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
502 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
503 u0
= (struct my_u0
*)rx_desc
;
504 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
505 if (staterr
& IXGBE_RXD_STAT_DD
) {
506 /* Descriptor Done */
507 pr_info("RWB[0x%03X] %016llX "
508 "%016llX ---------------- %p", i
,
511 rx_buffer_info
->skb
);
513 pr_info("R [0x%03X] %016llX "
514 "%016llX %016llX %p", i
,
517 (u64
)rx_buffer_info
->dma
,
518 rx_buffer_info
->skb
);
520 if (netif_msg_pktdata(adapter
)) {
521 print_hex_dump(KERN_INFO
, "",
522 DUMP_PREFIX_ADDRESS
, 16, 1,
523 phys_to_virt(rx_buffer_info
->dma
),
524 rx_ring
->rx_buf_len
, true);
526 if (rx_ring
->rx_buf_len
527 < IXGBE_RXBUFFER_2048
)
528 print_hex_dump(KERN_INFO
, "",
529 DUMP_PREFIX_ADDRESS
, 16, 1,
531 rx_buffer_info
->page_dma
+
532 rx_buffer_info
->page_offset
538 if (i
== rx_ring
->next_to_use
)
540 else if (i
== rx_ring
->next_to_clean
)
552 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
556 /* Let firmware take over control of h/w */
557 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
558 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
559 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
562 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
566 /* Let firmware know the driver has taken over */
567 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
568 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
569 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
573 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
574 * @adapter: pointer to adapter struct
575 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
576 * @queue: queue to map the corresponding interrupt to
577 * @msix_vector: the vector to map to the corresponding queue
580 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
581 u8 queue
, u8 msix_vector
)
584 struct ixgbe_hw
*hw
= &adapter
->hw
;
585 switch (hw
->mac
.type
) {
586 case ixgbe_mac_82598EB
:
587 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
590 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
591 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
592 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
593 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
594 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
596 case ixgbe_mac_82599EB
:
598 if (direction
== -1) {
600 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
601 index
= ((queue
& 1) * 8);
602 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
603 ivar
&= ~(0xFF << index
);
604 ivar
|= (msix_vector
<< index
);
605 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
608 /* tx or rx causes */
609 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
610 index
= ((16 * (queue
& 1)) + (8 * direction
));
611 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
612 ivar
&= ~(0xFF << index
);
613 ivar
|= (msix_vector
<< index
);
614 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
622 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
627 switch (adapter
->hw
.mac
.type
) {
628 case ixgbe_mac_82598EB
:
629 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
630 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
632 case ixgbe_mac_82599EB
:
634 mask
= (qmask
& 0xFFFFFFFF);
635 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
636 mask
= (qmask
>> 32);
637 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
644 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring
*tx_ring
,
645 struct ixgbe_tx_buffer
*tx_buffer_info
)
647 if (tx_buffer_info
->dma
) {
648 if (tx_buffer_info
->mapped_as_page
)
649 dma_unmap_page(tx_ring
->dev
,
651 tx_buffer_info
->length
,
654 dma_unmap_single(tx_ring
->dev
,
656 tx_buffer_info
->length
,
658 tx_buffer_info
->dma
= 0;
660 if (tx_buffer_info
->skb
) {
661 dev_kfree_skb_any(tx_buffer_info
->skb
);
662 tx_buffer_info
->skb
= NULL
;
664 tx_buffer_info
->time_stamp
= 0;
665 /* tx_buffer_info must be completely set up in the transmit path */
668 static void ixgbe_update_xoff_received(struct ixgbe_adapter
*adapter
)
670 struct ixgbe_hw
*hw
= &adapter
->hw
;
671 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
676 if ((hw
->fc
.current_mode
== ixgbe_fc_full
) ||
677 (hw
->fc
.current_mode
== ixgbe_fc_rx_pause
)) {
678 switch (hw
->mac
.type
) {
679 case ixgbe_mac_82598EB
:
680 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
683 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
685 hwstats
->lxoffrxc
+= data
;
687 /* refill credits (no tx hang) if we received xoff */
691 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
692 clear_bit(__IXGBE_HANG_CHECK_ARMED
,
693 &adapter
->tx_ring
[i
]->state
);
695 } else if (!(adapter
->dcb_cfg
.pfc_mode_enable
))
698 /* update stats for each tc, only valid with PFC enabled */
699 for (i
= 0; i
< MAX_TX_PACKET_BUFFERS
; i
++) {
700 switch (hw
->mac
.type
) {
701 case ixgbe_mac_82598EB
:
702 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
705 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXCNT(i
));
707 hwstats
->pxoffrxc
[i
] += xoff
[i
];
710 /* disarm tx queues that have received xoff frames */
711 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
712 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
713 u8 tc
= tx_ring
->dcb_tc
;
716 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
720 static u64
ixgbe_get_tx_completed(struct ixgbe_ring
*ring
)
722 return ring
->tx_stats
.completed
;
725 static u64
ixgbe_get_tx_pending(struct ixgbe_ring
*ring
)
727 struct ixgbe_adapter
*adapter
= netdev_priv(ring
->netdev
);
728 struct ixgbe_hw
*hw
= &adapter
->hw
;
730 u32 head
= IXGBE_READ_REG(hw
, IXGBE_TDH(ring
->reg_idx
));
731 u32 tail
= IXGBE_READ_REG(hw
, IXGBE_TDT(ring
->reg_idx
));
734 return (head
< tail
) ?
735 tail
- head
: (tail
+ ring
->count
- head
);
740 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring
*tx_ring
)
742 u32 tx_done
= ixgbe_get_tx_completed(tx_ring
);
743 u32 tx_done_old
= tx_ring
->tx_stats
.tx_done_old
;
744 u32 tx_pending
= ixgbe_get_tx_pending(tx_ring
);
747 clear_check_for_tx_hang(tx_ring
);
750 * Check for a hung queue, but be thorough. This verifies
751 * that a transmit has been completed since the previous
752 * check AND there is at least one packet pending. The
753 * ARMED bit is set to indicate a potential hang. The
754 * bit is cleared if a pause frame is received to remove
755 * false hang detection due to PFC or 802.3x frames. By
756 * requiring this to fail twice we avoid races with
757 * pfc clearing the ARMED bit and conditions where we
758 * run the check_tx_hang logic with a transmit completion
759 * pending but without time to complete it yet.
761 if ((tx_done_old
== tx_done
) && tx_pending
) {
762 /* make sure it is true for two checks in a row */
763 ret
= test_and_set_bit(__IXGBE_HANG_CHECK_ARMED
,
766 /* update completed stats and continue */
767 tx_ring
->tx_stats
.tx_done_old
= tx_done
;
768 /* reset the countdown */
769 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
776 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
777 * @adapter: driver private struct
779 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter
*adapter
)
782 /* Do the reset outside of interrupt context */
783 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
784 adapter
->flags2
|= IXGBE_FLAG2_RESET_REQUESTED
;
785 ixgbe_service_event_schedule(adapter
);
790 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
791 * @q_vector: structure containing interrupt and ring information
792 * @tx_ring: tx ring to clean
794 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
795 struct ixgbe_ring
*tx_ring
)
797 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
798 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
799 struct ixgbe_tx_buffer
*tx_buffer_info
;
800 unsigned int total_bytes
= 0, total_packets
= 0;
801 u16 i
, eop
, count
= 0;
803 i
= tx_ring
->next_to_clean
;
804 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
805 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
807 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
808 (count
< q_vector
->tx
.work_limit
)) {
809 bool cleaned
= false;
810 rmb(); /* read buffer_info after eop_desc */
811 for ( ; !cleaned
; count
++) {
812 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
813 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
815 tx_desc
->wb
.status
= 0;
816 cleaned
= (i
== eop
);
819 if (i
== tx_ring
->count
)
822 if (cleaned
&& tx_buffer_info
->skb
) {
823 total_bytes
+= tx_buffer_info
->bytecount
;
824 total_packets
+= tx_buffer_info
->gso_segs
;
827 ixgbe_unmap_and_free_tx_resource(tx_ring
,
831 tx_ring
->tx_stats
.completed
++;
832 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
833 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
836 tx_ring
->next_to_clean
= i
;
837 tx_ring
->stats
.bytes
+= total_bytes
;
838 tx_ring
->stats
.packets
+= total_packets
;
839 u64_stats_update_begin(&tx_ring
->syncp
);
840 q_vector
->tx
.total_bytes
+= total_bytes
;
841 q_vector
->tx
.total_packets
+= total_packets
;
842 u64_stats_update_end(&tx_ring
->syncp
);
844 if (check_for_tx_hang(tx_ring
) && ixgbe_check_tx_hang(tx_ring
)) {
845 /* schedule immediate reset if we believe we hung */
846 struct ixgbe_hw
*hw
= &adapter
->hw
;
847 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
848 e_err(drv
, "Detected Tx Unit Hang\n"
850 " TDH, TDT <%x>, <%x>\n"
851 " next_to_use <%x>\n"
852 " next_to_clean <%x>\n"
853 "tx_buffer_info[next_to_clean]\n"
854 " time_stamp <%lx>\n"
856 tx_ring
->queue_index
,
857 IXGBE_READ_REG(hw
, IXGBE_TDH(tx_ring
->reg_idx
)),
858 IXGBE_READ_REG(hw
, IXGBE_TDT(tx_ring
->reg_idx
)),
859 tx_ring
->next_to_use
, eop
,
860 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
862 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
865 "tx hang %d detected on queue %d, resetting adapter\n",
866 adapter
->tx_timeout_count
+ 1, tx_ring
->queue_index
);
868 /* schedule immediate reset if we believe we hung */
869 ixgbe_tx_timeout_reset(adapter
);
871 /* the adapter is about to reset, no point in enabling stuff */
875 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
876 if (unlikely(count
&& netif_carrier_ok(tx_ring
->netdev
) &&
877 (ixgbe_desc_unused(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
878 /* Make sure that anybody stopping the queue after this
879 * sees the new next_to_clean.
882 if (__netif_subqueue_stopped(tx_ring
->netdev
, tx_ring
->queue_index
) &&
883 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
884 netif_wake_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
885 ++tx_ring
->tx_stats
.restart_queue
;
889 return count
< q_vector
->tx
.work_limit
;
892 #ifdef CONFIG_IXGBE_DCA
893 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
894 struct ixgbe_ring
*rx_ring
,
897 struct ixgbe_hw
*hw
= &adapter
->hw
;
899 u8 reg_idx
= rx_ring
->reg_idx
;
901 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
));
902 switch (hw
->mac
.type
) {
903 case ixgbe_mac_82598EB
:
904 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
905 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
907 case ixgbe_mac_82599EB
:
909 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
910 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
911 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
916 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
917 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
918 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
919 IXGBE_WRITE_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
), rxctrl
);
922 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
923 struct ixgbe_ring
*tx_ring
,
926 struct ixgbe_hw
*hw
= &adapter
->hw
;
928 u8 reg_idx
= tx_ring
->reg_idx
;
930 switch (hw
->mac
.type
) {
931 case ixgbe_mac_82598EB
:
932 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
));
933 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
934 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
935 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
936 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
), txctrl
);
938 case ixgbe_mac_82599EB
:
940 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
));
941 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
942 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
943 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
944 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
945 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
), txctrl
);
952 static void ixgbe_update_dca(struct ixgbe_q_vector
*q_vector
)
954 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
959 if (q_vector
->cpu
== cpu
)
962 r_idx
= find_first_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
);
963 for (i
= 0; i
< q_vector
->tx
.count
; i
++) {
964 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[r_idx
], cpu
);
965 r_idx
= find_next_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
,
969 r_idx
= find_first_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
);
970 for (i
= 0; i
< q_vector
->rx
.count
; i
++) {
971 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[r_idx
], cpu
);
972 r_idx
= find_next_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
,
981 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
986 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
989 /* always use CB2 mode, difference is masked in the CB driver */
990 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
992 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
993 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
997 for (i
= 0; i
< num_q_vectors
; i
++) {
998 adapter
->q_vector
[i
]->cpu
= -1;
999 ixgbe_update_dca(adapter
->q_vector
[i
]);
1003 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
1005 struct ixgbe_adapter
*adapter
= dev_get_drvdata(dev
);
1006 unsigned long event
= *(unsigned long *)data
;
1008 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
1012 case DCA_PROVIDER_ADD
:
1013 /* if we're already enabled, don't do it again */
1014 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1016 if (dca_add_requester(dev
) == 0) {
1017 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
1018 ixgbe_setup_dca(adapter
);
1021 /* Fall Through since DCA is disabled. */
1022 case DCA_PROVIDER_REMOVE
:
1023 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
1024 dca_remove_requester(dev
);
1025 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
1026 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
1033 #endif /* CONFIG_IXGBE_DCA */
1035 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc
*rx_desc
,
1036 struct sk_buff
*skb
)
1038 skb
->rxhash
= le32_to_cpu(rx_desc
->wb
.lower
.hi_dword
.rss
);
1042 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1043 * @adapter: address of board private structure
1044 * @rx_desc: advanced rx descriptor
1046 * Returns : true if it is FCoE pkt
1048 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter
*adapter
,
1049 union ixgbe_adv_rx_desc
*rx_desc
)
1051 __le16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1053 return (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
1054 ((pkt_info
& cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK
)) ==
1055 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE
<<
1056 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT
)));
1060 * ixgbe_receive_skb - Send a completed packet up the stack
1061 * @adapter: board private structure
1062 * @skb: packet to send up
1063 * @status: hardware indication of status of receive
1064 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1065 * @rx_desc: rx descriptor
1067 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
1068 struct sk_buff
*skb
, u8 status
,
1069 struct ixgbe_ring
*ring
,
1070 union ixgbe_adv_rx_desc
*rx_desc
)
1072 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1073 struct napi_struct
*napi
= &q_vector
->napi
;
1074 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
1075 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
1077 if (is_vlan
&& (tag
& VLAN_VID_MASK
))
1078 __vlan_hwaccel_put_tag(skb
, tag
);
1080 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
))
1081 napi_gro_receive(napi
, skb
);
1087 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1088 * @adapter: address of board private structure
1089 * @status_err: hardware indication of status of receive
1090 * @skb: skb currently being received and modified
1091 * @status_err: status error value of last descriptor in packet
1093 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
1094 union ixgbe_adv_rx_desc
*rx_desc
,
1095 struct sk_buff
*skb
,
1098 skb
->ip_summed
= CHECKSUM_NONE
;
1100 /* Rx csum disabled */
1101 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
1104 /* if IP and error */
1105 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
1106 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
1107 adapter
->hw_csum_rx_error
++;
1111 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
1114 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
1115 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1118 * 82599 errata, UDP frames with a 0 checksum can be marked as
1121 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
1122 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1125 adapter
->hw_csum_rx_error
++;
1129 /* It must be a TCP or UDP packet with a valid checksum */
1130 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1133 static inline void ixgbe_release_rx_desc(struct ixgbe_ring
*rx_ring
, u32 val
)
1136 * Force memory writes to complete before letting h/w
1137 * know there are new descriptors to fetch. (Only
1138 * applicable for weak-ordered memory model archs,
1142 writel(val
, rx_ring
->tail
);
1146 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1147 * @rx_ring: ring to place buffers on
1148 * @cleaned_count: number of buffers to replace
1150 void ixgbe_alloc_rx_buffers(struct ixgbe_ring
*rx_ring
, u16 cleaned_count
)
1152 union ixgbe_adv_rx_desc
*rx_desc
;
1153 struct ixgbe_rx_buffer
*bi
;
1154 struct sk_buff
*skb
;
1155 u16 i
= rx_ring
->next_to_use
;
1157 /* do nothing if no valid netdev defined */
1158 if (!rx_ring
->netdev
)
1161 while (cleaned_count
--) {
1162 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1163 bi
= &rx_ring
->rx_buffer_info
[i
];
1167 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
1168 rx_ring
->rx_buf_len
);
1170 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1173 /* initialize queue mapping */
1174 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
1179 bi
->dma
= dma_map_single(rx_ring
->dev
,
1181 rx_ring
->rx_buf_len
,
1183 if (dma_mapping_error(rx_ring
->dev
, bi
->dma
)) {
1184 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1190 if (ring_is_ps_enabled(rx_ring
)) {
1192 bi
->page
= netdev_alloc_page(rx_ring
->netdev
);
1194 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1199 if (!bi
->page_dma
) {
1200 /* use a half page if we're re-using */
1201 bi
->page_offset
^= PAGE_SIZE
/ 2;
1202 bi
->page_dma
= dma_map_page(rx_ring
->dev
,
1207 if (dma_mapping_error(rx_ring
->dev
,
1209 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1215 /* Refresh the desc even if buffer_addrs didn't change
1216 * because each write-back erases this info. */
1217 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
1218 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
1220 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
1221 rx_desc
->read
.hdr_addr
= 0;
1225 if (i
== rx_ring
->count
)
1230 if (rx_ring
->next_to_use
!= i
) {
1231 rx_ring
->next_to_use
= i
;
1232 ixgbe_release_rx_desc(rx_ring
, i
);
1236 static inline u16
ixgbe_get_hlen(union ixgbe_adv_rx_desc
*rx_desc
)
1238 /* HW will not DMA in data larger than the given buffer, even if it
1239 * parses the (NFS, of course) header to be larger. In that case, it
1240 * fills the header buffer and spills the rest into the page.
1242 u16 hdr_info
= le16_to_cpu(rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
);
1243 u16 hlen
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
1244 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
1245 if (hlen
> IXGBE_RX_HDR_SIZE
)
1246 hlen
= IXGBE_RX_HDR_SIZE
;
1251 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1252 * @skb: pointer to the last skb in the rsc queue
1254 * This function changes a queue full of hw rsc buffers into a completed
1255 * packet. It uses the ->prev pointers to find the first packet and then
1256 * turns it into the frag list owner.
1258 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
)
1260 unsigned int frag_list_size
= 0;
1261 unsigned int skb_cnt
= 1;
1264 struct sk_buff
*prev
= skb
->prev
;
1265 frag_list_size
+= skb
->len
;
1271 skb_shinfo(skb
)->frag_list
= skb
->next
;
1273 skb
->len
+= frag_list_size
;
1274 skb
->data_len
+= frag_list_size
;
1275 skb
->truesize
+= frag_list_size
;
1276 IXGBE_RSC_CB(skb
)->skb_cnt
= skb_cnt
;
1281 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc
*rx_desc
)
1283 return !!(le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
1284 IXGBE_RXDADV_RSCCNT_MASK
);
1287 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
1288 struct ixgbe_ring
*rx_ring
,
1289 int *work_done
, int work_to_do
)
1291 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1292 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
1293 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
1294 struct sk_buff
*skb
;
1295 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1296 const int current_node
= numa_node_id();
1299 #endif /* IXGBE_FCOE */
1302 u16 cleaned_count
= 0;
1303 bool pkt_is_rsc
= false;
1305 i
= rx_ring
->next_to_clean
;
1306 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1307 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1309 while (staterr
& IXGBE_RXD_STAT_DD
) {
1312 rmb(); /* read descriptor and rx_buffer_info after status DD */
1314 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1316 skb
= rx_buffer_info
->skb
;
1317 rx_buffer_info
->skb
= NULL
;
1318 prefetch(skb
->data
);
1320 if (ring_is_rsc_enabled(rx_ring
))
1321 pkt_is_rsc
= ixgbe_get_rsc_state(rx_desc
);
1323 /* if this is a skb from previous receive DMA will be 0 */
1324 if (rx_buffer_info
->dma
) {
1327 !(staterr
& IXGBE_RXD_STAT_EOP
) &&
1330 * When HWRSC is enabled, delay unmapping
1331 * of the first packet. It carries the
1332 * header information, HW may still
1333 * access the header after the writeback.
1334 * Only unmap it when EOP is reached
1336 IXGBE_RSC_CB(skb
)->delay_unmap
= true;
1337 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
1339 dma_unmap_single(rx_ring
->dev
,
1340 rx_buffer_info
->dma
,
1341 rx_ring
->rx_buf_len
,
1344 rx_buffer_info
->dma
= 0;
1346 if (ring_is_ps_enabled(rx_ring
)) {
1347 hlen
= ixgbe_get_hlen(rx_desc
);
1348 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1350 hlen
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1355 /* assume packet split since header is unmapped */
1356 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1360 dma_unmap_page(rx_ring
->dev
,
1361 rx_buffer_info
->page_dma
,
1364 rx_buffer_info
->page_dma
= 0;
1365 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1366 rx_buffer_info
->page
,
1367 rx_buffer_info
->page_offset
,
1370 if ((page_count(rx_buffer_info
->page
) == 1) &&
1371 (page_to_nid(rx_buffer_info
->page
) == current_node
))
1372 get_page(rx_buffer_info
->page
);
1374 rx_buffer_info
->page
= NULL
;
1376 skb
->len
+= upper_len
;
1377 skb
->data_len
+= upper_len
;
1378 skb
->truesize
+= upper_len
;
1382 if (i
== rx_ring
->count
)
1385 next_rxd
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1390 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
1391 IXGBE_RXDADV_NEXTP_SHIFT
;
1392 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
1394 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
1397 if (!(staterr
& IXGBE_RXD_STAT_EOP
)) {
1398 if (ring_is_ps_enabled(rx_ring
)) {
1399 rx_buffer_info
->skb
= next_buffer
->skb
;
1400 rx_buffer_info
->dma
= next_buffer
->dma
;
1401 next_buffer
->skb
= skb
;
1402 next_buffer
->dma
= 0;
1404 skb
->next
= next_buffer
->skb
;
1405 skb
->next
->prev
= skb
;
1407 rx_ring
->rx_stats
.non_eop_descs
++;
1412 skb
= ixgbe_transform_rsc_queue(skb
);
1413 /* if we got here without RSC the packet is invalid */
1415 __pskb_trim(skb
, 0);
1416 rx_buffer_info
->skb
= skb
;
1421 if (ring_is_rsc_enabled(rx_ring
)) {
1422 if (IXGBE_RSC_CB(skb
)->delay_unmap
) {
1423 dma_unmap_single(rx_ring
->dev
,
1424 IXGBE_RSC_CB(skb
)->dma
,
1425 rx_ring
->rx_buf_len
,
1427 IXGBE_RSC_CB(skb
)->dma
= 0;
1428 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
1432 if (ring_is_ps_enabled(rx_ring
))
1433 rx_ring
->rx_stats
.rsc_count
+=
1434 skb_shinfo(skb
)->nr_frags
;
1436 rx_ring
->rx_stats
.rsc_count
+=
1437 IXGBE_RSC_CB(skb
)->skb_cnt
;
1438 rx_ring
->rx_stats
.rsc_flush
++;
1441 /* ERR_MASK will only have valid bits if EOP set */
1442 if (unlikely(staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
)) {
1443 dev_kfree_skb_any(skb
);
1447 ixgbe_rx_checksum(adapter
, rx_desc
, skb
, staterr
);
1448 if (adapter
->netdev
->features
& NETIF_F_RXHASH
)
1449 ixgbe_rx_hash(rx_desc
, skb
);
1451 /* probably a little skewed due to removing CRC */
1452 total_rx_bytes
+= skb
->len
;
1455 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1457 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1458 if (ixgbe_rx_is_fcoe(adapter
, rx_desc
)) {
1459 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
,
1464 #endif /* IXGBE_FCOE */
1465 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
1468 rx_desc
->wb
.upper
.status_error
= 0;
1471 if (*work_done
>= work_to_do
)
1474 /* return some buffers to hardware, one at a time is too slow */
1475 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
1476 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1480 /* use prefetched values */
1482 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1485 rx_ring
->next_to_clean
= i
;
1486 cleaned_count
= ixgbe_desc_unused(rx_ring
);
1489 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1492 /* include DDPed FCoE data */
1493 if (ddp_bytes
> 0) {
1496 mss
= rx_ring
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1497 sizeof(struct fc_frame_header
) -
1498 sizeof(struct fcoe_crc_eof
);
1501 total_rx_bytes
+= ddp_bytes
;
1502 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1504 #endif /* IXGBE_FCOE */
1506 u64_stats_update_begin(&rx_ring
->syncp
);
1507 rx_ring
->stats
.packets
+= total_rx_packets
;
1508 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1509 u64_stats_update_end(&rx_ring
->syncp
);
1510 q_vector
->rx
.total_packets
+= total_rx_packets
;
1511 q_vector
->rx
.total_bytes
+= total_rx_bytes
;
1514 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1516 * ixgbe_configure_msix - Configure MSI-X hardware
1517 * @adapter: board private structure
1519 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1522 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1524 struct ixgbe_q_vector
*q_vector
;
1525 int i
, q_vectors
, v_idx
, r_idx
;
1528 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1531 * Populate the IVAR table and set the ITR values to the
1532 * corresponding register.
1534 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1535 q_vector
= adapter
->q_vector
[v_idx
];
1536 /* XXX for_each_set_bit(...) */
1537 r_idx
= find_first_bit(q_vector
->rx
.idx
,
1538 adapter
->num_rx_queues
);
1540 for (i
= 0; i
< q_vector
->rx
.count
; i
++) {
1541 u8 reg_idx
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1542 ixgbe_set_ivar(adapter
, 0, reg_idx
, v_idx
);
1543 r_idx
= find_next_bit(q_vector
->rx
.idx
,
1544 adapter
->num_rx_queues
,
1547 r_idx
= find_first_bit(q_vector
->tx
.idx
,
1548 adapter
->num_tx_queues
);
1550 for (i
= 0; i
< q_vector
->tx
.count
; i
++) {
1551 u8 reg_idx
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1552 ixgbe_set_ivar(adapter
, 1, reg_idx
, v_idx
);
1553 r_idx
= find_next_bit(q_vector
->tx
.idx
,
1554 adapter
->num_tx_queues
,
1558 if (q_vector
->tx
.count
&& !q_vector
->rx
.count
)
1560 q_vector
->eitr
= adapter
->tx_eitr_param
;
1561 else if (q_vector
->rx
.count
)
1563 q_vector
->eitr
= adapter
->rx_eitr_param
;
1565 ixgbe_write_eitr(q_vector
);
1566 /* If ATR is enabled, set interrupt affinity */
1567 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
1569 * Allocate the affinity_hint cpumask, assign the mask
1570 * for this vector, and set our affinity_hint for
1573 if (!alloc_cpumask_var(&q_vector
->affinity_mask
,
1576 cpumask_set_cpu(v_idx
, q_vector
->affinity_mask
);
1577 irq_set_affinity_hint(adapter
->msix_entries
[v_idx
].vector
,
1578 q_vector
->affinity_mask
);
1582 switch (adapter
->hw
.mac
.type
) {
1583 case ixgbe_mac_82598EB
:
1584 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1587 case ixgbe_mac_82599EB
:
1588 case ixgbe_mac_X540
:
1589 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1595 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1597 /* set up to autoclear timer, and the vectors */
1598 mask
= IXGBE_EIMS_ENABLE_MASK
;
1599 if (adapter
->num_vfs
)
1600 mask
&= ~(IXGBE_EIMS_OTHER
|
1601 IXGBE_EIMS_MAILBOX
|
1604 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1605 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1608 enum latency_range
{
1612 latency_invalid
= 255
1616 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1617 * @q_vector: structure containing interrupt and ring information
1618 * @ring_container: structure containing ring performance data
1620 * Stores a new ITR value based on packets and byte
1621 * counts during the last interrupt. The advantage of per interrupt
1622 * computation is faster updates and more accurate ITR for the current
1623 * traffic pattern. Constants in this function were computed
1624 * based on theoretical maximum wire speed and thresholds were set based
1625 * on testing data as well as attempting to minimize response time
1626 * while increasing bulk throughput.
1627 * this functionality is controlled by the InterruptThrottleRate module
1628 * parameter (see ixgbe_param.c)
1630 static void ixgbe_update_itr(struct ixgbe_q_vector
*q_vector
,
1631 struct ixgbe_ring_container
*ring_container
)
1634 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1635 int bytes
= ring_container
->total_bytes
;
1636 int packets
= ring_container
->total_packets
;
1638 u8 itr_setting
= ring_container
->itr
;
1643 /* simple throttlerate management
1644 * 0-20MB/s lowest (100000 ints/s)
1645 * 20-100MB/s low (20000 ints/s)
1646 * 100-1249MB/s bulk (8000 ints/s)
1648 /* what was last interrupt timeslice? */
1649 timepassed_us
= 1000000/q_vector
->eitr
;
1650 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1652 switch (itr_setting
) {
1653 case lowest_latency
:
1654 if (bytes_perint
> adapter
->eitr_low
)
1655 itr_setting
= low_latency
;
1658 if (bytes_perint
> adapter
->eitr_high
)
1659 itr_setting
= bulk_latency
;
1660 else if (bytes_perint
<= adapter
->eitr_low
)
1661 itr_setting
= lowest_latency
;
1664 if (bytes_perint
<= adapter
->eitr_high
)
1665 itr_setting
= low_latency
;
1669 /* clear work counters since we have the values we need */
1670 ring_container
->total_bytes
= 0;
1671 ring_container
->total_packets
= 0;
1673 /* write updated itr to ring container */
1674 ring_container
->itr
= itr_setting
;
1678 * ixgbe_write_eitr - write EITR register in hardware specific way
1679 * @q_vector: structure containing interrupt and ring information
1681 * This function is made to be called by ethtool and by the driver
1682 * when it needs to update EITR registers at runtime. Hardware
1683 * specific quirks/differences are taken care of here.
1685 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1687 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1688 struct ixgbe_hw
*hw
= &adapter
->hw
;
1689 int v_idx
= q_vector
->v_idx
;
1690 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1692 switch (adapter
->hw
.mac
.type
) {
1693 case ixgbe_mac_82598EB
:
1694 /* must write high and low 16 bits to reset counter */
1695 itr_reg
|= (itr_reg
<< 16);
1697 case ixgbe_mac_82599EB
:
1698 case ixgbe_mac_X540
:
1700 * 82599 and X540 can support a value of zero, so allow it for
1701 * max interrupt rate, but there is an errata where it can
1702 * not be zero with RSC
1705 !(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
1709 * set the WDIS bit to not clear the timer bits and cause an
1710 * immediate assertion of the interrupt
1712 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1717 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1720 static void ixgbe_set_itr(struct ixgbe_q_vector
*q_vector
)
1722 u32 new_itr
= q_vector
->eitr
;
1725 ixgbe_update_itr(q_vector
, &q_vector
->tx
);
1726 ixgbe_update_itr(q_vector
, &q_vector
->rx
);
1728 current_itr
= max(q_vector
->rx
.itr
, q_vector
->tx
.itr
);
1730 switch (current_itr
) {
1731 /* counts and packets in update_itr are dependent on these numbers */
1732 case lowest_latency
:
1736 new_itr
= 20000; /* aka hwitr = ~200 */
1745 if (new_itr
!= q_vector
->eitr
) {
1746 /* do an exponential smoothing */
1747 new_itr
= ((q_vector
->eitr
* 9) + new_itr
)/10;
1749 /* save the algorithm value here */
1750 q_vector
->eitr
= new_itr
;
1752 ixgbe_write_eitr(q_vector
);
1757 * ixgbe_check_overtemp_subtask - check for over tempurature
1758 * @adapter: pointer to adapter
1760 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter
*adapter
)
1762 struct ixgbe_hw
*hw
= &adapter
->hw
;
1763 u32 eicr
= adapter
->interrupt_event
;
1765 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
1768 if (!(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1769 !(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_EVENT
))
1772 adapter
->flags2
&= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
1774 switch (hw
->device_id
) {
1775 case IXGBE_DEV_ID_82599_T3_LOM
:
1777 * Since the warning interrupt is for both ports
1778 * we don't have to check if:
1779 * - This interrupt wasn't for our port.
1780 * - We may have missed the interrupt so always have to
1781 * check if we got a LSC
1783 if (!(eicr
& IXGBE_EICR_GPI_SDP0
) &&
1784 !(eicr
& IXGBE_EICR_LSC
))
1787 if (!(eicr
& IXGBE_EICR_LSC
) && hw
->mac
.ops
.check_link
) {
1789 bool link_up
= false;
1791 hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
1797 /* Check if this is not due to overtemp */
1798 if (hw
->phy
.ops
.check_overtemp(hw
) != IXGBE_ERR_OVERTEMP
)
1803 if (!(eicr
& IXGBE_EICR_GPI_SDP0
))
1808 "Network adapter has been stopped because it has over heated. "
1809 "Restart the computer. If the problem persists, "
1810 "power off the system and replace the adapter\n");
1812 adapter
->interrupt_event
= 0;
1815 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1817 struct ixgbe_hw
*hw
= &adapter
->hw
;
1819 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1820 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1821 e_crit(probe
, "Fan has stopped, replace the adapter\n");
1822 /* write to clear the interrupt */
1823 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1827 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1829 struct ixgbe_hw
*hw
= &adapter
->hw
;
1831 if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1832 /* Clear the interrupt */
1833 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1834 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1835 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
1836 ixgbe_service_event_schedule(adapter
);
1840 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1841 /* Clear the interrupt */
1842 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1843 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1844 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_CONFIG
;
1845 ixgbe_service_event_schedule(adapter
);
1850 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1852 struct ixgbe_hw
*hw
= &adapter
->hw
;
1855 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1856 adapter
->link_check_timeout
= jiffies
;
1857 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1858 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1859 IXGBE_WRITE_FLUSH(hw
);
1860 ixgbe_service_event_schedule(adapter
);
1864 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1866 struct ixgbe_adapter
*adapter
= data
;
1867 struct ixgbe_hw
*hw
= &adapter
->hw
;
1871 * Workaround for Silicon errata. Use clear-by-write instead
1872 * of clear-by-read. Reading with EICS will return the
1873 * interrupt causes without clearing, which later be done
1874 * with the write to EICR.
1876 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1877 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1879 if (eicr
& IXGBE_EICR_LSC
)
1880 ixgbe_check_lsc(adapter
);
1882 if (eicr
& IXGBE_EICR_MAILBOX
)
1883 ixgbe_msg_task(adapter
);
1885 switch (hw
->mac
.type
) {
1886 case ixgbe_mac_82599EB
:
1887 case ixgbe_mac_X540
:
1888 /* Handle Flow Director Full threshold interrupt */
1889 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1890 int reinit_count
= 0;
1892 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1893 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
1894 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE
,
1899 /* no more flow director interrupts until after init */
1900 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_FLOW_DIR
);
1901 eicr
&= ~IXGBE_EICR_FLOW_DIR
;
1902 adapter
->flags2
|= IXGBE_FLAG2_FDIR_REQUIRES_REINIT
;
1903 ixgbe_service_event_schedule(adapter
);
1906 ixgbe_check_sfp_event(adapter
, eicr
);
1907 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1908 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
1909 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1910 adapter
->interrupt_event
= eicr
;
1911 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
1912 ixgbe_service_event_schedule(adapter
);
1920 ixgbe_check_fan_failure(adapter
, eicr
);
1922 /* re-enable the original interrupt state, no lsc, no queues */
1923 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1924 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, eicr
&
1925 ~(IXGBE_EIMS_LSC
| IXGBE_EIMS_RTX_QUEUE
));
1930 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1934 struct ixgbe_hw
*hw
= &adapter
->hw
;
1936 switch (hw
->mac
.type
) {
1937 case ixgbe_mac_82598EB
:
1938 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1939 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, mask
);
1941 case ixgbe_mac_82599EB
:
1942 case ixgbe_mac_X540
:
1943 mask
= (qmask
& 0xFFFFFFFF);
1945 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(0), mask
);
1946 mask
= (qmask
>> 32);
1948 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(1), mask
);
1953 /* skip the flush */
1956 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1960 struct ixgbe_hw
*hw
= &adapter
->hw
;
1962 switch (hw
->mac
.type
) {
1963 case ixgbe_mac_82598EB
:
1964 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1965 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, mask
);
1967 case ixgbe_mac_82599EB
:
1968 case ixgbe_mac_X540
:
1969 mask
= (qmask
& 0xFFFFFFFF);
1971 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(0), mask
);
1972 mask
= (qmask
>> 32);
1974 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(1), mask
);
1979 /* skip the flush */
1982 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1984 struct ixgbe_q_vector
*q_vector
= data
;
1985 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1986 struct ixgbe_ring
*tx_ring
;
1989 if (!q_vector
->tx
.count
)
1992 r_idx
= find_first_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
);
1993 for (i
= 0; i
< q_vector
->tx
.count
; i
++) {
1994 tx_ring
= adapter
->tx_ring
[r_idx
];
1995 r_idx
= find_next_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
,
1999 /* EIAM disabled interrupts (on this vector) for us */
2000 napi_schedule(&q_vector
->napi
);
2006 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2008 * @data: pointer to our q_vector struct for this interrupt vector
2010 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
2012 struct ixgbe_q_vector
*q_vector
= data
;
2013 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2014 struct ixgbe_ring
*rx_ring
;
2018 #ifdef CONFIG_IXGBE_DCA
2019 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2020 ixgbe_update_dca(q_vector
);
2023 r_idx
= find_first_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
);
2024 for (i
= 0; i
< q_vector
->rx
.count
; i
++) {
2025 rx_ring
= adapter
->rx_ring
[r_idx
];
2026 r_idx
= find_next_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
,
2030 if (!q_vector
->rx
.count
)
2033 /* EIAM disabled interrupts (on this vector) for us */
2034 napi_schedule(&q_vector
->napi
);
2039 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
2041 struct ixgbe_q_vector
*q_vector
= data
;
2042 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2043 struct ixgbe_ring
*ring
;
2047 if (!q_vector
->tx
.count
&& !q_vector
->rx
.count
)
2050 r_idx
= find_first_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
);
2051 for (i
= 0; i
< q_vector
->tx
.count
; i
++) {
2052 ring
= adapter
->tx_ring
[r_idx
];
2053 r_idx
= find_next_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
,
2057 r_idx
= find_first_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
);
2058 for (i
= 0; i
< q_vector
->rx
.count
; i
++) {
2059 ring
= adapter
->rx_ring
[r_idx
];
2060 r_idx
= find_next_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
,
2064 /* EIAM disabled interrupts (on this vector) for us */
2065 napi_schedule(&q_vector
->napi
);
2071 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2072 * @napi: napi struct with our devices info in it
2073 * @budget: amount of work driver is allowed to do this pass, in packets
2075 * This function is optimized for cleaning one queue only on a single
2078 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
2080 struct ixgbe_q_vector
*q_vector
=
2081 container_of(napi
, struct ixgbe_q_vector
, napi
);
2082 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2083 struct ixgbe_ring
*rx_ring
= NULL
;
2087 #ifdef CONFIG_IXGBE_DCA
2088 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2089 ixgbe_update_dca(q_vector
);
2092 r_idx
= find_first_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
);
2093 rx_ring
= adapter
->rx_ring
[r_idx
];
2095 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
2097 /* If all Rx work done, exit the polling mode */
2098 if (work_done
< budget
) {
2099 napi_complete(napi
);
2100 if (adapter
->rx_itr_setting
& 1)
2101 ixgbe_set_itr(q_vector
);
2102 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2103 ixgbe_irq_enable_queues(adapter
,
2104 ((u64
)1 << q_vector
->v_idx
));
2111 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2112 * @napi: napi struct with our devices info in it
2113 * @budget: amount of work driver is allowed to do this pass, in packets
2115 * This function will clean more than one rx queue associated with a
2118 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
2120 struct ixgbe_q_vector
*q_vector
=
2121 container_of(napi
, struct ixgbe_q_vector
, napi
);
2122 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2123 struct ixgbe_ring
*ring
= NULL
;
2124 int work_done
= 0, i
;
2126 bool tx_clean_complete
= true;
2128 #ifdef CONFIG_IXGBE_DCA
2129 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2130 ixgbe_update_dca(q_vector
);
2133 r_idx
= find_first_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
);
2134 for (i
= 0; i
< q_vector
->tx
.count
; i
++) {
2135 ring
= adapter
->tx_ring
[r_idx
];
2136 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
2137 r_idx
= find_next_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
,
2141 /* attempt to distribute budget to each queue fairly, but don't allow
2142 * the budget to go below 1 because we'll exit polling */
2143 budget
/= (q_vector
->rx
.count
?: 1);
2144 budget
= max(budget
, 1);
2145 r_idx
= find_first_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
);
2146 for (i
= 0; i
< q_vector
->rx
.count
; i
++) {
2147 ring
= adapter
->rx_ring
[r_idx
];
2148 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
2149 r_idx
= find_next_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
,
2153 r_idx
= find_first_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
);
2154 ring
= adapter
->rx_ring
[r_idx
];
2155 /* If all Rx work done, exit the polling mode */
2156 if (work_done
< budget
) {
2157 napi_complete(napi
);
2158 if (adapter
->rx_itr_setting
& 1)
2159 ixgbe_set_itr(q_vector
);
2160 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2161 ixgbe_irq_enable_queues(adapter
,
2162 ((u64
)1 << q_vector
->v_idx
));
2170 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2171 * @napi: napi struct with our devices info in it
2172 * @budget: amount of work driver is allowed to do this pass, in packets
2174 * This function is optimized for cleaning one queue only on a single
2177 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
2179 struct ixgbe_q_vector
*q_vector
=
2180 container_of(napi
, struct ixgbe_q_vector
, napi
);
2181 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2182 struct ixgbe_ring
*tx_ring
= NULL
;
2186 #ifdef CONFIG_IXGBE_DCA
2187 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2188 ixgbe_update_dca(q_vector
);
2191 r_idx
= find_first_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
);
2192 tx_ring
= adapter
->tx_ring
[r_idx
];
2194 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
2197 /* If all Tx work done, exit the polling mode */
2198 if (work_done
< budget
) {
2199 napi_complete(napi
);
2200 if (adapter
->tx_itr_setting
& 1)
2201 ixgbe_set_itr(q_vector
);
2202 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2203 ixgbe_irq_enable_queues(adapter
,
2204 ((u64
)1 << q_vector
->v_idx
));
2210 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
2213 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2214 struct ixgbe_ring
*rx_ring
= a
->rx_ring
[r_idx
];
2216 set_bit(r_idx
, q_vector
->rx
.idx
);
2217 q_vector
->rx
.count
++;
2218 rx_ring
->q_vector
= q_vector
;
2221 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
2224 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2225 struct ixgbe_ring
*tx_ring
= a
->tx_ring
[t_idx
];
2227 set_bit(t_idx
, q_vector
->tx
.idx
);
2228 q_vector
->tx
.count
++;
2229 tx_ring
->q_vector
= q_vector
;
2230 q_vector
->tx
.work_limit
= a
->tx_work_limit
;
2234 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2235 * @adapter: board private structure to initialize
2237 * This function maps descriptor rings to the queue-specific vectors
2238 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2239 * one vector per ring/queue, but on a constrained vector budget, we
2240 * group the rings as "efficiently" as possible. You would add new
2241 * mapping configurations in here.
2243 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
)
2247 int rxr_idx
= 0, txr_idx
= 0;
2248 int rxr_remaining
= adapter
->num_rx_queues
;
2249 int txr_remaining
= adapter
->num_tx_queues
;
2254 /* No mapping required if MSI-X is disabled. */
2255 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2258 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2261 * The ideal configuration...
2262 * We have enough vectors to map one per queue.
2264 if (q_vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
2265 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
2266 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
2268 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
2269 map_vector_to_txq(adapter
, v_start
, txr_idx
);
2275 * If we don't have enough vectors for a 1-to-1
2276 * mapping, we'll have to group them so there are
2277 * multiple queues per vector.
2279 /* Re-adjusting *qpv takes care of the remainder. */
2280 for (i
= v_start
; i
< q_vectors
; i
++) {
2281 rqpv
= DIV_ROUND_UP(rxr_remaining
, q_vectors
- i
);
2282 for (j
= 0; j
< rqpv
; j
++) {
2283 map_vector_to_rxq(adapter
, i
, rxr_idx
);
2287 tqpv
= DIV_ROUND_UP(txr_remaining
, q_vectors
- i
);
2288 for (j
= 0; j
< tqpv
; j
++) {
2289 map_vector_to_txq(adapter
, i
, txr_idx
);
2299 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2300 * @adapter: board private structure
2302 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2303 * interrupts from the kernel.
2305 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
2307 struct net_device
*netdev
= adapter
->netdev
;
2308 irqreturn_t (*handler
)(int, void *);
2309 int i
, vector
, q_vectors
, err
;
2312 /* Decrement for Other and TCP Timer vectors */
2313 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2315 err
= ixgbe_map_rings_to_vectors(adapter
);
2319 #define SET_HANDLER(_v) (((_v)->rx.count && (_v)->tx.count) \
2320 ? &ixgbe_msix_clean_many : \
2321 (_v)->rx.count ? &ixgbe_msix_clean_rx : \
2322 (_v)->tx.count ? &ixgbe_msix_clean_tx : \
2324 for (vector
= 0; vector
< q_vectors
; vector
++) {
2325 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[vector
];
2326 handler
= SET_HANDLER(q_vector
);
2328 if (handler
== &ixgbe_msix_clean_rx
) {
2329 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2330 "%s-%s-%d", netdev
->name
, "rx", ri
++);
2331 } else if (handler
== &ixgbe_msix_clean_tx
) {
2332 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2333 "%s-%s-%d", netdev
->name
, "tx", ti
++);
2334 } else if (handler
== &ixgbe_msix_clean_many
) {
2335 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2336 "%s-%s-%d", netdev
->name
, "TxRx", ri
++);
2339 /* skip this unused q_vector */
2342 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2343 handler
, 0, q_vector
->name
,
2346 e_err(probe
, "request_irq failed for MSIX interrupt "
2347 "Error: %d\n", err
);
2348 goto free_queue_irqs
;
2352 sprintf(adapter
->lsc_int_name
, "%s:lsc", netdev
->name
);
2353 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2354 ixgbe_msix_lsc
, 0, adapter
->lsc_int_name
, adapter
);
2356 e_err(probe
, "request_irq for msix_lsc failed: %d\n", err
);
2357 goto free_queue_irqs
;
2363 for (i
= vector
- 1; i
>= 0; i
--)
2364 free_irq(adapter
->msix_entries
[--vector
].vector
,
2365 adapter
->q_vector
[i
]);
2366 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2367 pci_disable_msix(adapter
->pdev
);
2368 kfree(adapter
->msix_entries
);
2369 adapter
->msix_entries
= NULL
;
2374 * ixgbe_irq_enable - Enable default interrupt generation settings
2375 * @adapter: board private structure
2377 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
, bool queues
,
2382 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
2383 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
2384 mask
|= IXGBE_EIMS_GPI_SDP0
;
2385 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
2386 mask
|= IXGBE_EIMS_GPI_SDP1
;
2387 switch (adapter
->hw
.mac
.type
) {
2388 case ixgbe_mac_82599EB
:
2389 case ixgbe_mac_X540
:
2390 mask
|= IXGBE_EIMS_ECC
;
2391 mask
|= IXGBE_EIMS_GPI_SDP1
;
2392 mask
|= IXGBE_EIMS_GPI_SDP2
;
2393 if (adapter
->num_vfs
)
2394 mask
|= IXGBE_EIMS_MAILBOX
;
2399 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)
2400 mask
|= IXGBE_EIMS_FLOW_DIR
;
2402 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
2404 ixgbe_irq_enable_queues(adapter
, ~0);
2406 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2408 if (adapter
->num_vfs
> 32) {
2409 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
2410 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
2415 * ixgbe_intr - legacy mode Interrupt Handler
2416 * @irq: interrupt number
2417 * @data: pointer to a network interface device structure
2419 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
2421 struct ixgbe_adapter
*adapter
= data
;
2422 struct ixgbe_hw
*hw
= &adapter
->hw
;
2423 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2427 * Workaround for silicon errata on 82598. Mask the interrupts
2428 * before the read of EICR.
2430 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
2432 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2433 * therefore no explict interrupt disable is necessary */
2434 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
2437 * shared interrupt alert!
2438 * make sure interrupts are enabled because the read will
2439 * have disabled interrupts due to EIAM
2440 * finish the workaround of silicon errata on 82598. Unmask
2441 * the interrupt that we masked before the EICR read.
2443 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2444 ixgbe_irq_enable(adapter
, true, true);
2445 return IRQ_NONE
; /* Not our interrupt */
2448 if (eicr
& IXGBE_EICR_LSC
)
2449 ixgbe_check_lsc(adapter
);
2451 switch (hw
->mac
.type
) {
2452 case ixgbe_mac_82599EB
:
2453 ixgbe_check_sfp_event(adapter
, eicr
);
2454 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
2455 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
2456 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
2457 adapter
->interrupt_event
= eicr
;
2458 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
2459 ixgbe_service_event_schedule(adapter
);
2467 ixgbe_check_fan_failure(adapter
, eicr
);
2469 if (napi_schedule_prep(&(q_vector
->napi
))) {
2470 /* would disable interrupts here but EIAM disabled it */
2471 __napi_schedule(&(q_vector
->napi
));
2475 * re-enable link(maybe) and non-queue interrupts, no flush.
2476 * ixgbe_poll will re-enable the queue interrupts
2479 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2480 ixgbe_irq_enable(adapter
, false, false);
2485 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
2487 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2489 for (i
= 0; i
< q_vectors
; i
++) {
2490 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
2491 bitmap_zero(q_vector
->rx
.idx
, MAX_RX_QUEUES
);
2492 bitmap_zero(q_vector
->tx
.idx
, MAX_TX_QUEUES
);
2493 q_vector
->rx
.count
= 0;
2494 q_vector
->tx
.count
= 0;
2499 * ixgbe_request_irq - initialize interrupts
2500 * @adapter: board private structure
2502 * Attempts to configure interrupts using the best available
2503 * capabilities of the hardware and kernel.
2505 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
2507 struct net_device
*netdev
= adapter
->netdev
;
2510 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2511 err
= ixgbe_request_msix_irqs(adapter
);
2512 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
2513 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
2514 netdev
->name
, adapter
);
2516 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
2517 netdev
->name
, adapter
);
2521 e_err(probe
, "request_irq failed, Error %d\n", err
);
2526 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
2528 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2531 q_vectors
= adapter
->num_msix_vectors
;
2534 free_irq(adapter
->msix_entries
[i
].vector
, adapter
);
2537 for (; i
>= 0; i
--) {
2538 /* free only the irqs that were actually requested */
2539 if (!adapter
->q_vector
[i
]->rx
.count
&&
2540 !adapter
->q_vector
[i
]->tx
.count
)
2543 free_irq(adapter
->msix_entries
[i
].vector
,
2544 adapter
->q_vector
[i
]);
2547 ixgbe_reset_q_vectors(adapter
);
2549 free_irq(adapter
->pdev
->irq
, adapter
);
2554 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2555 * @adapter: board private structure
2557 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
2559 switch (adapter
->hw
.mac
.type
) {
2560 case ixgbe_mac_82598EB
:
2561 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2563 case ixgbe_mac_82599EB
:
2564 case ixgbe_mac_X540
:
2565 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2566 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2567 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2568 if (adapter
->num_vfs
> 32)
2569 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
2574 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2575 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2577 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2578 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2580 synchronize_irq(adapter
->pdev
->irq
);
2585 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2588 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2590 struct ixgbe_hw
*hw
= &adapter
->hw
;
2592 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2593 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2595 ixgbe_set_ivar(adapter
, 0, 0, 0);
2596 ixgbe_set_ivar(adapter
, 1, 0, 0);
2598 map_vector_to_rxq(adapter
, 0, 0);
2599 map_vector_to_txq(adapter
, 0, 0);
2601 e_info(hw
, "Legacy interrupt IVAR setup done\n");
2605 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2606 * @adapter: board private structure
2607 * @ring: structure containing ring specific data
2609 * Configure the Tx descriptor ring after a reset.
2611 void ixgbe_configure_tx_ring(struct ixgbe_adapter
*adapter
,
2612 struct ixgbe_ring
*ring
)
2614 struct ixgbe_hw
*hw
= &adapter
->hw
;
2615 u64 tdba
= ring
->dma
;
2618 u8 reg_idx
= ring
->reg_idx
;
2620 /* disable queue to avoid issues while updating state */
2621 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2622 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
),
2623 txdctl
& ~IXGBE_TXDCTL_ENABLE
);
2624 IXGBE_WRITE_FLUSH(hw
);
2626 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(reg_idx
),
2627 (tdba
& DMA_BIT_MASK(32)));
2628 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(reg_idx
), (tdba
>> 32));
2629 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(reg_idx
),
2630 ring
->count
* sizeof(union ixgbe_adv_tx_desc
));
2631 IXGBE_WRITE_REG(hw
, IXGBE_TDH(reg_idx
), 0);
2632 IXGBE_WRITE_REG(hw
, IXGBE_TDT(reg_idx
), 0);
2633 ring
->tail
= hw
->hw_addr
+ IXGBE_TDT(reg_idx
);
2635 /* configure fetching thresholds */
2636 if (adapter
->rx_itr_setting
== 0) {
2637 /* cannot set wthresh when itr==0 */
2638 txdctl
&= ~0x007F0000;
2640 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2641 txdctl
|= (8 << 16);
2643 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2644 /* PThresh workaround for Tx hang with DFP enabled. */
2648 /* reinitialize flowdirector state */
2649 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) &&
2650 adapter
->atr_sample_rate
) {
2651 ring
->atr_sample_rate
= adapter
->atr_sample_rate
;
2652 ring
->atr_count
= 0;
2653 set_bit(__IXGBE_TX_FDIR_INIT_DONE
, &ring
->state
);
2655 ring
->atr_sample_rate
= 0;
2658 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &ring
->state
);
2661 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2662 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), txdctl
);
2664 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2665 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2666 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2669 /* poll to verify queue is enabled */
2671 usleep_range(1000, 2000);
2672 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2673 } while (--wait_loop
&& !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2675 e_err(drv
, "Could not enable Tx Queue %d\n", reg_idx
);
2678 static void ixgbe_setup_mtqc(struct ixgbe_adapter
*adapter
)
2680 struct ixgbe_hw
*hw
= &adapter
->hw
;
2683 u8 tcs
= netdev_get_num_tc(adapter
->netdev
);
2685 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2688 /* disable the arbiter while setting MTQC */
2689 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2690 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2691 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2693 /* set transmit pool layout */
2694 switch (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2695 case (IXGBE_FLAG_SRIOV_ENABLED
):
2696 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2697 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2701 reg
= IXGBE_MTQC_64Q_1PB
;
2703 reg
= IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_4TC_4TQ
;
2705 reg
= IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
;
2707 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, reg
);
2709 /* Enable Security TX Buffer IFG for multiple pb */
2711 reg
= IXGBE_READ_REG(hw
, IXGBE_SECTXMINIFG
);
2712 reg
|= IXGBE_SECTX_DCB
;
2713 IXGBE_WRITE_REG(hw
, IXGBE_SECTXMINIFG
, reg
);
2718 /* re-enable the arbiter */
2719 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2720 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2724 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2725 * @adapter: board private structure
2727 * Configure the Tx unit of the MAC after a reset.
2729 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2731 struct ixgbe_hw
*hw
= &adapter
->hw
;
2735 ixgbe_setup_mtqc(adapter
);
2737 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
2738 /* DMATXCTL.EN must be before Tx queues are enabled */
2739 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2740 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2741 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2744 /* Setup the HW Tx Head and Tail descriptor pointers */
2745 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2746 ixgbe_configure_tx_ring(adapter
, adapter
->tx_ring
[i
]);
2749 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2751 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2752 struct ixgbe_ring
*rx_ring
)
2755 u8 reg_idx
= rx_ring
->reg_idx
;
2757 switch (adapter
->hw
.mac
.type
) {
2758 case ixgbe_mac_82598EB
: {
2759 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2760 const int mask
= feature
[RING_F_RSS
].mask
;
2761 reg_idx
= reg_idx
& mask
;
2764 case ixgbe_mac_82599EB
:
2765 case ixgbe_mac_X540
:
2770 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
));
2772 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2773 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2774 if (adapter
->num_vfs
)
2775 srrctl
|= IXGBE_SRRCTL_DROP_EN
;
2777 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2778 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2780 if (ring_is_ps_enabled(rx_ring
)) {
2781 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2782 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2784 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2786 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2788 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2789 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2790 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2793 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
), srrctl
);
2796 static void ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2798 struct ixgbe_hw
*hw
= &adapter
->hw
;
2799 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2800 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2801 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2802 u32 mrqc
= 0, reta
= 0;
2805 u8 tcs
= netdev_get_num_tc(adapter
->netdev
);
2806 int maxq
= adapter
->ring_feature
[RING_F_RSS
].indices
;
2809 maxq
= min(maxq
, adapter
->num_tx_queues
/ tcs
);
2811 /* Fill out hash function seeds */
2812 for (i
= 0; i
< 10; i
++)
2813 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2815 /* Fill out redirection table */
2816 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2819 /* reta = 4-byte sliding window of
2820 * 0x00..(indices-1)(indices-1)00..etc. */
2821 reta
= (reta
<< 8) | (j
* 0x11);
2823 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2826 /* Disable indicating checksum in descriptor, enables RSS hash */
2827 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2828 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2829 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2831 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
&&
2832 (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)) {
2833 mrqc
= IXGBE_MRQC_RSSEN
;
2835 int mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2836 | IXGBE_FLAG_SRIOV_ENABLED
);
2839 case (IXGBE_FLAG_RSS_ENABLED
):
2841 mrqc
= IXGBE_MRQC_RSSEN
;
2843 mrqc
= IXGBE_MRQC_RTRSS4TCEN
;
2845 mrqc
= IXGBE_MRQC_RTRSS8TCEN
;
2847 case (IXGBE_FLAG_SRIOV_ENABLED
):
2848 mrqc
= IXGBE_MRQC_VMDQEN
;
2855 /* Perform hash on these packet types */
2856 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2857 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2858 | IXGBE_MRQC_RSS_FIELD_IPV6
2859 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
;
2861 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2865 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2866 * @adapter: address of board private structure
2867 * @index: index of ring to set
2869 static void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
,
2870 struct ixgbe_ring
*ring
)
2872 struct ixgbe_hw
*hw
= &adapter
->hw
;
2875 u8 reg_idx
= ring
->reg_idx
;
2877 if (!ring_is_rsc_enabled(ring
))
2880 rx_buf_len
= ring
->rx_buf_len
;
2881 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
2882 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2884 * we must limit the number of descriptors so that the
2885 * total size of max desc * buf_len is not greater
2888 if (ring_is_ps_enabled(ring
)) {
2889 #if (MAX_SKB_FRAGS > 16)
2890 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2891 #elif (MAX_SKB_FRAGS > 8)
2892 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2893 #elif (MAX_SKB_FRAGS > 4)
2894 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2896 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2899 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2900 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2901 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2902 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2904 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2906 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
2910 * ixgbe_set_uta - Set unicast filter table address
2911 * @adapter: board private structure
2913 * The unicast table address is a register array of 32-bit registers.
2914 * The table is meant to be used in a way similar to how the MTA is used
2915 * however due to certain limitations in the hardware it is necessary to
2916 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2917 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2919 static void ixgbe_set_uta(struct ixgbe_adapter
*adapter
)
2921 struct ixgbe_hw
*hw
= &adapter
->hw
;
2924 /* The UTA table only exists on 82599 hardware and newer */
2925 if (hw
->mac
.type
< ixgbe_mac_82599EB
)
2928 /* we only need to do this if VMDq is enabled */
2929 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
2932 for (i
= 0; i
< 128; i
++)
2933 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), ~0);
2936 #define IXGBE_MAX_RX_DESC_POLL 10
2937 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
2938 struct ixgbe_ring
*ring
)
2940 struct ixgbe_hw
*hw
= &adapter
->hw
;
2941 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
2943 u8 reg_idx
= ring
->reg_idx
;
2945 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2946 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2947 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2951 usleep_range(1000, 2000);
2952 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2953 } while (--wait_loop
&& !(rxdctl
& IXGBE_RXDCTL_ENABLE
));
2956 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not set within "
2957 "the polling period\n", reg_idx
);
2961 void ixgbe_disable_rx_queue(struct ixgbe_adapter
*adapter
,
2962 struct ixgbe_ring
*ring
)
2964 struct ixgbe_hw
*hw
= &adapter
->hw
;
2965 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
2967 u8 reg_idx
= ring
->reg_idx
;
2969 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2970 rxdctl
&= ~IXGBE_RXDCTL_ENABLE
;
2972 /* write value back with RXDCTL.ENABLE bit cleared */
2973 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
2975 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2976 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2979 /* the hardware may take up to 100us to really disable the rx queue */
2982 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2983 } while (--wait_loop
&& (rxdctl
& IXGBE_RXDCTL_ENABLE
));
2986 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2987 "the polling period\n", reg_idx
);
2991 void ixgbe_configure_rx_ring(struct ixgbe_adapter
*adapter
,
2992 struct ixgbe_ring
*ring
)
2994 struct ixgbe_hw
*hw
= &adapter
->hw
;
2995 u64 rdba
= ring
->dma
;
2997 u8 reg_idx
= ring
->reg_idx
;
2999 /* disable queue to avoid issues while updating state */
3000 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3001 ixgbe_disable_rx_queue(adapter
, ring
);
3003 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(reg_idx
), (rdba
& DMA_BIT_MASK(32)));
3004 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(reg_idx
), (rdba
>> 32));
3005 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(reg_idx
),
3006 ring
->count
* sizeof(union ixgbe_adv_rx_desc
));
3007 IXGBE_WRITE_REG(hw
, IXGBE_RDH(reg_idx
), 0);
3008 IXGBE_WRITE_REG(hw
, IXGBE_RDT(reg_idx
), 0);
3009 ring
->tail
= hw
->hw_addr
+ IXGBE_RDT(reg_idx
);
3011 ixgbe_configure_srrctl(adapter
, ring
);
3012 ixgbe_configure_rscctl(adapter
, ring
);
3014 /* If operating in IOV mode set RLPML for X540 */
3015 if ((adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) &&
3016 hw
->mac
.type
== ixgbe_mac_X540
) {
3017 rxdctl
&= ~IXGBE_RXDCTL_RLPMLMASK
;
3018 rxdctl
|= ((ring
->netdev
->mtu
+ ETH_HLEN
+
3019 ETH_FCS_LEN
+ VLAN_HLEN
) | IXGBE_RXDCTL_RLPML_EN
);
3022 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
3024 * enable cache line friendly hardware writes:
3025 * PTHRESH=32 descriptors (half the internal cache),
3026 * this also removes ugly rx_no_buffer_count increment
3027 * HTHRESH=4 descriptors (to minimize latency on fetch)
3028 * WTHRESH=8 burst writeback up to two cache lines
3030 rxdctl
&= ~0x3FFFFF;
3034 /* enable receive descriptor ring */
3035 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
3036 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
3038 ixgbe_rx_desc_queue_enable(adapter
, ring
);
3039 ixgbe_alloc_rx_buffers(ring
, ixgbe_desc_unused(ring
));
3042 static void ixgbe_setup_psrtype(struct ixgbe_adapter
*adapter
)
3044 struct ixgbe_hw
*hw
= &adapter
->hw
;
3047 /* PSRTYPE must be initialized in non 82598 adapters */
3048 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
3049 IXGBE_PSRTYPE_UDPHDR
|
3050 IXGBE_PSRTYPE_IPV4HDR
|
3051 IXGBE_PSRTYPE_L2HDR
|
3052 IXGBE_PSRTYPE_IPV6HDR
;
3054 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3057 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)
3058 psrtype
|= (adapter
->num_rx_queues_per_pool
<< 29);
3060 for (p
= 0; p
< adapter
->num_rx_pools
; p
++)
3061 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(adapter
->num_vfs
+ p
),
3065 static void ixgbe_configure_virtualization(struct ixgbe_adapter
*adapter
)
3067 struct ixgbe_hw
*hw
= &adapter
->hw
;
3070 u32 reg_offset
, vf_shift
;
3073 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
3076 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
3077 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
| IXGBE_VT_CTL_REPLEN
;
3078 vt_reg_bits
|= (adapter
->num_vfs
<< IXGBE_VT_CTL_POOL_SHIFT
);
3079 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
3081 vf_shift
= adapter
->num_vfs
% 32;
3082 reg_offset
= (adapter
->num_vfs
> 32) ? 1 : 0;
3084 /* Enable only the PF's pool for Tx/Rx */
3085 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
3086 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
^ 1), 0);
3087 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
3088 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
^ 1), 0);
3089 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
3091 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3092 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
3095 * Set up VF register offsets for selected VT Mode,
3096 * i.e. 32 or 64 VFs for SR-IOV
3098 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
3099 gcr_ext
|= IXGBE_GCR_EXT_MSIX_EN
;
3100 gcr_ext
|= IXGBE_GCR_EXT_VT_MODE_64
;
3101 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
3103 /* enable Tx loopback for VF/PF communication */
3104 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
3105 /* Enable MAC Anti-Spoofing */
3106 hw
->mac
.ops
.set_mac_anti_spoofing(hw
,
3107 (adapter
->antispoofing_enabled
=
3108 (adapter
->num_vfs
!= 0)),
3112 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter
*adapter
)
3114 struct ixgbe_hw
*hw
= &adapter
->hw
;
3115 struct net_device
*netdev
= adapter
->netdev
;
3116 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3118 struct ixgbe_ring
*rx_ring
;
3122 /* Decide whether to use packet split mode or not */
3124 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
3126 /* Do not use packet split if we're in SR-IOV Mode */
3127 if (adapter
->num_vfs
)
3128 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
3130 /* Disable packet split due to 82599 erratum #45 */
3131 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3132 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
3134 /* Set the RX buffer length according to the mode */
3135 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
3136 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
3138 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
3139 (netdev
->mtu
<= ETH_DATA_LEN
))
3140 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
3142 rx_buf_len
= ALIGN(max_frame
+ VLAN_HLEN
, 1024);
3146 /* adjust max frame to be able to do baby jumbo for FCoE */
3147 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
3148 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
3149 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3151 #endif /* IXGBE_FCOE */
3152 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
3153 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
3154 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
3155 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
3157 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
3160 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
3161 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3162 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
3163 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
3166 * Setup the HW Rx Head and Tail Descriptor Pointers and
3167 * the Base and Length of the Rx Descriptor Ring
3169 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3170 rx_ring
= adapter
->rx_ring
[i
];
3171 rx_ring
->rx_buf_len
= rx_buf_len
;
3173 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
3174 set_ring_ps_enabled(rx_ring
);
3176 clear_ring_ps_enabled(rx_ring
);
3178 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
3179 set_ring_rsc_enabled(rx_ring
);
3181 clear_ring_rsc_enabled(rx_ring
);
3184 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
3185 struct ixgbe_ring_feature
*f
;
3186 f
= &adapter
->ring_feature
[RING_F_FCOE
];
3187 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
3188 clear_ring_ps_enabled(rx_ring
);
3189 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
3190 rx_ring
->rx_buf_len
=
3191 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3192 } else if (!ring_is_rsc_enabled(rx_ring
) &&
3193 !ring_is_ps_enabled(rx_ring
)) {
3194 rx_ring
->rx_buf_len
=
3195 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3198 #endif /* IXGBE_FCOE */
3202 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter
*adapter
)
3204 struct ixgbe_hw
*hw
= &adapter
->hw
;
3205 u32 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
3207 switch (hw
->mac
.type
) {
3208 case ixgbe_mac_82598EB
:
3210 * For VMDq support of different descriptor types or
3211 * buffer sizes through the use of multiple SRRCTL
3212 * registers, RDRXCTL.MVMEN must be set to 1
3214 * also, the manual doesn't mention it clearly but DCA hints
3215 * will only use queue 0's tags unless this bit is set. Side
3216 * effects of setting this bit are only that SRRCTL must be
3217 * fully programmed [0..15]
3219 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
3221 case ixgbe_mac_82599EB
:
3222 case ixgbe_mac_X540
:
3223 /* Disable RSC for ACK packets */
3224 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
3225 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
3226 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
3227 /* hardware requires some bits to be set by default */
3228 rdrxctl
|= (IXGBE_RDRXCTL_RSCACKC
| IXGBE_RDRXCTL_FCOE_WRFIX
);
3229 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
3232 /* We should do nothing since we don't know this hardware */
3236 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
3240 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3241 * @adapter: board private structure
3243 * Configure the Rx unit of the MAC after a reset.
3245 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
3247 struct ixgbe_hw
*hw
= &adapter
->hw
;
3251 /* disable receives while setting up the descriptors */
3252 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3253 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3255 ixgbe_setup_psrtype(adapter
);
3256 ixgbe_setup_rdrxctl(adapter
);
3258 /* Program registers for the distribution of queues */
3259 ixgbe_setup_mrqc(adapter
);
3261 ixgbe_set_uta(adapter
);
3263 /* set_rx_buffer_len must be called before ring initialization */
3264 ixgbe_set_rx_buffer_len(adapter
);
3267 * Setup the HW Rx Head and Tail Descriptor Pointers and
3268 * the Base and Length of the Rx Descriptor Ring
3270 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3271 ixgbe_configure_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3273 /* disable drop enable for 82598 parts */
3274 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3275 rxctrl
|= IXGBE_RXCTRL_DMBYPS
;
3277 /* enable all receives */
3278 rxctrl
|= IXGBE_RXCTRL_RXEN
;
3279 hw
->mac
.ops
.enable_rx_dma(hw
, rxctrl
);
3282 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
3284 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3285 struct ixgbe_hw
*hw
= &adapter
->hw
;
3286 int pool_ndx
= adapter
->num_vfs
;
3288 /* add VID to filter table */
3289 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
3290 set_bit(vid
, adapter
->active_vlans
);
3293 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
3295 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3296 struct ixgbe_hw
*hw
= &adapter
->hw
;
3297 int pool_ndx
= adapter
->num_vfs
;
3299 /* remove VID from filter table */
3300 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
3301 clear_bit(vid
, adapter
->active_vlans
);
3305 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3306 * @adapter: driver data
3308 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
3310 struct ixgbe_hw
*hw
= &adapter
->hw
;
3313 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3314 vlnctrl
&= ~(IXGBE_VLNCTRL_VFE
| IXGBE_VLNCTRL_CFIEN
);
3315 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3319 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3320 * @adapter: driver data
3322 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
3324 struct ixgbe_hw
*hw
= &adapter
->hw
;
3327 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3328 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
3329 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
3330 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3334 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3335 * @adapter: driver data
3337 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter
*adapter
)
3339 struct ixgbe_hw
*hw
= &adapter
->hw
;
3343 switch (hw
->mac
.type
) {
3344 case ixgbe_mac_82598EB
:
3345 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3346 vlnctrl
&= ~IXGBE_VLNCTRL_VME
;
3347 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3349 case ixgbe_mac_82599EB
:
3350 case ixgbe_mac_X540
:
3351 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3352 j
= adapter
->rx_ring
[i
]->reg_idx
;
3353 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3354 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
3355 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3364 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3365 * @adapter: driver data
3367 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter
*adapter
)
3369 struct ixgbe_hw
*hw
= &adapter
->hw
;
3373 switch (hw
->mac
.type
) {
3374 case ixgbe_mac_82598EB
:
3375 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3376 vlnctrl
|= IXGBE_VLNCTRL_VME
;
3377 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3379 case ixgbe_mac_82599EB
:
3380 case ixgbe_mac_X540
:
3381 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3382 j
= adapter
->rx_ring
[i
]->reg_idx
;
3383 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3384 vlnctrl
|= IXGBE_RXDCTL_VME
;
3385 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3393 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
3397 ixgbe_vlan_rx_add_vid(adapter
->netdev
, 0);
3399 for_each_set_bit(vid
, adapter
->active_vlans
, VLAN_N_VID
)
3400 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
3404 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3405 * @netdev: network interface device structure
3407 * Writes unicast address list to the RAR table.
3408 * Returns: -ENOMEM on failure/insufficient address space
3409 * 0 on no addresses written
3410 * X on writing X addresses to the RAR table
3412 static int ixgbe_write_uc_addr_list(struct net_device
*netdev
)
3414 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3415 struct ixgbe_hw
*hw
= &adapter
->hw
;
3416 unsigned int vfn
= adapter
->num_vfs
;
3417 unsigned int rar_entries
= IXGBE_MAX_PF_MACVLANS
;
3420 /* return ENOMEM indicating insufficient memory for addresses */
3421 if (netdev_uc_count(netdev
) > rar_entries
)
3424 if (!netdev_uc_empty(netdev
) && rar_entries
) {
3425 struct netdev_hw_addr
*ha
;
3426 /* return error if we do not support writing to RAR table */
3427 if (!hw
->mac
.ops
.set_rar
)
3430 netdev_for_each_uc_addr(ha
, netdev
) {
3433 hw
->mac
.ops
.set_rar(hw
, rar_entries
--, ha
->addr
,
3438 /* write the addresses in reverse order to avoid write combining */
3439 for (; rar_entries
> 0 ; rar_entries
--)
3440 hw
->mac
.ops
.clear_rar(hw
, rar_entries
);
3446 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3447 * @netdev: network interface device structure
3449 * The set_rx_method entry point is called whenever the unicast/multicast
3450 * address list or the network interface flags are updated. This routine is
3451 * responsible for configuring the hardware for proper unicast, multicast and
3454 void ixgbe_set_rx_mode(struct net_device
*netdev
)
3456 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3457 struct ixgbe_hw
*hw
= &adapter
->hw
;
3458 u32 fctrl
, vmolr
= IXGBE_VMOLR_BAM
| IXGBE_VMOLR_AUPE
;
3461 /* Check for Promiscuous and All Multicast modes */
3463 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
3465 /* set all bits that we expect to always be set */
3466 fctrl
|= IXGBE_FCTRL_BAM
;
3467 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
3468 fctrl
|= IXGBE_FCTRL_PMCF
;
3470 /* clear the bits we are changing the status of */
3471 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3473 if (netdev
->flags
& IFF_PROMISC
) {
3474 hw
->addr_ctrl
.user_set_promisc
= true;
3475 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3476 vmolr
|= (IXGBE_VMOLR_ROPE
| IXGBE_VMOLR_MPE
);
3477 /* don't hardware filter vlans in promisc mode */
3478 ixgbe_vlan_filter_disable(adapter
);
3480 if (netdev
->flags
& IFF_ALLMULTI
) {
3481 fctrl
|= IXGBE_FCTRL_MPE
;
3482 vmolr
|= IXGBE_VMOLR_MPE
;
3485 * Write addresses to the MTA, if the attempt fails
3486 * then we should just turn on promiscuous mode so
3487 * that we can at least receive multicast traffic
3489 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
3490 vmolr
|= IXGBE_VMOLR_ROMPE
;
3492 ixgbe_vlan_filter_enable(adapter
);
3493 hw
->addr_ctrl
.user_set_promisc
= false;
3495 * Write addresses to available RAR registers, if there is not
3496 * sufficient space to store all the addresses then enable
3497 * unicast promiscuous mode
3499 count
= ixgbe_write_uc_addr_list(netdev
);
3501 fctrl
|= IXGBE_FCTRL_UPE
;
3502 vmolr
|= IXGBE_VMOLR_ROPE
;
3506 if (adapter
->num_vfs
) {
3507 ixgbe_restore_vf_multicasts(adapter
);
3508 vmolr
|= IXGBE_READ_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
)) &
3509 ~(IXGBE_VMOLR_MPE
| IXGBE_VMOLR_ROMPE
|
3511 IXGBE_WRITE_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
), vmolr
);
3514 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
3516 if (netdev
->features
& NETIF_F_HW_VLAN_RX
)
3517 ixgbe_vlan_strip_enable(adapter
);
3519 ixgbe_vlan_strip_disable(adapter
);
3522 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
3525 struct ixgbe_q_vector
*q_vector
;
3526 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3528 /* legacy and MSI only use one vector */
3529 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3532 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3533 struct napi_struct
*napi
;
3534 q_vector
= adapter
->q_vector
[q_idx
];
3535 napi
= &q_vector
->napi
;
3536 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3537 if (!q_vector
->rx
.count
|| !q_vector
->tx
.count
) {
3538 if (q_vector
->tx
.count
== 1)
3539 napi
->poll
= &ixgbe_clean_txonly
;
3540 else if (q_vector
->rx
.count
== 1)
3541 napi
->poll
= &ixgbe_clean_rxonly
;
3549 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
3552 struct ixgbe_q_vector
*q_vector
;
3553 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3555 /* legacy and MSI only use one vector */
3556 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3559 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3560 q_vector
= adapter
->q_vector
[q_idx
];
3561 napi_disable(&q_vector
->napi
);
3565 #ifdef CONFIG_IXGBE_DCB
3567 * ixgbe_configure_dcb - Configure DCB hardware
3568 * @adapter: ixgbe adapter struct
3570 * This is called by the driver on open to configure the DCB hardware.
3571 * This is also called by the gennetlink interface when reconfiguring
3574 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
3576 struct ixgbe_hw
*hw
= &adapter
->hw
;
3577 int max_frame
= adapter
->netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3579 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)) {
3580 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3581 netif_set_gso_max_size(adapter
->netdev
, 65536);
3585 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3586 netif_set_gso_max_size(adapter
->netdev
, 32768);
3589 /* Enable VLAN tag insert/strip */
3590 adapter
->netdev
->features
|= NETIF_F_HW_VLAN_RX
;
3592 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
3594 /* reconfigure the hardware */
3595 if (adapter
->dcbx_cap
& DCB_CAP_DCBX_VER_CEE
) {
3597 if (adapter
->netdev
->features
& NETIF_F_FCOE_MTU
)
3598 max_frame
= max(max_frame
, IXGBE_FCOE_JUMBO_FRAME_SIZE
);
3600 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3602 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3604 ixgbe_dcb_hw_config(hw
, &adapter
->dcb_cfg
);
3606 struct net_device
*dev
= adapter
->netdev
;
3608 if (adapter
->ixgbe_ieee_ets
)
3609 dev
->dcbnl_ops
->ieee_setets(dev
,
3610 adapter
->ixgbe_ieee_ets
);
3611 if (adapter
->ixgbe_ieee_pfc
)
3612 dev
->dcbnl_ops
->ieee_setpfc(dev
,
3613 adapter
->ixgbe_ieee_pfc
);
3616 /* Enable RSS Hash per TC */
3617 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
3621 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
3623 u8 cnt
= adapter
->netdev
->tc_to_txq
[i
].count
;
3628 reg
|= msb
<< IXGBE_RQTC_SHIFT_TC(i
);
3630 IXGBE_WRITE_REG(hw
, IXGBE_RQTC
, reg
);
3636 static void ixgbe_configure_pb(struct ixgbe_adapter
*adapter
)
3639 int num_tc
= netdev_get_num_tc(adapter
->netdev
);
3640 struct ixgbe_hw
*hw
= &adapter
->hw
;
3642 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3643 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3644 hdrm
= 64 << adapter
->fdir_pballoc
;
3646 hw
->mac
.ops
.set_rxpba(&adapter
->hw
, num_tc
, hdrm
, PBA_STRATEGY_EQUAL
);
3649 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter
*adapter
)
3651 struct ixgbe_hw
*hw
= &adapter
->hw
;
3652 struct hlist_node
*node
, *node2
;
3653 struct ixgbe_fdir_filter
*filter
;
3655 spin_lock(&adapter
->fdir_perfect_lock
);
3657 if (!hlist_empty(&adapter
->fdir_filter_list
))
3658 ixgbe_fdir_set_input_mask_82599(hw
, &adapter
->fdir_mask
);
3660 hlist_for_each_entry_safe(filter
, node
, node2
,
3661 &adapter
->fdir_filter_list
, fdir_node
) {
3662 ixgbe_fdir_write_perfect_filter_82599(hw
,
3665 (filter
->action
== IXGBE_FDIR_DROP_QUEUE
) ?
3666 IXGBE_FDIR_DROP_QUEUE
:
3667 adapter
->rx_ring
[filter
->action
]->reg_idx
);
3670 spin_unlock(&adapter
->fdir_perfect_lock
);
3673 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
3675 struct net_device
*netdev
= adapter
->netdev
;
3676 struct ixgbe_hw
*hw
= &adapter
->hw
;
3679 ixgbe_configure_pb(adapter
);
3680 #ifdef CONFIG_IXGBE_DCB
3681 ixgbe_configure_dcb(adapter
);
3684 ixgbe_set_rx_mode(netdev
);
3685 ixgbe_restore_vlan(adapter
);
3688 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
3689 ixgbe_configure_fcoe(adapter
);
3691 #endif /* IXGBE_FCOE */
3692 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
3693 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3694 adapter
->tx_ring
[i
]->atr_sample_rate
=
3695 adapter
->atr_sample_rate
;
3696 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
3697 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
3698 ixgbe_init_fdir_perfect_82599(&adapter
->hw
,
3699 adapter
->fdir_pballoc
);
3700 ixgbe_fdir_filter_restore(adapter
);
3702 ixgbe_configure_virtualization(adapter
);
3704 ixgbe_configure_tx(adapter
);
3705 ixgbe_configure_rx(adapter
);
3708 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
3710 switch (hw
->phy
.type
) {
3711 case ixgbe_phy_sfp_avago
:
3712 case ixgbe_phy_sfp_ftl
:
3713 case ixgbe_phy_sfp_intel
:
3714 case ixgbe_phy_sfp_unknown
:
3715 case ixgbe_phy_sfp_passive_tyco
:
3716 case ixgbe_phy_sfp_passive_unknown
:
3717 case ixgbe_phy_sfp_active_unknown
:
3718 case ixgbe_phy_sfp_ftl_active
:
3726 * ixgbe_sfp_link_config - set up SFP+ link
3727 * @adapter: pointer to private adapter struct
3729 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
3732 * We are assuming the worst case scenerio here, and that
3733 * is that an SFP was inserted/removed after the reset
3734 * but before SFP detection was enabled. As such the best
3735 * solution is to just start searching as soon as we start
3737 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
3738 adapter
->flags2
|= IXGBE_FLAG2_SEARCH_FOR_SFP
;
3740 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
3744 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3745 * @hw: pointer to private hardware struct
3747 * Returns 0 on success, negative on failure
3749 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
3752 bool negotiation
, link_up
= false;
3753 u32 ret
= IXGBE_ERR_LINK_SETUP
;
3755 if (hw
->mac
.ops
.check_link
)
3756 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
3761 autoneg
= hw
->phy
.autoneg_advertised
;
3762 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
3763 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
,
3768 if (hw
->mac
.ops
.setup_link
)
3769 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
3774 static void ixgbe_setup_gpie(struct ixgbe_adapter
*adapter
)
3776 struct ixgbe_hw
*hw
= &adapter
->hw
;
3779 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3780 gpie
= IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_PBA_SUPPORT
|
3782 gpie
|= IXGBE_GPIE_EIAME
;
3784 * use EIAM to auto-mask when MSI-X interrupt is asserted
3785 * this saves a register write for every interrupt
3787 switch (hw
->mac
.type
) {
3788 case ixgbe_mac_82598EB
:
3789 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3791 case ixgbe_mac_82599EB
:
3792 case ixgbe_mac_X540
:
3794 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3795 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3799 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3800 * specifically only auto mask tx and rx interrupts */
3801 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3804 /* XXX: to interrupt immediately for EICS writes, enable this */
3805 /* gpie |= IXGBE_GPIE_EIMEN; */
3807 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
3808 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
3809 gpie
|= IXGBE_GPIE_VTMODE_64
;
3812 /* Enable fan failure interrupt */
3813 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
3814 gpie
|= IXGBE_SDP1_GPIEN
;
3816 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3817 gpie
|= IXGBE_SDP1_GPIEN
;
3818 gpie
|= IXGBE_SDP2_GPIEN
;
3821 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3824 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
3826 struct ixgbe_hw
*hw
= &adapter
->hw
;
3830 ixgbe_get_hw_control(adapter
);
3831 ixgbe_setup_gpie(adapter
);
3833 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3834 ixgbe_configure_msix(adapter
);
3836 ixgbe_configure_msi_and_legacy(adapter
);
3838 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3839 if (hw
->mac
.ops
.enable_tx_laser
&&
3840 ((hw
->phy
.multispeed_fiber
) ||
3841 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
3842 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
3843 hw
->mac
.ops
.enable_tx_laser(hw
);
3845 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3846 ixgbe_napi_enable_all(adapter
);
3848 if (ixgbe_is_sfp(hw
)) {
3849 ixgbe_sfp_link_config(adapter
);
3851 err
= ixgbe_non_sfp_link_config(hw
);
3853 e_err(probe
, "link_config FAILED %d\n", err
);
3856 /* clear any pending interrupts, may auto mask */
3857 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3858 ixgbe_irq_enable(adapter
, true, true);
3861 * If this adapter has a fan, check to see if we had a failure
3862 * before we enabled the interrupt.
3864 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3865 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3866 if (esdp
& IXGBE_ESDP_SDP1
)
3867 e_crit(drv
, "Fan has stopped, replace the adapter\n");
3870 /* enable transmits */
3871 netif_tx_start_all_queues(adapter
->netdev
);
3873 /* bring the link up in the watchdog, this could race with our first
3874 * link up interrupt but shouldn't be a problem */
3875 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3876 adapter
->link_check_timeout
= jiffies
;
3877 mod_timer(&adapter
->service_timer
, jiffies
);
3879 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3880 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3881 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3882 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3887 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3889 WARN_ON(in_interrupt());
3890 /* put off any impending NetWatchDogTimeout */
3891 adapter
->netdev
->trans_start
= jiffies
;
3893 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3894 usleep_range(1000, 2000);
3895 ixgbe_down(adapter
);
3897 * If SR-IOV enabled then wait a bit before bringing the adapter
3898 * back up to give the VFs time to respond to the reset. The
3899 * two second wait is based upon the watchdog timer cycle in
3902 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3905 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3908 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3910 /* hardware has been reset, we need to reload some things */
3911 ixgbe_configure(adapter
);
3913 return ixgbe_up_complete(adapter
);
3916 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3918 struct ixgbe_hw
*hw
= &adapter
->hw
;
3921 /* lock SFP init bit to prevent race conditions with the watchdog */
3922 while (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
3923 usleep_range(1000, 2000);
3925 /* clear all SFP and link config related flags while holding SFP_INIT */
3926 adapter
->flags2
&= ~(IXGBE_FLAG2_SEARCH_FOR_SFP
|
3927 IXGBE_FLAG2_SFP_NEEDS_RESET
);
3928 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_CONFIG
;
3930 err
= hw
->mac
.ops
.init_hw(hw
);
3933 case IXGBE_ERR_SFP_NOT_PRESENT
:
3934 case IXGBE_ERR_SFP_NOT_SUPPORTED
:
3936 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3937 e_dev_err("master disable timed out\n");
3939 case IXGBE_ERR_EEPROM_VERSION
:
3940 /* We are running on a pre-production device, log a warning */
3941 e_dev_warn("This device is a pre-production adapter/LOM. "
3942 "Please be aware there may be issuesassociated with "
3943 "your hardware. If you are experiencing problems "
3944 "please contact your Intel or hardware "
3945 "representative who provided you with this "
3949 e_dev_err("Hardware Error: %d\n", err
);
3952 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
3954 /* reprogram the RAR[0] in case user changed it. */
3955 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3960 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3961 * @rx_ring: ring to free buffers from
3963 static void ixgbe_clean_rx_ring(struct ixgbe_ring
*rx_ring
)
3965 struct device
*dev
= rx_ring
->dev
;
3969 /* ring already cleared, nothing to do */
3970 if (!rx_ring
->rx_buffer_info
)
3973 /* Free all the Rx ring sk_buffs */
3974 for (i
= 0; i
< rx_ring
->count
; i
++) {
3975 struct ixgbe_rx_buffer
*rx_buffer_info
;
3977 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3978 if (rx_buffer_info
->dma
) {
3979 dma_unmap_single(rx_ring
->dev
, rx_buffer_info
->dma
,
3980 rx_ring
->rx_buf_len
,
3982 rx_buffer_info
->dma
= 0;
3984 if (rx_buffer_info
->skb
) {
3985 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3986 rx_buffer_info
->skb
= NULL
;
3988 struct sk_buff
*this = skb
;
3989 if (IXGBE_RSC_CB(this)->delay_unmap
) {
3990 dma_unmap_single(dev
,
3991 IXGBE_RSC_CB(this)->dma
,
3992 rx_ring
->rx_buf_len
,
3994 IXGBE_RSC_CB(this)->dma
= 0;
3995 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
3998 dev_kfree_skb(this);
4001 if (!rx_buffer_info
->page
)
4003 if (rx_buffer_info
->page_dma
) {
4004 dma_unmap_page(dev
, rx_buffer_info
->page_dma
,
4005 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
4006 rx_buffer_info
->page_dma
= 0;
4008 put_page(rx_buffer_info
->page
);
4009 rx_buffer_info
->page
= NULL
;
4010 rx_buffer_info
->page_offset
= 0;
4013 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
4014 memset(rx_ring
->rx_buffer_info
, 0, size
);
4016 /* Zero out the descriptor ring */
4017 memset(rx_ring
->desc
, 0, rx_ring
->size
);
4019 rx_ring
->next_to_clean
= 0;
4020 rx_ring
->next_to_use
= 0;
4024 * ixgbe_clean_tx_ring - Free Tx Buffers
4025 * @tx_ring: ring to be cleaned
4027 static void ixgbe_clean_tx_ring(struct ixgbe_ring
*tx_ring
)
4029 struct ixgbe_tx_buffer
*tx_buffer_info
;
4033 /* ring already cleared, nothing to do */
4034 if (!tx_ring
->tx_buffer_info
)
4037 /* Free all the Tx ring sk_buffs */
4038 for (i
= 0; i
< tx_ring
->count
; i
++) {
4039 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4040 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
4043 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4044 memset(tx_ring
->tx_buffer_info
, 0, size
);
4046 /* Zero out the descriptor ring */
4047 memset(tx_ring
->desc
, 0, tx_ring
->size
);
4049 tx_ring
->next_to_use
= 0;
4050 tx_ring
->next_to_clean
= 0;
4054 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4055 * @adapter: board private structure
4057 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
4061 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4062 ixgbe_clean_rx_ring(adapter
->rx_ring
[i
]);
4066 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4067 * @adapter: board private structure
4069 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
4073 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4074 ixgbe_clean_tx_ring(adapter
->tx_ring
[i
]);
4077 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter
*adapter
)
4079 struct hlist_node
*node
, *node2
;
4080 struct ixgbe_fdir_filter
*filter
;
4082 spin_lock(&adapter
->fdir_perfect_lock
);
4084 hlist_for_each_entry_safe(filter
, node
, node2
,
4085 &adapter
->fdir_filter_list
, fdir_node
) {
4086 hlist_del(&filter
->fdir_node
);
4089 adapter
->fdir_filter_count
= 0;
4091 spin_unlock(&adapter
->fdir_perfect_lock
);
4094 void ixgbe_down(struct ixgbe_adapter
*adapter
)
4096 struct net_device
*netdev
= adapter
->netdev
;
4097 struct ixgbe_hw
*hw
= &adapter
->hw
;
4100 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4102 /* signal that we are down to the interrupt handler */
4103 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4105 /* disable receives */
4106 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
4107 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
4109 /* disable all enabled rx queues */
4110 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4111 /* this call also flushes the previous write */
4112 ixgbe_disable_rx_queue(adapter
, adapter
->rx_ring
[i
]);
4114 usleep_range(10000, 20000);
4116 netif_tx_stop_all_queues(netdev
);
4118 /* call carrier off first to avoid false dev_watchdog timeouts */
4119 netif_carrier_off(netdev
);
4120 netif_tx_disable(netdev
);
4122 ixgbe_irq_disable(adapter
);
4124 ixgbe_napi_disable_all(adapter
);
4126 adapter
->flags2
&= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT
|
4127 IXGBE_FLAG2_RESET_REQUESTED
);
4128 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
4130 del_timer_sync(&adapter
->service_timer
);
4132 /* disable receive for all VFs and wait one second */
4133 if (adapter
->num_vfs
) {
4134 /* ping all the active vfs to let them know we are going down */
4135 ixgbe_ping_all_vfs(adapter
);
4137 /* Disable all VFTE/VFRE TX/RX */
4138 ixgbe_disable_tx_rx(adapter
);
4140 /* Mark all the VFs as inactive */
4141 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
4142 adapter
->vfinfo
[i
].clear_to_send
= 0;
4145 /* Cleanup the affinity_hint CPU mask memory and callback */
4146 for (i
= 0; i
< num_q_vectors
; i
++) {
4147 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
4148 /* clear the affinity_mask in the IRQ descriptor */
4149 irq_set_affinity_hint(adapter
->msix_entries
[i
]. vector
, NULL
);
4150 /* release the CPU mask memory */
4151 free_cpumask_var(q_vector
->affinity_mask
);
4154 /* disable transmits in the hardware now that interrupts are off */
4155 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4156 u8 reg_idx
= adapter
->tx_ring
[i
]->reg_idx
;
4157 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), IXGBE_TXDCTL_SWFLSH
);
4160 /* Disable the Tx DMA engine on 82599 and X540 */
4161 switch (hw
->mac
.type
) {
4162 case ixgbe_mac_82599EB
:
4163 case ixgbe_mac_X540
:
4164 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
4165 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
4166 ~IXGBE_DMATXCTL_TE
));
4172 if (!pci_channel_offline(adapter
->pdev
))
4173 ixgbe_reset(adapter
);
4175 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4176 if (hw
->mac
.ops
.disable_tx_laser
&&
4177 ((hw
->phy
.multispeed_fiber
) ||
4178 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
4179 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
4180 hw
->mac
.ops
.disable_tx_laser(hw
);
4182 ixgbe_clean_all_tx_rings(adapter
);
4183 ixgbe_clean_all_rx_rings(adapter
);
4185 #ifdef CONFIG_IXGBE_DCA
4186 /* since we reset the hardware DCA settings were cleared */
4187 ixgbe_setup_dca(adapter
);
4192 * ixgbe_poll - NAPI Rx polling callback
4193 * @napi: structure for representing this polling device
4194 * @budget: how many packets driver is allowed to clean
4196 * This function is used for legacy and MSI, NAPI mode
4198 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
4200 struct ixgbe_q_vector
*q_vector
=
4201 container_of(napi
, struct ixgbe_q_vector
, napi
);
4202 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
4203 int tx_clean_complete
, work_done
= 0;
4205 #ifdef CONFIG_IXGBE_DCA
4206 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
4207 ixgbe_update_dca(q_vector
);
4210 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
4211 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
4213 if (!tx_clean_complete
)
4216 /* If budget not fully consumed, exit the polling mode */
4217 if (work_done
< budget
) {
4218 napi_complete(napi
);
4219 if (adapter
->rx_itr_setting
& 1)
4220 ixgbe_set_itr(q_vector
);
4221 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
4222 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
4228 * ixgbe_tx_timeout - Respond to a Tx Hang
4229 * @netdev: network interface device structure
4231 static void ixgbe_tx_timeout(struct net_device
*netdev
)
4233 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4235 /* Do the reset outside of interrupt context */
4236 ixgbe_tx_timeout_reset(adapter
);
4240 * ixgbe_set_rss_queues: Allocate queues for RSS
4241 * @adapter: board private structure to initialize
4243 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4244 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4247 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
4250 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
4252 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4254 adapter
->num_rx_queues
= f
->indices
;
4255 adapter
->num_tx_queues
= f
->indices
;
4265 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4266 * @adapter: board private structure to initialize
4268 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4269 * to the original CPU that initiated the Tx session. This runs in addition
4270 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4271 * Rx load across CPUs using RSS.
4274 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
4277 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
4279 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
4282 /* Flow Director must have RSS enabled */
4283 if ((adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) &&
4284 (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)) {
4285 adapter
->num_tx_queues
= f_fdir
->indices
;
4286 adapter
->num_rx_queues
= f_fdir
->indices
;
4289 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4296 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4297 * @adapter: board private structure to initialize
4299 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4300 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4301 * rx queues out of the max number of rx queues, instead, it is used as the
4302 * index of the first rx queue used by FCoE.
4305 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
4307 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4309 if (!(adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
))
4312 f
->indices
= min((int)num_online_cpus(), f
->indices
);
4314 adapter
->num_rx_queues
= 1;
4315 adapter
->num_tx_queues
= 1;
4317 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4318 e_info(probe
, "FCoE enabled with RSS\n");
4319 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)
4320 ixgbe_set_fdir_queues(adapter
);
4322 ixgbe_set_rss_queues(adapter
);
4325 /* adding FCoE rx rings to the end */
4326 f
->mask
= adapter
->num_rx_queues
;
4327 adapter
->num_rx_queues
+= f
->indices
;
4328 adapter
->num_tx_queues
+= f
->indices
;
4332 #endif /* IXGBE_FCOE */
4334 /* Artificial max queue cap per traffic class in DCB mode */
4335 #define DCB_QUEUE_CAP 8
4337 #ifdef CONFIG_IXGBE_DCB
4338 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
4340 int per_tc_q
, q
, i
, offset
= 0;
4341 struct net_device
*dev
= adapter
->netdev
;
4342 int tcs
= netdev_get_num_tc(dev
);
4347 /* Map queue offset and counts onto allocated tx queues */
4348 per_tc_q
= min(dev
->num_tx_queues
/ tcs
, (unsigned int)DCB_QUEUE_CAP
);
4349 q
= min((int)num_online_cpus(), per_tc_q
);
4351 for (i
= 0; i
< tcs
; i
++) {
4352 netdev_set_prio_tc_map(dev
, i
, i
);
4353 netdev_set_tc_queue(dev
, i
, q
, offset
);
4357 adapter
->num_tx_queues
= q
* tcs
;
4358 adapter
->num_rx_queues
= q
* tcs
;
4361 /* FCoE enabled queues require special configuration indexed
4362 * by feature specific indices and mask. Here we map FCoE
4363 * indices onto the DCB queue pairs allowing FCoE to own
4364 * configuration later.
4366 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4368 struct ixgbe_ring_feature
*f
=
4369 &adapter
->ring_feature
[RING_F_FCOE
];
4371 tc
= netdev_get_prio_tc_map(dev
, adapter
->fcoe
.up
);
4372 f
->indices
= dev
->tc_to_txq
[tc
].count
;
4373 f
->mask
= dev
->tc_to_txq
[tc
].offset
;
4382 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4383 * @adapter: board private structure to initialize
4385 * IOV doesn't actually use anything, so just NAK the
4386 * request for now and let the other queue routines
4387 * figure out what to do.
4389 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
4395 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4396 * @adapter: board private structure to initialize
4398 * This is the top level queue allocation routine. The order here is very
4399 * important, starting with the "most" number of features turned on at once,
4400 * and ending with the smallest set of features. This way large combinations
4401 * can be allocated if they're turned on, and smaller combinations are the
4402 * fallthrough conditions.
4405 static int ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
4407 /* Start with base case */
4408 adapter
->num_rx_queues
= 1;
4409 adapter
->num_tx_queues
= 1;
4410 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
4411 adapter
->num_rx_queues_per_pool
= 1;
4413 if (ixgbe_set_sriov_queues(adapter
))
4416 #ifdef CONFIG_IXGBE_DCB
4417 if (ixgbe_set_dcb_queues(adapter
))
4422 if (ixgbe_set_fcoe_queues(adapter
))
4425 #endif /* IXGBE_FCOE */
4426 if (ixgbe_set_fdir_queues(adapter
))
4429 if (ixgbe_set_rss_queues(adapter
))
4432 /* fallback to base case */
4433 adapter
->num_rx_queues
= 1;
4434 adapter
->num_tx_queues
= 1;
4437 /* Notify the stack of the (possibly) reduced queue counts. */
4438 netif_set_real_num_tx_queues(adapter
->netdev
, adapter
->num_tx_queues
);
4439 return netif_set_real_num_rx_queues(adapter
->netdev
,
4440 adapter
->num_rx_queues
);
4443 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
4446 int err
, vector_threshold
;
4448 /* We'll want at least 3 (vector_threshold):
4451 * 3) Other (Link Status Change, etc.)
4452 * 4) TCP Timer (optional)
4454 vector_threshold
= MIN_MSIX_COUNT
;
4456 /* The more we get, the more we will assign to Tx/Rx Cleanup
4457 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4458 * Right now, we simply care about how many we'll get; we'll
4459 * set them up later while requesting irq's.
4461 while (vectors
>= vector_threshold
) {
4462 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
4464 if (!err
) /* Success in acquiring all requested vectors. */
4467 vectors
= 0; /* Nasty failure, quit now */
4468 else /* err == number of vectors we should try again with */
4472 if (vectors
< vector_threshold
) {
4473 /* Can't allocate enough MSI-X interrupts? Oh well.
4474 * This just means we'll go with either a single MSI
4475 * vector or fall back to legacy interrupts.
4477 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4478 "Unable to allocate MSI-X interrupts\n");
4479 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4480 kfree(adapter
->msix_entries
);
4481 adapter
->msix_entries
= NULL
;
4483 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
4485 * Adjust for only the vectors we'll use, which is minimum
4486 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4487 * vectors we were allocated.
4489 adapter
->num_msix_vectors
= min(vectors
,
4490 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
4495 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4496 * @adapter: board private structure to initialize
4498 * Cache the descriptor ring offsets for RSS to the assigned rings.
4501 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
4505 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
))
4508 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4509 adapter
->rx_ring
[i
]->reg_idx
= i
;
4510 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4511 adapter
->tx_ring
[i
]->reg_idx
= i
;
4516 #ifdef CONFIG_IXGBE_DCB
4518 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4519 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter
*adapter
, u8 tc
,
4520 unsigned int *tx
, unsigned int *rx
)
4522 struct net_device
*dev
= adapter
->netdev
;
4523 struct ixgbe_hw
*hw
= &adapter
->hw
;
4524 u8 num_tcs
= netdev_get_num_tc(dev
);
4529 switch (hw
->mac
.type
) {
4530 case ixgbe_mac_82598EB
:
4534 case ixgbe_mac_82599EB
:
4535 case ixgbe_mac_X540
:
4540 } else if (tc
< 5) {
4541 *tx
= ((tc
+ 2) << 4);
4543 } else if (tc
< num_tcs
) {
4544 *tx
= ((tc
+ 8) << 3);
4547 } else if (num_tcs
== 4) {
4573 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4574 * @adapter: board private structure to initialize
4576 * Cache the descriptor ring offsets for DCB to the assigned rings.
4579 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
4581 struct net_device
*dev
= adapter
->netdev
;
4583 u8 num_tcs
= netdev_get_num_tc(dev
);
4588 for (i
= 0, k
= 0; i
< num_tcs
; i
++) {
4589 unsigned int tx_s
, rx_s
;
4590 u16 count
= dev
->tc_to_txq
[i
].count
;
4592 ixgbe_get_first_reg_idx(adapter
, i
, &tx_s
, &rx_s
);
4593 for (j
= 0; j
< count
; j
++, k
++) {
4594 adapter
->tx_ring
[k
]->reg_idx
= tx_s
+ j
;
4595 adapter
->rx_ring
[k
]->reg_idx
= rx_s
+ j
;
4596 adapter
->tx_ring
[k
]->dcb_tc
= i
;
4597 adapter
->rx_ring
[k
]->dcb_tc
= i
;
4606 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4607 * @adapter: board private structure to initialize
4609 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4612 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
4617 if ((adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) &&
4618 (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)) {
4619 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4620 adapter
->rx_ring
[i
]->reg_idx
= i
;
4621 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4622 adapter
->tx_ring
[i
]->reg_idx
= i
;
4631 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4632 * @adapter: board private structure to initialize
4634 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4637 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
4639 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4641 u8 fcoe_rx_i
= 0, fcoe_tx_i
= 0;
4643 if (!(adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
))
4646 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4647 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)
4648 ixgbe_cache_ring_fdir(adapter
);
4650 ixgbe_cache_ring_rss(adapter
);
4652 fcoe_rx_i
= f
->mask
;
4653 fcoe_tx_i
= f
->mask
;
4655 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
4656 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
4657 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
4662 #endif /* IXGBE_FCOE */
4664 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4665 * @adapter: board private structure to initialize
4667 * SR-IOV doesn't use any descriptor rings but changes the default if
4668 * no other mapping is used.
4671 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
4673 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4674 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4675 if (adapter
->num_vfs
)
4682 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4683 * @adapter: board private structure to initialize
4685 * Once we know the feature-set enabled for the device, we'll cache
4686 * the register offset the descriptor ring is assigned to.
4688 * Note, the order the various feature calls is important. It must start with
4689 * the "most" features enabled at the same time, then trickle down to the
4690 * least amount of features turned on at once.
4692 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
4694 /* start with default case */
4695 adapter
->rx_ring
[0]->reg_idx
= 0;
4696 adapter
->tx_ring
[0]->reg_idx
= 0;
4698 if (ixgbe_cache_ring_sriov(adapter
))
4701 #ifdef CONFIG_IXGBE_DCB
4702 if (ixgbe_cache_ring_dcb(adapter
))
4707 if (ixgbe_cache_ring_fcoe(adapter
))
4709 #endif /* IXGBE_FCOE */
4711 if (ixgbe_cache_ring_fdir(adapter
))
4714 if (ixgbe_cache_ring_rss(adapter
))
4719 * ixgbe_alloc_queues - Allocate memory for all rings
4720 * @adapter: board private structure to initialize
4722 * We allocate one ring per queue at run-time since we don't know the
4723 * number of queues at compile-time. The polling_netdev array is
4724 * intended for Multiqueue, but should work fine with a single queue.
4726 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
4728 int rx
= 0, tx
= 0, nid
= adapter
->node
;
4730 if (nid
< 0 || !node_online(nid
))
4731 nid
= first_online_node
;
4733 for (; tx
< adapter
->num_tx_queues
; tx
++) {
4734 struct ixgbe_ring
*ring
;
4736 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4738 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4740 goto err_allocation
;
4741 ring
->count
= adapter
->tx_ring_count
;
4742 ring
->queue_index
= tx
;
4743 ring
->numa_node
= nid
;
4744 ring
->dev
= &adapter
->pdev
->dev
;
4745 ring
->netdev
= adapter
->netdev
;
4747 adapter
->tx_ring
[tx
] = ring
;
4750 for (; rx
< adapter
->num_rx_queues
; rx
++) {
4751 struct ixgbe_ring
*ring
;
4753 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4755 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4757 goto err_allocation
;
4758 ring
->count
= adapter
->rx_ring_count
;
4759 ring
->queue_index
= rx
;
4760 ring
->numa_node
= nid
;
4761 ring
->dev
= &adapter
->pdev
->dev
;
4762 ring
->netdev
= adapter
->netdev
;
4764 adapter
->rx_ring
[rx
] = ring
;
4767 ixgbe_cache_ring_register(adapter
);
4773 kfree(adapter
->tx_ring
[--tx
]);
4776 kfree(adapter
->rx_ring
[--rx
]);
4781 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4782 * @adapter: board private structure to initialize
4784 * Attempt to configure the interrupts using the best available
4785 * capabilities of the hardware and the kernel.
4787 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
4789 struct ixgbe_hw
*hw
= &adapter
->hw
;
4791 int vector
, v_budget
;
4794 * It's easy to be greedy for MSI-X vectors, but it really
4795 * doesn't do us much good if we have a lot more vectors
4796 * than CPU's. So let's be conservative and only ask for
4797 * (roughly) the same number of vectors as there are CPU's.
4799 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
4800 (int)num_online_cpus()) + NON_Q_VECTORS
;
4803 * At the same time, hardware can only support a maximum of
4804 * hw.mac->max_msix_vectors vectors. With features
4805 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4806 * descriptor queues supported by our device. Thus, we cap it off in
4807 * those rare cases where the cpu count also exceeds our vector limit.
4809 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
4811 /* A failure in MSI-X entry allocation isn't fatal, but it does
4812 * mean we disable MSI-X capabilities of the adapter. */
4813 adapter
->msix_entries
= kcalloc(v_budget
,
4814 sizeof(struct msix_entry
), GFP_KERNEL
);
4815 if (adapter
->msix_entries
) {
4816 for (vector
= 0; vector
< v_budget
; vector
++)
4817 adapter
->msix_entries
[vector
].entry
= vector
;
4819 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4821 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4825 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4826 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4827 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
4829 "ATR is not supported while multiple "
4830 "queues are disabled. Disabling Flow Director\n");
4832 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4833 adapter
->atr_sample_rate
= 0;
4834 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4835 ixgbe_disable_sriov(adapter
);
4837 err
= ixgbe_set_num_queues(adapter
);
4841 err
= pci_enable_msi(adapter
->pdev
);
4843 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4845 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4846 "Unable to allocate MSI interrupt, "
4847 "falling back to legacy. Error: %d\n", err
);
4857 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4858 * @adapter: board private structure to initialize
4860 * We allocate one q_vector per queue interrupt. If allocation fails we
4863 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4865 int q_idx
, num_q_vectors
;
4866 struct ixgbe_q_vector
*q_vector
;
4867 int (*poll
)(struct napi_struct
*, int);
4869 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4870 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4871 poll
= &ixgbe_clean_rxtx_many
;
4877 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4878 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4879 GFP_KERNEL
, adapter
->node
);
4881 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4885 q_vector
->adapter
= adapter
;
4886 if (q_vector
->tx
.count
&& !q_vector
->rx
.count
)
4887 q_vector
->eitr
= adapter
->tx_eitr_param
;
4889 q_vector
->eitr
= adapter
->rx_eitr_param
;
4890 q_vector
->v_idx
= q_idx
;
4891 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
4892 adapter
->q_vector
[q_idx
] = q_vector
;
4900 q_vector
= adapter
->q_vector
[q_idx
];
4901 netif_napi_del(&q_vector
->napi
);
4903 adapter
->q_vector
[q_idx
] = NULL
;
4909 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4910 * @adapter: board private structure to initialize
4912 * This function frees the memory allocated to the q_vectors. In addition if
4913 * NAPI is enabled it will delete any references to the NAPI struct prior
4914 * to freeing the q_vector.
4916 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4918 int q_idx
, num_q_vectors
;
4920 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4921 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4925 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4926 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4927 adapter
->q_vector
[q_idx
] = NULL
;
4928 netif_napi_del(&q_vector
->napi
);
4933 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4935 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4936 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4937 pci_disable_msix(adapter
->pdev
);
4938 kfree(adapter
->msix_entries
);
4939 adapter
->msix_entries
= NULL
;
4940 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4941 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4942 pci_disable_msi(adapter
->pdev
);
4947 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4948 * @adapter: board private structure to initialize
4950 * We determine which interrupt scheme to use based on...
4951 * - Kernel support (MSI, MSI-X)
4952 * - which can be user-defined (via MODULE_PARAM)
4953 * - Hardware queue count (num_*_queues)
4954 * - defined by miscellaneous hardware support/features (RSS, etc.)
4956 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4960 /* Number of supported queues */
4961 err
= ixgbe_set_num_queues(adapter
);
4965 err
= ixgbe_set_interrupt_capability(adapter
);
4967 e_dev_err("Unable to setup interrupt capabilities\n");
4968 goto err_set_interrupt
;
4971 err
= ixgbe_alloc_q_vectors(adapter
);
4973 e_dev_err("Unable to allocate memory for queue vectors\n");
4974 goto err_alloc_q_vectors
;
4977 err
= ixgbe_alloc_queues(adapter
);
4979 e_dev_err("Unable to allocate memory for queues\n");
4980 goto err_alloc_queues
;
4983 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4984 (adapter
->num_rx_queues
> 1) ? "Enabled" : "Disabled",
4985 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
4987 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4992 ixgbe_free_q_vectors(adapter
);
4993 err_alloc_q_vectors
:
4994 ixgbe_reset_interrupt_capability(adapter
);
5000 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5001 * @adapter: board private structure to clear interrupt scheme on
5003 * We go through and clear interrupt specific resources and reset the structure
5004 * to pre-load conditions
5006 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
5010 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5011 kfree(adapter
->tx_ring
[i
]);
5012 adapter
->tx_ring
[i
] = NULL
;
5014 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5015 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
5017 /* ixgbe_get_stats64() might access this ring, we must wait
5018 * a grace period before freeing it.
5020 kfree_rcu(ring
, rcu
);
5021 adapter
->rx_ring
[i
] = NULL
;
5024 adapter
->num_tx_queues
= 0;
5025 adapter
->num_rx_queues
= 0;
5027 ixgbe_free_q_vectors(adapter
);
5028 ixgbe_reset_interrupt_capability(adapter
);
5032 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5033 * @adapter: board private structure to initialize
5035 * ixgbe_sw_init initializes the Adapter private data structure.
5036 * Fields are initialized based on PCI device information and
5037 * OS network device settings (MTU size).
5039 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
5041 struct ixgbe_hw
*hw
= &adapter
->hw
;
5042 struct pci_dev
*pdev
= adapter
->pdev
;
5043 struct net_device
*dev
= adapter
->netdev
;
5045 #ifdef CONFIG_IXGBE_DCB
5047 struct tc_configuration
*tc
;
5049 int max_frame
= dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5051 /* PCI config space info */
5053 hw
->vendor_id
= pdev
->vendor
;
5054 hw
->device_id
= pdev
->device
;
5055 hw
->revision_id
= pdev
->revision
;
5056 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
5057 hw
->subsystem_device_id
= pdev
->subsystem_device
;
5059 /* Set capability flags */
5060 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
5061 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
5062 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
5063 switch (hw
->mac
.type
) {
5064 case ixgbe_mac_82598EB
:
5065 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
5066 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
5067 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
5069 case ixgbe_mac_82599EB
:
5070 case ixgbe_mac_X540
:
5071 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
5072 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
5073 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
5074 if (hw
->device_id
== IXGBE_DEV_ID_82599_T3_LOM
)
5075 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
;
5076 /* Flow Director hash filters enabled */
5077 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
5078 adapter
->atr_sample_rate
= 20;
5079 adapter
->ring_feature
[RING_F_FDIR
].indices
=
5080 IXGBE_MAX_FDIR_INDICES
;
5081 adapter
->fdir_pballoc
= IXGBE_FDIR_PBALLOC_64K
;
5083 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
5084 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
5085 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
5086 #ifdef CONFIG_IXGBE_DCB
5087 /* Default traffic class to use for FCoE */
5088 adapter
->fcoe
.up
= IXGBE_FCOE_DEFTC
;
5090 #endif /* IXGBE_FCOE */
5096 /* n-tuple support exists, always init our spinlock */
5097 spin_lock_init(&adapter
->fdir_perfect_lock
);
5099 #ifdef CONFIG_IXGBE_DCB
5100 /* Configure DCB traffic classes */
5101 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
5102 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
5103 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
5104 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5105 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
5106 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5107 tc
->dcb_pfc
= pfc_disabled
;
5109 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
5110 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
5111 adapter
->dcb_cfg
.pfc_mode_enable
= false;
5112 adapter
->dcb_set_bitmap
= 0x00;
5113 adapter
->dcbx_cap
= DCB_CAP_DCBX_HOST
| DCB_CAP_DCBX_VER_CEE
;
5114 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
5119 /* default flow control settings */
5120 hw
->fc
.requested_mode
= ixgbe_fc_full
;
5121 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
5123 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
5125 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5126 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5127 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
5128 hw
->fc
.send_xon
= true;
5129 hw
->fc
.disable_fc_autoneg
= false;
5131 /* enable itr by default in dynamic mode */
5132 adapter
->rx_itr_setting
= 1;
5133 adapter
->rx_eitr_param
= 20000;
5134 adapter
->tx_itr_setting
= 1;
5135 adapter
->tx_eitr_param
= 10000;
5137 /* set defaults for eitr in MegaBytes */
5138 adapter
->eitr_low
= 10;
5139 adapter
->eitr_high
= 20;
5141 /* set default ring sizes */
5142 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
5143 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
5145 /* set default work limits */
5146 adapter
->tx_work_limit
= adapter
->tx_ring_count
;
5148 /* initialize eeprom parameters */
5149 if (ixgbe_init_eeprom_params_generic(hw
)) {
5150 e_dev_err("EEPROM initialization failed\n");
5154 /* enable rx csum by default */
5155 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
5157 /* get assigned NUMA node */
5158 adapter
->node
= dev_to_node(&pdev
->dev
);
5160 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5166 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5167 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5169 * Return 0 on success, negative on failure
5171 int ixgbe_setup_tx_resources(struct ixgbe_ring
*tx_ring
)
5173 struct device
*dev
= tx_ring
->dev
;
5176 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
5177 tx_ring
->tx_buffer_info
= vzalloc_node(size
, tx_ring
->numa_node
);
5178 if (!tx_ring
->tx_buffer_info
)
5179 tx_ring
->tx_buffer_info
= vzalloc(size
);
5180 if (!tx_ring
->tx_buffer_info
)
5183 /* round up to nearest 4K */
5184 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
5185 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
5187 tx_ring
->desc
= dma_alloc_coherent(dev
, tx_ring
->size
,
5188 &tx_ring
->dma
, GFP_KERNEL
);
5192 tx_ring
->next_to_use
= 0;
5193 tx_ring
->next_to_clean
= 0;
5197 vfree(tx_ring
->tx_buffer_info
);
5198 tx_ring
->tx_buffer_info
= NULL
;
5199 dev_err(dev
, "Unable to allocate memory for the Tx descriptor ring\n");
5204 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5205 * @adapter: board private structure
5207 * If this function returns with an error, then it's possible one or
5208 * more of the rings is populated (while the rest are not). It is the
5209 * callers duty to clean those orphaned rings.
5211 * Return 0 on success, negative on failure
5213 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
5217 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5218 err
= ixgbe_setup_tx_resources(adapter
->tx_ring
[i
]);
5221 e_err(probe
, "Allocation for Tx Queue %u failed\n", i
);
5229 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5230 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5232 * Returns 0 on success, negative on failure
5234 int ixgbe_setup_rx_resources(struct ixgbe_ring
*rx_ring
)
5236 struct device
*dev
= rx_ring
->dev
;
5239 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
5240 rx_ring
->rx_buffer_info
= vzalloc_node(size
, rx_ring
->numa_node
);
5241 if (!rx_ring
->rx_buffer_info
)
5242 rx_ring
->rx_buffer_info
= vzalloc(size
);
5243 if (!rx_ring
->rx_buffer_info
)
5246 /* Round up to nearest 4K */
5247 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
5248 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
5250 rx_ring
->desc
= dma_alloc_coherent(dev
, rx_ring
->size
,
5251 &rx_ring
->dma
, GFP_KERNEL
);
5256 rx_ring
->next_to_clean
= 0;
5257 rx_ring
->next_to_use
= 0;
5261 vfree(rx_ring
->rx_buffer_info
);
5262 rx_ring
->rx_buffer_info
= NULL
;
5263 dev_err(dev
, "Unable to allocate memory for the Rx descriptor ring\n");
5268 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5269 * @adapter: board private structure
5271 * If this function returns with an error, then it's possible one or
5272 * more of the rings is populated (while the rest are not). It is the
5273 * callers duty to clean those orphaned rings.
5275 * Return 0 on success, negative on failure
5277 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
5281 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5282 err
= ixgbe_setup_rx_resources(adapter
->rx_ring
[i
]);
5285 e_err(probe
, "Allocation for Rx Queue %u failed\n", i
);
5293 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5294 * @tx_ring: Tx descriptor ring for a specific queue
5296 * Free all transmit software resources
5298 void ixgbe_free_tx_resources(struct ixgbe_ring
*tx_ring
)
5300 ixgbe_clean_tx_ring(tx_ring
);
5302 vfree(tx_ring
->tx_buffer_info
);
5303 tx_ring
->tx_buffer_info
= NULL
;
5305 /* if not set, then don't free */
5309 dma_free_coherent(tx_ring
->dev
, tx_ring
->size
,
5310 tx_ring
->desc
, tx_ring
->dma
);
5312 tx_ring
->desc
= NULL
;
5316 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5317 * @adapter: board private structure
5319 * Free all transmit software resources
5321 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
5325 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5326 if (adapter
->tx_ring
[i
]->desc
)
5327 ixgbe_free_tx_resources(adapter
->tx_ring
[i
]);
5331 * ixgbe_free_rx_resources - Free Rx Resources
5332 * @rx_ring: ring to clean the resources from
5334 * Free all receive software resources
5336 void ixgbe_free_rx_resources(struct ixgbe_ring
*rx_ring
)
5338 ixgbe_clean_rx_ring(rx_ring
);
5340 vfree(rx_ring
->rx_buffer_info
);
5341 rx_ring
->rx_buffer_info
= NULL
;
5343 /* if not set, then don't free */
5347 dma_free_coherent(rx_ring
->dev
, rx_ring
->size
,
5348 rx_ring
->desc
, rx_ring
->dma
);
5350 rx_ring
->desc
= NULL
;
5354 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5355 * @adapter: board private structure
5357 * Free all receive software resources
5359 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
5363 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5364 if (adapter
->rx_ring
[i
]->desc
)
5365 ixgbe_free_rx_resources(adapter
->rx_ring
[i
]);
5369 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5370 * @netdev: network interface device structure
5371 * @new_mtu: new value for maximum frame size
5373 * Returns 0 on success, negative on failure
5375 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
5377 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5378 struct ixgbe_hw
*hw
= &adapter
->hw
;
5379 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5381 /* MTU < 68 is an error and causes problems on some kernels */
5382 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
&&
5383 hw
->mac
.type
!= ixgbe_mac_X540
) {
5384 if ((new_mtu
< 68) || (max_frame
> MAXIMUM_ETHERNET_VLAN_SIZE
))
5387 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
5391 e_info(probe
, "changing MTU from %d to %d\n", netdev
->mtu
, new_mtu
);
5392 /* must set new MTU before calling down or up */
5393 netdev
->mtu
= new_mtu
;
5395 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5396 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5398 if (netif_running(netdev
))
5399 ixgbe_reinit_locked(adapter
);
5405 * ixgbe_open - Called when a network interface is made active
5406 * @netdev: network interface device structure
5408 * Returns 0 on success, negative value on failure
5410 * The open entry point is called when a network interface is made
5411 * active by the system (IFF_UP). At this point all resources needed
5412 * for transmit and receive operations are allocated, the interrupt
5413 * handler is registered with the OS, the watchdog timer is started,
5414 * and the stack is notified that the interface is ready.
5416 static int ixgbe_open(struct net_device
*netdev
)
5418 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5421 /* disallow open during test */
5422 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
5425 netif_carrier_off(netdev
);
5427 /* allocate transmit descriptors */
5428 err
= ixgbe_setup_all_tx_resources(adapter
);
5432 /* allocate receive descriptors */
5433 err
= ixgbe_setup_all_rx_resources(adapter
);
5437 ixgbe_configure(adapter
);
5439 err
= ixgbe_request_irq(adapter
);
5443 err
= ixgbe_up_complete(adapter
);
5447 netif_tx_start_all_queues(netdev
);
5452 ixgbe_release_hw_control(adapter
);
5453 ixgbe_free_irq(adapter
);
5456 ixgbe_free_all_rx_resources(adapter
);
5458 ixgbe_free_all_tx_resources(adapter
);
5459 ixgbe_reset(adapter
);
5465 * ixgbe_close - Disables a network interface
5466 * @netdev: network interface device structure
5468 * Returns 0, this is not allowed to fail
5470 * The close entry point is called when an interface is de-activated
5471 * by the OS. The hardware is still under the drivers control, but
5472 * needs to be disabled. A global MAC reset is issued to stop the
5473 * hardware, and all transmit and receive resources are freed.
5475 static int ixgbe_close(struct net_device
*netdev
)
5477 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5479 ixgbe_down(adapter
);
5480 ixgbe_free_irq(adapter
);
5482 ixgbe_fdir_filter_exit(adapter
);
5484 ixgbe_free_all_tx_resources(adapter
);
5485 ixgbe_free_all_rx_resources(adapter
);
5487 ixgbe_release_hw_control(adapter
);
5493 static int ixgbe_resume(struct pci_dev
*pdev
)
5495 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5496 struct net_device
*netdev
= adapter
->netdev
;
5499 pci_set_power_state(pdev
, PCI_D0
);
5500 pci_restore_state(pdev
);
5502 * pci_restore_state clears dev->state_saved so call
5503 * pci_save_state to restore it.
5505 pci_save_state(pdev
);
5507 err
= pci_enable_device_mem(pdev
);
5509 e_dev_err("Cannot enable PCI device from suspend\n");
5512 pci_set_master(pdev
);
5514 pci_wake_from_d3(pdev
, false);
5516 err
= ixgbe_init_interrupt_scheme(adapter
);
5518 e_dev_err("Cannot initialize interrupts for device\n");
5522 ixgbe_reset(adapter
);
5524 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5526 if (netif_running(netdev
)) {
5527 err
= ixgbe_open(netdev
);
5532 netif_device_attach(netdev
);
5536 #endif /* CONFIG_PM */
5538 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5540 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5541 struct net_device
*netdev
= adapter
->netdev
;
5542 struct ixgbe_hw
*hw
= &adapter
->hw
;
5544 u32 wufc
= adapter
->wol
;
5549 netif_device_detach(netdev
);
5551 if (netif_running(netdev
)) {
5552 ixgbe_down(adapter
);
5553 ixgbe_free_irq(adapter
);
5554 ixgbe_free_all_tx_resources(adapter
);
5555 ixgbe_free_all_rx_resources(adapter
);
5558 ixgbe_clear_interrupt_scheme(adapter
);
5560 kfree(adapter
->ixgbe_ieee_pfc
);
5561 kfree(adapter
->ixgbe_ieee_ets
);
5565 retval
= pci_save_state(pdev
);
5571 ixgbe_set_rx_mode(netdev
);
5573 /* turn on all-multi mode if wake on multicast is enabled */
5574 if (wufc
& IXGBE_WUFC_MC
) {
5575 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5576 fctrl
|= IXGBE_FCTRL_MPE
;
5577 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
5580 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
5581 ctrl
|= IXGBE_CTRL_GIO_DIS
;
5582 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
5584 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
5586 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
5587 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
5590 switch (hw
->mac
.type
) {
5591 case ixgbe_mac_82598EB
:
5592 pci_wake_from_d3(pdev
, false);
5594 case ixgbe_mac_82599EB
:
5595 case ixgbe_mac_X540
:
5596 pci_wake_from_d3(pdev
, !!wufc
);
5602 *enable_wake
= !!wufc
;
5604 ixgbe_release_hw_control(adapter
);
5606 pci_disable_device(pdev
);
5612 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5617 retval
= __ixgbe_shutdown(pdev
, &wake
);
5622 pci_prepare_to_sleep(pdev
);
5624 pci_wake_from_d3(pdev
, false);
5625 pci_set_power_state(pdev
, PCI_D3hot
);
5630 #endif /* CONFIG_PM */
5632 static void ixgbe_shutdown(struct pci_dev
*pdev
)
5636 __ixgbe_shutdown(pdev
, &wake
);
5638 if (system_state
== SYSTEM_POWER_OFF
) {
5639 pci_wake_from_d3(pdev
, wake
);
5640 pci_set_power_state(pdev
, PCI_D3hot
);
5645 * ixgbe_update_stats - Update the board statistics counters.
5646 * @adapter: board private structure
5648 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
5650 struct net_device
*netdev
= adapter
->netdev
;
5651 struct ixgbe_hw
*hw
= &adapter
->hw
;
5652 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
5654 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
5655 u64 non_eop_descs
= 0, restart_queue
= 0, tx_busy
= 0;
5656 u64 alloc_rx_page_failed
= 0, alloc_rx_buff_failed
= 0;
5657 u64 bytes
= 0, packets
= 0;
5659 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5660 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5663 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
5666 for (i
= 0; i
< 16; i
++)
5667 adapter
->hw_rx_no_dma_resources
+=
5668 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5669 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5670 rsc_count
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_count
;
5671 rsc_flush
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_flush
;
5673 adapter
->rsc_total_count
= rsc_count
;
5674 adapter
->rsc_total_flush
= rsc_flush
;
5677 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5678 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[i
];
5679 non_eop_descs
+= rx_ring
->rx_stats
.non_eop_descs
;
5680 alloc_rx_page_failed
+= rx_ring
->rx_stats
.alloc_rx_page_failed
;
5681 alloc_rx_buff_failed
+= rx_ring
->rx_stats
.alloc_rx_buff_failed
;
5682 bytes
+= rx_ring
->stats
.bytes
;
5683 packets
+= rx_ring
->stats
.packets
;
5685 adapter
->non_eop_descs
= non_eop_descs
;
5686 adapter
->alloc_rx_page_failed
= alloc_rx_page_failed
;
5687 adapter
->alloc_rx_buff_failed
= alloc_rx_buff_failed
;
5688 netdev
->stats
.rx_bytes
= bytes
;
5689 netdev
->stats
.rx_packets
= packets
;
5693 /* gather some stats to the adapter struct that are per queue */
5694 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5695 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
5696 restart_queue
+= tx_ring
->tx_stats
.restart_queue
;
5697 tx_busy
+= tx_ring
->tx_stats
.tx_busy
;
5698 bytes
+= tx_ring
->stats
.bytes
;
5699 packets
+= tx_ring
->stats
.packets
;
5701 adapter
->restart_queue
= restart_queue
;
5702 adapter
->tx_busy
= tx_busy
;
5703 netdev
->stats
.tx_bytes
= bytes
;
5704 netdev
->stats
.tx_packets
= packets
;
5706 hwstats
->crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
5707 for (i
= 0; i
< 8; i
++) {
5708 /* for packet buffers not used, the register should read 0 */
5709 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
5711 hwstats
->mpc
[i
] += mpc
;
5712 total_mpc
+= hwstats
->mpc
[i
];
5713 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5714 hwstats
->rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
5715 hwstats
->qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
5716 hwstats
->qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
5717 hwstats
->qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
5718 hwstats
->qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
5719 switch (hw
->mac
.type
) {
5720 case ixgbe_mac_82598EB
:
5721 hwstats
->pxonrxc
[i
] +=
5722 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
5724 case ixgbe_mac_82599EB
:
5725 case ixgbe_mac_X540
:
5726 hwstats
->pxonrxc
[i
] +=
5727 IXGBE_READ_REG(hw
, IXGBE_PXONRXCNT(i
));
5732 hwstats
->pxontxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
5733 hwstats
->pxofftxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
5735 hwstats
->gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
5736 /* work around hardware counting issue */
5737 hwstats
->gprc
-= missed_rx
;
5739 ixgbe_update_xoff_received(adapter
);
5741 /* 82598 hardware only has a 32 bit counter in the high register */
5742 switch (hw
->mac
.type
) {
5743 case ixgbe_mac_82598EB
:
5744 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
5745 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
5746 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
5747 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
5749 case ixgbe_mac_X540
:
5750 /* OS2BMC stats are X540 only*/
5751 hwstats
->o2bgptc
+= IXGBE_READ_REG(hw
, IXGBE_O2BGPTC
);
5752 hwstats
->o2bspc
+= IXGBE_READ_REG(hw
, IXGBE_O2BSPC
);
5753 hwstats
->b2ospc
+= IXGBE_READ_REG(hw
, IXGBE_B2OSPC
);
5754 hwstats
->b2ogprc
+= IXGBE_READ_REG(hw
, IXGBE_B2OGPRC
);
5755 case ixgbe_mac_82599EB
:
5756 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
5757 IXGBE_READ_REG(hw
, IXGBE_GORCH
); /* to clear */
5758 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
5759 IXGBE_READ_REG(hw
, IXGBE_GOTCH
); /* to clear */
5760 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
5761 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
5762 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
5763 hwstats
->fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
5764 hwstats
->fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
5766 hwstats
->fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
5767 hwstats
->fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
5768 hwstats
->fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
5769 hwstats
->fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
5770 hwstats
->fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
5771 hwstats
->fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
5772 #endif /* IXGBE_FCOE */
5777 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
5778 hwstats
->bprc
+= bprc
;
5779 hwstats
->mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
5780 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5781 hwstats
->mprc
-= bprc
;
5782 hwstats
->roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
5783 hwstats
->prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
5784 hwstats
->prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
5785 hwstats
->prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
5786 hwstats
->prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
5787 hwstats
->prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
5788 hwstats
->prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
5789 hwstats
->rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
5790 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
5791 hwstats
->lxontxc
+= lxon
;
5792 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
5793 hwstats
->lxofftxc
+= lxoff
;
5794 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5795 hwstats
->gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
5796 hwstats
->mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
5798 * 82598 errata - tx of flow control packets is included in tx counters
5800 xon_off_tot
= lxon
+ lxoff
;
5801 hwstats
->gptc
-= xon_off_tot
;
5802 hwstats
->mptc
-= xon_off_tot
;
5803 hwstats
->gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
5804 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5805 hwstats
->rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
5806 hwstats
->rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
5807 hwstats
->tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
5808 hwstats
->ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
5809 hwstats
->ptc64
-= xon_off_tot
;
5810 hwstats
->ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
5811 hwstats
->ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
5812 hwstats
->ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
5813 hwstats
->ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
5814 hwstats
->ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
5815 hwstats
->bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
5817 /* Fill out the OS statistics structure */
5818 netdev
->stats
.multicast
= hwstats
->mprc
;
5821 netdev
->stats
.rx_errors
= hwstats
->crcerrs
+ hwstats
->rlec
;
5822 netdev
->stats
.rx_dropped
= 0;
5823 netdev
->stats
.rx_length_errors
= hwstats
->rlec
;
5824 netdev
->stats
.rx_crc_errors
= hwstats
->crcerrs
;
5825 netdev
->stats
.rx_missed_errors
= total_mpc
;
5829 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5830 * @adapter - pointer to the device adapter structure
5832 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter
*adapter
)
5834 struct ixgbe_hw
*hw
= &adapter
->hw
;
5837 if (!(adapter
->flags2
& IXGBE_FLAG2_FDIR_REQUIRES_REINIT
))
5840 adapter
->flags2
&= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT
;
5842 /* if interface is down do nothing */
5843 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5846 /* do nothing if we are not using signature filters */
5847 if (!(adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
))
5850 adapter
->fdir_overflow
++;
5852 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5853 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5854 set_bit(__IXGBE_TX_FDIR_INIT_DONE
,
5855 &(adapter
->tx_ring
[i
]->state
));
5856 /* re-enable flow director interrupts */
5857 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_FLOW_DIR
);
5859 e_err(probe
, "failed to finish FDIR re-initialization, "
5860 "ignored adding FDIR ATR filters\n");
5865 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5866 * @adapter - pointer to the device adapter structure
5868 * This function serves two purposes. First it strobes the interrupt lines
5869 * in order to make certain interrupts are occuring. Secondly it sets the
5870 * bits needed to check for TX hangs. As a result we should immediately
5871 * determine if a hang has occured.
5873 static void ixgbe_check_hang_subtask(struct ixgbe_adapter
*adapter
)
5875 struct ixgbe_hw
*hw
= &adapter
->hw
;
5879 /* If we're down or resetting, just bail */
5880 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5881 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5884 /* Force detection of hung controller */
5885 if (netif_carrier_ok(adapter
->netdev
)) {
5886 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5887 set_check_for_tx_hang(adapter
->tx_ring
[i
]);
5890 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5892 * for legacy and MSI interrupts don't set any bits
5893 * that are enabled for EIAM, because this operation
5894 * would set *both* EIMS and EICS for any bit in EIAM
5896 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5897 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5899 /* get one bit for every active tx/rx interrupt vector */
5900 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5901 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5902 if (qv
->rx
.count
|| qv
->tx
.count
)
5903 eics
|= ((u64
)1 << i
);
5907 /* Cause software interrupt to ensure rings are cleaned */
5908 ixgbe_irq_rearm_queues(adapter
, eics
);
5913 * ixgbe_watchdog_update_link - update the link status
5914 * @adapter - pointer to the device adapter structure
5915 * @link_speed - pointer to a u32 to store the link_speed
5917 static void ixgbe_watchdog_update_link(struct ixgbe_adapter
*adapter
)
5919 struct ixgbe_hw
*hw
= &adapter
->hw
;
5920 u32 link_speed
= adapter
->link_speed
;
5921 bool link_up
= adapter
->link_up
;
5924 if (!(adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
))
5927 if (hw
->mac
.ops
.check_link
) {
5928 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5930 /* always assume link is up, if no check link function */
5931 link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
5935 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5936 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5937 hw
->mac
.ops
.fc_enable(hw
, i
);
5939 hw
->mac
.ops
.fc_enable(hw
, 0);
5944 time_after(jiffies
, (adapter
->link_check_timeout
+
5945 IXGBE_TRY_LINK_TIMEOUT
))) {
5946 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5947 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
5948 IXGBE_WRITE_FLUSH(hw
);
5951 adapter
->link_up
= link_up
;
5952 adapter
->link_speed
= link_speed
;
5956 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5957 * print link up message
5958 * @adapter - pointer to the device adapter structure
5960 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter
*adapter
)
5962 struct net_device
*netdev
= adapter
->netdev
;
5963 struct ixgbe_hw
*hw
= &adapter
->hw
;
5964 u32 link_speed
= adapter
->link_speed
;
5965 bool flow_rx
, flow_tx
;
5967 /* only continue if link was previously down */
5968 if (netif_carrier_ok(netdev
))
5971 adapter
->flags2
&= ~IXGBE_FLAG2_SEARCH_FOR_SFP
;
5973 switch (hw
->mac
.type
) {
5974 case ixgbe_mac_82598EB
: {
5975 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5976 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
5977 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
5978 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
5981 case ixgbe_mac_X540
:
5982 case ixgbe_mac_82599EB
: {
5983 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
5984 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
5985 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
5986 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
5994 e_info(drv
, "NIC Link is Up %s, Flow Control: %s\n",
5995 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
5997 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
5999 (link_speed
== IXGBE_LINK_SPEED_100_FULL
?
6002 ((flow_rx
&& flow_tx
) ? "RX/TX" :
6004 (flow_tx
? "TX" : "None"))));
6006 netif_carrier_on(netdev
);
6007 ixgbe_check_vf_rate_limit(adapter
);
6011 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6012 * print link down message
6013 * @adapter - pointer to the adapter structure
6015 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter
* adapter
)
6017 struct net_device
*netdev
= adapter
->netdev
;
6018 struct ixgbe_hw
*hw
= &adapter
->hw
;
6020 adapter
->link_up
= false;
6021 adapter
->link_speed
= 0;
6023 /* only continue if link was up previously */
6024 if (!netif_carrier_ok(netdev
))
6027 /* poll for SFP+ cable when link is down */
6028 if (ixgbe_is_sfp(hw
) && hw
->mac
.type
== ixgbe_mac_82598EB
)
6029 adapter
->flags2
|= IXGBE_FLAG2_SEARCH_FOR_SFP
;
6031 e_info(drv
, "NIC Link is Down\n");
6032 netif_carrier_off(netdev
);
6036 * ixgbe_watchdog_flush_tx - flush queues on link down
6037 * @adapter - pointer to the device adapter structure
6039 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter
*adapter
)
6042 int some_tx_pending
= 0;
6044 if (!netif_carrier_ok(adapter
->netdev
)) {
6045 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
6046 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
6047 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
6048 some_tx_pending
= 1;
6053 if (some_tx_pending
) {
6054 /* We've lost link, so the controller stops DMA,
6055 * but we've got queued Tx work that's never going
6056 * to get done, so reset controller to flush Tx.
6057 * (Do the reset outside of interrupt context).
6059 adapter
->flags2
|= IXGBE_FLAG2_RESET_REQUESTED
;
6064 static void ixgbe_spoof_check(struct ixgbe_adapter
*adapter
)
6068 /* Do not perform spoof check for 82598 */
6069 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
6072 ssvpc
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SSVPC
);
6075 * ssvpc register is cleared on read, if zero then no
6076 * spoofed packets in the last interval.
6081 e_warn(drv
, "%d Spoofed packets detected\n", ssvpc
);
6085 * ixgbe_watchdog_subtask - check and bring link up
6086 * @adapter - pointer to the device adapter structure
6088 static void ixgbe_watchdog_subtask(struct ixgbe_adapter
*adapter
)
6090 /* if interface is down do nothing */
6091 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6094 ixgbe_watchdog_update_link(adapter
);
6096 if (adapter
->link_up
)
6097 ixgbe_watchdog_link_is_up(adapter
);
6099 ixgbe_watchdog_link_is_down(adapter
);
6101 ixgbe_spoof_check(adapter
);
6102 ixgbe_update_stats(adapter
);
6104 ixgbe_watchdog_flush_tx(adapter
);
6108 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6109 * @adapter - the ixgbe adapter structure
6111 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter
*adapter
)
6113 struct ixgbe_hw
*hw
= &adapter
->hw
;
6116 /* not searching for SFP so there is nothing to do here */
6117 if (!(adapter
->flags2
& IXGBE_FLAG2_SEARCH_FOR_SFP
) &&
6118 !(adapter
->flags2
& IXGBE_FLAG2_SFP_NEEDS_RESET
))
6121 /* someone else is in init, wait until next service event */
6122 if (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
6125 err
= hw
->phy
.ops
.identify_sfp(hw
);
6126 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
6129 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
) {
6130 /* If no cable is present, then we need to reset
6131 * the next time we find a good cable. */
6132 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
6139 /* exit if reset not needed */
6140 if (!(adapter
->flags2
& IXGBE_FLAG2_SFP_NEEDS_RESET
))
6143 adapter
->flags2
&= ~IXGBE_FLAG2_SFP_NEEDS_RESET
;
6146 * A module may be identified correctly, but the EEPROM may not have
6147 * support for that module. setup_sfp() will fail in that case, so
6148 * we should not allow that module to load.
6150 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
6151 err
= hw
->phy
.ops
.reset(hw
);
6153 err
= hw
->mac
.ops
.setup_sfp(hw
);
6155 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
6158 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_CONFIG
;
6159 e_info(probe
, "detected SFP+: %d\n", hw
->phy
.sfp_type
);
6162 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
6164 if ((err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) &&
6165 (adapter
->netdev
->reg_state
== NETREG_REGISTERED
)) {
6166 e_dev_err("failed to initialize because an unsupported "
6167 "SFP+ module type was detected.\n");
6168 e_dev_err("Reload the driver after installing a "
6169 "supported module.\n");
6170 unregister_netdev(adapter
->netdev
);
6175 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6176 * @adapter - the ixgbe adapter structure
6178 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter
*adapter
)
6180 struct ixgbe_hw
*hw
= &adapter
->hw
;
6184 if (!(adapter
->flags
& IXGBE_FLAG_NEED_LINK_CONFIG
))
6187 /* someone else is in init, wait until next service event */
6188 if (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
6191 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_CONFIG
;
6193 autoneg
= hw
->phy
.autoneg_advertised
;
6194 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
6195 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
6196 hw
->mac
.autotry_restart
= false;
6197 if (hw
->mac
.ops
.setup_link
)
6198 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
6200 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
6201 adapter
->link_check_timeout
= jiffies
;
6202 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
6206 * ixgbe_service_timer - Timer Call-back
6207 * @data: pointer to adapter cast into an unsigned long
6209 static void ixgbe_service_timer(unsigned long data
)
6211 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
6212 unsigned long next_event_offset
;
6214 /* poll faster when waiting for link */
6215 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
)
6216 next_event_offset
= HZ
/ 10;
6218 next_event_offset
= HZ
* 2;
6220 /* Reset the timer */
6221 mod_timer(&adapter
->service_timer
, next_event_offset
+ jiffies
);
6223 ixgbe_service_event_schedule(adapter
);
6226 static void ixgbe_reset_subtask(struct ixgbe_adapter
*adapter
)
6228 if (!(adapter
->flags2
& IXGBE_FLAG2_RESET_REQUESTED
))
6231 adapter
->flags2
&= ~IXGBE_FLAG2_RESET_REQUESTED
;
6233 /* If we're already down or resetting, just bail */
6234 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
6235 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
6238 ixgbe_dump(adapter
);
6239 netdev_err(adapter
->netdev
, "Reset adapter\n");
6240 adapter
->tx_timeout_count
++;
6242 ixgbe_reinit_locked(adapter
);
6246 * ixgbe_service_task - manages and runs subtasks
6247 * @work: pointer to work_struct containing our data
6249 static void ixgbe_service_task(struct work_struct
*work
)
6251 struct ixgbe_adapter
*adapter
= container_of(work
,
6252 struct ixgbe_adapter
,
6255 ixgbe_reset_subtask(adapter
);
6256 ixgbe_sfp_detection_subtask(adapter
);
6257 ixgbe_sfp_link_config_subtask(adapter
);
6258 ixgbe_check_overtemp_subtask(adapter
);
6259 ixgbe_watchdog_subtask(adapter
);
6260 ixgbe_fdir_reinit_subtask(adapter
);
6261 ixgbe_check_hang_subtask(adapter
);
6263 ixgbe_service_event_complete(adapter
);
6266 void ixgbe_tx_ctxtdesc(struct ixgbe_ring
*tx_ring
, u32 vlan_macip_lens
,
6267 u32 fcoe_sof_eof
, u32 type_tucmd
, u32 mss_l4len_idx
)
6269 struct ixgbe_adv_tx_context_desc
*context_desc
;
6270 u16 i
= tx_ring
->next_to_use
;
6272 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
6275 tx_ring
->next_to_use
= (i
< tx_ring
->count
) ? i
: 0;
6277 /* set bits to identify this as an advanced context descriptor */
6278 type_tucmd
|= IXGBE_TXD_CMD_DEXT
| IXGBE_ADVTXD_DTYP_CTXT
;
6280 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
6281 context_desc
->seqnum_seed
= cpu_to_le32(fcoe_sof_eof
);
6282 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd
);
6283 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
6286 static int ixgbe_tso(struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
6287 u32 tx_flags
, __be16 protocol
, u8
*hdr_len
)
6290 u32 vlan_macip_lens
, type_tucmd
;
6291 u32 mss_l4len_idx
, l4len
;
6293 if (!skb_is_gso(skb
))
6296 if (skb_header_cloned(skb
)) {
6297 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
6302 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6303 type_tucmd
= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6305 if (protocol
== __constant_htons(ETH_P_IP
)) {
6306 struct iphdr
*iph
= ip_hdr(skb
);
6309 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
6313 type_tucmd
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6314 } else if (skb_is_gso_v6(skb
)) {
6315 ipv6_hdr(skb
)->payload_len
= 0;
6316 tcp_hdr(skb
)->check
=
6317 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
6318 &ipv6_hdr(skb
)->daddr
,
6322 l4len
= tcp_hdrlen(skb
);
6323 *hdr_len
= skb_transport_offset(skb
) + l4len
;
6325 /* mss_l4len_id: use 1 as index for TSO */
6326 mss_l4len_idx
= l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
;
6327 mss_l4len_idx
|= skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
;
6328 mss_l4len_idx
|= 1 << IXGBE_ADVTXD_IDX_SHIFT
;
6330 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6331 vlan_macip_lens
= skb_network_header_len(skb
);
6332 vlan_macip_lens
|= skb_network_offset(skb
) << IXGBE_ADVTXD_MACLEN_SHIFT
;
6333 vlan_macip_lens
|= tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
;
6335 ixgbe_tx_ctxtdesc(tx_ring
, vlan_macip_lens
, 0, type_tucmd
,
6341 static bool ixgbe_tx_csum(struct ixgbe_ring
*tx_ring
,
6342 struct sk_buff
*skb
, u32 tx_flags
,
6345 u32 vlan_macip_lens
= 0;
6346 u32 mss_l4len_idx
= 0;
6349 if (skb
->ip_summed
!= CHECKSUM_PARTIAL
) {
6350 if (!(tx_flags
& IXGBE_TX_FLAGS_VLAN
))
6355 case __constant_htons(ETH_P_IP
):
6356 vlan_macip_lens
|= skb_network_header_len(skb
);
6357 type_tucmd
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6358 l4_hdr
= ip_hdr(skb
)->protocol
;
6360 case __constant_htons(ETH_P_IPV6
):
6361 vlan_macip_lens
|= skb_network_header_len(skb
);
6362 l4_hdr
= ipv6_hdr(skb
)->nexthdr
;
6365 if (unlikely(net_ratelimit())) {
6366 dev_warn(tx_ring
->dev
,
6367 "partial checksum but proto=%x!\n",
6375 type_tucmd
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6376 mss_l4len_idx
= tcp_hdrlen(skb
) <<
6377 IXGBE_ADVTXD_L4LEN_SHIFT
;
6380 type_tucmd
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
6381 mss_l4len_idx
= sizeof(struct sctphdr
) <<
6382 IXGBE_ADVTXD_L4LEN_SHIFT
;
6385 mss_l4len_idx
= sizeof(struct udphdr
) <<
6386 IXGBE_ADVTXD_L4LEN_SHIFT
;
6389 if (unlikely(net_ratelimit())) {
6390 dev_warn(tx_ring
->dev
,
6391 "partial checksum but l4 proto=%x!\n",
6398 vlan_macip_lens
|= skb_network_offset(skb
) << IXGBE_ADVTXD_MACLEN_SHIFT
;
6399 vlan_macip_lens
|= tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
;
6401 ixgbe_tx_ctxtdesc(tx_ring
, vlan_macip_lens
, 0,
6402 type_tucmd
, mss_l4len_idx
);
6404 return (skb
->ip_summed
== CHECKSUM_PARTIAL
);
6407 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
6408 struct ixgbe_ring
*tx_ring
,
6409 struct sk_buff
*skb
, u32 tx_flags
,
6410 unsigned int first
, const u8 hdr_len
)
6412 struct device
*dev
= tx_ring
->dev
;
6413 struct ixgbe_tx_buffer
*tx_buffer_info
;
6415 unsigned int total
= skb
->len
;
6416 unsigned int offset
= 0, size
, count
= 0;
6417 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
6419 unsigned int bytecount
= skb
->len
;
6423 i
= tx_ring
->next_to_use
;
6425 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
6426 /* excluding fcoe_crc_eof for FCoE */
6427 total
-= sizeof(struct fcoe_crc_eof
);
6429 len
= min(skb_headlen(skb
), total
);
6431 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6432 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6434 tx_buffer_info
->length
= size
;
6435 tx_buffer_info
->mapped_as_page
= false;
6436 tx_buffer_info
->dma
= dma_map_single(dev
,
6438 size
, DMA_TO_DEVICE
);
6439 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6441 tx_buffer_info
->time_stamp
= jiffies
;
6442 tx_buffer_info
->next_to_watch
= i
;
6451 if (i
== tx_ring
->count
)
6456 for (f
= 0; f
< nr_frags
; f
++) {
6457 struct skb_frag_struct
*frag
;
6459 frag
= &skb_shinfo(skb
)->frags
[f
];
6460 len
= min((unsigned int)frag
->size
, total
);
6461 offset
= frag
->page_offset
;
6465 if (i
== tx_ring
->count
)
6468 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6469 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6471 tx_buffer_info
->length
= size
;
6472 tx_buffer_info
->dma
= dma_map_page(dev
,
6476 tx_buffer_info
->mapped_as_page
= true;
6477 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6479 tx_buffer_info
->time_stamp
= jiffies
;
6480 tx_buffer_info
->next_to_watch
= i
;
6491 if (tx_flags
& IXGBE_TX_FLAGS_TSO
)
6492 gso_segs
= skb_shinfo(skb
)->gso_segs
;
6494 /* adjust for FCoE Sequence Offload */
6495 else if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6496 gso_segs
= DIV_ROUND_UP(skb
->len
- hdr_len
,
6497 skb_shinfo(skb
)->gso_size
);
6498 #endif /* IXGBE_FCOE */
6499 bytecount
+= (gso_segs
- 1) * hdr_len
;
6501 /* multiply data chunks by size of headers */
6502 tx_ring
->tx_buffer_info
[i
].bytecount
= bytecount
;
6503 tx_ring
->tx_buffer_info
[i
].gso_segs
= gso_segs
;
6504 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
6505 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
6510 e_dev_err("TX DMA map failed\n");
6512 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6513 tx_buffer_info
->dma
= 0;
6514 tx_buffer_info
->time_stamp
= 0;
6515 tx_buffer_info
->next_to_watch
= 0;
6519 /* clear timestamp and dma mappings for remaining portion of packet */
6522 i
+= tx_ring
->count
;
6524 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6525 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
6531 static void ixgbe_tx_queue(struct ixgbe_ring
*tx_ring
,
6532 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
6534 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
6535 struct ixgbe_tx_buffer
*tx_buffer_info
;
6536 u32 olinfo_status
= 0, cmd_type_len
= 0;
6538 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
6540 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
6542 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
6544 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6545 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
6547 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
6548 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6550 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6551 IXGBE_ADVTXD_POPTS_SHIFT
;
6553 /* use index 1 context for tso */
6554 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6555 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
6556 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
6557 IXGBE_ADVTXD_POPTS_SHIFT
;
6559 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
6560 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6561 IXGBE_ADVTXD_POPTS_SHIFT
;
6563 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6564 olinfo_status
|= IXGBE_ADVTXD_CC
;
6565 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6566 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6567 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6570 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
6572 i
= tx_ring
->next_to_use
;
6574 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6575 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
6576 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
6577 tx_desc
->read
.cmd_type_len
=
6578 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
6579 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
6581 if (i
== tx_ring
->count
)
6585 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
6588 * Force memory writes to complete before letting h/w
6589 * know there are new descriptors to fetch. (Only
6590 * applicable for weak-ordered memory model archs,
6595 tx_ring
->next_to_use
= i
;
6596 writel(i
, tx_ring
->tail
);
6599 static void ixgbe_atr(struct ixgbe_ring
*ring
, struct sk_buff
*skb
,
6600 u32 tx_flags
, __be16 protocol
)
6602 struct ixgbe_q_vector
*q_vector
= ring
->q_vector
;
6603 union ixgbe_atr_hash_dword input
= { .dword
= 0 };
6604 union ixgbe_atr_hash_dword common
= { .dword
= 0 };
6606 unsigned char *network
;
6608 struct ipv6hdr
*ipv6
;
6613 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6617 /* do nothing if sampling is disabled */
6618 if (!ring
->atr_sample_rate
)
6623 /* snag network header to get L4 type and address */
6624 hdr
.network
= skb_network_header(skb
);
6626 /* Currently only IPv4/IPv6 with TCP is supported */
6627 if ((protocol
!= __constant_htons(ETH_P_IPV6
) ||
6628 hdr
.ipv6
->nexthdr
!= IPPROTO_TCP
) &&
6629 (protocol
!= __constant_htons(ETH_P_IP
) ||
6630 hdr
.ipv4
->protocol
!= IPPROTO_TCP
))
6635 /* skip this packet since the socket is closing */
6639 /* sample on all syn packets or once every atr sample count */
6640 if (!th
->syn
&& (ring
->atr_count
< ring
->atr_sample_rate
))
6643 /* reset sample count */
6644 ring
->atr_count
= 0;
6646 vlan_id
= htons(tx_flags
>> IXGBE_TX_FLAGS_VLAN_SHIFT
);
6649 * src and dst are inverted, think how the receiver sees them
6651 * The input is broken into two sections, a non-compressed section
6652 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6653 * is XORed together and stored in the compressed dword.
6655 input
.formatted
.vlan_id
= vlan_id
;
6658 * since src port and flex bytes occupy the same word XOR them together
6659 * and write the value to source port portion of compressed dword
6662 common
.port
.src
^= th
->dest
^ __constant_htons(ETH_P_8021Q
);
6664 common
.port
.src
^= th
->dest
^ protocol
;
6665 common
.port
.dst
^= th
->source
;
6667 if (protocol
== __constant_htons(ETH_P_IP
)) {
6668 input
.formatted
.flow_type
= IXGBE_ATR_FLOW_TYPE_TCPV4
;
6669 common
.ip
^= hdr
.ipv4
->saddr
^ hdr
.ipv4
->daddr
;
6671 input
.formatted
.flow_type
= IXGBE_ATR_FLOW_TYPE_TCPV6
;
6672 common
.ip
^= hdr
.ipv6
->saddr
.s6_addr32
[0] ^
6673 hdr
.ipv6
->saddr
.s6_addr32
[1] ^
6674 hdr
.ipv6
->saddr
.s6_addr32
[2] ^
6675 hdr
.ipv6
->saddr
.s6_addr32
[3] ^
6676 hdr
.ipv6
->daddr
.s6_addr32
[0] ^
6677 hdr
.ipv6
->daddr
.s6_addr32
[1] ^
6678 hdr
.ipv6
->daddr
.s6_addr32
[2] ^
6679 hdr
.ipv6
->daddr
.s6_addr32
[3];
6682 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6683 ixgbe_fdir_add_signature_filter_82599(&q_vector
->adapter
->hw
,
6684 input
, common
, ring
->queue_index
);
6687 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, u16 size
)
6689 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6690 /* Herbert's original patch had:
6691 * smp_mb__after_netif_stop_queue();
6692 * but since that doesn't exist yet, just open code it. */
6695 /* We need to check again in a case another CPU has just
6696 * made room available. */
6697 if (likely(ixgbe_desc_unused(tx_ring
) < size
))
6700 /* A reprieve! - use start_queue because it doesn't call schedule */
6701 netif_start_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6702 ++tx_ring
->tx_stats
.restart_queue
;
6706 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, u16 size
)
6708 if (likely(ixgbe_desc_unused(tx_ring
) >= size
))
6710 return __ixgbe_maybe_stop_tx(tx_ring
, size
);
6713 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
6715 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6716 int txq
= skb_rx_queue_recorded(skb
) ? skb_get_rx_queue(skb
) :
6719 __be16 protocol
= vlan_get_protocol(skb
);
6721 if (((protocol
== htons(ETH_P_FCOE
)) ||
6722 (protocol
== htons(ETH_P_FIP
))) &&
6723 (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)) {
6724 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
6725 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
6730 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
6731 while (unlikely(txq
>= dev
->real_num_tx_queues
))
6732 txq
-= dev
->real_num_tx_queues
;
6736 return skb_tx_hash(dev
, skb
);
6739 netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*skb
,
6740 struct ixgbe_adapter
*adapter
,
6741 struct ixgbe_ring
*tx_ring
)
6745 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6749 u16 count
= TXD_USE_COUNT(skb_headlen(skb
));
6754 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6755 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6756 * + 2 desc gap to keep tail from touching head,
6757 * + 1 desc for context descriptor,
6758 * otherwise try next time
6760 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6761 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
6762 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
6764 count
+= skb_shinfo(skb
)->nr_frags
;
6766 if (ixgbe_maybe_stop_tx(tx_ring
, count
+ 3)) {
6767 tx_ring
->tx_stats
.tx_busy
++;
6768 return NETDEV_TX_BUSY
;
6771 protocol
= vlan_get_protocol(skb
);
6773 if (vlan_tx_tag_present(skb
)) {
6774 tx_flags
|= vlan_tx_tag_get(skb
);
6775 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6776 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
6777 tx_flags
|= tx_ring
->dcb_tc
<< 13;
6779 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6780 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6781 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
&&
6782 skb
->priority
!= TC_PRIO_CONTROL
) {
6783 tx_flags
|= tx_ring
->dcb_tc
<< 13;
6784 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6785 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6789 /* for FCoE with DCB, we force the priority to what
6790 * was specified by the switch */
6791 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
&&
6792 (protocol
== htons(ETH_P_FCOE
)))
6793 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
6796 /* record the location of the first descriptor for this packet */
6797 first
= tx_ring
->next_to_use
;
6799 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6801 /* setup tx offload for FCoE */
6802 tso
= ixgbe_fso(tx_ring
, skb
, tx_flags
, &hdr_len
);
6806 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
6807 #endif /* IXGBE_FCOE */
6809 if (protocol
== htons(ETH_P_IP
))
6810 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
6811 tso
= ixgbe_tso(tx_ring
, skb
, tx_flags
, protocol
, &hdr_len
);
6815 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
6816 else if (ixgbe_tx_csum(tx_ring
, skb
, tx_flags
, protocol
))
6817 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
6820 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
, hdr_len
);
6822 /* add the ATR filter if ATR is on */
6823 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE
, &tx_ring
->state
))
6824 ixgbe_atr(tx_ring
, skb
, tx_flags
, protocol
);
6825 ixgbe_tx_queue(tx_ring
, tx_flags
, count
, skb
->len
, hdr_len
);
6826 ixgbe_maybe_stop_tx(tx_ring
, DESC_NEEDED
);
6829 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
6830 tx_ring
->next_to_use
= first
;
6834 return NETDEV_TX_OK
;
6837 dev_kfree_skb_any(skb
);
6838 return NETDEV_TX_OK
;
6841 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
6843 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6844 struct ixgbe_ring
*tx_ring
;
6846 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
6847 return ixgbe_xmit_frame_ring(skb
, adapter
, tx_ring
);
6851 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6852 * @netdev: network interface device structure
6853 * @p: pointer to an address structure
6855 * Returns 0 on success, negative on failure
6857 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
6859 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6860 struct ixgbe_hw
*hw
= &adapter
->hw
;
6861 struct sockaddr
*addr
= p
;
6863 if (!is_valid_ether_addr(addr
->sa_data
))
6864 return -EADDRNOTAVAIL
;
6866 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
6867 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
6869 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
6876 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
6878 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6879 struct ixgbe_hw
*hw
= &adapter
->hw
;
6883 if (prtad
!= hw
->phy
.mdio
.prtad
)
6885 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
6891 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
6892 u16 addr
, u16 value
)
6894 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6895 struct ixgbe_hw
*hw
= &adapter
->hw
;
6897 if (prtad
!= hw
->phy
.mdio
.prtad
)
6899 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
6902 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
6904 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6906 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
6910 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6912 * @netdev: network interface device structure
6914 * Returns non-zero on failure
6916 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
6919 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6920 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6922 if (is_valid_ether_addr(mac
->san_addr
)) {
6924 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6931 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6933 * @netdev: network interface device structure
6935 * Returns non-zero on failure
6937 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
6940 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6941 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6943 if (is_valid_ether_addr(mac
->san_addr
)) {
6945 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6951 #ifdef CONFIG_NET_POLL_CONTROLLER
6953 * Polling 'interrupt' - used by things like netconsole to send skbs
6954 * without having to re-enable interrupts. It's not called while
6955 * the interrupt routine is executing.
6957 static void ixgbe_netpoll(struct net_device
*netdev
)
6959 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6962 /* if interface is down do nothing */
6963 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6966 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
6967 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
6968 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
6969 for (i
= 0; i
< num_q_vectors
; i
++) {
6970 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
6971 ixgbe_msix_clean_many(0, q_vector
);
6974 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
6976 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
6980 static struct rtnl_link_stats64
*ixgbe_get_stats64(struct net_device
*netdev
,
6981 struct rtnl_link_stats64
*stats
)
6983 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6987 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
6988 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->rx_ring
[i
]);
6994 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
6995 packets
= ring
->stats
.packets
;
6996 bytes
= ring
->stats
.bytes
;
6997 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
6998 stats
->rx_packets
+= packets
;
6999 stats
->rx_bytes
+= bytes
;
7003 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
7004 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->tx_ring
[i
]);
7010 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
7011 packets
= ring
->stats
.packets
;
7012 bytes
= ring
->stats
.bytes
;
7013 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
7014 stats
->tx_packets
+= packets
;
7015 stats
->tx_bytes
+= bytes
;
7019 /* following stats updated by ixgbe_watchdog_task() */
7020 stats
->multicast
= netdev
->stats
.multicast
;
7021 stats
->rx_errors
= netdev
->stats
.rx_errors
;
7022 stats
->rx_length_errors
= netdev
->stats
.rx_length_errors
;
7023 stats
->rx_crc_errors
= netdev
->stats
.rx_crc_errors
;
7024 stats
->rx_missed_errors
= netdev
->stats
.rx_missed_errors
;
7028 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7029 * #adapter: pointer to ixgbe_adapter
7030 * @tc: number of traffic classes currently enabled
7032 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7033 * 802.1Q priority maps to a packet buffer that exists.
7035 static void ixgbe_validate_rtr(struct ixgbe_adapter
*adapter
, u8 tc
)
7037 struct ixgbe_hw
*hw
= &adapter
->hw
;
7041 /* 82598 have a static priority to TC mapping that can not
7042 * be changed so no validation is needed.
7044 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
7047 reg
= IXGBE_READ_REG(hw
, IXGBE_RTRUP2TC
);
7050 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
7051 u8 up2tc
= reg
>> (i
* IXGBE_RTRUP2TC_UP_SHIFT
);
7053 /* If up2tc is out of bounds default to zero */
7055 reg
&= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT
);
7059 IXGBE_WRITE_REG(hw
, IXGBE_RTRUP2TC
, reg
);
7065 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7068 * @netdev: net device to configure
7069 * @tc: number of traffic classes to enable
7071 int ixgbe_setup_tc(struct net_device
*dev
, u8 tc
)
7073 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
7074 struct ixgbe_hw
*hw
= &adapter
->hw
;
7076 /* If DCB is anabled do not remove traffic classes, multiple
7077 * traffic classes are required to implement DCB
7079 if (!tc
&& (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
7082 /* Hardware supports up to 8 traffic classes */
7083 if (tc
> MAX_TRAFFIC_CLASS
||
7084 (hw
->mac
.type
== ixgbe_mac_82598EB
&& tc
< MAX_TRAFFIC_CLASS
))
7087 /* Hardware has to reinitialize queues and interrupts to
7088 * match packet buffer alignment. Unfortunantly, the
7089 * hardware is not flexible enough to do this dynamically.
7091 if (netif_running(dev
))
7093 ixgbe_clear_interrupt_scheme(adapter
);
7096 netdev_set_num_tc(dev
, tc
);
7098 netdev_reset_tc(dev
);
7100 ixgbe_init_interrupt_scheme(adapter
);
7101 ixgbe_validate_rtr(adapter
, tc
);
7102 if (netif_running(dev
))
7108 void ixgbe_do_reset(struct net_device
*netdev
)
7110 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7112 if (netif_running(netdev
))
7113 ixgbe_reinit_locked(adapter
);
7115 ixgbe_reset(adapter
);
7118 static u32
ixgbe_fix_features(struct net_device
*netdev
, u32 data
)
7120 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7123 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
7124 data
&= ~NETIF_F_HW_VLAN_RX
;
7127 /* return error if RXHASH is being enabled when RSS is not supported */
7128 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
))
7129 data
&= ~NETIF_F_RXHASH
;
7131 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7132 if (!(data
& NETIF_F_RXCSUM
))
7133 data
&= ~NETIF_F_LRO
;
7135 /* Turn off LRO if not RSC capable or invalid ITR settings */
7136 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)) {
7137 data
&= ~NETIF_F_LRO
;
7138 } else if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
7139 (adapter
->rx_itr_setting
!= 1 &&
7140 adapter
->rx_itr_setting
> IXGBE_MAX_RSC_INT_RATE
)) {
7141 data
&= ~NETIF_F_LRO
;
7142 e_info(probe
, "rx-usecs set too low, not enabling RSC\n");
7148 static int ixgbe_set_features(struct net_device
*netdev
, u32 data
)
7150 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7151 bool need_reset
= false;
7153 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7154 if (!(data
& NETIF_F_RXCSUM
))
7155 adapter
->flags
&= ~IXGBE_FLAG_RX_CSUM_ENABLED
;
7157 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
7159 /* Make sure RSC matches LRO, reset if change */
7160 if (!!(data
& NETIF_F_LRO
) !=
7161 !!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)) {
7162 adapter
->flags2
^= IXGBE_FLAG2_RSC_ENABLED
;
7163 switch (adapter
->hw
.mac
.type
) {
7164 case ixgbe_mac_X540
:
7165 case ixgbe_mac_82599EB
:
7174 * Check if Flow Director n-tuple support was enabled or disabled. If
7175 * the state changed, we need to reset.
7177 if (!(adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)) {
7178 /* turn off ATR, enable perfect filters and reset */
7179 if (data
& NETIF_F_NTUPLE
) {
7180 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
7181 adapter
->flags
|= IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
7184 } else if (!(data
& NETIF_F_NTUPLE
)) {
7185 /* turn off Flow Director, set ATR and reset */
7186 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
7187 if ((adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) &&
7188 !(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
7189 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
7194 ixgbe_do_reset(netdev
);
7200 static const struct net_device_ops ixgbe_netdev_ops
= {
7201 .ndo_open
= ixgbe_open
,
7202 .ndo_stop
= ixgbe_close
,
7203 .ndo_start_xmit
= ixgbe_xmit_frame
,
7204 .ndo_select_queue
= ixgbe_select_queue
,
7205 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
7206 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
7207 .ndo_validate_addr
= eth_validate_addr
,
7208 .ndo_set_mac_address
= ixgbe_set_mac
,
7209 .ndo_change_mtu
= ixgbe_change_mtu
,
7210 .ndo_tx_timeout
= ixgbe_tx_timeout
,
7211 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
7212 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
7213 .ndo_do_ioctl
= ixgbe_ioctl
,
7214 .ndo_set_vf_mac
= ixgbe_ndo_set_vf_mac
,
7215 .ndo_set_vf_vlan
= ixgbe_ndo_set_vf_vlan
,
7216 .ndo_set_vf_tx_rate
= ixgbe_ndo_set_vf_bw
,
7217 .ndo_get_vf_config
= ixgbe_ndo_get_vf_config
,
7218 .ndo_get_stats64
= ixgbe_get_stats64
,
7219 .ndo_setup_tc
= ixgbe_setup_tc
,
7220 #ifdef CONFIG_NET_POLL_CONTROLLER
7221 .ndo_poll_controller
= ixgbe_netpoll
,
7224 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
7225 .ndo_fcoe_ddp_target
= ixgbe_fcoe_ddp_target
,
7226 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
7227 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
7228 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
7229 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
7230 #endif /* IXGBE_FCOE */
7231 .ndo_set_features
= ixgbe_set_features
,
7232 .ndo_fix_features
= ixgbe_fix_features
,
7235 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
7236 const struct ixgbe_info
*ii
)
7238 #ifdef CONFIG_PCI_IOV
7239 struct ixgbe_hw
*hw
= &adapter
->hw
;
7241 int num_vf_macvlans
, i
;
7242 struct vf_macvlans
*mv_list
;
7244 if (hw
->mac
.type
== ixgbe_mac_82598EB
|| !max_vfs
)
7247 /* The 82599 supports up to 64 VFs per physical function
7248 * but this implementation limits allocation to 63 so that
7249 * basic networking resources are still available to the
7252 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
7253 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
7254 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
7256 e_err(probe
, "Failed to enable PCI sriov: %d\n", err
);
7260 num_vf_macvlans
= hw
->mac
.num_rar_entries
-
7261 (IXGBE_MAX_PF_MACVLANS
+ 1 + adapter
->num_vfs
);
7263 adapter
->mv_list
= mv_list
= kcalloc(num_vf_macvlans
,
7264 sizeof(struct vf_macvlans
),
7267 /* Initialize list of VF macvlans */
7268 INIT_LIST_HEAD(&adapter
->vf_mvs
.l
);
7269 for (i
= 0; i
< num_vf_macvlans
; i
++) {
7271 mv_list
->free
= true;
7272 mv_list
->rar_entry
= hw
->mac
.num_rar_entries
-
7273 (i
+ adapter
->num_vfs
+ 1);
7274 list_add(&mv_list
->l
, &adapter
->vf_mvs
.l
);
7279 /* If call to enable VFs succeeded then allocate memory
7280 * for per VF control structures.
7283 kcalloc(adapter
->num_vfs
,
7284 sizeof(struct vf_data_storage
), GFP_KERNEL
);
7285 if (adapter
->vfinfo
) {
7286 /* Now that we're sure SR-IOV is enabled
7287 * and memory allocated set up the mailbox parameters
7289 ixgbe_init_mbx_params_pf(hw
);
7290 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
7291 sizeof(hw
->mbx
.ops
));
7293 /* Disable RSC when in SR-IOV mode */
7294 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
7295 IXGBE_FLAG2_RSC_ENABLED
);
7300 e_err(probe
, "Unable to allocate memory for VF Data Storage - "
7301 "SRIOV disabled\n");
7302 pci_disable_sriov(adapter
->pdev
);
7305 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
7306 adapter
->num_vfs
= 0;
7307 #endif /* CONFIG_PCI_IOV */
7311 * ixgbe_probe - Device Initialization Routine
7312 * @pdev: PCI device information struct
7313 * @ent: entry in ixgbe_pci_tbl
7315 * Returns 0 on success, negative on failure
7317 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7318 * The OS initialization, configuring of the adapter private structure,
7319 * and a hardware reset occur.
7321 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
7322 const struct pci_device_id
*ent
)
7324 struct net_device
*netdev
;
7325 struct ixgbe_adapter
*adapter
= NULL
;
7326 struct ixgbe_hw
*hw
;
7327 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
7328 static int cards_found
;
7329 int i
, err
, pci_using_dac
;
7330 u8 part_str
[IXGBE_PBANUM_LENGTH
];
7331 unsigned int indices
= num_possible_cpus();
7337 /* Catch broken hardware that put the wrong VF device ID in
7338 * the PCIe SR-IOV capability.
7340 if (pdev
->is_virtfn
) {
7341 WARN(1, KERN_ERR
"%s (%hx:%hx) should not be a VF!\n",
7342 pci_name(pdev
), pdev
->vendor
, pdev
->device
);
7346 err
= pci_enable_device_mem(pdev
);
7350 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
7351 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
7354 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
7356 err
= dma_set_coherent_mask(&pdev
->dev
,
7360 "No usable DMA configuration, aborting\n");
7367 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
7368 IORESOURCE_MEM
), ixgbe_driver_name
);
7371 "pci_request_selected_regions failed 0x%x\n", err
);
7375 pci_enable_pcie_error_reporting(pdev
);
7377 pci_set_master(pdev
);
7378 pci_save_state(pdev
);
7380 #ifdef CONFIG_IXGBE_DCB
7381 indices
*= MAX_TRAFFIC_CLASS
;
7384 if (ii
->mac
== ixgbe_mac_82598EB
)
7385 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
7387 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
7390 indices
+= min_t(unsigned int, num_possible_cpus(),
7391 IXGBE_MAX_FCOE_INDICES
);
7393 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
7396 goto err_alloc_etherdev
;
7399 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
7401 adapter
= netdev_priv(netdev
);
7402 pci_set_drvdata(pdev
, adapter
);
7404 adapter
->netdev
= netdev
;
7405 adapter
->pdev
= pdev
;
7408 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
7410 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
7411 pci_resource_len(pdev
, 0));
7417 for (i
= 1; i
<= 5; i
++) {
7418 if (pci_resource_len(pdev
, i
) == 0)
7422 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
7423 ixgbe_set_ethtool_ops(netdev
);
7424 netdev
->watchdog_timeo
= 5 * HZ
;
7425 strncpy(netdev
->name
, pci_name(pdev
), sizeof(netdev
->name
) - 1);
7427 adapter
->bd_number
= cards_found
;
7430 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
7431 hw
->mac
.type
= ii
->mac
;
7434 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
7435 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
7436 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7437 if (!(eec
& (1 << 8)))
7438 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
7441 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
7442 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
7443 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7444 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
7445 hw
->phy
.mdio
.mmds
= 0;
7446 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
7447 hw
->phy
.mdio
.dev
= netdev
;
7448 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
7449 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
7451 ii
->get_invariants(hw
);
7453 /* setup the private structure */
7454 err
= ixgbe_sw_init(adapter
);
7458 /* Make it possible the adapter to be woken up via WOL */
7459 switch (adapter
->hw
.mac
.type
) {
7460 case ixgbe_mac_82599EB
:
7461 case ixgbe_mac_X540
:
7462 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7469 * If there is a fan on this device and it has failed log the
7472 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
7473 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
7474 if (esdp
& IXGBE_ESDP_SDP1
)
7475 e_crit(probe
, "Fan has stopped, replace the adapter\n");
7478 /* reset_hw fills in the perm_addr as well */
7479 hw
->phy
.reset_if_overtemp
= true;
7480 err
= hw
->mac
.ops
.reset_hw(hw
);
7481 hw
->phy
.reset_if_overtemp
= false;
7482 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
7483 hw
->mac
.type
== ixgbe_mac_82598EB
) {
7485 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
7486 e_dev_err("failed to load because an unsupported SFP+ "
7487 "module type was detected.\n");
7488 e_dev_err("Reload the driver after installing a supported "
7492 e_dev_err("HW Init failed: %d\n", err
);
7496 ixgbe_probe_vf(adapter
, ii
);
7498 netdev
->features
= NETIF_F_SG
|
7501 NETIF_F_HW_VLAN_TX
|
7502 NETIF_F_HW_VLAN_RX
|
7503 NETIF_F_HW_VLAN_FILTER
|
7510 netdev
->hw_features
= netdev
->features
;
7512 switch (adapter
->hw
.mac
.type
) {
7513 case ixgbe_mac_82599EB
:
7514 case ixgbe_mac_X540
:
7515 netdev
->features
|= NETIF_F_SCTP_CSUM
;
7516 netdev
->hw_features
|= NETIF_F_SCTP_CSUM
|
7523 netdev
->vlan_features
|= NETIF_F_TSO
;
7524 netdev
->vlan_features
|= NETIF_F_TSO6
;
7525 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
7526 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
7527 netdev
->vlan_features
|= NETIF_F_SG
;
7529 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7530 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
7531 IXGBE_FLAG_DCB_ENABLED
);
7533 #ifdef CONFIG_IXGBE_DCB
7534 netdev
->dcbnl_ops
= &dcbnl_ops
;
7538 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7539 if (hw
->mac
.ops
.get_device_caps
) {
7540 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
7541 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
7542 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
7545 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7546 netdev
->vlan_features
|= NETIF_F_FCOE_CRC
;
7547 netdev
->vlan_features
|= NETIF_F_FSO
;
7548 netdev
->vlan_features
|= NETIF_F_FCOE_MTU
;
7550 #endif /* IXGBE_FCOE */
7551 if (pci_using_dac
) {
7552 netdev
->features
|= NETIF_F_HIGHDMA
;
7553 netdev
->vlan_features
|= NETIF_F_HIGHDMA
;
7556 if (adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)
7557 netdev
->hw_features
|= NETIF_F_LRO
;
7558 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
7559 netdev
->features
|= NETIF_F_LRO
;
7561 /* make sure the EEPROM is good */
7562 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
7563 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7568 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7569 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7571 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
7572 e_dev_err("invalid MAC address\n");
7577 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7578 if (hw
->mac
.ops
.disable_tx_laser
&&
7579 ((hw
->phy
.multispeed_fiber
) ||
7580 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
7581 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
7582 hw
->mac
.ops
.disable_tx_laser(hw
);
7584 setup_timer(&adapter
->service_timer
, &ixgbe_service_timer
,
7585 (unsigned long) adapter
);
7587 INIT_WORK(&adapter
->service_task
, ixgbe_service_task
);
7588 clear_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
);
7590 err
= ixgbe_init_interrupt_scheme(adapter
);
7594 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)) {
7595 netdev
->hw_features
&= ~NETIF_F_RXHASH
;
7596 netdev
->features
&= ~NETIF_F_RXHASH
;
7599 switch (pdev
->device
) {
7600 case IXGBE_DEV_ID_82599_SFP
:
7601 /* Only this subdevice supports WOL */
7602 if (pdev
->subsystem_device
== IXGBE_SUBDEV_ID_82599_SFP
)
7603 adapter
->wol
= IXGBE_WUFC_MAG
;
7605 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
7606 /* All except this subdevice support WOL */
7607 if (pdev
->subsystem_device
!= IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ
)
7608 adapter
->wol
= IXGBE_WUFC_MAG
;
7610 case IXGBE_DEV_ID_82599_KX4
:
7611 adapter
->wol
= IXGBE_WUFC_MAG
;
7617 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
7619 /* pick up the PCI bus settings for reporting later */
7620 hw
->mac
.ops
.get_bus_info(hw
);
7622 /* print bus type/speed/width info */
7623 e_dev_info("(PCI Express:%s:%s) %pM\n",
7624 (hw
->bus
.speed
== ixgbe_bus_speed_5000
? "5.0GT/s" :
7625 hw
->bus
.speed
== ixgbe_bus_speed_2500
? "2.5GT/s" :
7627 (hw
->bus
.width
== ixgbe_bus_width_pcie_x8
? "Width x8" :
7628 hw
->bus
.width
== ixgbe_bus_width_pcie_x4
? "Width x4" :
7629 hw
->bus
.width
== ixgbe_bus_width_pcie_x1
? "Width x1" :
7633 err
= ixgbe_read_pba_string_generic(hw
, part_str
, IXGBE_PBANUM_LENGTH
);
7635 strncpy(part_str
, "Unknown", IXGBE_PBANUM_LENGTH
);
7636 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
7637 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7638 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
7641 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7642 hw
->mac
.type
, hw
->phy
.type
, part_str
);
7644 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
7645 e_dev_warn("PCI-Express bandwidth available for this card is "
7646 "not sufficient for optimal performance.\n");
7647 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7651 /* save off EEPROM version number */
7652 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
7654 /* reset the hardware with the new settings */
7655 err
= hw
->mac
.ops
.start_hw(hw
);
7657 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
7658 /* We are running on a pre-production device, log a warning */
7659 e_dev_warn("This device is a pre-production adapter/LOM. "
7660 "Please be aware there may be issues associated "
7661 "with your hardware. If you are experiencing "
7662 "problems please contact your Intel or hardware "
7663 "representative who provided you with this "
7666 strcpy(netdev
->name
, "eth%d");
7667 err
= register_netdev(netdev
);
7671 /* carrier off reporting is important to ethtool even BEFORE open */
7672 netif_carrier_off(netdev
);
7674 #ifdef CONFIG_IXGBE_DCA
7675 if (dca_add_requester(&pdev
->dev
) == 0) {
7676 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
7677 ixgbe_setup_dca(adapter
);
7680 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
7681 e_info(probe
, "IOV is enabled with %d VFs\n", adapter
->num_vfs
);
7682 for (i
= 0; i
< adapter
->num_vfs
; i
++)
7683 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
7686 /* Inform firmware of driver version */
7687 if (hw
->mac
.ops
.set_fw_drv_ver
)
7688 hw
->mac
.ops
.set_fw_drv_ver(hw
, MAJ
, MIN
, BUILD
,
7691 /* add san mac addr to netdev */
7692 ixgbe_add_sanmac_netdev(netdev
);
7694 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7699 ixgbe_release_hw_control(adapter
);
7700 ixgbe_clear_interrupt_scheme(adapter
);
7703 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7704 ixgbe_disable_sriov(adapter
);
7705 adapter
->flags2
&= ~IXGBE_FLAG2_SEARCH_FOR_SFP
;
7706 iounmap(hw
->hw_addr
);
7708 free_netdev(netdev
);
7710 pci_release_selected_regions(pdev
,
7711 pci_select_bars(pdev
, IORESOURCE_MEM
));
7714 pci_disable_device(pdev
);
7719 * ixgbe_remove - Device Removal Routine
7720 * @pdev: PCI device information struct
7722 * ixgbe_remove is called by the PCI subsystem to alert the driver
7723 * that it should release a PCI device. The could be caused by a
7724 * Hot-Plug event, or because the driver is going to be removed from
7727 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
7729 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7730 struct net_device
*netdev
= adapter
->netdev
;
7732 set_bit(__IXGBE_DOWN
, &adapter
->state
);
7733 cancel_work_sync(&adapter
->service_task
);
7735 #ifdef CONFIG_IXGBE_DCA
7736 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
7737 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
7738 dca_remove_requester(&pdev
->dev
);
7739 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
7744 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
7745 ixgbe_cleanup_fcoe(adapter
);
7747 #endif /* IXGBE_FCOE */
7749 /* remove the added san mac */
7750 ixgbe_del_sanmac_netdev(netdev
);
7752 if (netdev
->reg_state
== NETREG_REGISTERED
)
7753 unregister_netdev(netdev
);
7755 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7756 ixgbe_disable_sriov(adapter
);
7758 ixgbe_clear_interrupt_scheme(adapter
);
7760 ixgbe_release_hw_control(adapter
);
7762 iounmap(adapter
->hw
.hw_addr
);
7763 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
7766 e_dev_info("complete\n");
7768 free_netdev(netdev
);
7770 pci_disable_pcie_error_reporting(pdev
);
7772 pci_disable_device(pdev
);
7776 * ixgbe_io_error_detected - called when PCI error is detected
7777 * @pdev: Pointer to PCI device
7778 * @state: The current pci connection state
7780 * This function is called after a PCI bus error affecting
7781 * this device has been detected.
7783 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
7784 pci_channel_state_t state
)
7786 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7787 struct net_device
*netdev
= adapter
->netdev
;
7789 netif_device_detach(netdev
);
7791 if (state
== pci_channel_io_perm_failure
)
7792 return PCI_ERS_RESULT_DISCONNECT
;
7794 if (netif_running(netdev
))
7795 ixgbe_down(adapter
);
7796 pci_disable_device(pdev
);
7798 /* Request a slot reset. */
7799 return PCI_ERS_RESULT_NEED_RESET
;
7803 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7804 * @pdev: Pointer to PCI device
7806 * Restart the card from scratch, as if from a cold-boot.
7808 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
7810 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7811 pci_ers_result_t result
;
7814 if (pci_enable_device_mem(pdev
)) {
7815 e_err(probe
, "Cannot re-enable PCI device after reset.\n");
7816 result
= PCI_ERS_RESULT_DISCONNECT
;
7818 pci_set_master(pdev
);
7819 pci_restore_state(pdev
);
7820 pci_save_state(pdev
);
7822 pci_wake_from_d3(pdev
, false);
7824 ixgbe_reset(adapter
);
7825 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7826 result
= PCI_ERS_RESULT_RECOVERED
;
7829 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7831 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7832 "failed 0x%0x\n", err
);
7833 /* non-fatal, continue */
7840 * ixgbe_io_resume - called when traffic can start flowing again.
7841 * @pdev: Pointer to PCI device
7843 * This callback is called when the error recovery driver tells us that
7844 * its OK to resume normal operation.
7846 static void ixgbe_io_resume(struct pci_dev
*pdev
)
7848 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7849 struct net_device
*netdev
= adapter
->netdev
;
7851 if (netif_running(netdev
)) {
7852 if (ixgbe_up(adapter
)) {
7853 e_info(probe
, "ixgbe_up failed after reset\n");
7858 netif_device_attach(netdev
);
7861 static struct pci_error_handlers ixgbe_err_handler
= {
7862 .error_detected
= ixgbe_io_error_detected
,
7863 .slot_reset
= ixgbe_io_slot_reset
,
7864 .resume
= ixgbe_io_resume
,
7867 static struct pci_driver ixgbe_driver
= {
7868 .name
= ixgbe_driver_name
,
7869 .id_table
= ixgbe_pci_tbl
,
7870 .probe
= ixgbe_probe
,
7871 .remove
= __devexit_p(ixgbe_remove
),
7873 .suspend
= ixgbe_suspend
,
7874 .resume
= ixgbe_resume
,
7876 .shutdown
= ixgbe_shutdown
,
7877 .err_handler
= &ixgbe_err_handler
7881 * ixgbe_init_module - Driver Registration Routine
7883 * ixgbe_init_module is the first routine called when the driver is
7884 * loaded. All it does is register with the PCI subsystem.
7886 static int __init
ixgbe_init_module(void)
7889 pr_info("%s - version %s\n", ixgbe_driver_string
, ixgbe_driver_version
);
7890 pr_info("%s\n", ixgbe_copyright
);
7892 #ifdef CONFIG_IXGBE_DCA
7893 dca_register_notify(&dca_notifier
);
7896 ret
= pci_register_driver(&ixgbe_driver
);
7900 module_init(ixgbe_init_module
);
7903 * ixgbe_exit_module - Driver Exit Cleanup Routine
7905 * ixgbe_exit_module is called just before the driver is removed
7908 static void __exit
ixgbe_exit_module(void)
7910 #ifdef CONFIG_IXGBE_DCA
7911 dca_unregister_notify(&dca_notifier
);
7913 pci_unregister_driver(&ixgbe_driver
);
7914 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7917 #ifdef CONFIG_IXGBE_DCA
7918 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
7923 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
7924 __ixgbe_notify_dca
);
7926 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
7929 #endif /* CONFIG_IXGBE_DCA */
7931 module_exit(ixgbe_exit_module
);