drivers/net/mipsnet.h

   1 //
   2 // <COPYRIGHT CLASS="1B" YEAR="2005">
   3 // Unpublished work (c) MIPS Technologies, Inc.  All rights reserved.
   4 // Unpublished rights reserved under the copyright laws of the U.S.A. and
   5 //  other countries.
   6 //
   7 // PROPRIETARY / SECRET CONFIDENTIAL INFORMATION OF MIPS TECHNOLOGIES, INC.
   8 // FOR INTERNAL USE ONLY.
   9 //
  10 // Under no circumstances (contract or otherwise) may this information be
  11 // disclosed to, or copied, modified or used by anyone other than employees
  12 // or contractors of MIPS Technologies having a need to know.
  13 // </COPYRIGHT>
  14 //
  15 //++
  16 // File: MIPS_Net.h
  17 //
  18 // Description:
  19 //   The definition of the emulated MIPSNET device's interface.
  20 //
  21 // Notes: This include file needs to work from a Linux device drivers.
  22 //
  23 //--
  24 //
  25
  26 #ifndef __MIPSNET_H
  27 #define __MIPSNET_H
  28
  29 /*
  30  *  Id of this Net device, as seen by the core.
  31  */
  32 #define MIPS_NET_DEV_ID ((uint64_t)           \
  33                              ((uint64_t)'M'<< 0)| \
  34                              ((uint64_t)'I'<< 8)| \
  35                              ((uint64_t)'P'<<16)| \
  36                              ((uint64_t)'S'<<24)| \
  37                              ((uint64_t)'N'<<32)| \
  38                              ((uint64_t)'E'<<40)| \
  39                              ((uint64_t)'T'<<48)| \
  40                              ((uint64_t)'0'<<56))
  41
  42 /*
  43  * Net status/control block as seen by sw in the core.
  44  * (Why not use bit fields? can't be bothered with cross-platform struct
  45  *  packing.)
  46  */
  47 typedef struct _net_control_block {
  48         /// dev info for probing
  49         ///  reads as MIPSNET%d where %d is some form of version
  50         uint64_t devId;         /*0x00 */
  51
  52         /*
  53          * read only busy flag.
  54          * Set and cleared by the Net Device to indicate that an rx or a tx
  55          * is in progress.
  56          */
  57         uint32_t busy;          /*0x08 */
  58
  59         /*
  60          * Set by the Net Device.
  61          * The device will set it once data has been received.
  62          * The value is the number of bytes that should be read from
  63          * rxDataBuffer.  The value will decrease till 0 until all the data
  64          * from rxDataBuffer has been read.
  65          */
  66         uint32_t rxDataCount;   /*0x0c */
  67 #define MIPSNET_MAX_RXTX_DATACOUNT (1<<16)
  68
  69         /*
  70          * Settable from the MIPS core, cleared by the Net Device.
  71          * The core should set the number of bytes it wants to send,
  72          *   then it should write those bytes of data to txDataBuffer.
  73          * The device will clear txDataCount has been processed (not necessarily sent).
  74          */
  75         uint32_t txDataCount;   /*0x10 */
  76
  77         /*
  78          * Interrupt control
  79          *
  80          * Used to clear the interrupted generated by this dev.
  81          * Write a 1 to clear the interrupt. (except bit31).
  82          *
  83          * Bit0 is set if it was a tx-done interrupt.
  84          * Bit1 is set when new rx-data is available.
  85          *      Until this bit is cleared there will be no other RXs.
  86          *
  87          * Bit31 is used for testing, it clears after a read.
  88          *    Writing 1 to this bit will cause an interrupt to be generated.
  89          *    To clear the test interrupt, write 0 to this register.
  90          */
  91         uint32_t interruptControl;      /*0x14 */
  92 #define MIPSNET_INTCTL_TXDONE     ((uint32_t)(1<< 0))
  93 #define MIPSNET_INTCTL_RXDONE     ((uint32_t)(1<< 1))
  94 #define MIPSNET_INTCTL_TESTBIT    ((uint32_t)(1<<31))
  95 #define MIPSNET_INTCTL_ALLSOURCES (MIPSNET_INTCTL_TXDONE|MIPSNET_INTCTL_RXDONE|MIPSNET_INTCTL_TESTBIT)
  96
  97         /*
  98          * Readonly core-specific interrupt info for the device to signal the core.
  99          * The meaning of the contents of this field might change.
 100          */
 101         /*###\todo: the whole memIntf interrupt scheme is messy: the device should have
 102          *  no control what so ever of what VPE/register set is being used.
 103          *  The MemIntf should only expose interrupt lines, and something in the
 104          *  config should be responsible for the line<->core/vpe bindings.
 105          */
 106         uint32_t interruptInfo; /*0x18 */
 107
 108         /*
 109          *  This is where the received data is read out.
 110          *  There is more data to read until rxDataReady is 0.
 111          *  Only 1 byte at this regs offset is used.
 112          */
 113         uint32_t rxDataBuffer;  /*0x1c */
 114
 115         /*
 116          * This is where the data to transmit is written.
 117          * Data should be written for the amount specified in the txDataCount register.
 118          *  Only 1 byte at this regs offset is used.
 119          */
 120         uint32_t txDataBuffer;  /*0x20 */
 121 } MIPS_T_NetControl;
 122
 123 #define MIPSNET_IO_EXTENT 0x40  /* being generous */
 124
 125 #define field_offset(field) ((int)&((MIPS_T_NetControl*)(0))->field)
 126
 127 #endif /* __MIPSNET_H */