2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/mlx4/doorbell.h>
49 MODULE_AUTHOR("Roland Dreier");
50 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
51 MODULE_LICENSE("Dual BSD/GPL");
52 MODULE_VERSION(DRV_VERSION
);
54 #ifdef CONFIG_MLX4_DEBUG
56 int mlx4_debug_level
= 0;
57 module_param_named(debug_level
, mlx4_debug_level
, int, 0644);
58 MODULE_PARM_DESC(debug_level
, "Enable debug tracing if > 0");
60 #endif /* CONFIG_MLX4_DEBUG */
65 module_param(msi_x
, int, 0444);
66 MODULE_PARM_DESC(msi_x
, "attempt to use MSI-X if nonzero");
68 #else /* CONFIG_PCI_MSI */
72 #endif /* CONFIG_PCI_MSI */
74 static const char mlx4_version
[] __devinitdata
=
75 DRV_NAME
": Mellanox ConnectX core driver v"
76 DRV_VERSION
" (" DRV_RELDATE
")\n";
78 static struct mlx4_profile default_profile
= {
81 .rdmarc_per_qp
= 1 << 4,
88 static int __devinit
mlx4_dev_cap(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
)
93 err
= mlx4_QUERY_DEV_CAP(dev
, dev_cap
);
95 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
99 if (dev_cap
->min_page_sz
> PAGE_SIZE
) {
100 mlx4_err(dev
, "HCA minimum page size of %d bigger than "
101 "kernel PAGE_SIZE of %ld, aborting.\n",
102 dev_cap
->min_page_sz
, PAGE_SIZE
);
105 if (dev_cap
->num_ports
> MLX4_MAX_PORTS
) {
106 mlx4_err(dev
, "HCA has %d ports, but we only support %d, "
108 dev_cap
->num_ports
, MLX4_MAX_PORTS
);
112 if (dev_cap
->uar_size
> pci_resource_len(dev
->pdev
, 2)) {
113 mlx4_err(dev
, "HCA reported UAR size of 0x%x bigger than "
114 "PCI resource 2 size of 0x%llx, aborting.\n",
116 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
120 dev
->caps
.num_ports
= dev_cap
->num_ports
;
121 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
122 dev
->caps
.vl_cap
[i
] = dev_cap
->max_vl
[i
];
123 dev
->caps
.mtu_cap
[i
] = dev_cap
->max_mtu
[i
];
124 dev
->caps
.gid_table_len
[i
] = dev_cap
->max_gids
[i
];
125 dev
->caps
.pkey_table_len
[i
] = dev_cap
->max_pkeys
[i
];
126 dev
->caps
.port_width_cap
[i
] = dev_cap
->max_port_width
[i
];
129 dev
->caps
.num_uars
= dev_cap
->uar_size
/ PAGE_SIZE
;
130 dev
->caps
.local_ca_ack_delay
= dev_cap
->local_ca_ack_delay
;
131 dev
->caps
.bf_reg_size
= dev_cap
->bf_reg_size
;
132 dev
->caps
.bf_regs_per_page
= dev_cap
->bf_regs_per_page
;
133 dev
->caps
.max_sq_sg
= dev_cap
->max_sq_sg
;
134 dev
->caps
.max_rq_sg
= dev_cap
->max_rq_sg
;
135 dev
->caps
.max_wqes
= dev_cap
->max_qp_sz
;
136 dev
->caps
.max_qp_init_rdma
= dev_cap
->max_requester_per_qp
;
137 dev
->caps
.reserved_qps
= dev_cap
->reserved_qps
;
138 dev
->caps
.max_srq_wqes
= dev_cap
->max_srq_sz
;
139 dev
->caps
.max_srq_sge
= dev_cap
->max_rq_sg
- 1;
140 dev
->caps
.reserved_srqs
= dev_cap
->reserved_srqs
;
141 dev
->caps
.max_sq_desc_sz
= dev_cap
->max_sq_desc_sz
;
142 dev
->caps
.max_rq_desc_sz
= dev_cap
->max_rq_desc_sz
;
143 dev
->caps
.num_qp_per_mgm
= MLX4_QP_PER_MGM
;
145 * Subtract 1 from the limit because we need to allocate a
146 * spare CQE so the HCA HW can tell the difference between an
147 * empty CQ and a full CQ.
149 dev
->caps
.max_cqes
= dev_cap
->max_cq_sz
- 1;
150 dev
->caps
.reserved_cqs
= dev_cap
->reserved_cqs
;
151 dev
->caps
.reserved_eqs
= dev_cap
->reserved_eqs
;
152 dev
->caps
.reserved_mtts
= dev_cap
->reserved_mtts
;
153 dev
->caps
.reserved_mrws
= dev_cap
->reserved_mrws
;
154 dev
->caps
.reserved_uars
= dev_cap
->reserved_uars
;
155 dev
->caps
.reserved_pds
= dev_cap
->reserved_pds
;
156 dev
->caps
.mtt_entry_sz
= MLX4_MTT_ENTRY_PER_SEG
* dev_cap
->mtt_entry_sz
;
157 dev
->caps
.max_msg_sz
= dev_cap
->max_msg_sz
;
158 dev
->caps
.page_size_cap
= ~(u32
) (dev_cap
->min_page_sz
- 1);
159 dev
->caps
.flags
= dev_cap
->flags
;
160 dev
->caps
.stat_rate_support
= dev_cap
->stat_rate_support
;
165 static int __devinit
mlx4_load_fw(struct mlx4_dev
*dev
)
167 struct mlx4_priv
*priv
= mlx4_priv(dev
);
170 priv
->fw
.fw_icm
= mlx4_alloc_icm(dev
, priv
->fw
.fw_pages
,
171 GFP_HIGHUSER
| __GFP_NOWARN
);
172 if (!priv
->fw
.fw_icm
) {
173 mlx4_err(dev
, "Couldn't allocate FW area, aborting.\n");
177 err
= mlx4_MAP_FA(dev
, priv
->fw
.fw_icm
);
179 mlx4_err(dev
, "MAP_FA command failed, aborting.\n");
183 err
= mlx4_RUN_FW(dev
);
185 mlx4_err(dev
, "RUN_FW command failed, aborting.\n");
195 mlx4_free_icm(dev
, priv
->fw
.fw_icm
);
199 static int __devinit
mlx4_init_cmpt_table(struct mlx4_dev
*dev
, u64 cmpt_base
,
202 struct mlx4_priv
*priv
= mlx4_priv(dev
);
205 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.cmpt_table
,
207 ((u64
) (MLX4_CMPT_TYPE_QP
*
208 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
209 cmpt_entry_sz
, dev
->caps
.num_qps
,
210 dev
->caps
.reserved_qps
, 0);
214 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.cmpt_table
,
216 ((u64
) (MLX4_CMPT_TYPE_SRQ
*
217 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
218 cmpt_entry_sz
, dev
->caps
.num_srqs
,
219 dev
->caps
.reserved_srqs
, 0);
223 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.cmpt_table
,
225 ((u64
) (MLX4_CMPT_TYPE_CQ
*
226 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
227 cmpt_entry_sz
, dev
->caps
.num_cqs
,
228 dev
->caps
.reserved_cqs
, 0);
232 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.cmpt_table
,
234 ((u64
) (MLX4_CMPT_TYPE_EQ
*
235 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
237 roundup_pow_of_two(MLX4_NUM_EQ
+
238 dev
->caps
.reserved_eqs
),
239 MLX4_NUM_EQ
+ dev
->caps
.reserved_eqs
, 0);
246 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
249 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
252 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
258 static int __devinit
mlx4_init_icm(struct mlx4_dev
*dev
,
259 struct mlx4_dev_cap
*dev_cap
,
260 struct mlx4_init_hca_param
*init_hca
,
263 struct mlx4_priv
*priv
= mlx4_priv(dev
);
267 err
= mlx4_SET_ICM_SIZE(dev
, icm_size
, &aux_pages
);
269 mlx4_err(dev
, "SET_ICM_SIZE command failed, aborting.\n");
273 mlx4_dbg(dev
, "%lld KB of HCA context requires %lld KB aux memory.\n",
274 (unsigned long long) icm_size
>> 10,
275 (unsigned long long) aux_pages
<< 2);
277 priv
->fw
.aux_icm
= mlx4_alloc_icm(dev
, aux_pages
,
278 GFP_HIGHUSER
| __GFP_NOWARN
);
279 if (!priv
->fw
.aux_icm
) {
280 mlx4_err(dev
, "Couldn't allocate aux memory, aborting.\n");
284 err
= mlx4_MAP_ICM_AUX(dev
, priv
->fw
.aux_icm
);
286 mlx4_err(dev
, "MAP_ICM_AUX command failed, aborting.\n");
290 err
= mlx4_init_cmpt_table(dev
, init_hca
->cmpt_base
, dev_cap
->cmpt_entry_sz
);
292 mlx4_err(dev
, "Failed to map cMPT context memory, aborting.\n");
296 err
= mlx4_map_eq_icm(dev
, init_hca
->eqc_base
);
298 mlx4_err(dev
, "Failed to map EQ context memory, aborting.\n");
302 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.mtt_table
,
304 dev
->caps
.mtt_entry_sz
,
305 dev
->caps
.num_mtt_segs
,
306 dev
->caps
.reserved_mtts
, 1);
308 mlx4_err(dev
, "Failed to map MTT context memory, aborting.\n");
312 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.dmpt_table
,
314 dev_cap
->dmpt_entry_sz
,
316 dev
->caps
.reserved_mrws
, 1);
318 mlx4_err(dev
, "Failed to map dMPT context memory, aborting.\n");
322 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.qp_table
,
324 dev_cap
->qpc_entry_sz
,
326 dev
->caps
.reserved_qps
, 0);
328 mlx4_err(dev
, "Failed to map QP context memory, aborting.\n");
332 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.auxc_table
,
334 dev_cap
->aux_entry_sz
,
336 dev
->caps
.reserved_qps
, 0);
338 mlx4_err(dev
, "Failed to map AUXC context memory, aborting.\n");
342 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.altc_table
,
344 dev_cap
->altc_entry_sz
,
346 dev
->caps
.reserved_qps
, 0);
348 mlx4_err(dev
, "Failed to map ALTC context memory, aborting.\n");
352 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.rdmarc_table
,
353 init_hca
->rdmarc_base
,
354 dev_cap
->rdmarc_entry_sz
<< priv
->qp_table
.rdmarc_shift
,
356 dev
->caps
.reserved_qps
, 0);
358 mlx4_err(dev
, "Failed to map RDMARC context memory, aborting\n");
362 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.table
,
364 dev_cap
->cqc_entry_sz
,
366 dev
->caps
.reserved_cqs
, 0);
368 mlx4_err(dev
, "Failed to map CQ context memory, aborting.\n");
369 goto err_unmap_rdmarc
;
372 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.table
,
374 dev_cap
->srq_entry_sz
,
376 dev
->caps
.reserved_srqs
, 0);
378 mlx4_err(dev
, "Failed to map SRQ context memory, aborting.\n");
383 * It's not strictly required, but for simplicity just map the
384 * whole multicast group table now. The table isn't very big
385 * and it's a lot easier than trying to track ref counts.
387 err
= mlx4_init_icm_table(dev
, &priv
->mcg_table
.table
,
388 init_hca
->mc_base
, MLX4_MGM_ENTRY_SIZE
,
389 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
390 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
393 mlx4_err(dev
, "Failed to map MCG context memory, aborting.\n");
400 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
403 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
406 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
409 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
412 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
415 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
418 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
421 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
424 mlx4_unmap_eq_icm(dev
);
427 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
428 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
429 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
430 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
433 mlx4_UNMAP_ICM_AUX(dev
);
436 mlx4_free_icm(dev
, priv
->fw
.aux_icm
);
441 static void mlx4_free_icms(struct mlx4_dev
*dev
)
443 struct mlx4_priv
*priv
= mlx4_priv(dev
);
445 mlx4_cleanup_icm_table(dev
, &priv
->mcg_table
.table
);
446 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
447 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
448 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
449 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
450 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
451 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
452 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
453 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
454 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
455 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
456 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
457 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
458 mlx4_unmap_eq_icm(dev
);
460 mlx4_UNMAP_ICM_AUX(dev
);
461 mlx4_free_icm(dev
, priv
->fw
.aux_icm
);
464 static void mlx4_close_hca(struct mlx4_dev
*dev
)
466 mlx4_CLOSE_HCA(dev
, 0);
469 mlx4_free_icm(dev
, mlx4_priv(dev
)->fw
.fw_icm
);
472 static int __devinit
mlx4_init_hca(struct mlx4_dev
*dev
)
474 struct mlx4_priv
*priv
= mlx4_priv(dev
);
475 struct mlx4_adapter adapter
;
476 struct mlx4_dev_cap dev_cap
;
477 struct mlx4_profile profile
;
478 struct mlx4_init_hca_param init_hca
;
482 err
= mlx4_QUERY_FW(dev
);
484 mlx4_err(dev
, "QUERY_FW command failed, aborting.\n");
488 err
= mlx4_load_fw(dev
);
490 mlx4_err(dev
, "Failed to start FW, aborting.\n");
494 err
= mlx4_dev_cap(dev
, &dev_cap
);
496 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
500 profile
= default_profile
;
502 icm_size
= mlx4_make_profile(dev
, &profile
, &dev_cap
, &init_hca
);
503 if ((long long) icm_size
< 0) {
508 init_hca
.log_uar_sz
= ilog2(dev
->caps
.num_uars
);
510 err
= mlx4_init_icm(dev
, &dev_cap
, &init_hca
, icm_size
);
514 err
= mlx4_INIT_HCA(dev
, &init_hca
);
516 mlx4_err(dev
, "INIT_HCA command failed, aborting.\n");
520 err
= mlx4_QUERY_ADAPTER(dev
, &adapter
);
522 mlx4_err(dev
, "QUERY_ADAPTER command failed, aborting.\n");
526 priv
->eq_table
.inta_pin
= adapter
.inta_pin
;
527 dev
->rev_id
= adapter
.revision_id
;
528 memcpy(dev
->board_id
, adapter
.board_id
, sizeof dev
->board_id
);
540 mlx4_free_icm(dev
, priv
->fw
.fw_icm
);
545 static int __devinit
mlx4_setup_hca(struct mlx4_dev
*dev
)
547 struct mlx4_priv
*priv
= mlx4_priv(dev
);
550 err
= mlx4_init_uar_table(dev
);
552 mlx4_err(dev
, "Failed to initialize "
553 "user access region table, aborting.\n");
557 err
= mlx4_uar_alloc(dev
, &priv
->driver_uar
);
559 mlx4_err(dev
, "Failed to allocate driver access region, "
561 goto err_uar_table_free
;
564 priv
->kar
= ioremap(priv
->driver_uar
.pfn
<< PAGE_SHIFT
, PAGE_SIZE
);
566 mlx4_err(dev
, "Couldn't map kernel access region, "
572 err
= mlx4_init_pd_table(dev
);
574 mlx4_err(dev
, "Failed to initialize "
575 "protection domain table, aborting.\n");
579 err
= mlx4_init_mr_table(dev
);
581 mlx4_err(dev
, "Failed to initialize "
582 "memory region table, aborting.\n");
583 goto err_pd_table_free
;
586 err
= mlx4_init_eq_table(dev
);
588 mlx4_err(dev
, "Failed to initialize "
589 "event queue table, aborting.\n");
590 goto err_mr_table_free
;
593 err
= mlx4_cmd_use_events(dev
);
595 mlx4_err(dev
, "Failed to switch to event-driven "
596 "firmware commands, aborting.\n");
597 goto err_eq_table_free
;
602 if (dev
->flags
& MLX4_FLAG_MSI_X
) {
603 mlx4_warn(dev
, "NOP command failed to generate MSI-X "
604 "interrupt IRQ %d).\n",
605 priv
->eq_table
.eq
[MLX4_EQ_ASYNC
].irq
);
606 mlx4_warn(dev
, "Trying again without MSI-X.\n");
608 mlx4_err(dev
, "NOP command failed to generate interrupt "
609 "(IRQ %d), aborting.\n",
610 priv
->eq_table
.eq
[MLX4_EQ_ASYNC
].irq
);
611 mlx4_err(dev
, "BIOS or ACPI interrupt routing problem?\n");
617 mlx4_dbg(dev
, "NOP command IRQ test passed\n");
619 err
= mlx4_init_cq_table(dev
);
621 mlx4_err(dev
, "Failed to initialize "
622 "completion queue table, aborting.\n");
626 err
= mlx4_init_srq_table(dev
);
628 mlx4_err(dev
, "Failed to initialize "
629 "shared receive queue table, aborting.\n");
630 goto err_cq_table_free
;
633 err
= mlx4_init_qp_table(dev
);
635 mlx4_err(dev
, "Failed to initialize "
636 "queue pair table, aborting.\n");
637 goto err_srq_table_free
;
640 err
= mlx4_init_mcg_table(dev
);
642 mlx4_err(dev
, "Failed to initialize "
643 "multicast group table, aborting.\n");
644 goto err_qp_table_free
;
650 mlx4_cleanup_qp_table(dev
);
653 mlx4_cleanup_srq_table(dev
);
656 mlx4_cleanup_cq_table(dev
);
659 mlx4_cmd_use_polling(dev
);
662 mlx4_cleanup_eq_table(dev
);
665 mlx4_cleanup_mr_table(dev
);
668 mlx4_cleanup_pd_table(dev
);
674 mlx4_uar_free(dev
, &priv
->driver_uar
);
677 mlx4_cleanup_uar_table(dev
);
681 static void __devinit
mlx4_enable_msi_x(struct mlx4_dev
*dev
)
683 struct mlx4_priv
*priv
= mlx4_priv(dev
);
684 struct msix_entry entries
[MLX4_NUM_EQ
];
689 for (i
= 0; i
< MLX4_NUM_EQ
; ++i
)
690 entries
[i
].entry
= i
;
692 err
= pci_enable_msix(dev
->pdev
, entries
, ARRAY_SIZE(entries
));
695 mlx4_info(dev
, "Only %d MSI-X vectors available, "
696 "not using MSI-X\n", err
);
700 for (i
= 0; i
< MLX4_NUM_EQ
; ++i
)
701 priv
->eq_table
.eq
[i
].irq
= entries
[i
].vector
;
703 dev
->flags
|= MLX4_FLAG_MSI_X
;
708 for (i
= 0; i
< MLX4_NUM_EQ
; ++i
)
709 priv
->eq_table
.eq
[i
].irq
= dev
->pdev
->irq
;
712 static int __devinit
mlx4_init_one(struct pci_dev
*pdev
,
713 const struct pci_device_id
*id
)
715 static int mlx4_version_printed
;
716 struct mlx4_priv
*priv
;
717 struct mlx4_dev
*dev
;
720 if (!mlx4_version_printed
) {
721 printk(KERN_INFO
"%s", mlx4_version
);
722 ++mlx4_version_printed
;
725 printk(KERN_INFO PFX
"Initializing %s\n",
728 err
= pci_enable_device(pdev
);
730 dev_err(&pdev
->dev
, "Cannot enable PCI device, "
736 * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
739 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
) ||
740 pci_resource_len(pdev
, 0) != 1 << 20) {
741 dev_err(&pdev
->dev
, "Missing DCS, aborting.\n");
743 goto err_disable_pdev
;
745 if (!(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
746 dev_err(&pdev
->dev
, "Missing UAR, aborting.\n");
748 goto err_disable_pdev
;
751 err
= pci_request_region(pdev
, 0, DRV_NAME
);
753 dev_err(&pdev
->dev
, "Cannot request control region, aborting.\n");
754 goto err_disable_pdev
;
757 err
= pci_request_region(pdev
, 2, DRV_NAME
);
759 dev_err(&pdev
->dev
, "Cannot request UAR region, aborting.\n");
760 goto err_release_bar0
;
763 pci_set_master(pdev
);
765 err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
);
767 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask.\n");
768 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
770 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting.\n");
771 goto err_release_bar2
;
774 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
776 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit "
777 "consistent PCI DMA mask.\n");
778 err
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
780 dev_err(&pdev
->dev
, "Can't set consistent PCI DMA mask, "
782 goto err_release_bar2
;
786 priv
= kzalloc(sizeof *priv
, GFP_KERNEL
);
788 dev_err(&pdev
->dev
, "Device struct alloc failed, "
791 goto err_release_bar2
;
796 INIT_LIST_HEAD(&priv
->ctx_list
);
797 spin_lock_init(&priv
->ctx_lock
);
800 * Now reset the HCA before we touch the PCI capabilities or
801 * attempt a firmware command, since a boot ROM may have left
802 * the HCA in an undefined state.
804 err
= mlx4_reset(dev
);
806 mlx4_err(dev
, "Failed to reset HCA, aborting.\n");
810 if (mlx4_cmd_init(dev
)) {
811 mlx4_err(dev
, "Failed to init command interface, aborting.\n");
815 err
= mlx4_init_hca(dev
);
819 mlx4_enable_msi_x(dev
);
821 err
= mlx4_setup_hca(dev
);
822 if (err
== -EBUSY
&& (dev
->flags
& MLX4_FLAG_MSI_X
)) {
823 dev
->flags
&= ~MLX4_FLAG_MSI_X
;
824 pci_disable_msix(pdev
);
825 err
= mlx4_setup_hca(dev
);
831 err
= mlx4_register_device(dev
);
835 pci_set_drvdata(pdev
, dev
);
840 mlx4_cleanup_mcg_table(dev
);
841 mlx4_cleanup_qp_table(dev
);
842 mlx4_cleanup_srq_table(dev
);
843 mlx4_cleanup_cq_table(dev
);
844 mlx4_cmd_use_polling(dev
);
845 mlx4_cleanup_eq_table(dev
);
846 mlx4_cleanup_mr_table(dev
);
847 mlx4_cleanup_pd_table(dev
);
848 mlx4_cleanup_uar_table(dev
);
851 if (dev
->flags
& MLX4_FLAG_MSI_X
)
852 pci_disable_msix(pdev
);
857 mlx4_cmd_cleanup(dev
);
863 pci_release_region(pdev
, 2);
866 pci_release_region(pdev
, 0);
869 pci_disable_device(pdev
);
870 pci_set_drvdata(pdev
, NULL
);
874 static void __devexit
mlx4_remove_one(struct pci_dev
*pdev
)
876 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
877 struct mlx4_priv
*priv
= mlx4_priv(dev
);
881 mlx4_unregister_device(dev
);
883 for (p
= 1; p
<= dev
->caps
.num_ports
; ++p
)
884 mlx4_CLOSE_PORT(dev
, p
);
886 mlx4_cleanup_mcg_table(dev
);
887 mlx4_cleanup_qp_table(dev
);
888 mlx4_cleanup_srq_table(dev
);
889 mlx4_cleanup_cq_table(dev
);
890 mlx4_cmd_use_polling(dev
);
891 mlx4_cleanup_eq_table(dev
);
892 mlx4_cleanup_mr_table(dev
);
893 mlx4_cleanup_pd_table(dev
);
896 mlx4_uar_free(dev
, &priv
->driver_uar
);
897 mlx4_cleanup_uar_table(dev
);
899 mlx4_cmd_cleanup(dev
);
901 if (dev
->flags
& MLX4_FLAG_MSI_X
)
902 pci_disable_msix(pdev
);
905 pci_release_region(pdev
, 2);
906 pci_release_region(pdev
, 0);
907 pci_disable_device(pdev
);
908 pci_set_drvdata(pdev
, NULL
);
912 int mlx4_restart_one(struct pci_dev
*pdev
)
914 mlx4_remove_one(pdev
);
915 return mlx4_init_one(pdev
, NULL
);
918 static struct pci_device_id mlx4_pci_table
[] = {
919 { PCI_VDEVICE(MELLANOX
, 0x6340) }, /* MT25408 "Hermon" SDR */
920 { PCI_VDEVICE(MELLANOX
, 0x634a) }, /* MT25408 "Hermon" DDR */
921 { PCI_VDEVICE(MELLANOX
, 0x6354) }, /* MT25408 "Hermon" QDR */
922 { PCI_VDEVICE(MELLANOX
, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
923 { PCI_VDEVICE(MELLANOX
, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
927 MODULE_DEVICE_TABLE(pci
, mlx4_pci_table
);
929 static struct pci_driver mlx4_driver
= {
931 .id_table
= mlx4_pci_table
,
932 .probe
= mlx4_init_one
,
933 .remove
= __devexit_p(mlx4_remove_one
)
936 static int __init
mlx4_init(void)
940 ret
= mlx4_catas_init();
944 ret
= pci_register_driver(&mlx4_driver
);
945 return ret
< 0 ? ret
: 0;
948 static void __exit
mlx4_cleanup(void)
950 pci_unregister_driver(&mlx4_driver
);
951 mlx4_catas_cleanup();
954 module_init(mlx4_init
);
955 module_exit(mlx4_cleanup
);