2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.
26 #include "netxen_nic.h"
27 #include "netxen_nic_hw.h"
31 #define MASK(n) ((1ULL<<(n))-1)
32 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
33 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
34 #define MS_WIN(addr) (addr & 0x0ffc0000)
36 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
38 #define CRB_BLK(off) ((off >> 20) & 0x3f)
39 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
40 #define CRB_WINDOW_2M (0x130060)
41 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
42 #define CRB_INDIRECT_2M (0x1e0000UL)
44 static void netxen_nic_io_write_128M(struct netxen_adapter
*adapter
,
45 void __iomem
*addr
, u32 data
);
46 static u32
netxen_nic_io_read_128M(struct netxen_adapter
*adapter
,
50 static inline u64
readq(void __iomem
*addr
)
52 return readl(addr
) | (((u64
) readl(addr
+ 4)) << 32LL);
57 static inline void writeq(u64 val
, void __iomem
*addr
)
59 writel(((u32
) (val
)), (addr
));
60 writel(((u32
) (val
>> 32)), (addr
+ 4));
64 #define ADDR_IN_RANGE(addr, low, high) \
65 (((addr) < (high)) && ((addr) >= (low)))
67 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
68 ((adapter)->ahw.pci_base0 + (off))
69 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
70 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
71 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
72 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
74 static void __iomem
*pci_base_offset(struct netxen_adapter
*adapter
,
77 if (ADDR_IN_RANGE(off
, FIRST_PAGE_GROUP_START
, FIRST_PAGE_GROUP_END
))
78 return PCI_OFFSET_FIRST_RANGE(adapter
, off
);
80 if (ADDR_IN_RANGE(off
, SECOND_PAGE_GROUP_START
, SECOND_PAGE_GROUP_END
))
81 return PCI_OFFSET_SECOND_RANGE(adapter
, off
);
83 if (ADDR_IN_RANGE(off
, THIRD_PAGE_GROUP_START
, THIRD_PAGE_GROUP_END
))
84 return PCI_OFFSET_THIRD_RANGE(adapter
, off
);
89 static crb_128M_2M_block_map_t
90 crb_128M_2M_map
[64] __cacheline_aligned_in_smp
= {
91 {{{0, 0, 0, 0} } }, /* 0: PCI */
92 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
93 {1, 0x0110000, 0x0120000, 0x130000},
94 {1, 0x0120000, 0x0122000, 0x124000},
95 {1, 0x0130000, 0x0132000, 0x126000},
96 {1, 0x0140000, 0x0142000, 0x128000},
97 {1, 0x0150000, 0x0152000, 0x12a000},
98 {1, 0x0160000, 0x0170000, 0x110000},
99 {1, 0x0170000, 0x0172000, 0x12e000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {1, 0x01e0000, 0x01e0800, 0x122000},
107 {0, 0x0000000, 0x0000000, 0x000000} } },
108 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
109 {{{0, 0, 0, 0} } }, /* 3: */
110 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
111 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
112 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
113 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
114 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {1, 0x08f0000, 0x08f2000, 0x172000} } },
130 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {1, 0x09f0000, 0x09f2000, 0x176000} } },
146 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
162 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
178 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
179 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
180 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
181 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
182 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
183 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
184 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
185 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
186 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
187 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
188 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
189 {{{0, 0, 0, 0} } }, /* 23: */
190 {{{0, 0, 0, 0} } }, /* 24: */
191 {{{0, 0, 0, 0} } }, /* 25: */
192 {{{0, 0, 0, 0} } }, /* 26: */
193 {{{0, 0, 0, 0} } }, /* 27: */
194 {{{0, 0, 0, 0} } }, /* 28: */
195 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
196 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
197 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
198 {{{0} } }, /* 32: PCI */
199 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
200 {1, 0x2110000, 0x2120000, 0x130000},
201 {1, 0x2120000, 0x2122000, 0x124000},
202 {1, 0x2130000, 0x2132000, 0x126000},
203 {1, 0x2140000, 0x2142000, 0x128000},
204 {1, 0x2150000, 0x2152000, 0x12a000},
205 {1, 0x2160000, 0x2170000, 0x110000},
206 {1, 0x2170000, 0x2172000, 0x12e000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000} } },
215 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
221 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
222 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
223 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
224 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
225 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
226 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
227 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
228 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
229 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
230 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
231 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
232 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
234 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
235 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
236 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
237 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
238 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
239 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
240 {{{0} } }, /* 59: I2C0 */
241 {{{0} } }, /* 60: I2C1 */
242 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
243 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
244 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
248 * top 12 bits of crb internal address (hub, agent)
250 static unsigned crb_hub_agt
[64] =
253 NETXEN_HW_CRB_HUB_AGT_ADR_PS
,
254 NETXEN_HW_CRB_HUB_AGT_ADR_MN
,
255 NETXEN_HW_CRB_HUB_AGT_ADR_MS
,
257 NETXEN_HW_CRB_HUB_AGT_ADR_SRE
,
258 NETXEN_HW_CRB_HUB_AGT_ADR_NIU
,
259 NETXEN_HW_CRB_HUB_AGT_ADR_QMN
,
260 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0
,
261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1
,
262 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2
,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3
,
264 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q
,
265 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR
,
266 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB
,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4
,
268 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA
,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0
,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1
,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2
,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3
,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGND
,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI
,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0
,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1
,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2
,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3
,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI
,
281 NETXEN_HW_CRB_HUB_AGT_ADR_SN
,
283 NETXEN_HW_CRB_HUB_AGT_ADR_EG
,
285 NETXEN_HW_CRB_HUB_AGT_ADR_PS
,
286 NETXEN_HW_CRB_HUB_AGT_ADR_CAM
,
292 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR
,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1
,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2
,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3
,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4
,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5
,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6
,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7
,
301 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA
,
302 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q
,
303 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB
,
305 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0
,
306 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8
,
307 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9
,
308 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0
,
310 NETXEN_HW_CRB_HUB_AGT_ADR_SMB
,
311 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0
,
312 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1
,
314 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC
,
318 /* PCI Windowing for DDR regions. */
320 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
322 #define NETXEN_PCIE_SEM_TIMEOUT 10000
325 netxen_pcie_sem_lock(struct netxen_adapter
*adapter
, int sem
, u32 id_reg
)
327 int done
= 0, timeout
= 0;
330 done
= NXRD32(adapter
, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem
)));
333 if (++timeout
>= NETXEN_PCIE_SEM_TIMEOUT
)
339 NXWR32(adapter
, id_reg
, adapter
->portnum
);
345 netxen_pcie_sem_unlock(struct netxen_adapter
*adapter
, int sem
)
348 val
= NXRD32(adapter
, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem
)));
351 int netxen_niu_xg_init_port(struct netxen_adapter
*adapter
, int port
)
353 if (NX_IS_REVISION_P2(adapter
->ahw
.revision_id
)) {
354 NXWR32(adapter
, NETXEN_NIU_XGE_CONFIG_1
+(0x10000*port
), 0x1447);
355 NXWR32(adapter
, NETXEN_NIU_XGE_CONFIG_0
+(0x10000*port
), 0x5);
361 /* Disable an XG interface */
362 int netxen_niu_disable_xg_port(struct netxen_adapter
*adapter
)
365 u32 port
= adapter
->physical_port
;
367 if (NX_IS_REVISION_P3(adapter
->ahw
.revision_id
))
370 if (port
> NETXEN_NIU_MAX_XG_PORTS
)
375 NETXEN_NIU_XGE_CONFIG_0
+ (0x10000 * port
), mac_cfg
))
380 #define NETXEN_UNICAST_ADDR(port, index) \
381 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
382 #define NETXEN_MCAST_ADDR(port, index) \
383 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
384 #define MAC_HI(addr) \
385 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
386 #define MAC_LO(addr) \
387 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
389 int netxen_p2_nic_set_promisc(struct netxen_adapter
*adapter
, u32 mode
)
392 u32 port
= adapter
->physical_port
;
394 if (port
> NETXEN_NIU_MAX_XG_PORTS
)
397 reg
= NXRD32(adapter
, NETXEN_NIU_XGE_CONFIG_1
+ (0x10000 * port
));
398 if (mode
== NETXEN_NIU_PROMISC_MODE
)
399 reg
= (reg
| 0x2000UL
);
401 reg
= (reg
& ~0x2000UL
);
403 if (mode
== NETXEN_NIU_ALLMULTI_MODE
)
404 reg
= (reg
| 0x1000UL
);
406 reg
= (reg
& ~0x1000UL
);
408 NXWR32(adapter
, NETXEN_NIU_XGE_CONFIG_1
+ (0x10000 * port
), reg
);
413 int netxen_p2_nic_set_mac_addr(struct netxen_adapter
*adapter
, u8
*addr
)
418 u8 phy
= adapter
->physical_port
;
420 if (phy
>= NETXEN_NIU_MAX_XG_PORTS
)
423 mac_lo
= ((u32
)addr
[0] << 16) | ((u32
)addr
[1] << 24);
424 mac_hi
= addr
[2] | ((u32
)addr
[3] << 8) |
425 ((u32
)addr
[4] << 16) | ((u32
)addr
[5] << 24);
427 reg_lo
= NETXEN_NIU_XGE_STATION_ADDR_0_1
+ (0x10000 * phy
);
428 reg_hi
= NETXEN_NIU_XGE_STATION_ADDR_0_HI
+ (0x10000 * phy
);
430 /* write twice to flush */
431 if (NXWR32(adapter
, reg_lo
, mac_lo
) || NXWR32(adapter
, reg_hi
, mac_hi
))
433 if (NXWR32(adapter
, reg_lo
, mac_lo
) || NXWR32(adapter
, reg_hi
, mac_hi
))
440 netxen_nic_enable_mcast_filter(struct netxen_adapter
*adapter
)
443 u16 port
= adapter
->physical_port
;
444 u8
*addr
= adapter
->netdev
->dev_addr
;
446 if (adapter
->mc_enabled
)
449 val
= NXRD32(adapter
, NETXEN_MAC_ADDR_CNTL_REG
);
450 val
|= (1UL << (28+port
));
451 NXWR32(adapter
, NETXEN_MAC_ADDR_CNTL_REG
, val
);
453 /* add broadcast addr to filter */
455 NXWR32(adapter
, NETXEN_UNICAST_ADDR(port
, 0), val
);
456 NXWR32(adapter
, NETXEN_UNICAST_ADDR(port
, 0)+4, val
);
458 /* add station addr to filter */
460 NXWR32(adapter
, NETXEN_UNICAST_ADDR(port
, 1), val
);
462 NXWR32(adapter
, NETXEN_UNICAST_ADDR(port
, 1)+4, val
);
464 adapter
->mc_enabled
= 1;
469 netxen_nic_disable_mcast_filter(struct netxen_adapter
*adapter
)
472 u16 port
= adapter
->physical_port
;
473 u8
*addr
= adapter
->netdev
->dev_addr
;
475 if (!adapter
->mc_enabled
)
478 val
= NXRD32(adapter
, NETXEN_MAC_ADDR_CNTL_REG
);
479 val
&= ~(1UL << (28+port
));
480 NXWR32(adapter
, NETXEN_MAC_ADDR_CNTL_REG
, val
);
483 NXWR32(adapter
, NETXEN_UNICAST_ADDR(port
, 0), val
);
485 NXWR32(adapter
, NETXEN_UNICAST_ADDR(port
, 0)+4, val
);
487 NXWR32(adapter
, NETXEN_UNICAST_ADDR(port
, 1), 0);
488 NXWR32(adapter
, NETXEN_UNICAST_ADDR(port
, 1)+4, 0);
490 adapter
->mc_enabled
= 0;
495 netxen_nic_set_mcast_addr(struct netxen_adapter
*adapter
,
499 u16 port
= adapter
->physical_port
;
504 NXWR32(adapter
, NETXEN_MCAST_ADDR(port
, index
), hi
);
505 NXWR32(adapter
, NETXEN_MCAST_ADDR(port
, index
)+4, lo
);
510 void netxen_p2_nic_set_multi(struct net_device
*netdev
)
512 struct netxen_adapter
*adapter
= netdev_priv(netdev
);
513 struct dev_mc_list
*mc_ptr
;
517 memset(null_addr
, 0, 6);
519 if (netdev
->flags
& IFF_PROMISC
) {
521 adapter
->set_promisc(adapter
,
522 NETXEN_NIU_PROMISC_MODE
);
524 /* Full promiscuous mode */
525 netxen_nic_disable_mcast_filter(adapter
);
530 if (netdev
->mc_count
== 0) {
531 adapter
->set_promisc(adapter
,
532 NETXEN_NIU_NON_PROMISC_MODE
);
533 netxen_nic_disable_mcast_filter(adapter
);
537 adapter
->set_promisc(adapter
, NETXEN_NIU_ALLMULTI_MODE
);
538 if (netdev
->flags
& IFF_ALLMULTI
||
539 netdev
->mc_count
> adapter
->max_mc_count
) {
540 netxen_nic_disable_mcast_filter(adapter
);
544 netxen_nic_enable_mcast_filter(adapter
);
546 for (mc_ptr
= netdev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
, index
++)
547 netxen_nic_set_mcast_addr(adapter
, index
, mc_ptr
->dmi_addr
);
549 if (index
!= netdev
->mc_count
)
550 printk(KERN_WARNING
"%s: %s multicast address count mismatch\n",
551 netxen_nic_driver_name
, netdev
->name
);
553 /* Clear out remaining addresses */
554 for (; index
< adapter
->max_mc_count
; index
++)
555 netxen_nic_set_mcast_addr(adapter
, index
, null_addr
);
559 netxen_send_cmd_descs(struct netxen_adapter
*adapter
,
560 struct cmd_desc_type0
*cmd_desc_arr
, int nr_desc
)
562 u32 i
, producer
, consumer
;
563 struct netxen_cmd_buffer
*pbuf
;
564 struct cmd_desc_type0
*cmd_desc
;
565 struct nx_host_tx_ring
*tx_ring
;
569 if (adapter
->is_up
!= NETXEN_ADAPTER_UP_MAGIC
)
572 tx_ring
= adapter
->tx_ring
;
573 __netif_tx_lock_bh(tx_ring
->txq
);
575 producer
= tx_ring
->producer
;
576 consumer
= tx_ring
->sw_consumer
;
578 if (nr_desc
>= netxen_tx_avail(tx_ring
)) {
579 netif_tx_stop_queue(tx_ring
->txq
);
580 __netif_tx_unlock_bh(tx_ring
->txq
);
585 cmd_desc
= &cmd_desc_arr
[i
];
587 pbuf
= &tx_ring
->cmd_buf_arr
[producer
];
589 pbuf
->frag_count
= 0;
591 memcpy(&tx_ring
->desc_head
[producer
],
592 &cmd_desc_arr
[i
], sizeof(struct cmd_desc_type0
));
594 producer
= get_next_index(producer
, tx_ring
->num_desc
);
597 } while (i
!= nr_desc
);
599 tx_ring
->producer
= producer
;
601 netxen_nic_update_cmd_producer(adapter
, tx_ring
);
603 __netif_tx_unlock_bh(tx_ring
->txq
);
609 nx_p3_sre_macaddr_change(struct netxen_adapter
*adapter
, u8
*addr
, unsigned op
)
612 nx_mac_req_t
*mac_req
;
615 memset(&req
, 0, sizeof(nx_nic_req_t
));
616 req
.qhdr
= cpu_to_le64(NX_NIC_REQUEST
<< 23);
618 word
= NX_MAC_EVENT
| ((u64
)adapter
->portnum
<< 16);
619 req
.req_hdr
= cpu_to_le64(word
);
621 mac_req
= (nx_mac_req_t
*)&req
.words
[0];
623 memcpy(mac_req
->mac_addr
, addr
, 6);
625 return netxen_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
628 static int nx_p3_nic_add_mac(struct netxen_adapter
*adapter
,
629 u8
*addr
, struct list_head
*del_list
)
631 struct list_head
*head
;
634 /* look up if already exists */
635 list_for_each(head
, del_list
) {
636 cur
= list_entry(head
, nx_mac_list_t
, list
);
638 if (memcmp(addr
, cur
->mac_addr
, ETH_ALEN
) == 0) {
639 list_move_tail(head
, &adapter
->mac_list
);
644 cur
= kzalloc(sizeof(nx_mac_list_t
), GFP_ATOMIC
);
646 printk(KERN_ERR
"%s: failed to add mac address filter\n",
647 adapter
->netdev
->name
);
650 memcpy(cur
->mac_addr
, addr
, ETH_ALEN
);
651 list_add_tail(&cur
->list
, &adapter
->mac_list
);
652 return nx_p3_sre_macaddr_change(adapter
,
653 cur
->mac_addr
, NETXEN_MAC_ADD
);
656 void netxen_p3_nic_set_multi(struct net_device
*netdev
)
658 struct netxen_adapter
*adapter
= netdev_priv(netdev
);
659 struct dev_mc_list
*mc_ptr
;
660 u8 bcast_addr
[ETH_ALEN
] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
661 u32 mode
= VPORT_MISS_MODE_DROP
;
663 struct list_head
*head
;
666 list_splice_tail_init(&adapter
->mac_list
, &del_list
);
668 nx_p3_nic_add_mac(adapter
, netdev
->dev_addr
, &del_list
);
669 nx_p3_nic_add_mac(adapter
, bcast_addr
, &del_list
);
671 if (netdev
->flags
& IFF_PROMISC
) {
672 mode
= VPORT_MISS_MODE_ACCEPT_ALL
;
676 if ((netdev
->flags
& IFF_ALLMULTI
) ||
677 (netdev
->mc_count
> adapter
->max_mc_count
)) {
678 mode
= VPORT_MISS_MODE_ACCEPT_MULTI
;
682 if (netdev
->mc_count
> 0) {
683 for (mc_ptr
= netdev
->mc_list
; mc_ptr
;
684 mc_ptr
= mc_ptr
->next
) {
685 nx_p3_nic_add_mac(adapter
, mc_ptr
->dmi_addr
, &del_list
);
690 adapter
->set_promisc(adapter
, mode
);
692 while (!list_empty(head
)) {
693 cur
= list_entry(head
->next
, nx_mac_list_t
, list
);
695 nx_p3_sre_macaddr_change(adapter
,
696 cur
->mac_addr
, NETXEN_MAC_DEL
);
697 list_del(&cur
->list
);
702 int netxen_p3_nic_set_promisc(struct netxen_adapter
*adapter
, u32 mode
)
707 memset(&req
, 0, sizeof(nx_nic_req_t
));
709 req
.qhdr
= cpu_to_le64(NX_HOST_REQUEST
<< 23);
711 word
= NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE
|
712 ((u64
)adapter
->portnum
<< 16);
713 req
.req_hdr
= cpu_to_le64(word
);
715 req
.words
[0] = cpu_to_le64(mode
);
717 return netxen_send_cmd_descs(adapter
,
718 (struct cmd_desc_type0
*)&req
, 1);
721 void netxen_p3_free_mac_list(struct netxen_adapter
*adapter
)
724 struct list_head
*head
= &adapter
->mac_list
;
726 while (!list_empty(head
)) {
727 cur
= list_entry(head
->next
, nx_mac_list_t
, list
);
728 nx_p3_sre_macaddr_change(adapter
,
729 cur
->mac_addr
, NETXEN_MAC_DEL
);
730 list_del(&cur
->list
);
735 int netxen_p3_nic_set_mac_addr(struct netxen_adapter
*adapter
, u8
*addr
)
737 /* assuming caller has already copied new addr to netdev */
738 netxen_p3_nic_set_multi(adapter
->netdev
);
742 #define NETXEN_CONFIG_INTR_COALESCE 3
745 * Send the interrupt coalescing parameter set by ethtool to the card.
747 int netxen_config_intr_coalesce(struct netxen_adapter
*adapter
)
753 memset(&req
, 0, sizeof(nx_nic_req_t
));
755 req
.qhdr
= cpu_to_le64(NX_HOST_REQUEST
<< 23);
757 word
= NETXEN_CONFIG_INTR_COALESCE
| ((u64
)adapter
->portnum
<< 16);
758 req
.req_hdr
= cpu_to_le64(word
);
760 memcpy(&req
.words
[0], &adapter
->coal
, sizeof(adapter
->coal
));
762 rv
= netxen_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
764 printk(KERN_ERR
"ERROR. Could not send "
765 "interrupt coalescing parameters\n");
771 int netxen_config_hw_lro(struct netxen_adapter
*adapter
, int enable
)
777 if ((adapter
->flags
& NETXEN_NIC_LRO_ENABLED
) == enable
)
780 memset(&req
, 0, sizeof(nx_nic_req_t
));
782 req
.qhdr
= cpu_to_le64(NX_HOST_REQUEST
<< 23);
784 word
= NX_NIC_H2C_OPCODE_CONFIG_HW_LRO
| ((u64
)adapter
->portnum
<< 16);
785 req
.req_hdr
= cpu_to_le64(word
);
787 req
.words
[0] = cpu_to_le64(enable
);
789 rv
= netxen_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
791 printk(KERN_ERR
"ERROR. Could not send "
792 "configure hw lro request\n");
795 adapter
->flags
^= NETXEN_NIC_LRO_ENABLED
;
800 int netxen_config_bridged_mode(struct netxen_adapter
*adapter
, int enable
)
806 if (!!(adapter
->flags
& NETXEN_NIC_BRIDGE_ENABLED
) == enable
)
809 memset(&req
, 0, sizeof(nx_nic_req_t
));
811 req
.qhdr
= cpu_to_le64(NX_HOST_REQUEST
<< 23);
813 word
= NX_NIC_H2C_OPCODE_CONFIG_BRIDGING
|
814 ((u64
)adapter
->portnum
<< 16);
815 req
.req_hdr
= cpu_to_le64(word
);
817 req
.words
[0] = cpu_to_le64(enable
);
819 rv
= netxen_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
821 printk(KERN_ERR
"ERROR. Could not send "
822 "configure bridge mode request\n");
825 adapter
->flags
^= NETXEN_NIC_BRIDGE_ENABLED
;
831 #define RSS_HASHTYPE_IP_TCP 0x3
833 int netxen_config_rss(struct netxen_adapter
*adapter
, int enable
)
839 u64 key
[] = { 0xbeac01fa6a42b73bULL
, 0x8030f20c77cb2da3ULL
,
840 0xae7b30b4d0ca2bcbULL
, 0x43a38fb04167253dULL
,
841 0x255b0ec26d5a56daULL
};
844 memset(&req
, 0, sizeof(nx_nic_req_t
));
845 req
.qhdr
= cpu_to_le64(NX_HOST_REQUEST
<< 23);
847 word
= NX_NIC_H2C_OPCODE_CONFIG_RSS
| ((u64
)adapter
->portnum
<< 16);
848 req
.req_hdr
= cpu_to_le64(word
);
852 * bits 3-0: hash_method
853 * 5-4: hash_type_ipv4
854 * 7-6: hash_type_ipv6
856 * 9: use indirection table
858 * 63-48: indirection table mask
860 word
= ((u64
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 4) |
861 ((u64
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 6) |
862 ((u64
)(enable
& 0x1) << 8) |
864 req
.words
[0] = cpu_to_le64(word
);
865 for (i
= 0; i
< 5; i
++)
866 req
.words
[i
+1] = cpu_to_le64(key
[i
]);
869 rv
= netxen_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
871 printk(KERN_ERR
"%s: could not configure RSS\n",
872 adapter
->netdev
->name
);
878 int netxen_config_ipaddr(struct netxen_adapter
*adapter
, u32 ip
, int cmd
)
884 memset(&req
, 0, sizeof(nx_nic_req_t
));
885 req
.qhdr
= cpu_to_le64(NX_HOST_REQUEST
<< 23);
887 word
= NX_NIC_H2C_OPCODE_CONFIG_IPADDR
| ((u64
)adapter
->portnum
<< 16);
888 req
.req_hdr
= cpu_to_le64(word
);
890 req
.words
[0] = cpu_to_le64(cmd
);
891 req
.words
[1] = cpu_to_le64(ip
);
893 rv
= netxen_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
895 printk(KERN_ERR
"%s: could not notify %s IP 0x%x reuqest\n",
896 adapter
->netdev
->name
,
897 (cmd
== NX_IP_UP
) ? "Add" : "Remove", ip
);
902 int netxen_linkevent_request(struct netxen_adapter
*adapter
, int enable
)
908 memset(&req
, 0, sizeof(nx_nic_req_t
));
909 req
.qhdr
= cpu_to_le64(NX_HOST_REQUEST
<< 23);
911 word
= NX_NIC_H2C_OPCODE_GET_LINKEVENT
| ((u64
)adapter
->portnum
<< 16);
912 req
.req_hdr
= cpu_to_le64(word
);
913 req
.words
[0] = cpu_to_le64(enable
| (enable
<< 8));
915 rv
= netxen_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
917 printk(KERN_ERR
"%s: could not configure link notification\n",
918 adapter
->netdev
->name
);
924 int netxen_send_lro_cleanup(struct netxen_adapter
*adapter
)
930 memset(&req
, 0, sizeof(nx_nic_req_t
));
931 req
.qhdr
= cpu_to_le64(NX_HOST_REQUEST
<< 23);
933 word
= NX_NIC_H2C_OPCODE_LRO_REQUEST
|
934 ((u64
)adapter
->portnum
<< 16) |
935 ((u64
)NX_NIC_LRO_REQUEST_CLEANUP
<< 56) ;
937 req
.req_hdr
= cpu_to_le64(word
);
939 rv
= netxen_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
941 printk(KERN_ERR
"%s: could not cleanup lro flows\n",
942 adapter
->netdev
->name
);
948 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
949 * @returns 0 on success, negative on failure
952 #define MTU_FUDGE_FACTOR 100
954 int netxen_nic_change_mtu(struct net_device
*netdev
, int mtu
)
956 struct netxen_adapter
*adapter
= netdev_priv(netdev
);
960 if (NX_IS_REVISION_P3(adapter
->ahw
.revision_id
))
961 max_mtu
= P3_MAX_MTU
;
963 max_mtu
= P2_MAX_MTU
;
966 printk(KERN_ERR
"%s: mtu > %d bytes unsupported\n",
967 netdev
->name
, max_mtu
);
971 if (adapter
->set_mtu
)
972 rc
= adapter
->set_mtu(adapter
, mtu
);
980 static int netxen_get_flash_block(struct netxen_adapter
*adapter
, int base
,
981 int size
, __le32
* buf
)
988 for (i
= 0; i
< size
/ sizeof(u32
); i
++) {
989 if (netxen_rom_fast_read(adapter
, addr
, &v
) == -1)
991 *ptr32
= cpu_to_le32(v
);
995 if ((char *)buf
+ size
> (char *)ptr32
) {
997 if (netxen_rom_fast_read(adapter
, addr
, &v
) == -1)
999 local
= cpu_to_le32(v
);
1000 memcpy(ptr32
, &local
, (char *)buf
+ size
- (char *)ptr32
);
1006 int netxen_get_flash_mac_addr(struct netxen_adapter
*adapter
, __le64
*mac
)
1008 __le32
*pmac
= (__le32
*) mac
;
1011 offset
= NX_FW_MAC_ADDR_OFFSET
+ (adapter
->portnum
* sizeof(u64
));
1013 if (netxen_get_flash_block(adapter
, offset
, sizeof(u64
), pmac
) == -1)
1016 if (*mac
== cpu_to_le64(~0ULL)) {
1018 offset
= NX_OLD_MAC_ADDR_OFFSET
+
1019 (adapter
->portnum
* sizeof(u64
));
1021 if (netxen_get_flash_block(adapter
,
1022 offset
, sizeof(u64
), pmac
) == -1)
1025 if (*mac
== cpu_to_le64(~0ULL))
1031 int netxen_p3_get_mac_addr(struct netxen_adapter
*adapter
, __le64
*mac
)
1033 uint32_t crbaddr
, mac_hi
, mac_lo
;
1034 int pci_func
= adapter
->ahw
.pci_func
;
1036 crbaddr
= CRB_MAC_BLOCK_START
+
1037 (4 * ((pci_func
/2) * 3)) + (4 * (pci_func
& 1));
1039 mac_lo
= NXRD32(adapter
, crbaddr
);
1040 mac_hi
= NXRD32(adapter
, crbaddr
+4);
1043 *mac
= le64_to_cpu((mac_lo
>> 16) | ((u64
)mac_hi
<< 16));
1045 *mac
= le64_to_cpu((u64
)mac_lo
| ((u64
)mac_hi
<< 32));
1051 * Changes the CRB window to the specified window.
1054 netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter
*adapter
,
1057 void __iomem
*offset
;
1059 u8 func
= adapter
->ahw
.pci_func
;
1061 if (adapter
->ahw
.crb_win
== window
)
1064 offset
= PCI_OFFSET_SECOND_RANGE(adapter
,
1065 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func
)));
1067 writel(window
, offset
);
1069 if (window
== readl(offset
))
1072 if (printk_ratelimit())
1073 dev_warn(&adapter
->pdev
->dev
,
1074 "failed to set CRB window to %d\n",
1075 (window
== NETXEN_WINDOW_ONE
));
1078 } while (--count
> 0);
1081 adapter
->ahw
.crb_win
= window
;
1085 * Return -1 if off is not valid,
1086 * 1 if window access is needed. 'off' is set to offset from
1087 * CRB space in 128M pci map
1088 * 0 if no window access is needed. 'off' is set to 2M addr
1089 * In: 'off' is offset from base in 128M pci map
1092 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter
*adapter
, ulong
*off
)
1094 crb_128M_2M_sub_block_map_t
*m
;
1097 if (*off
>= NETXEN_CRB_MAX
)
1100 if (*off
>= NETXEN_PCI_CAMQM
&& (*off
< NETXEN_PCI_CAMQM_2M_END
)) {
1101 *off
= (*off
- NETXEN_PCI_CAMQM
) + NETXEN_PCI_CAMQM_2M_BASE
+
1102 (ulong
)adapter
->ahw
.pci_base0
;
1106 if (*off
< NETXEN_PCI_CRBSPACE
)
1109 *off
-= NETXEN_PCI_CRBSPACE
;
1114 m
= &crb_128M_2M_map
[CRB_BLK(*off
)].sub_block
[CRB_SUBBLK(*off
)];
1116 if (m
->valid
&& (m
->start_128M
<= *off
) && (m
->end_128M
> *off
)) {
1117 *off
= *off
+ m
->start_2M
- m
->start_128M
+
1118 (ulong
)adapter
->ahw
.pci_base0
;
1123 * Not in direct map, use crb window
1129 * In: 'off' is offset from CRB space in 128M pci map
1130 * Out: 'off' is 2M pci map addr
1131 * side effect: lock crb window
1134 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter
*adapter
, ulong
*off
)
1137 void __iomem
*addr
= adapter
->ahw
.pci_base0
+ CRB_WINDOW_2M
;
1139 window
= CRB_HI(*off
);
1141 if (adapter
->ahw
.crb_win
== window
)
1144 writel(window
, addr
);
1145 if (readl(addr
) != window
) {
1146 if (printk_ratelimit())
1147 dev_warn(&adapter
->pdev
->dev
,
1148 "failed to set CRB window to %d off 0x%lx\n",
1151 adapter
->ahw
.crb_win
= window
;
1154 *off
= (*off
& MASK(16)) + CRB_INDIRECT_2M
+
1155 (ulong
)adapter
->ahw
.pci_base0
;
1159 netxen_nic_hw_write_wx_128M(struct netxen_adapter
*adapter
, ulong off
, u32 data
)
1161 unsigned long flags
;
1164 if (ADDR_IN_WINDOW1(off
))
1165 addr
= NETXEN_CRB_NORMALIZE(adapter
, off
);
1167 addr
= pci_base_offset(adapter
, off
);
1171 if (ADDR_IN_WINDOW1(off
)) { /* Window 1 */
1172 netxen_nic_io_write_128M(adapter
, addr
, data
);
1173 } else { /* Window 0 */
1174 write_lock_irqsave(&adapter
->ahw
.crb_lock
, flags
);
1175 addr
= pci_base_offset(adapter
, off
);
1176 netxen_nic_pci_set_crbwindow_128M(adapter
, 0);
1178 netxen_nic_pci_set_crbwindow_128M(adapter
,
1180 write_unlock_irqrestore(&adapter
->ahw
.crb_lock
, flags
);
1187 netxen_nic_hw_read_wx_128M(struct netxen_adapter
*adapter
, ulong off
)
1189 unsigned long flags
;
1193 if (ADDR_IN_WINDOW1(off
))
1194 addr
= NETXEN_CRB_NORMALIZE(adapter
, off
);
1196 addr
= pci_base_offset(adapter
, off
);
1200 if (ADDR_IN_WINDOW1(off
)) { /* Window 1 */
1201 data
= netxen_nic_io_read_128M(adapter
, addr
);
1202 } else { /* Window 0 */
1203 write_lock_irqsave(&adapter
->ahw
.crb_lock
, flags
);
1204 netxen_nic_pci_set_crbwindow_128M(adapter
, 0);
1206 netxen_nic_pci_set_crbwindow_128M(adapter
,
1208 write_unlock_irqrestore(&adapter
->ahw
.crb_lock
, flags
);
1215 netxen_nic_hw_write_wx_2M(struct netxen_adapter
*adapter
, ulong off
, u32 data
)
1217 unsigned long flags
;
1220 rv
= netxen_nic_pci_get_crb_addr_2M(adapter
, &off
);
1223 printk(KERN_ERR
"%s: invalid offset: 0x%016lx\n",
1230 write_lock_irqsave(&adapter
->ahw
.crb_lock
, flags
);
1231 crb_win_lock(adapter
);
1232 netxen_nic_pci_set_crbwindow_2M(adapter
, &off
);
1233 writel(data
, (void __iomem
*)off
);
1234 crb_win_unlock(adapter
);
1235 write_unlock_irqrestore(&adapter
->ahw
.crb_lock
, flags
);
1237 writel(data
, (void __iomem
*)off
);
1244 netxen_nic_hw_read_wx_2M(struct netxen_adapter
*adapter
, ulong off
)
1246 unsigned long flags
;
1250 rv
= netxen_nic_pci_get_crb_addr_2M(adapter
, &off
);
1253 printk(KERN_ERR
"%s: invalid offset: 0x%016lx\n",
1260 write_lock_irqsave(&adapter
->ahw
.crb_lock
, flags
);
1261 crb_win_lock(adapter
);
1262 netxen_nic_pci_set_crbwindow_2M(adapter
, &off
);
1263 data
= readl((void __iomem
*)off
);
1264 crb_win_unlock(adapter
);
1265 write_unlock_irqrestore(&adapter
->ahw
.crb_lock
, flags
);
1267 data
= readl((void __iomem
*)off
);
1272 /* window 1 registers only */
1273 static void netxen_nic_io_write_128M(struct netxen_adapter
*adapter
,
1274 void __iomem
*addr
, u32 data
)
1276 read_lock(&adapter
->ahw
.crb_lock
);
1278 read_unlock(&adapter
->ahw
.crb_lock
);
1281 static u32
netxen_nic_io_read_128M(struct netxen_adapter
*adapter
,
1286 read_lock(&adapter
->ahw
.crb_lock
);
1288 read_unlock(&adapter
->ahw
.crb_lock
);
1293 static void netxen_nic_io_write_2M(struct netxen_adapter
*adapter
,
1294 void __iomem
*addr
, u32 data
)
1299 static u32
netxen_nic_io_read_2M(struct netxen_adapter
*adapter
,
1306 netxen_get_ioaddr(struct netxen_adapter
*adapter
, u32 offset
)
1310 if (NX_IS_REVISION_P2(adapter
->ahw
.revision_id
)) {
1311 if (offset
< NETXEN_CRB_PCIX_HOST2
&&
1312 offset
> NETXEN_CRB_PCIX_HOST
)
1313 return PCI_OFFSET_SECOND_RANGE(adapter
, offset
);
1314 return NETXEN_CRB_NORMALIZE(adapter
, offset
);
1317 BUG_ON(netxen_nic_pci_get_crb_addr_2M(adapter
, &off
));
1318 return (void __iomem
*)off
;
1322 netxen_nic_pci_set_window_128M(struct netxen_adapter
*adapter
,
1323 u64 addr
, u32
*start
)
1325 if (ADDR_IN_RANGE(addr
, NETXEN_ADDR_OCM0
, NETXEN_ADDR_OCM0_MAX
)) {
1326 *start
= (addr
- NETXEN_ADDR_OCM0
+ NETXEN_PCI_OCM0
);
1328 } else if (ADDR_IN_RANGE(addr
,
1329 NETXEN_ADDR_OCM1
, NETXEN_ADDR_OCM1_MAX
)) {
1330 *start
= (addr
- NETXEN_ADDR_OCM1
+ NETXEN_PCI_OCM1
);
1338 netxen_nic_pci_set_window_2M(struct netxen_adapter
*adapter
,
1339 u64 addr
, u32
*start
)
1341 u32 win_read
, window
;
1342 struct pci_dev
*pdev
= adapter
->pdev
;
1344 if ((addr
& 0x00ff800) == 0xff800) {
1345 if (printk_ratelimit())
1346 dev_warn(&pdev
->dev
, "QM access not handled\n");
1350 window
= OCM_WIN(addr
);
1351 writel(window
, adapter
->ahw
.ocm_win_crb
);
1352 win_read
= readl(adapter
->ahw
.ocm_win_crb
);
1353 if ((win_read
>> 7) != window
) {
1354 if (printk_ratelimit())
1355 dev_warn(&pdev
->dev
, "failed to set OCM window\n");
1359 adapter
->ahw
.ocm_win
= window
;
1360 *start
= NETXEN_PCI_OCM0_2M
+ GET_MEM_OFFS_2M(addr
);
1365 netxen_nic_pci_mem_access_direct(struct netxen_adapter
*adapter
, u64 off
,
1368 void __iomem
*addr
, *mem_ptr
= NULL
;
1369 resource_size_t mem_base
;
1373 spin_lock(&adapter
->ahw
.mem_lock
);
1375 ret
= adapter
->pci_set_window(adapter
, off
, &start
);
1379 addr
= pci_base_offset(adapter
, start
);
1383 mem_base
= pci_resource_start(adapter
->pdev
, 0) + (start
& PAGE_MASK
);
1385 mem_ptr
= ioremap(mem_base
, PAGE_SIZE
);
1386 if (mem_ptr
== NULL
) {
1391 addr
= mem_ptr
+ (start
& (PAGE_SIZE
- 1));
1394 if (op
== 0) /* read */
1395 *data
= readq(addr
);
1397 writeq(*data
, addr
);
1400 spin_unlock(&adapter
->ahw
.mem_lock
);
1407 #define MAX_CTL_CHECK 1000
1410 netxen_nic_pci_mem_write_128M(struct netxen_adapter
*adapter
,
1414 u32 temp
, off_lo
, off_hi
, addr_hi
, data_hi
, data_lo
;
1415 void __iomem
*mem_crb
;
1417 /* Only 64-bit aligned access */
1421 /* P2 has different SIU and MIU test agent base addr */
1422 if (ADDR_IN_RANGE(off
, NETXEN_ADDR_QDR_NET
,
1423 NETXEN_ADDR_QDR_NET_MAX_P2
)) {
1424 mem_crb
= pci_base_offset(adapter
,
1425 NETXEN_CRB_QDR_NET
+SIU_TEST_AGT_BASE
);
1426 addr_hi
= SIU_TEST_AGT_ADDR_HI
;
1427 data_lo
= SIU_TEST_AGT_WRDATA_LO
;
1428 data_hi
= SIU_TEST_AGT_WRDATA_HI
;
1429 off_lo
= off
& SIU_TEST_AGT_ADDR_MASK
;
1430 off_hi
= SIU_TEST_AGT_UPPER_ADDR(off
);
1434 if (ADDR_IN_RANGE(off
, NETXEN_ADDR_DDR_NET
, NETXEN_ADDR_DDR_NET_MAX
)) {
1435 mem_crb
= pci_base_offset(adapter
,
1436 NETXEN_CRB_DDR_NET
+MIU_TEST_AGT_BASE
);
1437 addr_hi
= MIU_TEST_AGT_ADDR_HI
;
1438 data_lo
= MIU_TEST_AGT_WRDATA_LO
;
1439 data_hi
= MIU_TEST_AGT_WRDATA_HI
;
1440 off_lo
= off
& MIU_TEST_AGT_ADDR_MASK
;
1445 if (ADDR_IN_RANGE(off
, NETXEN_ADDR_OCM0
, NETXEN_ADDR_OCM0_MAX
) ||
1446 ADDR_IN_RANGE(off
, NETXEN_ADDR_OCM1
, NETXEN_ADDR_OCM1_MAX
)) {
1447 if (adapter
->ahw
.pci_len0
!= 0) {
1448 return netxen_nic_pci_mem_access_direct(adapter
,
1456 spin_lock(&adapter
->ahw
.mem_lock
);
1457 netxen_nic_pci_set_crbwindow_128M(adapter
, 0);
1459 writel(off_lo
, (mem_crb
+ MIU_TEST_AGT_ADDR_LO
));
1460 writel(off_hi
, (mem_crb
+ addr_hi
));
1461 writel(data
& 0xffffffff, (mem_crb
+ data_lo
));
1462 writel((data
>> 32) & 0xffffffff, (mem_crb
+ data_hi
));
1463 writel((TA_CTL_ENABLE
| TA_CTL_WRITE
), (mem_crb
+ TEST_AGT_CTRL
));
1464 writel((TA_CTL_START
| TA_CTL_ENABLE
| TA_CTL_WRITE
),
1465 (mem_crb
+ TEST_AGT_CTRL
));
1467 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1468 temp
= readl((mem_crb
+ TEST_AGT_CTRL
));
1469 if ((temp
& TA_CTL_BUSY
) == 0)
1473 if (j
>= MAX_CTL_CHECK
) {
1474 if (printk_ratelimit())
1475 dev_err(&adapter
->pdev
->dev
,
1476 "failed to write through agent\n");
1481 netxen_nic_pci_set_crbwindow_128M(adapter
, NETXEN_WINDOW_ONE
);
1482 spin_unlock(&adapter
->ahw
.mem_lock
);
1487 netxen_nic_pci_mem_read_128M(struct netxen_adapter
*adapter
,
1491 u32 temp
, off_lo
, off_hi
, addr_hi
, data_hi
, data_lo
;
1493 void __iomem
*mem_crb
;
1495 /* Only 64-bit aligned access */
1499 /* P2 has different SIU and MIU test agent base addr */
1500 if (ADDR_IN_RANGE(off
, NETXEN_ADDR_QDR_NET
,
1501 NETXEN_ADDR_QDR_NET_MAX_P2
)) {
1502 mem_crb
= pci_base_offset(adapter
,
1503 NETXEN_CRB_QDR_NET
+SIU_TEST_AGT_BASE
);
1504 addr_hi
= SIU_TEST_AGT_ADDR_HI
;
1505 data_lo
= SIU_TEST_AGT_RDDATA_LO
;
1506 data_hi
= SIU_TEST_AGT_RDDATA_HI
;
1507 off_lo
= off
& SIU_TEST_AGT_ADDR_MASK
;
1508 off_hi
= SIU_TEST_AGT_UPPER_ADDR(off
);
1512 if (ADDR_IN_RANGE(off
, NETXEN_ADDR_DDR_NET
, NETXEN_ADDR_DDR_NET_MAX
)) {
1513 mem_crb
= pci_base_offset(adapter
,
1514 NETXEN_CRB_DDR_NET
+MIU_TEST_AGT_BASE
);
1515 addr_hi
= MIU_TEST_AGT_ADDR_HI
;
1516 data_lo
= MIU_TEST_AGT_RDDATA_LO
;
1517 data_hi
= MIU_TEST_AGT_RDDATA_HI
;
1518 off_lo
= off
& MIU_TEST_AGT_ADDR_MASK
;
1523 if (ADDR_IN_RANGE(off
, NETXEN_ADDR_OCM0
, NETXEN_ADDR_OCM0_MAX
) ||
1524 ADDR_IN_RANGE(off
, NETXEN_ADDR_OCM1
, NETXEN_ADDR_OCM1_MAX
)) {
1525 if (adapter
->ahw
.pci_len0
!= 0) {
1526 return netxen_nic_pci_mem_access_direct(adapter
,
1534 spin_lock(&adapter
->ahw
.mem_lock
);
1535 netxen_nic_pci_set_crbwindow_128M(adapter
, 0);
1537 writel(off_lo
, (mem_crb
+ MIU_TEST_AGT_ADDR_LO
));
1538 writel(off_hi
, (mem_crb
+ addr_hi
));
1539 writel(TA_CTL_ENABLE
, (mem_crb
+ TEST_AGT_CTRL
));
1540 writel((TA_CTL_START
|TA_CTL_ENABLE
), (mem_crb
+ TEST_AGT_CTRL
));
1542 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1543 temp
= readl(mem_crb
+ TEST_AGT_CTRL
);
1544 if ((temp
& TA_CTL_BUSY
) == 0)
1548 if (j
>= MAX_CTL_CHECK
) {
1549 if (printk_ratelimit())
1550 dev_err(&adapter
->pdev
->dev
,
1551 "failed to read through agent\n");
1555 temp
= readl(mem_crb
+ data_hi
);
1556 val
= ((u64
)temp
<< 32);
1557 val
|= readl(mem_crb
+ data_lo
);
1562 netxen_nic_pci_set_crbwindow_128M(adapter
, NETXEN_WINDOW_ONE
);
1563 spin_unlock(&adapter
->ahw
.mem_lock
);
1569 netxen_nic_pci_mem_write_2M(struct netxen_adapter
*adapter
,
1575 void __iomem
*mem_crb
;
1577 /* Only 64-bit aligned access */
1581 /* P3 onward, test agent base for MIU and SIU is same */
1582 if (ADDR_IN_RANGE(off
, NETXEN_ADDR_QDR_NET
,
1583 NETXEN_ADDR_QDR_NET_MAX_P3
)) {
1584 mem_crb
= netxen_get_ioaddr(adapter
,
1585 NETXEN_CRB_QDR_NET
+MIU_TEST_AGT_BASE
);
1589 if (ADDR_IN_RANGE(off
, NETXEN_ADDR_DDR_NET
, NETXEN_ADDR_DDR_NET_MAX
)) {
1590 mem_crb
= netxen_get_ioaddr(adapter
,
1591 NETXEN_CRB_DDR_NET
+MIU_TEST_AGT_BASE
);
1595 if (ADDR_IN_RANGE(off
, NETXEN_ADDR_OCM0
, NETXEN_ADDR_OCM0_MAX
))
1596 return netxen_nic_pci_mem_access_direct(adapter
, off
, &data
, 1);
1601 stride
= NX_IS_REVISION_P3P(adapter
->ahw
.revision_id
) ? 16 : 8;
1603 off8
= off
& ~(stride
-1);
1605 spin_lock(&adapter
->ahw
.mem_lock
);
1607 writel(off8
, (mem_crb
+ MIU_TEST_AGT_ADDR_LO
));
1608 writel(0, (mem_crb
+ MIU_TEST_AGT_ADDR_HI
));
1612 writel(TA_CTL_ENABLE
, (mem_crb
+ TEST_AGT_CTRL
));
1613 writel((TA_CTL_START
| TA_CTL_ENABLE
),
1614 (mem_crb
+ TEST_AGT_CTRL
));
1616 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1617 temp
= readl(mem_crb
+ TEST_AGT_CTRL
);
1618 if ((temp
& TA_CTL_BUSY
) == 0)
1622 if (j
>= MAX_CTL_CHECK
) {
1627 i
= (off
& 0xf) ? 0 : 2;
1628 writel(readl(mem_crb
+ MIU_TEST_AGT_RDDATA(i
)),
1629 mem_crb
+ MIU_TEST_AGT_WRDATA(i
));
1630 writel(readl(mem_crb
+ MIU_TEST_AGT_RDDATA(i
+1)),
1631 mem_crb
+ MIU_TEST_AGT_WRDATA(i
+1));
1632 i
= (off
& 0xf) ? 2 : 0;
1635 writel(data
& 0xffffffff,
1636 mem_crb
+ MIU_TEST_AGT_WRDATA(i
));
1637 writel((data
>> 32) & 0xffffffff,
1638 mem_crb
+ MIU_TEST_AGT_WRDATA(i
+1));
1640 writel((TA_CTL_ENABLE
| TA_CTL_WRITE
), (mem_crb
+ TEST_AGT_CTRL
));
1641 writel((TA_CTL_START
| TA_CTL_ENABLE
| TA_CTL_WRITE
),
1642 (mem_crb
+ TEST_AGT_CTRL
));
1644 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1645 temp
= readl(mem_crb
+ TEST_AGT_CTRL
);
1646 if ((temp
& TA_CTL_BUSY
) == 0)
1650 if (j
>= MAX_CTL_CHECK
) {
1651 if (printk_ratelimit())
1652 dev_err(&adapter
->pdev
->dev
,
1653 "failed to write through agent\n");
1659 spin_unlock(&adapter
->ahw
.mem_lock
);
1665 netxen_nic_pci_mem_read_2M(struct netxen_adapter
*adapter
,
1671 void __iomem
*mem_crb
;
1673 /* Only 64-bit aligned access */
1677 /* P3 onward, test agent base for MIU and SIU is same */
1678 if (ADDR_IN_RANGE(off
, NETXEN_ADDR_QDR_NET
,
1679 NETXEN_ADDR_QDR_NET_MAX_P3
)) {
1680 mem_crb
= netxen_get_ioaddr(adapter
,
1681 NETXEN_CRB_QDR_NET
+MIU_TEST_AGT_BASE
);
1685 if (ADDR_IN_RANGE(off
, NETXEN_ADDR_DDR_NET
, NETXEN_ADDR_DDR_NET_MAX
)) {
1686 mem_crb
= netxen_get_ioaddr(adapter
,
1687 NETXEN_CRB_DDR_NET
+MIU_TEST_AGT_BASE
);
1691 if (ADDR_IN_RANGE(off
, NETXEN_ADDR_OCM0
, NETXEN_ADDR_OCM0_MAX
)) {
1692 return netxen_nic_pci_mem_access_direct(adapter
,
1699 stride
= NX_IS_REVISION_P3P(adapter
->ahw
.revision_id
) ? 16 : 8;
1701 off8
= off
& ~(stride
-1);
1703 spin_lock(&adapter
->ahw
.mem_lock
);
1705 writel(off8
, (mem_crb
+ MIU_TEST_AGT_ADDR_LO
));
1706 writel(0, (mem_crb
+ MIU_TEST_AGT_ADDR_HI
));
1707 writel(TA_CTL_ENABLE
, (mem_crb
+ TEST_AGT_CTRL
));
1708 writel((TA_CTL_START
| TA_CTL_ENABLE
), (mem_crb
+ TEST_AGT_CTRL
));
1710 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1711 temp
= readl(mem_crb
+ TEST_AGT_CTRL
);
1712 if ((temp
& TA_CTL_BUSY
) == 0)
1716 if (j
>= MAX_CTL_CHECK
) {
1717 if (printk_ratelimit())
1718 dev_err(&adapter
->pdev
->dev
,
1719 "failed to read through agent\n");
1722 off8
= MIU_TEST_AGT_RDDATA_LO
;
1723 if ((stride
== 16) && (off
& 0xf))
1724 off8
= MIU_TEST_AGT_RDDATA_UPPER_LO
;
1726 temp
= readl(mem_crb
+ off8
+ 4);
1727 val
= (u64
)temp
<< 32;
1728 val
|= readl(mem_crb
+ off8
);
1733 spin_unlock(&adapter
->ahw
.mem_lock
);
1739 netxen_setup_hwops(struct netxen_adapter
*adapter
)
1741 adapter
->init_port
= netxen_niu_xg_init_port
;
1742 adapter
->stop_port
= netxen_niu_disable_xg_port
;
1744 if (NX_IS_REVISION_P2(adapter
->ahw
.revision_id
)) {
1745 adapter
->crb_read
= netxen_nic_hw_read_wx_128M
,
1746 adapter
->crb_write
= netxen_nic_hw_write_wx_128M
,
1747 adapter
->pci_set_window
= netxen_nic_pci_set_window_128M
,
1748 adapter
->pci_mem_read
= netxen_nic_pci_mem_read_128M
,
1749 adapter
->pci_mem_write
= netxen_nic_pci_mem_write_128M
,
1750 adapter
->io_read
= netxen_nic_io_read_128M
,
1751 adapter
->io_write
= netxen_nic_io_write_128M
,
1753 adapter
->macaddr_set
= netxen_p2_nic_set_mac_addr
;
1754 adapter
->set_multi
= netxen_p2_nic_set_multi
;
1755 adapter
->set_mtu
= netxen_nic_set_mtu_xgb
;
1756 adapter
->set_promisc
= netxen_p2_nic_set_promisc
;
1759 adapter
->crb_read
= netxen_nic_hw_read_wx_2M
,
1760 adapter
->crb_write
= netxen_nic_hw_write_wx_2M
,
1761 adapter
->pci_set_window
= netxen_nic_pci_set_window_2M
,
1762 adapter
->pci_mem_read
= netxen_nic_pci_mem_read_2M
,
1763 adapter
->pci_mem_write
= netxen_nic_pci_mem_write_2M
,
1764 adapter
->io_read
= netxen_nic_io_read_2M
,
1765 adapter
->io_write
= netxen_nic_io_write_2M
,
1767 adapter
->set_mtu
= nx_fw_cmd_set_mtu
;
1768 adapter
->set_promisc
= netxen_p3_nic_set_promisc
;
1769 adapter
->macaddr_set
= netxen_p3_nic_set_mac_addr
;
1770 adapter
->set_multi
= netxen_p3_nic_set_multi
;
1772 adapter
->phy_read
= nx_fw_cmd_query_phy
;
1773 adapter
->phy_write
= nx_fw_cmd_set_phy
;
1777 int netxen_nic_get_board_info(struct netxen_adapter
*adapter
)
1779 int offset
, board_type
, magic
, header_version
;
1780 struct pci_dev
*pdev
= adapter
->pdev
;
1782 offset
= NX_FW_MAGIC_OFFSET
;
1783 if (netxen_rom_fast_read(adapter
, offset
, &magic
))
1786 offset
= NX_HDR_VERSION_OFFSET
;
1787 if (netxen_rom_fast_read(adapter
, offset
, &header_version
))
1790 if (magic
!= NETXEN_BDINFO_MAGIC
||
1791 header_version
!= NETXEN_BDINFO_VERSION
) {
1793 "invalid board config, magic=%08x, version=%08x\n",
1794 magic
, header_version
);
1798 offset
= NX_BRDTYPE_OFFSET
;
1799 if (netxen_rom_fast_read(adapter
, offset
, &board_type
))
1802 adapter
->ahw
.board_type
= board_type
;
1804 if (board_type
== NETXEN_BRDTYPE_P3_4_GB_MM
) {
1805 u32 gpio
= NXRD32(adapter
, NETXEN_ROMUSB_GLB_PAD_GPIO_I
);
1806 if ((gpio
& 0x8000) == 0)
1807 board_type
= NETXEN_BRDTYPE_P3_10G_TP
;
1810 switch (board_type
) {
1811 case NETXEN_BRDTYPE_P2_SB35_4G
:
1812 adapter
->ahw
.port_type
= NETXEN_NIC_GBE
;
1814 case NETXEN_BRDTYPE_P2_SB31_10G
:
1815 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ
:
1816 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ
:
1817 case NETXEN_BRDTYPE_P2_SB31_10G_CX4
:
1818 case NETXEN_BRDTYPE_P3_HMEZ
:
1819 case NETXEN_BRDTYPE_P3_XG_LOM
:
1820 case NETXEN_BRDTYPE_P3_10G_CX4
:
1821 case NETXEN_BRDTYPE_P3_10G_CX4_LP
:
1822 case NETXEN_BRDTYPE_P3_IMEZ
:
1823 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS
:
1824 case NETXEN_BRDTYPE_P3_10G_SFP_CT
:
1825 case NETXEN_BRDTYPE_P3_10G_SFP_QT
:
1826 case NETXEN_BRDTYPE_P3_10G_XFP
:
1827 case NETXEN_BRDTYPE_P3_10000_BASE_T
:
1828 adapter
->ahw
.port_type
= NETXEN_NIC_XGBE
;
1830 case NETXEN_BRDTYPE_P1_BD
:
1831 case NETXEN_BRDTYPE_P1_SB
:
1832 case NETXEN_BRDTYPE_P1_SMAX
:
1833 case NETXEN_BRDTYPE_P1_SOCK
:
1834 case NETXEN_BRDTYPE_P3_REF_QG
:
1835 case NETXEN_BRDTYPE_P3_4_GB
:
1836 case NETXEN_BRDTYPE_P3_4_GB_MM
:
1837 adapter
->ahw
.port_type
= NETXEN_NIC_GBE
;
1839 case NETXEN_BRDTYPE_P3_10G_TP
:
1840 adapter
->ahw
.port_type
= (adapter
->portnum
< 2) ?
1841 NETXEN_NIC_XGBE
: NETXEN_NIC_GBE
;
1844 dev_err(&pdev
->dev
, "unknown board type %x\n", board_type
);
1845 adapter
->ahw
.port_type
= NETXEN_NIC_XGBE
;
1852 /* NIU access sections */
1854 int netxen_nic_set_mtu_gb(struct netxen_adapter
*adapter
, int new_mtu
)
1856 new_mtu
+= MTU_FUDGE_FACTOR
;
1857 NXWR32(adapter
, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter
->physical_port
),
1862 int netxen_nic_set_mtu_xgb(struct netxen_adapter
*adapter
, int new_mtu
)
1864 new_mtu
+= MTU_FUDGE_FACTOR
;
1865 if (adapter
->physical_port
== 0)
1866 NXWR32(adapter
, NETXEN_NIU_XGE_MAX_FRAME_SIZE
, new_mtu
);
1868 NXWR32(adapter
, NETXEN_NIU_XG1_MAX_FRAME_SIZE
, new_mtu
);
1872 void netxen_nic_set_link_parameters(struct netxen_adapter
*adapter
)
1878 if (!netif_carrier_ok(adapter
->netdev
)) {
1879 adapter
->link_speed
= 0;
1880 adapter
->link_duplex
= -1;
1881 adapter
->link_autoneg
= AUTONEG_ENABLE
;
1885 if (adapter
->ahw
.port_type
== NETXEN_NIC_GBE
) {
1886 port_mode
= NXRD32(adapter
, NETXEN_PORT_MODE_ADDR
);
1887 if (port_mode
== NETXEN_PORT_MODE_802_3_AP
) {
1888 adapter
->link_speed
= SPEED_1000
;
1889 adapter
->link_duplex
= DUPLEX_FULL
;
1890 adapter
->link_autoneg
= AUTONEG_DISABLE
;
1894 if (adapter
->phy_read
1895 && adapter
->phy_read(adapter
,
1896 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS
,
1898 if (netxen_get_phy_link(status
)) {
1899 switch (netxen_get_phy_speed(status
)) {
1901 adapter
->link_speed
= SPEED_10
;
1904 adapter
->link_speed
= SPEED_100
;
1907 adapter
->link_speed
= SPEED_1000
;
1910 adapter
->link_speed
= 0;
1913 switch (netxen_get_phy_duplex(status
)) {
1915 adapter
->link_duplex
= DUPLEX_HALF
;
1918 adapter
->link_duplex
= DUPLEX_FULL
;
1921 adapter
->link_duplex
= -1;
1924 if (adapter
->phy_read
1925 && adapter
->phy_read(adapter
,
1926 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG
,
1928 adapter
->link_autoneg
= autoneg
;
1933 adapter
->link_speed
= 0;
1934 adapter
->link_duplex
= -1;
1940 netxen_nic_wol_supported(struct netxen_adapter
*adapter
)
1944 if (NX_IS_REVISION_P2(adapter
->ahw
.revision_id
))
1947 wol_cfg
= NXRD32(adapter
, NETXEN_WOL_CONFIG_NV
);
1948 if (wol_cfg
& (1UL << adapter
->portnum
)) {
1949 wol_cfg
= NXRD32(adapter
, NETXEN_WOL_CONFIG
);
1950 if (wol_cfg
& (1 << adapter
->portnum
))