1 /* niu.c: Neptune ethernet driver.
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
7 #include <linux/init.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/netdevice.h>
11 #include <linux/ethtool.h>
12 #include <linux/etherdevice.h>
13 #include <linux/platform_device.h>
14 #include <linux/delay.h>
15 #include <linux/bitops.h>
16 #include <linux/mii.h>
17 #include <linux/if_ether.h>
18 #include <linux/if_vlan.h>
21 #include <linux/ipv6.h>
22 #include <linux/log2.h>
23 #include <linux/jiffies.h>
24 #include <linux/crc32.h>
29 #include <linux/of_device.h>
34 #define DRV_MODULE_NAME "niu"
35 #define PFX DRV_MODULE_NAME ": "
36 #define DRV_MODULE_VERSION "0.9"
37 #define DRV_MODULE_RELDATE "May 4, 2008"
39 static char version
[] __devinitdata
=
40 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION
);
47 #ifndef DMA_44BIT_MASK
48 #define DMA_44BIT_MASK 0x00000fffffffffffULL
52 static u64
readq(void __iomem
*reg
)
54 return (((u64
)readl(reg
+ 0x4UL
) << 32) |
58 static void writeq(u64 val
, void __iomem
*reg
)
60 writel(val
& 0xffffffff, reg
);
61 writel(val
>> 32, reg
+ 0x4UL
);
65 static struct pci_device_id niu_pci_tbl
[] = {
66 {PCI_DEVICE(PCI_VENDOR_ID_SUN
, 0xabcd)},
70 MODULE_DEVICE_TABLE(pci
, niu_pci_tbl
);
72 #define NIU_TX_TIMEOUT (5 * HZ)
74 #define nr64(reg) readq(np->regs + (reg))
75 #define nw64(reg, val) writeq((val), np->regs + (reg))
77 #define nr64_mac(reg) readq(np->mac_regs + (reg))
78 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
80 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
81 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
83 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
84 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
86 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
87 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
89 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
92 static int debug
= -1;
93 module_param(debug
, int, 0);
94 MODULE_PARM_DESC(debug
, "NIU debug level");
96 #define niudbg(TYPE, f, a...) \
97 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
98 printk(KERN_DEBUG PFX f, ## a); \
101 #define niuinfo(TYPE, f, a...) \
102 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
103 printk(KERN_INFO PFX f, ## a); \
106 #define niuwarn(TYPE, f, a...) \
107 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
108 printk(KERN_WARNING PFX f, ## a); \
111 #define niu_lock_parent(np, flags) \
112 spin_lock_irqsave(&np->parent->lock, flags)
113 #define niu_unlock_parent(np, flags) \
114 spin_unlock_irqrestore(&np->parent->lock, flags)
116 static int serdes_init_10g_serdes(struct niu
*np
);
118 static int __niu_wait_bits_clear_mac(struct niu
*np
, unsigned long reg
,
119 u64 bits
, int limit
, int delay
)
121 while (--limit
>= 0) {
122 u64 val
= nr64_mac(reg
);
133 static int __niu_set_and_wait_clear_mac(struct niu
*np
, unsigned long reg
,
134 u64 bits
, int limit
, int delay
,
135 const char *reg_name
)
140 err
= __niu_wait_bits_clear_mac(np
, reg
, bits
, limit
, delay
);
142 dev_err(np
->device
, PFX
"%s: bits (%llx) of register %s "
143 "would not clear, val[%llx]\n",
144 np
->dev
->name
, (unsigned long long) bits
, reg_name
,
145 (unsigned long long) nr64_mac(reg
));
149 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
150 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
151 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
154 static int __niu_wait_bits_clear_ipp(struct niu
*np
, unsigned long reg
,
155 u64 bits
, int limit
, int delay
)
157 while (--limit
>= 0) {
158 u64 val
= nr64_ipp(reg
);
169 static int __niu_set_and_wait_clear_ipp(struct niu
*np
, unsigned long reg
,
170 u64 bits
, int limit
, int delay
,
171 const char *reg_name
)
180 err
= __niu_wait_bits_clear_ipp(np
, reg
, bits
, limit
, delay
);
182 dev_err(np
->device
, PFX
"%s: bits (%llx) of register %s "
183 "would not clear, val[%llx]\n",
184 np
->dev
->name
, (unsigned long long) bits
, reg_name
,
185 (unsigned long long) nr64_ipp(reg
));
189 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
190 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
191 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
194 static int __niu_wait_bits_clear(struct niu
*np
, unsigned long reg
,
195 u64 bits
, int limit
, int delay
)
197 while (--limit
>= 0) {
209 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
210 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
211 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
214 static int __niu_set_and_wait_clear(struct niu
*np
, unsigned long reg
,
215 u64 bits
, int limit
, int delay
,
216 const char *reg_name
)
221 err
= __niu_wait_bits_clear(np
, reg
, bits
, limit
, delay
);
223 dev_err(np
->device
, PFX
"%s: bits (%llx) of register %s "
224 "would not clear, val[%llx]\n",
225 np
->dev
->name
, (unsigned long long) bits
, reg_name
,
226 (unsigned long long) nr64(reg
));
230 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
231 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
232 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
235 static void niu_ldg_rearm(struct niu
*np
, struct niu_ldg
*lp
, int on
)
237 u64 val
= (u64
) lp
->timer
;
240 val
|= LDG_IMGMT_ARM
;
242 nw64(LDG_IMGMT(lp
->ldg_num
), val
);
245 static int niu_ldn_irq_enable(struct niu
*np
, int ldn
, int on
)
247 unsigned long mask_reg
, bits
;
250 if (ldn
< 0 || ldn
> LDN_MAX
)
254 mask_reg
= LD_IM0(ldn
);
257 mask_reg
= LD_IM1(ldn
- 64);
261 val
= nr64(mask_reg
);
271 static int niu_enable_ldn_in_ldg(struct niu
*np
, struct niu_ldg
*lp
, int on
)
273 struct niu_parent
*parent
= np
->parent
;
276 for (i
= 0; i
<= LDN_MAX
; i
++) {
279 if (parent
->ldg_map
[i
] != lp
->ldg_num
)
282 err
= niu_ldn_irq_enable(np
, i
, on
);
289 static int niu_enable_interrupts(struct niu
*np
, int on
)
293 for (i
= 0; i
< np
->num_ldg
; i
++) {
294 struct niu_ldg
*lp
= &np
->ldg
[i
];
297 err
= niu_enable_ldn_in_ldg(np
, lp
, on
);
301 for (i
= 0; i
< np
->num_ldg
; i
++)
302 niu_ldg_rearm(np
, &np
->ldg
[i
], on
);
307 static u32
phy_encode(u32 type
, int port
)
309 return (type
<< (port
* 2));
312 static u32
phy_decode(u32 val
, int port
)
314 return (val
>> (port
* 2)) & PORT_TYPE_MASK
;
317 static int mdio_wait(struct niu
*np
)
322 while (--limit
> 0) {
323 val
= nr64(MIF_FRAME_OUTPUT
);
324 if ((val
>> MIF_FRAME_OUTPUT_TA_SHIFT
) & 0x1)
325 return val
& MIF_FRAME_OUTPUT_DATA
;
333 static int mdio_read(struct niu
*np
, int port
, int dev
, int reg
)
337 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
342 nw64(MIF_FRAME_OUTPUT
, MDIO_READ_OP(port
, dev
));
343 return mdio_wait(np
);
346 static int mdio_write(struct niu
*np
, int port
, int dev
, int reg
, int data
)
350 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
355 nw64(MIF_FRAME_OUTPUT
, MDIO_WRITE_OP(port
, dev
, data
));
363 static int mii_read(struct niu
*np
, int port
, int reg
)
365 nw64(MIF_FRAME_OUTPUT
, MII_READ_OP(port
, reg
));
366 return mdio_wait(np
);
369 static int mii_write(struct niu
*np
, int port
, int reg
, int data
)
373 nw64(MIF_FRAME_OUTPUT
, MII_WRITE_OP(port
, reg
, data
));
381 static int esr2_set_tx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
385 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
386 ESR2_TI_PLL_TX_CFG_L(channel
),
389 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
390 ESR2_TI_PLL_TX_CFG_H(channel
),
395 static int esr2_set_rx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
399 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
400 ESR2_TI_PLL_RX_CFG_L(channel
),
403 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
404 ESR2_TI_PLL_RX_CFG_H(channel
),
409 /* Mode is always 10G fiber. */
410 static int serdes_init_niu(struct niu
*np
)
412 struct niu_link_config
*lp
= &np
->link_config
;
416 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
);
417 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
418 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
419 PLL_RX_CFG_EQ_LP_ADAPTIVE
);
421 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
422 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
424 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
425 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
427 tx_cfg
|= PLL_TX_CFG_ENTEST
;
428 rx_cfg
|= PLL_RX_CFG_ENTEST
;
431 /* Initialize all 4 lanes of the SERDES. */
432 for (i
= 0; i
< 4; i
++) {
433 int err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
438 for (i
= 0; i
< 4; i
++) {
439 int err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
447 static int esr_read_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32
*val
)
451 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
, ESR_RXTX_CTRL_L(chan
));
453 *val
= (err
& 0xffff);
454 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
455 ESR_RXTX_CTRL_H(chan
));
457 *val
|= ((err
& 0xffff) << 16);
463 static int esr_read_glue0(struct niu
*np
, unsigned long chan
, u32
*val
)
467 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
468 ESR_GLUE_CTRL0_L(chan
));
470 *val
= (err
& 0xffff);
471 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
472 ESR_GLUE_CTRL0_H(chan
));
474 *val
|= ((err
& 0xffff) << 16);
481 static int esr_read_reset(struct niu
*np
, u32
*val
)
485 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
486 ESR_RXTX_RESET_CTRL_L
);
488 *val
= (err
& 0xffff);
489 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
490 ESR_RXTX_RESET_CTRL_H
);
492 *val
|= ((err
& 0xffff) << 16);
499 static int esr_write_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32 val
)
503 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
504 ESR_RXTX_CTRL_L(chan
), val
& 0xffff);
506 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
507 ESR_RXTX_CTRL_H(chan
), (val
>> 16));
511 static int esr_write_glue0(struct niu
*np
, unsigned long chan
, u32 val
)
515 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
516 ESR_GLUE_CTRL0_L(chan
), val
& 0xffff);
518 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
519 ESR_GLUE_CTRL0_H(chan
), (val
>> 16));
523 static int esr_reset(struct niu
*np
)
528 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
529 ESR_RXTX_RESET_CTRL_L
, 0x0000);
532 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
533 ESR_RXTX_RESET_CTRL_H
, 0xffff);
538 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
539 ESR_RXTX_RESET_CTRL_L
, 0xffff);
544 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
545 ESR_RXTX_RESET_CTRL_H
, 0x0000);
550 err
= esr_read_reset(np
, &reset
);
554 dev_err(np
->device
, PFX
"Port %u ESR_RESET "
555 "did not clear [%08x]\n",
563 static int serdes_init_10g(struct niu
*np
)
565 struct niu_link_config
*lp
= &np
->link_config
;
566 unsigned long ctrl_reg
, test_cfg_reg
, i
;
567 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
572 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
573 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
576 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
577 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
583 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
584 ENET_SERDES_CTRL_SDET_1
|
585 ENET_SERDES_CTRL_SDET_2
|
586 ENET_SERDES_CTRL_SDET_3
|
587 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
588 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
589 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
590 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
591 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
592 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
593 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
594 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
597 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
598 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
599 ENET_SERDES_TEST_MD_0_SHIFT
) |
600 (ENET_TEST_MD_PAD_LOOPBACK
<<
601 ENET_SERDES_TEST_MD_1_SHIFT
) |
602 (ENET_TEST_MD_PAD_LOOPBACK
<<
603 ENET_SERDES_TEST_MD_2_SHIFT
) |
604 (ENET_TEST_MD_PAD_LOOPBACK
<<
605 ENET_SERDES_TEST_MD_3_SHIFT
));
608 nw64(ctrl_reg
, ctrl_val
);
609 nw64(test_cfg_reg
, test_cfg_val
);
611 /* Initialize all 4 lanes of the SERDES. */
612 for (i
= 0; i
< 4; i
++) {
613 u32 rxtx_ctrl
, glue0
;
615 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
618 err
= esr_read_glue0(np
, i
, &glue0
);
622 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
623 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
624 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
626 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
627 ESR_GLUE_CTRL0_THCNT
|
628 ESR_GLUE_CTRL0_BLTIME
);
629 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
630 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
631 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
632 (BLTIME_300_CYCLES
<<
633 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
635 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
638 err
= esr_write_glue0(np
, i
, glue0
);
647 sig
= nr64(ESR_INT_SIGNALS
);
650 mask
= ESR_INT_SIGNALS_P0_BITS
;
651 val
= (ESR_INT_SRDY0_P0
|
661 mask
= ESR_INT_SIGNALS_P1_BITS
;
662 val
= (ESR_INT_SRDY0_P1
|
675 if ((sig
& mask
) != val
) {
676 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
677 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
680 dev_err(np
->device
, PFX
"Port %u signal bits [%08x] are not "
681 "[%08x]\n", np
->port
, (int) (sig
& mask
), (int) val
);
684 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
)
685 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
689 static int serdes_init_1g(struct niu
*np
)
693 val
= nr64(ENET_SERDES_1_PLL_CFG
);
694 val
&= ~ENET_SERDES_PLL_FBDIV2
;
697 val
|= ENET_SERDES_PLL_HRATE0
;
700 val
|= ENET_SERDES_PLL_HRATE1
;
703 val
|= ENET_SERDES_PLL_HRATE2
;
706 val
|= ENET_SERDES_PLL_HRATE3
;
711 nw64(ENET_SERDES_1_PLL_CFG
, val
);
716 static int serdes_init_1g_serdes(struct niu
*np
)
718 struct niu_link_config
*lp
= &np
->link_config
;
719 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
720 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
722 u64 reset_val
, val_rd
;
724 val
= ENET_SERDES_PLL_HRATE0
| ENET_SERDES_PLL_HRATE1
|
725 ENET_SERDES_PLL_HRATE2
| ENET_SERDES_PLL_HRATE3
|
726 ENET_SERDES_PLL_FBDIV0
;
729 reset_val
= ENET_SERDES_RESET_0
;
730 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
731 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
732 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
735 reset_val
= ENET_SERDES_RESET_1
;
736 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
737 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
738 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
744 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
745 ENET_SERDES_CTRL_SDET_1
|
746 ENET_SERDES_CTRL_SDET_2
|
747 ENET_SERDES_CTRL_SDET_3
|
748 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
749 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
750 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
751 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
752 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
753 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
754 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
755 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
758 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
759 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
760 ENET_SERDES_TEST_MD_0_SHIFT
) |
761 (ENET_TEST_MD_PAD_LOOPBACK
<<
762 ENET_SERDES_TEST_MD_1_SHIFT
) |
763 (ENET_TEST_MD_PAD_LOOPBACK
<<
764 ENET_SERDES_TEST_MD_2_SHIFT
) |
765 (ENET_TEST_MD_PAD_LOOPBACK
<<
766 ENET_SERDES_TEST_MD_3_SHIFT
));
769 nw64(ENET_SERDES_RESET
, reset_val
);
771 val_rd
= nr64(ENET_SERDES_RESET
);
772 val_rd
&= ~reset_val
;
774 nw64(ctrl_reg
, ctrl_val
);
775 nw64(test_cfg_reg
, test_cfg_val
);
776 nw64(ENET_SERDES_RESET
, val_rd
);
779 /* Initialize all 4 lanes of the SERDES. */
780 for (i
= 0; i
< 4; i
++) {
781 u32 rxtx_ctrl
, glue0
;
783 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
786 err
= esr_read_glue0(np
, i
, &glue0
);
790 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
791 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
792 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
794 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
795 ESR_GLUE_CTRL0_THCNT
|
796 ESR_GLUE_CTRL0_BLTIME
);
797 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
798 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
799 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
800 (BLTIME_300_CYCLES
<<
801 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
803 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
806 err
= esr_write_glue0(np
, i
, glue0
);
812 sig
= nr64(ESR_INT_SIGNALS
);
815 val
= (ESR_INT_SRDY0_P0
| ESR_INT_DET0_P0
);
820 val
= (ESR_INT_SRDY0_P1
| ESR_INT_DET0_P1
);
828 if ((sig
& mask
) != val
) {
829 dev_err(np
->device
, PFX
"Port %u signal bits [%08x] are not "
830 "[%08x]\n", np
->port
, (int) (sig
& mask
), (int) val
);
837 static int link_status_1g_serdes(struct niu
*np
, int *link_up_p
)
839 struct niu_link_config
*lp
= &np
->link_config
;
847 current_speed
= SPEED_INVALID
;
848 current_duplex
= DUPLEX_INVALID
;
850 spin_lock_irqsave(&np
->lock
, flags
);
852 val
= nr64_pcs(PCS_MII_STAT
);
854 if (val
& PCS_MII_STAT_LINK_STATUS
) {
856 current_speed
= SPEED_1000
;
857 current_duplex
= DUPLEX_FULL
;
860 lp
->active_speed
= current_speed
;
861 lp
->active_duplex
= current_duplex
;
862 spin_unlock_irqrestore(&np
->lock
, flags
);
864 *link_up_p
= link_up
;
868 static int link_status_10g_serdes(struct niu
*np
, int *link_up_p
)
871 struct niu_link_config
*lp
= &np
->link_config
;
878 if (!(np
->flags
& NIU_FLAGS_10G
))
879 return link_status_1g_serdes(np
, link_up_p
);
881 current_speed
= SPEED_INVALID
;
882 current_duplex
= DUPLEX_INVALID
;
883 spin_lock_irqsave(&np
->lock
, flags
);
885 val
= nr64_xpcs(XPCS_STATUS(0));
886 val2
= nr64_mac(XMAC_INTER2
);
887 if (val2
& 0x01000000)
890 if ((val
& 0x1000ULL
) && link_ok
) {
892 current_speed
= SPEED_10000
;
893 current_duplex
= DUPLEX_FULL
;
895 lp
->active_speed
= current_speed
;
896 lp
->active_duplex
= current_duplex
;
897 spin_unlock_irqrestore(&np
->lock
, flags
);
898 *link_up_p
= link_up
;
902 static int link_status_1g_rgmii(struct niu
*np
, int *link_up_p
)
904 struct niu_link_config
*lp
= &np
->link_config
;
905 u16 current_speed
, bmsr
;
911 current_speed
= SPEED_INVALID
;
912 current_duplex
= DUPLEX_INVALID
;
914 spin_lock_irqsave(&np
->lock
, flags
);
918 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
923 if (bmsr
& BMSR_LSTATUS
) {
924 u16 adv
, lpa
, common
, estat
;
926 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
931 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
938 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
943 current_speed
= SPEED_1000
;
944 current_duplex
= DUPLEX_FULL
;
947 lp
->active_speed
= current_speed
;
948 lp
->active_duplex
= current_duplex
;
952 spin_unlock_irqrestore(&np
->lock
, flags
);
954 *link_up_p
= link_up
;
958 static int bcm8704_reset(struct niu
*np
)
962 err
= mdio_read(np
, np
->phy_addr
,
963 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
967 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
973 while (--limit
>= 0) {
974 err
= mdio_read(np
, np
->phy_addr
,
975 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
978 if (!(err
& BMCR_RESET
))
982 dev_err(np
->device
, PFX
"Port %u PHY will not reset "
983 "(bmcr=%04x)\n", np
->port
, (err
& 0xffff));
989 /* When written, certain PHY registers need to be read back twice
990 * in order for the bits to settle properly.
992 static int bcm8704_user_dev3_readback(struct niu
*np
, int reg
)
994 int err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
997 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
1003 static int bcm8706_init_user_dev3(struct niu
*np
)
1008 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1009 BCM8704_USER_OPT_DIGITAL_CTRL
);
1012 err
&= ~USER_ODIG_CTRL_GPIOS
;
1013 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1014 err
|= USER_ODIG_CTRL_RESV2
;
1015 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1016 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1025 static int bcm8704_init_user_dev3(struct niu
*np
)
1029 err
= mdio_write(np
, np
->phy_addr
,
1030 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_CONTROL
,
1031 (USER_CONTROL_OPTXRST_LVL
|
1032 USER_CONTROL_OPBIASFLT_LVL
|
1033 USER_CONTROL_OBTMPFLT_LVL
|
1034 USER_CONTROL_OPPRFLT_LVL
|
1035 USER_CONTROL_OPTXFLT_LVL
|
1036 USER_CONTROL_OPRXLOS_LVL
|
1037 USER_CONTROL_OPRXFLT_LVL
|
1038 USER_CONTROL_OPTXON_LVL
|
1039 (0x3f << USER_CONTROL_RES1_SHIFT
)));
1043 err
= mdio_write(np
, np
->phy_addr
,
1044 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_PMD_TX_CONTROL
,
1045 (USER_PMD_TX_CTL_XFP_CLKEN
|
1046 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH
) |
1047 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH
) |
1048 USER_PMD_TX_CTL_TSCK_LPWREN
));
1052 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_CONTROL
);
1055 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_PMD_TX_CONTROL
);
1059 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1060 BCM8704_USER_OPT_DIGITAL_CTRL
);
1063 err
&= ~USER_ODIG_CTRL_GPIOS
;
1064 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1065 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1066 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1075 static int mrvl88x2011_act_led(struct niu
*np
, int val
)
1079 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1080 MRVL88X2011_LED_8_TO_11_CTL
);
1084 err
&= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT
,MRVL88X2011_LED_CTL_MASK
);
1085 err
|= MRVL88X2011_LED(MRVL88X2011_LED_ACT
,val
);
1087 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1088 MRVL88X2011_LED_8_TO_11_CTL
, err
);
1091 static int mrvl88x2011_led_blink_rate(struct niu
*np
, int rate
)
1095 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1096 MRVL88X2011_LED_BLINK_CTL
);
1098 err
&= ~MRVL88X2011_LED_BLKRATE_MASK
;
1101 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1102 MRVL88X2011_LED_BLINK_CTL
, err
);
1108 static int xcvr_init_10g_mrvl88x2011(struct niu
*np
)
1112 /* Set LED functions */
1113 err
= mrvl88x2011_led_blink_rate(np
, MRVL88X2011_LED_BLKRATE_134MS
);
1118 err
= mrvl88x2011_act_led(np
, MRVL88X2011_LED_CTL_OFF
);
1122 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1123 MRVL88X2011_GENERAL_CTL
);
1127 err
|= MRVL88X2011_ENA_XFPREFCLK
;
1129 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1130 MRVL88X2011_GENERAL_CTL
, err
);
1134 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1135 MRVL88X2011_PMA_PMD_CTL_1
);
1139 if (np
->link_config
.loopback_mode
== LOOPBACK_MAC
)
1140 err
|= MRVL88X2011_LOOPBACK
;
1142 err
&= ~MRVL88X2011_LOOPBACK
;
1144 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1145 MRVL88X2011_PMA_PMD_CTL_1
, err
);
1150 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1151 MRVL88X2011_10G_PMD_TX_DIS
, MRVL88X2011_ENA_PMDTX
);
1155 static int xcvr_diag_bcm870x(struct niu
*np
)
1157 u16 analog_stat0
, tx_alarm_status
;
1161 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
1165 pr_info(PFX
"Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1168 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, 0x20);
1171 pr_info(PFX
"Port %u USER_DEV3(0x20) [%04x]\n",
1174 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1178 pr_info(PFX
"Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1182 /* XXX dig this out it might not be so useful XXX */
1183 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1184 BCM8704_USER_ANALOG_STATUS0
);
1187 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1188 BCM8704_USER_ANALOG_STATUS0
);
1193 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1194 BCM8704_USER_TX_ALARM_STATUS
);
1197 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1198 BCM8704_USER_TX_ALARM_STATUS
);
1201 tx_alarm_status
= err
;
1203 if (analog_stat0
!= 0x03fc) {
1204 if ((analog_stat0
== 0x43bc) && (tx_alarm_status
!= 0)) {
1205 pr_info(PFX
"Port %u cable not connected "
1206 "or bad cable.\n", np
->port
);
1207 } else if (analog_stat0
== 0x639c) {
1208 pr_info(PFX
"Port %u optical module is bad "
1209 "or missing.\n", np
->port
);
1216 static int xcvr_10g_set_lb_bcm870x(struct niu
*np
)
1218 struct niu_link_config
*lp
= &np
->link_config
;
1221 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1226 err
&= ~BMCR_LOOPBACK
;
1228 if (lp
->loopback_mode
== LOOPBACK_MAC
)
1229 err
|= BMCR_LOOPBACK
;
1231 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1239 static int xcvr_init_10g_bcm8706(struct niu
*np
)
1244 if ((np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) &&
1245 (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) == 0)
1248 val
= nr64_mac(XMAC_CONFIG
);
1249 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1250 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1251 nw64_mac(XMAC_CONFIG
, val
);
1253 val
= nr64(MIF_CONFIG
);
1254 val
|= MIF_CONFIG_INDIRECT_MODE
;
1255 nw64(MIF_CONFIG
, val
);
1257 err
= bcm8704_reset(np
);
1261 err
= xcvr_10g_set_lb_bcm870x(np
);
1265 err
= bcm8706_init_user_dev3(np
);
1269 err
= xcvr_diag_bcm870x(np
);
1276 static int xcvr_init_10g_bcm8704(struct niu
*np
)
1280 err
= bcm8704_reset(np
);
1284 err
= bcm8704_init_user_dev3(np
);
1288 err
= xcvr_10g_set_lb_bcm870x(np
);
1292 err
= xcvr_diag_bcm870x(np
);
1299 static int xcvr_init_10g(struct niu
*np
)
1304 val
= nr64_mac(XMAC_CONFIG
);
1305 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1306 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1307 nw64_mac(XMAC_CONFIG
, val
);
1309 /* XXX shared resource, lock parent XXX */
1310 val
= nr64(MIF_CONFIG
);
1311 val
|= MIF_CONFIG_INDIRECT_MODE
;
1312 nw64(MIF_CONFIG
, val
);
1314 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
1315 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
1317 /* handle different phy types */
1318 switch (phy_id
& NIU_PHY_ID_MASK
) {
1319 case NIU_PHY_ID_MRVL88X2011
:
1320 err
= xcvr_init_10g_mrvl88x2011(np
);
1323 default: /* bcom 8704 */
1324 err
= xcvr_init_10g_bcm8704(np
);
1331 static int mii_reset(struct niu
*np
)
1335 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, BMCR_RESET
);
1340 while (--limit
>= 0) {
1342 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1345 if (!(err
& BMCR_RESET
))
1349 dev_err(np
->device
, PFX
"Port %u MII would not reset, "
1350 "bmcr[%04x]\n", np
->port
, err
);
1357 static int xcvr_init_1g_rgmii(struct niu
*np
)
1361 u16 bmcr
, bmsr
, estat
;
1363 val
= nr64(MIF_CONFIG
);
1364 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1365 nw64(MIF_CONFIG
, val
);
1367 err
= mii_reset(np
);
1371 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1377 if (bmsr
& BMSR_ESTATEN
) {
1378 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1385 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1389 if (bmsr
& BMSR_ESTATEN
) {
1392 if (estat
& ESTATUS_1000_TFULL
)
1393 ctrl1000
|= ADVERTISE_1000FULL
;
1394 err
= mii_write(np
, np
->phy_addr
, MII_CTRL1000
, ctrl1000
);
1399 bmcr
= (BMCR_SPEED1000
| BMCR_FULLDPLX
);
1401 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1405 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1408 bmcr
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1410 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1417 static int mii_init_common(struct niu
*np
)
1419 struct niu_link_config
*lp
= &np
->link_config
;
1420 u16 bmcr
, bmsr
, adv
, estat
;
1423 err
= mii_reset(np
);
1427 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1433 if (bmsr
& BMSR_ESTATEN
) {
1434 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1441 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1445 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
1446 bmcr
|= BMCR_LOOPBACK
;
1447 if (lp
->active_speed
== SPEED_1000
)
1448 bmcr
|= BMCR_SPEED1000
;
1449 if (lp
->active_duplex
== DUPLEX_FULL
)
1450 bmcr
|= BMCR_FULLDPLX
;
1453 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
1456 aux
= (BCM5464R_AUX_CTL_EXT_LB
|
1457 BCM5464R_AUX_CTL_WRITE_1
);
1458 err
= mii_write(np
, np
->phy_addr
, BCM5464R_AUX_CTL
, aux
);
1463 /* XXX configurable XXX */
1464 /* XXX for now don't advertise half-duplex or asym pause... XXX */
1465 adv
= ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
;
1466 if (bmsr
& BMSR_10FULL
)
1467 adv
|= ADVERTISE_10FULL
;
1468 if (bmsr
& BMSR_100FULL
)
1469 adv
|= ADVERTISE_100FULL
;
1470 err
= mii_write(np
, np
->phy_addr
, MII_ADVERTISE
, adv
);
1474 if (bmsr
& BMSR_ESTATEN
) {
1477 if (estat
& ESTATUS_1000_TFULL
)
1478 ctrl1000
|= ADVERTISE_1000FULL
;
1479 err
= mii_write(np
, np
->phy_addr
, MII_CTRL1000
, ctrl1000
);
1483 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1485 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1489 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1492 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1496 pr_info(PFX
"Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1497 np
->port
, bmcr
, bmsr
);
1503 static int xcvr_init_1g(struct niu
*np
)
1507 /* XXX shared resource, lock parent XXX */
1508 val
= nr64(MIF_CONFIG
);
1509 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1510 nw64(MIF_CONFIG
, val
);
1512 return mii_init_common(np
);
1515 static int niu_xcvr_init(struct niu
*np
)
1517 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1522 err
= ops
->xcvr_init(np
);
1527 static int niu_serdes_init(struct niu
*np
)
1529 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1533 if (ops
->serdes_init
)
1534 err
= ops
->serdes_init(np
);
1539 static void niu_init_xif(struct niu
*);
1540 static void niu_handle_led(struct niu
*, int status
);
1542 static int niu_link_status_common(struct niu
*np
, int link_up
)
1544 struct niu_link_config
*lp
= &np
->link_config
;
1545 struct net_device
*dev
= np
->dev
;
1546 unsigned long flags
;
1548 if (!netif_carrier_ok(dev
) && link_up
) {
1549 niuinfo(LINK
, "%s: Link is up at %s, %s duplex\n",
1551 (lp
->active_speed
== SPEED_10000
?
1553 (lp
->active_speed
== SPEED_1000
?
1555 (lp
->active_speed
== SPEED_100
?
1556 "100Mbit/sec" : "10Mbit/sec"))),
1557 (lp
->active_duplex
== DUPLEX_FULL
?
1560 spin_lock_irqsave(&np
->lock
, flags
);
1562 niu_handle_led(np
, 1);
1563 spin_unlock_irqrestore(&np
->lock
, flags
);
1565 netif_carrier_on(dev
);
1566 } else if (netif_carrier_ok(dev
) && !link_up
) {
1567 niuwarn(LINK
, "%s: Link is down\n", dev
->name
);
1568 spin_lock_irqsave(&np
->lock
, flags
);
1569 niu_handle_led(np
, 0);
1570 spin_unlock_irqrestore(&np
->lock
, flags
);
1571 netif_carrier_off(dev
);
1577 static int link_status_10g_mrvl(struct niu
*np
, int *link_up_p
)
1579 int err
, link_up
, pma_status
, pcs_status
;
1583 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1584 MRVL88X2011_10G_PMD_STATUS_2
);
1588 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1589 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1590 MRVL88X2011_PMA_PMD_STATUS_1
);
1594 pma_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
1596 /* Check PMC Register : 3.0001.2 == 1: read twice */
1597 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1598 MRVL88X2011_PMA_PMD_STATUS_1
);
1602 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1603 MRVL88X2011_PMA_PMD_STATUS_1
);
1607 pcs_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
1609 /* Check XGXS Register : 4.0018.[0-3,12] */
1610 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV4_ADDR
,
1611 MRVL88X2011_10G_XGXS_LANE_STAT
);
1615 if (err
== (PHYXS_XGXS_LANE_STAT_ALINGED
| PHYXS_XGXS_LANE_STAT_LANE3
|
1616 PHYXS_XGXS_LANE_STAT_LANE2
| PHYXS_XGXS_LANE_STAT_LANE1
|
1617 PHYXS_XGXS_LANE_STAT_LANE0
| PHYXS_XGXS_LANE_STAT_MAGIC
|
1619 link_up
= (pma_status
&& pcs_status
) ? 1 : 0;
1621 np
->link_config
.active_speed
= SPEED_10000
;
1622 np
->link_config
.active_duplex
= DUPLEX_FULL
;
1625 mrvl88x2011_act_led(np
, (link_up
?
1626 MRVL88X2011_LED_CTL_PCS_ACT
:
1627 MRVL88X2011_LED_CTL_OFF
));
1629 *link_up_p
= link_up
;
1633 static int link_status_10g_bcm8706(struct niu
*np
, int *link_up_p
)
1638 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
1639 BCM8704_PMD_RCV_SIGDET
);
1642 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
1647 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1648 BCM8704_PCS_10G_R_STATUS
);
1652 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
1657 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1658 BCM8704_PHYXS_XGXS_LANE_STAT
);
1661 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
1662 PHYXS_XGXS_LANE_STAT_MAGIC
|
1663 PHYXS_XGXS_LANE_STAT_PATTEST
|
1664 PHYXS_XGXS_LANE_STAT_LANE3
|
1665 PHYXS_XGXS_LANE_STAT_LANE2
|
1666 PHYXS_XGXS_LANE_STAT_LANE1
|
1667 PHYXS_XGXS_LANE_STAT_LANE0
)) {
1669 np
->link_config
.active_speed
= SPEED_INVALID
;
1670 np
->link_config
.active_duplex
= DUPLEX_INVALID
;
1675 np
->link_config
.active_speed
= SPEED_10000
;
1676 np
->link_config
.active_duplex
= DUPLEX_FULL
;
1680 *link_up_p
= link_up
;
1681 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
)
1686 static int link_status_10g_bcom(struct niu
*np
, int *link_up_p
)
1692 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
1693 BCM8704_PMD_RCV_SIGDET
);
1696 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
1701 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1702 BCM8704_PCS_10G_R_STATUS
);
1705 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
1710 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1711 BCM8704_PHYXS_XGXS_LANE_STAT
);
1715 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
1716 PHYXS_XGXS_LANE_STAT_MAGIC
|
1717 PHYXS_XGXS_LANE_STAT_LANE3
|
1718 PHYXS_XGXS_LANE_STAT_LANE2
|
1719 PHYXS_XGXS_LANE_STAT_LANE1
|
1720 PHYXS_XGXS_LANE_STAT_LANE0
)) {
1726 np
->link_config
.active_speed
= SPEED_10000
;
1727 np
->link_config
.active_duplex
= DUPLEX_FULL
;
1731 *link_up_p
= link_up
;
1735 static int link_status_10g(struct niu
*np
, int *link_up_p
)
1737 unsigned long flags
;
1740 spin_lock_irqsave(&np
->lock
, flags
);
1742 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
1745 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
1746 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
1748 /* handle different phy types */
1749 switch (phy_id
& NIU_PHY_ID_MASK
) {
1750 case NIU_PHY_ID_MRVL88X2011
:
1751 err
= link_status_10g_mrvl(np
, link_up_p
);
1754 default: /* bcom 8704 */
1755 err
= link_status_10g_bcom(np
, link_up_p
);
1760 spin_unlock_irqrestore(&np
->lock
, flags
);
1765 static int niu_10g_phy_present(struct niu
*np
)
1769 sig
= nr64(ESR_INT_SIGNALS
);
1772 mask
= ESR_INT_SIGNALS_P0_BITS
;
1773 val
= (ESR_INT_SRDY0_P0
|
1776 ESR_INT_XDP_P0_CH3
|
1777 ESR_INT_XDP_P0_CH2
|
1778 ESR_INT_XDP_P0_CH1
|
1779 ESR_INT_XDP_P0_CH0
);
1783 mask
= ESR_INT_SIGNALS_P1_BITS
;
1784 val
= (ESR_INT_SRDY0_P1
|
1787 ESR_INT_XDP_P1_CH3
|
1788 ESR_INT_XDP_P1_CH2
|
1789 ESR_INT_XDP_P1_CH1
|
1790 ESR_INT_XDP_P1_CH0
);
1797 if ((sig
& mask
) != val
)
1802 static int link_status_10g_hotplug(struct niu
*np
, int *link_up_p
)
1804 unsigned long flags
;
1807 int phy_present_prev
;
1809 spin_lock_irqsave(&np
->lock
, flags
);
1811 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
1812 phy_present_prev
= (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) ?
1814 phy_present
= niu_10g_phy_present(np
);
1815 if (phy_present
!= phy_present_prev
) {
1818 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
1819 if (np
->phy_ops
->xcvr_init
)
1820 err
= np
->phy_ops
->xcvr_init(np
);
1823 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
1826 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
1828 niuwarn(LINK
, "%s: Hotplug PHY Removed\n",
1832 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
)
1833 err
= link_status_10g_bcm8706(np
, link_up_p
);
1836 spin_unlock_irqrestore(&np
->lock
, flags
);
1841 static int link_status_1g(struct niu
*np
, int *link_up_p
)
1843 struct niu_link_config
*lp
= &np
->link_config
;
1844 u16 current_speed
, bmsr
;
1845 unsigned long flags
;
1850 current_speed
= SPEED_INVALID
;
1851 current_duplex
= DUPLEX_INVALID
;
1853 spin_lock_irqsave(&np
->lock
, flags
);
1856 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
1859 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1864 if (bmsr
& BMSR_LSTATUS
) {
1865 u16 adv
, lpa
, common
, estat
;
1867 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
1872 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
1879 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1885 if (estat
& (ESTATUS_1000_TFULL
| ESTATUS_1000_THALF
)) {
1886 current_speed
= SPEED_1000
;
1887 if (estat
& ESTATUS_1000_TFULL
)
1888 current_duplex
= DUPLEX_FULL
;
1890 current_duplex
= DUPLEX_HALF
;
1892 if (common
& ADVERTISE_100BASE4
) {
1893 current_speed
= SPEED_100
;
1894 current_duplex
= DUPLEX_HALF
;
1895 } else if (common
& ADVERTISE_100FULL
) {
1896 current_speed
= SPEED_100
;
1897 current_duplex
= DUPLEX_FULL
;
1898 } else if (common
& ADVERTISE_100HALF
) {
1899 current_speed
= SPEED_100
;
1900 current_duplex
= DUPLEX_HALF
;
1901 } else if (common
& ADVERTISE_10FULL
) {
1902 current_speed
= SPEED_10
;
1903 current_duplex
= DUPLEX_FULL
;
1904 } else if (common
& ADVERTISE_10HALF
) {
1905 current_speed
= SPEED_10
;
1906 current_duplex
= DUPLEX_HALF
;
1911 lp
->active_speed
= current_speed
;
1912 lp
->active_duplex
= current_duplex
;
1916 spin_unlock_irqrestore(&np
->lock
, flags
);
1918 *link_up_p
= link_up
;
1922 static int niu_link_status(struct niu
*np
, int *link_up_p
)
1924 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1928 if (ops
->link_status
)
1929 err
= ops
->link_status(np
, link_up_p
);
1934 static void niu_timer(unsigned long __opaque
)
1936 struct niu
*np
= (struct niu
*) __opaque
;
1940 err
= niu_link_status(np
, &link_up
);
1942 niu_link_status_common(np
, link_up
);
1944 if (netif_carrier_ok(np
->dev
))
1948 np
->timer
.expires
= jiffies
+ off
;
1950 add_timer(&np
->timer
);
1953 static const struct niu_phy_ops phy_ops_10g_serdes
= {
1954 .serdes_init
= serdes_init_10g_serdes
,
1955 .link_status
= link_status_10g_serdes
,
1958 static const struct niu_phy_ops phy_ops_1g_rgmii
= {
1959 .xcvr_init
= xcvr_init_1g_rgmii
,
1960 .link_status
= link_status_1g_rgmii
,
1963 static const struct niu_phy_ops phy_ops_10g_fiber_niu
= {
1964 .serdes_init
= serdes_init_niu
,
1965 .xcvr_init
= xcvr_init_10g
,
1966 .link_status
= link_status_10g
,
1969 static const struct niu_phy_ops phy_ops_10g_fiber
= {
1970 .serdes_init
= serdes_init_10g
,
1971 .xcvr_init
= xcvr_init_10g
,
1972 .link_status
= link_status_10g
,
1975 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug
= {
1976 .serdes_init
= serdes_init_10g
,
1977 .xcvr_init
= xcvr_init_10g_bcm8706
,
1978 .link_status
= link_status_10g_hotplug
,
1981 static const struct niu_phy_ops phy_ops_10g_copper
= {
1982 .serdes_init
= serdes_init_10g
,
1983 .link_status
= link_status_10g
, /* XXX */
1986 static const struct niu_phy_ops phy_ops_1g_fiber
= {
1987 .serdes_init
= serdes_init_1g
,
1988 .xcvr_init
= xcvr_init_1g
,
1989 .link_status
= link_status_1g
,
1992 static const struct niu_phy_ops phy_ops_1g_copper
= {
1993 .xcvr_init
= xcvr_init_1g
,
1994 .link_status
= link_status_1g
,
1997 struct niu_phy_template
{
1998 const struct niu_phy_ops
*ops
;
2002 static const struct niu_phy_template phy_template_niu
= {
2003 .ops
= &phy_ops_10g_fiber_niu
,
2004 .phy_addr_base
= 16,
2007 static const struct niu_phy_template phy_template_10g_fiber
= {
2008 .ops
= &phy_ops_10g_fiber
,
2012 static const struct niu_phy_template phy_template_10g_fiber_hotplug
= {
2013 .ops
= &phy_ops_10g_fiber_hotplug
,
2017 static const struct niu_phy_template phy_template_10g_copper
= {
2018 .ops
= &phy_ops_10g_copper
,
2019 .phy_addr_base
= 10,
2022 static const struct niu_phy_template phy_template_1g_fiber
= {
2023 .ops
= &phy_ops_1g_fiber
,
2027 static const struct niu_phy_template phy_template_1g_copper
= {
2028 .ops
= &phy_ops_1g_copper
,
2032 static const struct niu_phy_template phy_template_1g_rgmii
= {
2033 .ops
= &phy_ops_1g_rgmii
,
2037 static const struct niu_phy_template phy_template_10g_serdes
= {
2038 .ops
= &phy_ops_10g_serdes
,
2042 static int niu_atca_port_num
[4] = {
2046 static int serdes_init_10g_serdes(struct niu
*np
)
2048 struct niu_link_config
*lp
= &np
->link_config
;
2049 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
2050 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
2056 reset_val
= ENET_SERDES_RESET_0
;
2057 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
2058 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
2059 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
2062 reset_val
= ENET_SERDES_RESET_1
;
2063 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
2064 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
2065 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
2071 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
2072 ENET_SERDES_CTRL_SDET_1
|
2073 ENET_SERDES_CTRL_SDET_2
|
2074 ENET_SERDES_CTRL_SDET_3
|
2075 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
2076 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
2077 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
2078 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
2079 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
2080 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
2081 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
2082 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
2085 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
2086 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
2087 ENET_SERDES_TEST_MD_0_SHIFT
) |
2088 (ENET_TEST_MD_PAD_LOOPBACK
<<
2089 ENET_SERDES_TEST_MD_1_SHIFT
) |
2090 (ENET_TEST_MD_PAD_LOOPBACK
<<
2091 ENET_SERDES_TEST_MD_2_SHIFT
) |
2092 (ENET_TEST_MD_PAD_LOOPBACK
<<
2093 ENET_SERDES_TEST_MD_3_SHIFT
));
2097 nw64(pll_cfg
, ENET_SERDES_PLL_FBDIV2
);
2098 nw64(ctrl_reg
, ctrl_val
);
2099 nw64(test_cfg_reg
, test_cfg_val
);
2101 /* Initialize all 4 lanes of the SERDES. */
2102 for (i
= 0; i
< 4; i
++) {
2103 u32 rxtx_ctrl
, glue0
;
2105 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
2108 err
= esr_read_glue0(np
, i
, &glue0
);
2112 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
2113 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
2114 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
2116 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
2117 ESR_GLUE_CTRL0_THCNT
|
2118 ESR_GLUE_CTRL0_BLTIME
);
2119 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
2120 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
2121 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
2122 (BLTIME_300_CYCLES
<<
2123 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
2125 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
2128 err
= esr_write_glue0(np
, i
, glue0
);
2134 sig
= nr64(ESR_INT_SIGNALS
);
2137 mask
= ESR_INT_SIGNALS_P0_BITS
;
2138 val
= (ESR_INT_SRDY0_P0
|
2141 ESR_INT_XDP_P0_CH3
|
2142 ESR_INT_XDP_P0_CH2
|
2143 ESR_INT_XDP_P0_CH1
|
2144 ESR_INT_XDP_P0_CH0
);
2148 mask
= ESR_INT_SIGNALS_P1_BITS
;
2149 val
= (ESR_INT_SRDY0_P1
|
2152 ESR_INT_XDP_P1_CH3
|
2153 ESR_INT_XDP_P1_CH2
|
2154 ESR_INT_XDP_P1_CH1
|
2155 ESR_INT_XDP_P1_CH0
);
2162 if ((sig
& mask
) != val
) {
2164 err
= serdes_init_1g_serdes(np
);
2166 np
->flags
&= ~NIU_FLAGS_10G
;
2167 np
->mac_xcvr
= MAC_XCVR_PCS
;
2169 dev_err(np
->device
, PFX
"Port %u 10G/1G SERDES Link Failed \n",
2178 static int niu_determine_phy_disposition(struct niu
*np
)
2180 struct niu_parent
*parent
= np
->parent
;
2181 u8 plat_type
= parent
->plat_type
;
2182 const struct niu_phy_template
*tp
;
2183 u32 phy_addr_off
= 0;
2185 if (plat_type
== PLAT_TYPE_NIU
) {
2186 tp
= &phy_template_niu
;
2187 phy_addr_off
+= np
->port
;
2192 NIU_FLAGS_XCVR_SERDES
)) {
2195 tp
= &phy_template_1g_copper
;
2196 if (plat_type
== PLAT_TYPE_VF_P0
)
2198 else if (plat_type
== PLAT_TYPE_VF_P1
)
2201 phy_addr_off
+= (np
->port
^ 0x3);
2206 tp
= &phy_template_1g_copper
;
2209 case NIU_FLAGS_FIBER
:
2211 tp
= &phy_template_1g_fiber
;
2214 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
2216 tp
= &phy_template_10g_fiber
;
2217 if (plat_type
== PLAT_TYPE_VF_P0
||
2218 plat_type
== PLAT_TYPE_VF_P1
)
2220 phy_addr_off
+= np
->port
;
2221 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
2222 tp
= &phy_template_10g_fiber_hotplug
;
2230 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
2231 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
2232 case NIU_FLAGS_XCVR_SERDES
:
2236 tp
= &phy_template_10g_serdes
;
2240 tp
= &phy_template_1g_rgmii
;
2246 phy_addr_off
= niu_atca_port_num
[np
->port
];
2254 np
->phy_ops
= tp
->ops
;
2255 np
->phy_addr
= tp
->phy_addr_base
+ phy_addr_off
;
2260 static int niu_init_link(struct niu
*np
)
2262 struct niu_parent
*parent
= np
->parent
;
2265 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
2266 err
= niu_xcvr_init(np
);
2271 err
= niu_serdes_init(np
);
2275 err
= niu_xcvr_init(np
);
2277 niu_link_status(np
, &ignore
);
2281 static void niu_set_primary_mac(struct niu
*np
, unsigned char *addr
)
2283 u16 reg0
= addr
[4] << 8 | addr
[5];
2284 u16 reg1
= addr
[2] << 8 | addr
[3];
2285 u16 reg2
= addr
[0] << 8 | addr
[1];
2287 if (np
->flags
& NIU_FLAGS_XMAC
) {
2288 nw64_mac(XMAC_ADDR0
, reg0
);
2289 nw64_mac(XMAC_ADDR1
, reg1
);
2290 nw64_mac(XMAC_ADDR2
, reg2
);
2292 nw64_mac(BMAC_ADDR0
, reg0
);
2293 nw64_mac(BMAC_ADDR1
, reg1
);
2294 nw64_mac(BMAC_ADDR2
, reg2
);
2298 static int niu_num_alt_addr(struct niu
*np
)
2300 if (np
->flags
& NIU_FLAGS_XMAC
)
2301 return XMAC_NUM_ALT_ADDR
;
2303 return BMAC_NUM_ALT_ADDR
;
2306 static int niu_set_alt_mac(struct niu
*np
, int index
, unsigned char *addr
)
2308 u16 reg0
= addr
[4] << 8 | addr
[5];
2309 u16 reg1
= addr
[2] << 8 | addr
[3];
2310 u16 reg2
= addr
[0] << 8 | addr
[1];
2312 if (index
>= niu_num_alt_addr(np
))
2315 if (np
->flags
& NIU_FLAGS_XMAC
) {
2316 nw64_mac(XMAC_ALT_ADDR0(index
), reg0
);
2317 nw64_mac(XMAC_ALT_ADDR1(index
), reg1
);
2318 nw64_mac(XMAC_ALT_ADDR2(index
), reg2
);
2320 nw64_mac(BMAC_ALT_ADDR0(index
), reg0
);
2321 nw64_mac(BMAC_ALT_ADDR1(index
), reg1
);
2322 nw64_mac(BMAC_ALT_ADDR2(index
), reg2
);
2328 static int niu_enable_alt_mac(struct niu
*np
, int index
, int on
)
2333 if (index
>= niu_num_alt_addr(np
))
2336 if (np
->flags
& NIU_FLAGS_XMAC
) {
2337 reg
= XMAC_ADDR_CMPEN
;
2340 reg
= BMAC_ADDR_CMPEN
;
2341 mask
= 1 << (index
+ 1);
2344 val
= nr64_mac(reg
);
2354 static void __set_rdc_table_num_hw(struct niu
*np
, unsigned long reg
,
2355 int num
, int mac_pref
)
2357 u64 val
= nr64_mac(reg
);
2358 val
&= ~(HOST_INFO_MACRDCTBLN
| HOST_INFO_MPR
);
2361 val
|= HOST_INFO_MPR
;
2365 static int __set_rdc_table_num(struct niu
*np
,
2366 int xmac_index
, int bmac_index
,
2367 int rdc_table_num
, int mac_pref
)
2371 if (rdc_table_num
& ~HOST_INFO_MACRDCTBLN
)
2373 if (np
->flags
& NIU_FLAGS_XMAC
)
2374 reg
= XMAC_HOST_INFO(xmac_index
);
2376 reg
= BMAC_HOST_INFO(bmac_index
);
2377 __set_rdc_table_num_hw(np
, reg
, rdc_table_num
, mac_pref
);
2381 static int niu_set_primary_mac_rdc_table(struct niu
*np
, int table_num
,
2384 return __set_rdc_table_num(np
, 17, 0, table_num
, mac_pref
);
2387 static int niu_set_multicast_mac_rdc_table(struct niu
*np
, int table_num
,
2390 return __set_rdc_table_num(np
, 16, 8, table_num
, mac_pref
);
2393 static int niu_set_alt_mac_rdc_table(struct niu
*np
, int idx
,
2394 int table_num
, int mac_pref
)
2396 if (idx
>= niu_num_alt_addr(np
))
2398 return __set_rdc_table_num(np
, idx
, idx
+ 1, table_num
, mac_pref
);
2401 static u64
vlan_entry_set_parity(u64 reg_val
)
2406 port01_mask
= 0x00ff;
2407 port23_mask
= 0xff00;
2409 if (hweight64(reg_val
& port01_mask
) & 1)
2410 reg_val
|= ENET_VLAN_TBL_PARITY0
;
2412 reg_val
&= ~ENET_VLAN_TBL_PARITY0
;
2414 if (hweight64(reg_val
& port23_mask
) & 1)
2415 reg_val
|= ENET_VLAN_TBL_PARITY1
;
2417 reg_val
&= ~ENET_VLAN_TBL_PARITY1
;
2422 static void vlan_tbl_write(struct niu
*np
, unsigned long index
,
2423 int port
, int vpr
, int rdc_table
)
2425 u64 reg_val
= nr64(ENET_VLAN_TBL(index
));
2427 reg_val
&= ~((ENET_VLAN_TBL_VPR
|
2428 ENET_VLAN_TBL_VLANRDCTBLN
) <<
2429 ENET_VLAN_TBL_SHIFT(port
));
2431 reg_val
|= (ENET_VLAN_TBL_VPR
<<
2432 ENET_VLAN_TBL_SHIFT(port
));
2433 reg_val
|= (rdc_table
<< ENET_VLAN_TBL_SHIFT(port
));
2435 reg_val
= vlan_entry_set_parity(reg_val
);
2437 nw64(ENET_VLAN_TBL(index
), reg_val
);
2440 static void vlan_tbl_clear(struct niu
*np
)
2444 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++)
2445 nw64(ENET_VLAN_TBL(i
), 0);
2448 static int tcam_wait_bit(struct niu
*np
, u64 bit
)
2452 while (--limit
> 0) {
2453 if (nr64(TCAM_CTL
) & bit
)
2463 static int tcam_flush(struct niu
*np
, int index
)
2465 nw64(TCAM_KEY_0
, 0x00);
2466 nw64(TCAM_KEY_MASK_0
, 0xff);
2467 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2469 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2473 static int tcam_read(struct niu
*np
, int index
,
2474 u64
*key
, u64
*mask
)
2478 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_READ
| index
));
2479 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2481 key
[0] = nr64(TCAM_KEY_0
);
2482 key
[1] = nr64(TCAM_KEY_1
);
2483 key
[2] = nr64(TCAM_KEY_2
);
2484 key
[3] = nr64(TCAM_KEY_3
);
2485 mask
[0] = nr64(TCAM_KEY_MASK_0
);
2486 mask
[1] = nr64(TCAM_KEY_MASK_1
);
2487 mask
[2] = nr64(TCAM_KEY_MASK_2
);
2488 mask
[3] = nr64(TCAM_KEY_MASK_3
);
2494 static int tcam_write(struct niu
*np
, int index
,
2495 u64
*key
, u64
*mask
)
2497 nw64(TCAM_KEY_0
, key
[0]);
2498 nw64(TCAM_KEY_1
, key
[1]);
2499 nw64(TCAM_KEY_2
, key
[2]);
2500 nw64(TCAM_KEY_3
, key
[3]);
2501 nw64(TCAM_KEY_MASK_0
, mask
[0]);
2502 nw64(TCAM_KEY_MASK_1
, mask
[1]);
2503 nw64(TCAM_KEY_MASK_2
, mask
[2]);
2504 nw64(TCAM_KEY_MASK_3
, mask
[3]);
2505 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2507 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2511 static int tcam_assoc_read(struct niu
*np
, int index
, u64
*data
)
2515 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_READ
| index
));
2516 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2518 *data
= nr64(TCAM_KEY_1
);
2524 static int tcam_assoc_write(struct niu
*np
, int index
, u64 assoc_data
)
2526 nw64(TCAM_KEY_1
, assoc_data
);
2527 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_WRITE
| index
));
2529 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2532 static void tcam_enable(struct niu
*np
, int on
)
2534 u64 val
= nr64(FFLP_CFG_1
);
2537 val
&= ~FFLP_CFG_1_TCAM_DIS
;
2539 val
|= FFLP_CFG_1_TCAM_DIS
;
2540 nw64(FFLP_CFG_1
, val
);
2543 static void tcam_set_lat_and_ratio(struct niu
*np
, u64 latency
, u64 ratio
)
2545 u64 val
= nr64(FFLP_CFG_1
);
2547 val
&= ~(FFLP_CFG_1_FFLPINITDONE
|
2549 FFLP_CFG_1_CAMRATIO
);
2550 val
|= (latency
<< FFLP_CFG_1_CAMLAT_SHIFT
);
2551 val
|= (ratio
<< FFLP_CFG_1_CAMRATIO_SHIFT
);
2552 nw64(FFLP_CFG_1
, val
);
2554 val
= nr64(FFLP_CFG_1
);
2555 val
|= FFLP_CFG_1_FFLPINITDONE
;
2556 nw64(FFLP_CFG_1
, val
);
2559 static int tcam_user_eth_class_enable(struct niu
*np
, unsigned long class,
2565 if (class < CLASS_CODE_ETHERTYPE1
||
2566 class > CLASS_CODE_ETHERTYPE2
)
2569 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2581 static int tcam_user_eth_class_set(struct niu
*np
, unsigned long class,
2587 if (class < CLASS_CODE_ETHERTYPE1
||
2588 class > CLASS_CODE_ETHERTYPE2
||
2589 (ether_type
& ~(u64
)0xffff) != 0)
2592 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2594 val
&= ~L2_CLS_ETYPE
;
2595 val
|= (ether_type
<< L2_CLS_ETYPE_SHIFT
);
2602 static int tcam_user_ip_class_enable(struct niu
*np
, unsigned long class,
2608 if (class < CLASS_CODE_USER_PROG1
||
2609 class > CLASS_CODE_USER_PROG4
)
2612 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
2615 val
|= L3_CLS_VALID
;
2617 val
&= ~L3_CLS_VALID
;
2624 static int tcam_user_ip_class_set(struct niu
*np
, unsigned long class,
2625 int ipv6
, u64 protocol_id
,
2626 u64 tos_mask
, u64 tos_val
)
2631 if (class < CLASS_CODE_USER_PROG1
||
2632 class > CLASS_CODE_USER_PROG4
||
2633 (protocol_id
& ~(u64
)0xff) != 0 ||
2634 (tos_mask
& ~(u64
)0xff) != 0 ||
2635 (tos_val
& ~(u64
)0xff) != 0)
2638 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
2640 val
&= ~(L3_CLS_IPVER
| L3_CLS_PID
|
2641 L3_CLS_TOSMASK
| L3_CLS_TOS
);
2643 val
|= L3_CLS_IPVER
;
2644 val
|= (protocol_id
<< L3_CLS_PID_SHIFT
);
2645 val
|= (tos_mask
<< L3_CLS_TOSMASK_SHIFT
);
2646 val
|= (tos_val
<< L3_CLS_TOS_SHIFT
);
2653 static int tcam_early_init(struct niu
*np
)
2659 tcam_set_lat_and_ratio(np
,
2660 DEFAULT_TCAM_LATENCY
,
2661 DEFAULT_TCAM_ACCESS_RATIO
);
2662 for (i
= CLASS_CODE_ETHERTYPE1
; i
<= CLASS_CODE_ETHERTYPE2
; i
++) {
2663 err
= tcam_user_eth_class_enable(np
, i
, 0);
2667 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_USER_PROG4
; i
++) {
2668 err
= tcam_user_ip_class_enable(np
, i
, 0);
2676 static int tcam_flush_all(struct niu
*np
)
2680 for (i
= 0; i
< np
->parent
->tcam_num_entries
; i
++) {
2681 int err
= tcam_flush(np
, i
);
2688 static u64
hash_addr_regval(unsigned long index
, unsigned long num_entries
)
2690 return ((u64
)index
| (num_entries
== 1 ?
2691 HASH_TBL_ADDR_AUTOINC
: 0));
2695 static int hash_read(struct niu
*np
, unsigned long partition
,
2696 unsigned long index
, unsigned long num_entries
,
2699 u64 val
= hash_addr_regval(index
, num_entries
);
2702 if (partition
>= FCRAM_NUM_PARTITIONS
||
2703 index
+ num_entries
> FCRAM_SIZE
)
2706 nw64(HASH_TBL_ADDR(partition
), val
);
2707 for (i
= 0; i
< num_entries
; i
++)
2708 data
[i
] = nr64(HASH_TBL_DATA(partition
));
2714 static int hash_write(struct niu
*np
, unsigned long partition
,
2715 unsigned long index
, unsigned long num_entries
,
2718 u64 val
= hash_addr_regval(index
, num_entries
);
2721 if (partition
>= FCRAM_NUM_PARTITIONS
||
2722 index
+ (num_entries
* 8) > FCRAM_SIZE
)
2725 nw64(HASH_TBL_ADDR(partition
), val
);
2726 for (i
= 0; i
< num_entries
; i
++)
2727 nw64(HASH_TBL_DATA(partition
), data
[i
]);
2732 static void fflp_reset(struct niu
*np
)
2736 nw64(FFLP_CFG_1
, FFLP_CFG_1_PIO_FIO_RST
);
2738 nw64(FFLP_CFG_1
, 0);
2740 val
= FFLP_CFG_1_FCRAMOUTDR_NORMAL
| FFLP_CFG_1_FFLPINITDONE
;
2741 nw64(FFLP_CFG_1
, val
);
2744 static void fflp_set_timings(struct niu
*np
)
2746 u64 val
= nr64(FFLP_CFG_1
);
2748 val
&= ~FFLP_CFG_1_FFLPINITDONE
;
2749 val
|= (DEFAULT_FCRAMRATIO
<< FFLP_CFG_1_FCRAMRATIO_SHIFT
);
2750 nw64(FFLP_CFG_1
, val
);
2752 val
= nr64(FFLP_CFG_1
);
2753 val
|= FFLP_CFG_1_FFLPINITDONE
;
2754 nw64(FFLP_CFG_1
, val
);
2756 val
= nr64(FCRAM_REF_TMR
);
2757 val
&= ~(FCRAM_REF_TMR_MAX
| FCRAM_REF_TMR_MIN
);
2758 val
|= (DEFAULT_FCRAM_REFRESH_MAX
<< FCRAM_REF_TMR_MAX_SHIFT
);
2759 val
|= (DEFAULT_FCRAM_REFRESH_MIN
<< FCRAM_REF_TMR_MIN_SHIFT
);
2760 nw64(FCRAM_REF_TMR
, val
);
2763 static int fflp_set_partition(struct niu
*np
, u64 partition
,
2764 u64 mask
, u64 base
, int enable
)
2769 if (partition
>= FCRAM_NUM_PARTITIONS
||
2770 (mask
& ~(u64
)0x1f) != 0 ||
2771 (base
& ~(u64
)0x1f) != 0)
2774 reg
= FLW_PRT_SEL(partition
);
2777 val
&= ~(FLW_PRT_SEL_EXT
| FLW_PRT_SEL_MASK
| FLW_PRT_SEL_BASE
);
2778 val
|= (mask
<< FLW_PRT_SEL_MASK_SHIFT
);
2779 val
|= (base
<< FLW_PRT_SEL_BASE_SHIFT
);
2781 val
|= FLW_PRT_SEL_EXT
;
2787 static int fflp_disable_all_partitions(struct niu
*np
)
2791 for (i
= 0; i
< FCRAM_NUM_PARTITIONS
; i
++) {
2792 int err
= fflp_set_partition(np
, 0, 0, 0, 0);
2799 static void fflp_llcsnap_enable(struct niu
*np
, int on
)
2801 u64 val
= nr64(FFLP_CFG_1
);
2804 val
|= FFLP_CFG_1_LLCSNAP
;
2806 val
&= ~FFLP_CFG_1_LLCSNAP
;
2807 nw64(FFLP_CFG_1
, val
);
2810 static void fflp_errors_enable(struct niu
*np
, int on
)
2812 u64 val
= nr64(FFLP_CFG_1
);
2815 val
&= ~FFLP_CFG_1_ERRORDIS
;
2817 val
|= FFLP_CFG_1_ERRORDIS
;
2818 nw64(FFLP_CFG_1
, val
);
2821 static int fflp_hash_clear(struct niu
*np
)
2823 struct fcram_hash_ipv4 ent
;
2826 /* IPV4 hash entry with valid bit clear, rest is don't care. */
2827 memset(&ent
, 0, sizeof(ent
));
2828 ent
.header
= HASH_HEADER_EXT
;
2830 for (i
= 0; i
< FCRAM_SIZE
; i
+= sizeof(ent
)) {
2831 int err
= hash_write(np
, 0, i
, 1, (u64
*) &ent
);
2838 static int fflp_early_init(struct niu
*np
)
2840 struct niu_parent
*parent
;
2841 unsigned long flags
;
2844 niu_lock_parent(np
, flags
);
2846 parent
= np
->parent
;
2848 if (!(parent
->flags
& PARENT_FLGS_CLS_HWINIT
)) {
2849 niudbg(PROBE
, "fflp_early_init: Initting hw on port %u\n",
2851 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
2853 fflp_set_timings(np
);
2854 err
= fflp_disable_all_partitions(np
);
2856 niudbg(PROBE
, "fflp_disable_all_partitions "
2857 "failed, err=%d\n", err
);
2862 err
= tcam_early_init(np
);
2864 niudbg(PROBE
, "tcam_early_init failed, err=%d\n",
2868 fflp_llcsnap_enable(np
, 1);
2869 fflp_errors_enable(np
, 0);
2873 err
= tcam_flush_all(np
);
2875 niudbg(PROBE
, "tcam_flush_all failed, err=%d\n",
2879 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
2880 err
= fflp_hash_clear(np
);
2882 niudbg(PROBE
, "fflp_hash_clear failed, "
2890 niudbg(PROBE
, "fflp_early_init: Success\n");
2891 parent
->flags
|= PARENT_FLGS_CLS_HWINIT
;
2894 niu_unlock_parent(np
, flags
);
2898 static int niu_set_flow_key(struct niu
*np
, unsigned long class_code
, u64 key
)
2900 if (class_code
< CLASS_CODE_USER_PROG1
||
2901 class_code
> CLASS_CODE_SCTP_IPV6
)
2904 nw64(FLOW_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
2908 static int niu_set_tcam_key(struct niu
*np
, unsigned long class_code
, u64 key
)
2910 if (class_code
< CLASS_CODE_USER_PROG1
||
2911 class_code
> CLASS_CODE_SCTP_IPV6
)
2914 nw64(TCAM_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
2918 static void niu_rx_skb_append(struct sk_buff
*skb
, struct page
*page
,
2919 u32 offset
, u32 size
)
2921 int i
= skb_shinfo(skb
)->nr_frags
;
2922 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2925 frag
->page_offset
= offset
;
2929 skb
->data_len
+= size
;
2930 skb
->truesize
+= size
;
2932 skb_shinfo(skb
)->nr_frags
= i
+ 1;
2935 static unsigned int niu_hash_rxaddr(struct rx_ring_info
*rp
, u64 a
)
2938 a
^= (a
>> ilog2(MAX_RBR_RING_SIZE
));
2940 return (a
& (MAX_RBR_RING_SIZE
- 1));
2943 static struct page
*niu_find_rxpage(struct rx_ring_info
*rp
, u64 addr
,
2944 struct page
***link
)
2946 unsigned int h
= niu_hash_rxaddr(rp
, addr
);
2947 struct page
*p
, **pp
;
2950 pp
= &rp
->rxhash
[h
];
2951 for (; (p
= *pp
) != NULL
; pp
= (struct page
**) &p
->mapping
) {
2952 if (p
->index
== addr
) {
2961 static void niu_hash_page(struct rx_ring_info
*rp
, struct page
*page
, u64 base
)
2963 unsigned int h
= niu_hash_rxaddr(rp
, base
);
2966 page
->mapping
= (struct address_space
*) rp
->rxhash
[h
];
2967 rp
->rxhash
[h
] = page
;
2970 static int niu_rbr_add_page(struct niu
*np
, struct rx_ring_info
*rp
,
2971 gfp_t mask
, int start_index
)
2977 page
= alloc_page(mask
);
2981 addr
= np
->ops
->map_page(np
->device
, page
, 0,
2982 PAGE_SIZE
, DMA_FROM_DEVICE
);
2984 niu_hash_page(rp
, page
, addr
);
2985 if (rp
->rbr_blocks_per_page
> 1)
2986 atomic_add(rp
->rbr_blocks_per_page
- 1,
2987 &compound_head(page
)->_count
);
2989 for (i
= 0; i
< rp
->rbr_blocks_per_page
; i
++) {
2990 __le32
*rbr
= &rp
->rbr
[start_index
+ i
];
2992 *rbr
= cpu_to_le32(addr
>> RBR_DESCR_ADDR_SHIFT
);
2993 addr
+= rp
->rbr_block_size
;
2999 static void niu_rbr_refill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3001 int index
= rp
->rbr_index
;
3004 if ((rp
->rbr_pending
% rp
->rbr_blocks_per_page
) == 0) {
3005 int err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3007 if (unlikely(err
)) {
3012 rp
->rbr_index
+= rp
->rbr_blocks_per_page
;
3013 BUG_ON(rp
->rbr_index
> rp
->rbr_table_size
);
3014 if (rp
->rbr_index
== rp
->rbr_table_size
)
3017 if (rp
->rbr_pending
>= rp
->rbr_kick_thresh
) {
3018 nw64(RBR_KICK(rp
->rx_channel
), rp
->rbr_pending
);
3019 rp
->rbr_pending
= 0;
3024 static int niu_rx_pkt_ignore(struct niu
*np
, struct rx_ring_info
*rp
)
3026 unsigned int index
= rp
->rcr_index
;
3031 struct page
*page
, **link
;
3037 val
= le64_to_cpup(&rp
->rcr
[index
]);
3038 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3039 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3040 page
= niu_find_rxpage(rp
, addr
, &link
);
3042 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3043 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3044 if ((page
->index
+ PAGE_SIZE
) - rcr_size
== addr
) {
3045 *link
= (struct page
*) page
->mapping
;
3046 np
->ops
->unmap_page(np
->device
, page
->index
,
3047 PAGE_SIZE
, DMA_FROM_DEVICE
);
3049 page
->mapping
= NULL
;
3051 rp
->rbr_refill_pending
++;
3054 index
= NEXT_RCR(rp
, index
);
3055 if (!(val
& RCR_ENTRY_MULTI
))
3059 rp
->rcr_index
= index
;
3064 static int niu_process_rx_pkt(struct niu
*np
, struct rx_ring_info
*rp
)
3066 unsigned int index
= rp
->rcr_index
;
3067 struct sk_buff
*skb
;
3070 skb
= netdev_alloc_skb(np
->dev
, RX_SKB_ALLOC_SIZE
);
3072 return niu_rx_pkt_ignore(np
, rp
);
3076 struct page
*page
, **link
;
3077 u32 rcr_size
, append_size
;
3082 val
= le64_to_cpup(&rp
->rcr
[index
]);
3084 len
= (val
& RCR_ENTRY_L2_LEN
) >>
3085 RCR_ENTRY_L2_LEN_SHIFT
;
3088 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3089 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3090 page
= niu_find_rxpage(rp
, addr
, &link
);
3092 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3093 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3095 off
= addr
& ~PAGE_MASK
;
3096 append_size
= rcr_size
;
3103 ptype
= (val
>> RCR_ENTRY_PKT_TYPE_SHIFT
);
3104 if ((ptype
== RCR_PKT_TYPE_TCP
||
3105 ptype
== RCR_PKT_TYPE_UDP
) &&
3106 !(val
& (RCR_ENTRY_NOPORT
|
3108 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3110 skb
->ip_summed
= CHECKSUM_NONE
;
3112 if (!(val
& RCR_ENTRY_MULTI
))
3113 append_size
= len
- skb
->len
;
3115 niu_rx_skb_append(skb
, page
, off
, append_size
);
3116 if ((page
->index
+ rp
->rbr_block_size
) - rcr_size
== addr
) {
3117 *link
= (struct page
*) page
->mapping
;
3118 np
->ops
->unmap_page(np
->device
, page
->index
,
3119 PAGE_SIZE
, DMA_FROM_DEVICE
);
3121 page
->mapping
= NULL
;
3122 rp
->rbr_refill_pending
++;
3126 index
= NEXT_RCR(rp
, index
);
3127 if (!(val
& RCR_ENTRY_MULTI
))
3131 rp
->rcr_index
= index
;
3133 skb_reserve(skb
, NET_IP_ALIGN
);
3134 __pskb_pull_tail(skb
, min(len
, NIU_RXPULL_MAX
));
3137 rp
->rx_bytes
+= skb
->len
;
3139 skb
->protocol
= eth_type_trans(skb
, np
->dev
);
3140 netif_receive_skb(skb
);
3145 static int niu_rbr_fill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3147 int blocks_per_page
= rp
->rbr_blocks_per_page
;
3148 int err
, index
= rp
->rbr_index
;
3151 while (index
< (rp
->rbr_table_size
- blocks_per_page
)) {
3152 err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3156 index
+= blocks_per_page
;
3159 rp
->rbr_index
= index
;
3163 static void niu_rbr_free(struct niu
*np
, struct rx_ring_info
*rp
)
3167 for (i
= 0; i
< MAX_RBR_RING_SIZE
; i
++) {
3170 page
= rp
->rxhash
[i
];
3172 struct page
*next
= (struct page
*) page
->mapping
;
3173 u64 base
= page
->index
;
3175 np
->ops
->unmap_page(np
->device
, base
, PAGE_SIZE
,
3178 page
->mapping
= NULL
;
3186 for (i
= 0; i
< rp
->rbr_table_size
; i
++)
3187 rp
->rbr
[i
] = cpu_to_le32(0);
3191 static int release_tx_packet(struct niu
*np
, struct tx_ring_info
*rp
, int idx
)
3193 struct tx_buff_info
*tb
= &rp
->tx_buffs
[idx
];
3194 struct sk_buff
*skb
= tb
->skb
;
3195 struct tx_pkt_hdr
*tp
;
3199 tp
= (struct tx_pkt_hdr
*) skb
->data
;
3200 tx_flags
= le64_to_cpup(&tp
->flags
);
3203 rp
->tx_bytes
+= (((tx_flags
& TXHDR_LEN
) >> TXHDR_LEN_SHIFT
) -
3204 ((tx_flags
& TXHDR_PAD
) / 2));
3206 len
= skb_headlen(skb
);
3207 np
->ops
->unmap_single(np
->device
, tb
->mapping
,
3208 len
, DMA_TO_DEVICE
);
3210 if (le64_to_cpu(rp
->descr
[idx
]) & TX_DESC_MARK
)
3215 idx
= NEXT_TX(rp
, idx
);
3216 len
-= MAX_TX_DESC_LEN
;
3219 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
3220 tb
= &rp
->tx_buffs
[idx
];
3221 BUG_ON(tb
->skb
!= NULL
);
3222 np
->ops
->unmap_page(np
->device
, tb
->mapping
,
3223 skb_shinfo(skb
)->frags
[i
].size
,
3225 idx
= NEXT_TX(rp
, idx
);
3233 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3235 static void niu_tx_work(struct niu
*np
, struct tx_ring_info
*rp
)
3237 struct netdev_queue
*txq
;
3242 index
= (rp
- np
->tx_rings
);
3243 txq
= netdev_get_tx_queue(np
->dev
, index
);
3246 if (unlikely(!(cs
& (TX_CS_MK
| TX_CS_MMK
))))
3249 tmp
= pkt_cnt
= (cs
& TX_CS_PKT_CNT
) >> TX_CS_PKT_CNT_SHIFT
;
3250 pkt_cnt
= (pkt_cnt
- rp
->last_pkt_cnt
) &
3251 (TX_CS_PKT_CNT
>> TX_CS_PKT_CNT_SHIFT
);
3253 rp
->last_pkt_cnt
= tmp
;
3257 niudbg(TX_DONE
, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3258 np
->dev
->name
, pkt_cnt
, cons
);
3261 cons
= release_tx_packet(np
, rp
, cons
);
3267 if (unlikely(netif_tx_queue_stopped(txq
) &&
3268 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))) {
3269 __netif_tx_lock(txq
, smp_processor_id());
3270 if (netif_tx_queue_stopped(txq
) &&
3271 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))
3272 netif_tx_wake_queue(txq
);
3273 __netif_tx_unlock(txq
);
3277 static int niu_rx_work(struct niu
*np
, struct rx_ring_info
*rp
, int budget
)
3279 int qlen
, rcr_done
= 0, work_done
= 0;
3280 struct rxdma_mailbox
*mbox
= rp
->mbox
;
3284 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3285 qlen
= nr64(RCRSTAT_A(rp
->rx_channel
)) & RCRSTAT_A_QLEN
;
3287 stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
3288 qlen
= (le64_to_cpup(&mbox
->rcrstat_a
) & RCRSTAT_A_QLEN
);
3290 mbox
->rx_dma_ctl_stat
= 0;
3291 mbox
->rcrstat_a
= 0;
3293 niudbg(RX_STATUS
, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3294 np
->dev
->name
, rp
->rx_channel
, (unsigned long long) stat
, qlen
);
3296 rcr_done
= work_done
= 0;
3297 qlen
= min(qlen
, budget
);
3298 while (work_done
< qlen
) {
3299 rcr_done
+= niu_process_rx_pkt(np
, rp
);
3303 if (rp
->rbr_refill_pending
>= rp
->rbr_kick_thresh
) {
3306 for (i
= 0; i
< rp
->rbr_refill_pending
; i
++)
3307 niu_rbr_refill(np
, rp
, GFP_ATOMIC
);
3308 rp
->rbr_refill_pending
= 0;
3311 stat
= (RX_DMA_CTL_STAT_MEX
|
3312 ((u64
)work_done
<< RX_DMA_CTL_STAT_PKTREAD_SHIFT
) |
3313 ((u64
)rcr_done
<< RX_DMA_CTL_STAT_PTRREAD_SHIFT
));
3315 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat
);
3320 static int niu_poll_core(struct niu
*np
, struct niu_ldg
*lp
, int budget
)
3323 u32 tx_vec
= (v0
>> 32);
3324 u32 rx_vec
= (v0
& 0xffffffff);
3325 int i
, work_done
= 0;
3327 niudbg(INTR
, "%s: niu_poll_core() v0[%016llx]\n",
3328 np
->dev
->name
, (unsigned long long) v0
);
3330 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
3331 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
3332 if (tx_vec
& (1 << rp
->tx_channel
))
3333 niu_tx_work(np
, rp
);
3334 nw64(LD_IM0(LDN_TXDMA(rp
->tx_channel
)), 0);
3337 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
3338 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
3340 if (rx_vec
& (1 << rp
->rx_channel
)) {
3343 this_work_done
= niu_rx_work(np
, rp
,
3346 budget
-= this_work_done
;
3347 work_done
+= this_work_done
;
3349 nw64(LD_IM0(LDN_RXDMA(rp
->rx_channel
)), 0);
3355 static int niu_poll(struct napi_struct
*napi
, int budget
)
3357 struct niu_ldg
*lp
= container_of(napi
, struct niu_ldg
, napi
);
3358 struct niu
*np
= lp
->np
;
3361 work_done
= niu_poll_core(np
, lp
, budget
);
3363 if (work_done
< budget
) {
3364 netif_rx_complete(np
->dev
, napi
);
3365 niu_ldg_rearm(np
, lp
, 1);
3370 static void niu_log_rxchan_errors(struct niu
*np
, struct rx_ring_info
*rp
,
3373 dev_err(np
->device
, PFX
"%s: RX channel %u errors ( ",
3374 np
->dev
->name
, rp
->rx_channel
);
3376 if (stat
& RX_DMA_CTL_STAT_RBR_TMOUT
)
3377 printk("RBR_TMOUT ");
3378 if (stat
& RX_DMA_CTL_STAT_RSP_CNT_ERR
)
3380 if (stat
& RX_DMA_CTL_STAT_BYTE_EN_BUS
)
3381 printk("BYTE_EN_BUS ");
3382 if (stat
& RX_DMA_CTL_STAT_RSP_DAT_ERR
)
3384 if (stat
& RX_DMA_CTL_STAT_RCR_ACK_ERR
)
3386 if (stat
& RX_DMA_CTL_STAT_RCR_SHA_PAR
)
3387 printk("RCR_SHA_PAR ");
3388 if (stat
& RX_DMA_CTL_STAT_RBR_PRE_PAR
)
3389 printk("RBR_PRE_PAR ");
3390 if (stat
& RX_DMA_CTL_STAT_CONFIG_ERR
)
3392 if (stat
& RX_DMA_CTL_STAT_RCRINCON
)
3393 printk("RCRINCON ");
3394 if (stat
& RX_DMA_CTL_STAT_RCRFULL
)
3396 if (stat
& RX_DMA_CTL_STAT_RBRFULL
)
3398 if (stat
& RX_DMA_CTL_STAT_RBRLOGPAGE
)
3399 printk("RBRLOGPAGE ");
3400 if (stat
& RX_DMA_CTL_STAT_CFIGLOGPAGE
)
3401 printk("CFIGLOGPAGE ");
3402 if (stat
& RX_DMA_CTL_STAT_DC_FIFO_ERR
)
3408 static int niu_rx_error(struct niu
*np
, struct rx_ring_info
*rp
)
3410 u64 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3414 if (stat
& (RX_DMA_CTL_STAT_CHAN_FATAL
|
3415 RX_DMA_CTL_STAT_PORT_FATAL
))
3419 dev_err(np
->device
, PFX
"%s: RX channel %u error, stat[%llx]\n",
3420 np
->dev
->name
, rp
->rx_channel
,
3421 (unsigned long long) stat
);
3423 niu_log_rxchan_errors(np
, rp
, stat
);
3426 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
3427 stat
& RX_DMA_CTL_WRITE_CLEAR_ERRS
);
3432 static void niu_log_txchan_errors(struct niu
*np
, struct tx_ring_info
*rp
,
3435 dev_err(np
->device
, PFX
"%s: TX channel %u errors ( ",
3436 np
->dev
->name
, rp
->tx_channel
);
3438 if (cs
& TX_CS_MBOX_ERR
)
3440 if (cs
& TX_CS_PKT_SIZE_ERR
)
3441 printk("PKT_SIZE ");
3442 if (cs
& TX_CS_TX_RING_OFLOW
)
3443 printk("TX_RING_OFLOW ");
3444 if (cs
& TX_CS_PREF_BUF_PAR_ERR
)
3445 printk("PREF_BUF_PAR ");
3446 if (cs
& TX_CS_NACK_PREF
)
3447 printk("NACK_PREF ");
3448 if (cs
& TX_CS_NACK_PKT_RD
)
3449 printk("NACK_PKT_RD ");
3450 if (cs
& TX_CS_CONF_PART_ERR
)
3451 printk("CONF_PART ");
3452 if (cs
& TX_CS_PKT_PRT_ERR
)
3458 static int niu_tx_error(struct niu
*np
, struct tx_ring_info
*rp
)
3462 cs
= nr64(TX_CS(rp
->tx_channel
));
3463 logh
= nr64(TX_RNG_ERR_LOGH(rp
->tx_channel
));
3464 logl
= nr64(TX_RNG_ERR_LOGL(rp
->tx_channel
));
3466 dev_err(np
->device
, PFX
"%s: TX channel %u error, "
3467 "cs[%llx] logh[%llx] logl[%llx]\n",
3468 np
->dev
->name
, rp
->tx_channel
,
3469 (unsigned long long) cs
,
3470 (unsigned long long) logh
,
3471 (unsigned long long) logl
);
3473 niu_log_txchan_errors(np
, rp
, cs
);
3478 static int niu_mif_interrupt(struct niu
*np
)
3480 u64 mif_status
= nr64(MIF_STATUS
);
3483 if (np
->flags
& NIU_FLAGS_XMAC
) {
3484 u64 xrxmac_stat
= nr64_mac(XRXMAC_STATUS
);
3486 if (xrxmac_stat
& XRXMAC_STATUS_PHY_MDINT
)
3490 dev_err(np
->device
, PFX
"%s: MIF interrupt, "
3491 "stat[%llx] phy_mdint(%d)\n",
3492 np
->dev
->name
, (unsigned long long) mif_status
, phy_mdint
);
3497 static void niu_xmac_interrupt(struct niu
*np
)
3499 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
3502 val
= nr64_mac(XTXMAC_STATUS
);
3503 if (val
& XTXMAC_STATUS_FRAME_CNT_EXP
)
3504 mp
->tx_frames
+= TXMAC_FRM_CNT_COUNT
;
3505 if (val
& XTXMAC_STATUS_BYTE_CNT_EXP
)
3506 mp
->tx_bytes
+= TXMAC_BYTE_CNT_COUNT
;
3507 if (val
& XTXMAC_STATUS_TXFIFO_XFR_ERR
)
3508 mp
->tx_fifo_errors
++;
3509 if (val
& XTXMAC_STATUS_TXMAC_OFLOW
)
3510 mp
->tx_overflow_errors
++;
3511 if (val
& XTXMAC_STATUS_MAX_PSIZE_ERR
)
3512 mp
->tx_max_pkt_size_errors
++;
3513 if (val
& XTXMAC_STATUS_TXMAC_UFLOW
)
3514 mp
->tx_underflow_errors
++;
3516 val
= nr64_mac(XRXMAC_STATUS
);
3517 if (val
& XRXMAC_STATUS_LCL_FLT_STATUS
)
3518 mp
->rx_local_faults
++;
3519 if (val
& XRXMAC_STATUS_RFLT_DET
)
3520 mp
->rx_remote_faults
++;
3521 if (val
& XRXMAC_STATUS_LFLT_CNT_EXP
)
3522 mp
->rx_link_faults
+= LINK_FAULT_CNT_COUNT
;
3523 if (val
& XRXMAC_STATUS_ALIGNERR_CNT_EXP
)
3524 mp
->rx_align_errors
+= RXMAC_ALIGN_ERR_CNT_COUNT
;
3525 if (val
& XRXMAC_STATUS_RXFRAG_CNT_EXP
)
3526 mp
->rx_frags
+= RXMAC_FRAG_CNT_COUNT
;
3527 if (val
& XRXMAC_STATUS_RXMULTF_CNT_EXP
)
3528 mp
->rx_mcasts
+= RXMAC_MC_FRM_CNT_COUNT
;
3529 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
3530 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
3531 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
3532 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
3533 if (val
& XRXMAC_STATUS_RXHIST1_CNT_EXP
)
3534 mp
->rx_hist_cnt1
+= RXMAC_HIST_CNT1_COUNT
;
3535 if (val
& XRXMAC_STATUS_RXHIST2_CNT_EXP
)
3536 mp
->rx_hist_cnt2
+= RXMAC_HIST_CNT2_COUNT
;
3537 if (val
& XRXMAC_STATUS_RXHIST3_CNT_EXP
)
3538 mp
->rx_hist_cnt3
+= RXMAC_HIST_CNT3_COUNT
;
3539 if (val
& XRXMAC_STATUS_RXHIST4_CNT_EXP
)
3540 mp
->rx_hist_cnt4
+= RXMAC_HIST_CNT4_COUNT
;
3541 if (val
& XRXMAC_STATUS_RXHIST5_CNT_EXP
)
3542 mp
->rx_hist_cnt5
+= RXMAC_HIST_CNT5_COUNT
;
3543 if (val
& XRXMAC_STATUS_RXHIST6_CNT_EXP
)
3544 mp
->rx_hist_cnt6
+= RXMAC_HIST_CNT6_COUNT
;
3545 if (val
& XRXMAC_STATUS_RXHIST7_CNT_EXP
)
3546 mp
->rx_hist_cnt7
+= RXMAC_HIST_CNT7_COUNT
;
3547 if (val
& XRXMAC_STAT_MSK_RXOCTET_CNT_EXP
)
3548 mp
->rx_octets
+= RXMAC_BT_CNT_COUNT
;
3549 if (val
& XRXMAC_STATUS_CVIOLERR_CNT_EXP
)
3550 mp
->rx_code_violations
+= RXMAC_CD_VIO_CNT_COUNT
;
3551 if (val
& XRXMAC_STATUS_LENERR_CNT_EXP
)
3552 mp
->rx_len_errors
+= RXMAC_MPSZER_CNT_COUNT
;
3553 if (val
& XRXMAC_STATUS_CRCERR_CNT_EXP
)
3554 mp
->rx_crc_errors
+= RXMAC_CRC_ER_CNT_COUNT
;
3555 if (val
& XRXMAC_STATUS_RXUFLOW
)
3556 mp
->rx_underflows
++;
3557 if (val
& XRXMAC_STATUS_RXOFLOW
)
3560 val
= nr64_mac(XMAC_FC_STAT
);
3561 if (val
& XMAC_FC_STAT_TX_MAC_NPAUSE
)
3562 mp
->pause_off_state
++;
3563 if (val
& XMAC_FC_STAT_TX_MAC_PAUSE
)
3564 mp
->pause_on_state
++;
3565 if (val
& XMAC_FC_STAT_RX_MAC_RPAUSE
)
3566 mp
->pause_received
++;
3569 static void niu_bmac_interrupt(struct niu
*np
)
3571 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
3574 val
= nr64_mac(BTXMAC_STATUS
);
3575 if (val
& BTXMAC_STATUS_UNDERRUN
)
3576 mp
->tx_underflow_errors
++;
3577 if (val
& BTXMAC_STATUS_MAX_PKT_ERR
)
3578 mp
->tx_max_pkt_size_errors
++;
3579 if (val
& BTXMAC_STATUS_BYTE_CNT_EXP
)
3580 mp
->tx_bytes
+= BTXMAC_BYTE_CNT_COUNT
;
3581 if (val
& BTXMAC_STATUS_FRAME_CNT_EXP
)
3582 mp
->tx_frames
+= BTXMAC_FRM_CNT_COUNT
;
3584 val
= nr64_mac(BRXMAC_STATUS
);
3585 if (val
& BRXMAC_STATUS_OVERFLOW
)
3587 if (val
& BRXMAC_STATUS_FRAME_CNT_EXP
)
3588 mp
->rx_frames
+= BRXMAC_FRAME_CNT_COUNT
;
3589 if (val
& BRXMAC_STATUS_ALIGN_ERR_EXP
)
3590 mp
->rx_align_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
3591 if (val
& BRXMAC_STATUS_CRC_ERR_EXP
)
3592 mp
->rx_crc_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
3593 if (val
& BRXMAC_STATUS_LEN_ERR_EXP
)
3594 mp
->rx_len_errors
+= BRXMAC_CODE_VIOL_ERR_CNT_COUNT
;
3596 val
= nr64_mac(BMAC_CTRL_STATUS
);
3597 if (val
& BMAC_CTRL_STATUS_NOPAUSE
)
3598 mp
->pause_off_state
++;
3599 if (val
& BMAC_CTRL_STATUS_PAUSE
)
3600 mp
->pause_on_state
++;
3601 if (val
& BMAC_CTRL_STATUS_PAUSE_RECV
)
3602 mp
->pause_received
++;
3605 static int niu_mac_interrupt(struct niu
*np
)
3607 if (np
->flags
& NIU_FLAGS_XMAC
)
3608 niu_xmac_interrupt(np
);
3610 niu_bmac_interrupt(np
);
3615 static void niu_log_device_error(struct niu
*np
, u64 stat
)
3617 dev_err(np
->device
, PFX
"%s: Core device errors ( ",
3620 if (stat
& SYS_ERR_MASK_META2
)
3622 if (stat
& SYS_ERR_MASK_META1
)
3624 if (stat
& SYS_ERR_MASK_PEU
)
3626 if (stat
& SYS_ERR_MASK_TXC
)
3628 if (stat
& SYS_ERR_MASK_RDMC
)
3630 if (stat
& SYS_ERR_MASK_TDMC
)
3632 if (stat
& SYS_ERR_MASK_ZCP
)
3634 if (stat
& SYS_ERR_MASK_FFLP
)
3636 if (stat
& SYS_ERR_MASK_IPP
)
3638 if (stat
& SYS_ERR_MASK_MAC
)
3640 if (stat
& SYS_ERR_MASK_SMX
)
3646 static int niu_device_error(struct niu
*np
)
3648 u64 stat
= nr64(SYS_ERR_STAT
);
3650 dev_err(np
->device
, PFX
"%s: Core device error, stat[%llx]\n",
3651 np
->dev
->name
, (unsigned long long) stat
);
3653 niu_log_device_error(np
, stat
);
3658 static int niu_slowpath_interrupt(struct niu
*np
, struct niu_ldg
*lp
,
3659 u64 v0
, u64 v1
, u64 v2
)
3668 if (v1
& 0x00000000ffffffffULL
) {
3669 u32 rx_vec
= (v1
& 0xffffffff);
3671 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
3672 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
3674 if (rx_vec
& (1 << rp
->rx_channel
)) {
3675 int r
= niu_rx_error(np
, rp
);
3680 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
3681 RX_DMA_CTL_STAT_MEX
);
3686 if (v1
& 0x7fffffff00000000ULL
) {
3687 u32 tx_vec
= (v1
>> 32) & 0x7fffffff;
3689 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
3690 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
3692 if (tx_vec
& (1 << rp
->tx_channel
)) {
3693 int r
= niu_tx_error(np
, rp
);
3699 if ((v0
| v1
) & 0x8000000000000000ULL
) {
3700 int r
= niu_mif_interrupt(np
);
3706 int r
= niu_mac_interrupt(np
);
3711 int r
= niu_device_error(np
);
3718 niu_enable_interrupts(np
, 0);
3723 static void niu_rxchan_intr(struct niu
*np
, struct rx_ring_info
*rp
,
3726 struct rxdma_mailbox
*mbox
= rp
->mbox
;
3727 u64 stat_write
, stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
3729 stat_write
= (RX_DMA_CTL_STAT_RCRTHRES
|
3730 RX_DMA_CTL_STAT_RCRTO
);
3731 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat_write
);
3733 niudbg(INTR
, "%s: rxchan_intr stat[%llx]\n",
3734 np
->dev
->name
, (unsigned long long) stat
);
3737 static void niu_txchan_intr(struct niu
*np
, struct tx_ring_info
*rp
,
3740 rp
->tx_cs
= nr64(TX_CS(rp
->tx_channel
));
3742 niudbg(INTR
, "%s: txchan_intr cs[%llx]\n",
3743 np
->dev
->name
, (unsigned long long) rp
->tx_cs
);
3746 static void __niu_fastpath_interrupt(struct niu
*np
, int ldg
, u64 v0
)
3748 struct niu_parent
*parent
= np
->parent
;
3752 tx_vec
= (v0
>> 32);
3753 rx_vec
= (v0
& 0xffffffff);
3755 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
3756 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
3757 int ldn
= LDN_RXDMA(rp
->rx_channel
);
3759 if (parent
->ldg_map
[ldn
] != ldg
)
3762 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
3763 if (rx_vec
& (1 << rp
->rx_channel
))
3764 niu_rxchan_intr(np
, rp
, ldn
);
3767 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
3768 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
3769 int ldn
= LDN_TXDMA(rp
->tx_channel
);
3771 if (parent
->ldg_map
[ldn
] != ldg
)
3774 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
3775 if (tx_vec
& (1 << rp
->tx_channel
))
3776 niu_txchan_intr(np
, rp
, ldn
);
3780 static void niu_schedule_napi(struct niu
*np
, struct niu_ldg
*lp
,
3781 u64 v0
, u64 v1
, u64 v2
)
3783 if (likely(netif_rx_schedule_prep(np
->dev
, &lp
->napi
))) {
3787 __niu_fastpath_interrupt(np
, lp
->ldg_num
, v0
);
3788 __netif_rx_schedule(np
->dev
, &lp
->napi
);
3792 static irqreturn_t
niu_interrupt(int irq
, void *dev_id
)
3794 struct niu_ldg
*lp
= dev_id
;
3795 struct niu
*np
= lp
->np
;
3796 int ldg
= lp
->ldg_num
;
3797 unsigned long flags
;
3800 if (netif_msg_intr(np
))
3801 printk(KERN_DEBUG PFX
"niu_interrupt() ldg[%p](%d) ",
3804 spin_lock_irqsave(&np
->lock
, flags
);
3806 v0
= nr64(LDSV0(ldg
));
3807 v1
= nr64(LDSV1(ldg
));
3808 v2
= nr64(LDSV2(ldg
));
3810 if (netif_msg_intr(np
))
3811 printk("v0[%llx] v1[%llx] v2[%llx]\n",
3812 (unsigned long long) v0
,
3813 (unsigned long long) v1
,
3814 (unsigned long long) v2
);
3816 if (unlikely(!v0
&& !v1
&& !v2
)) {
3817 spin_unlock_irqrestore(&np
->lock
, flags
);
3821 if (unlikely((v0
& ((u64
)1 << LDN_MIF
)) || v1
|| v2
)) {
3822 int err
= niu_slowpath_interrupt(np
, lp
, v0
, v1
, v2
);
3826 if (likely(v0
& ~((u64
)1 << LDN_MIF
)))
3827 niu_schedule_napi(np
, lp
, v0
, v1
, v2
);
3829 niu_ldg_rearm(np
, lp
, 1);
3831 spin_unlock_irqrestore(&np
->lock
, flags
);
3836 static void niu_free_rx_ring_info(struct niu
*np
, struct rx_ring_info
*rp
)
3839 np
->ops
->free_coherent(np
->device
,
3840 sizeof(struct rxdma_mailbox
),
3841 rp
->mbox
, rp
->mbox_dma
);
3845 np
->ops
->free_coherent(np
->device
,
3846 MAX_RCR_RING_SIZE
* sizeof(__le64
),
3847 rp
->rcr
, rp
->rcr_dma
);
3849 rp
->rcr_table_size
= 0;
3853 niu_rbr_free(np
, rp
);
3855 np
->ops
->free_coherent(np
->device
,
3856 MAX_RBR_RING_SIZE
* sizeof(__le32
),
3857 rp
->rbr
, rp
->rbr_dma
);
3859 rp
->rbr_table_size
= 0;
3866 static void niu_free_tx_ring_info(struct niu
*np
, struct tx_ring_info
*rp
)
3869 np
->ops
->free_coherent(np
->device
,
3870 sizeof(struct txdma_mailbox
),
3871 rp
->mbox
, rp
->mbox_dma
);
3877 for (i
= 0; i
< MAX_TX_RING_SIZE
; i
++) {
3878 if (rp
->tx_buffs
[i
].skb
)
3879 (void) release_tx_packet(np
, rp
, i
);
3882 np
->ops
->free_coherent(np
->device
,
3883 MAX_TX_RING_SIZE
* sizeof(__le64
),
3884 rp
->descr
, rp
->descr_dma
);
3893 static void niu_free_channels(struct niu
*np
)
3898 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
3899 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
3901 niu_free_rx_ring_info(np
, rp
);
3903 kfree(np
->rx_rings
);
3904 np
->rx_rings
= NULL
;
3905 np
->num_rx_rings
= 0;
3909 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
3910 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
3912 niu_free_tx_ring_info(np
, rp
);
3914 kfree(np
->tx_rings
);
3915 np
->tx_rings
= NULL
;
3916 np
->num_tx_rings
= 0;
3920 static int niu_alloc_rx_ring_info(struct niu
*np
,
3921 struct rx_ring_info
*rp
)
3923 BUILD_BUG_ON(sizeof(struct rxdma_mailbox
) != 64);
3925 rp
->rxhash
= kzalloc(MAX_RBR_RING_SIZE
* sizeof(struct page
*),
3930 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
3931 sizeof(struct rxdma_mailbox
),
3932 &rp
->mbox_dma
, GFP_KERNEL
);
3935 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
3936 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
3937 "RXDMA mailbox %p\n", np
->dev
->name
, rp
->mbox
);
3941 rp
->rcr
= np
->ops
->alloc_coherent(np
->device
,
3942 MAX_RCR_RING_SIZE
* sizeof(__le64
),
3943 &rp
->rcr_dma
, GFP_KERNEL
);
3946 if ((unsigned long)rp
->rcr
& (64UL - 1)) {
3947 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
3948 "RXDMA RCR table %p\n", np
->dev
->name
, rp
->rcr
);
3951 rp
->rcr_table_size
= MAX_RCR_RING_SIZE
;
3954 rp
->rbr
= np
->ops
->alloc_coherent(np
->device
,
3955 MAX_RBR_RING_SIZE
* sizeof(__le32
),
3956 &rp
->rbr_dma
, GFP_KERNEL
);
3959 if ((unsigned long)rp
->rbr
& (64UL - 1)) {
3960 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
3961 "RXDMA RBR table %p\n", np
->dev
->name
, rp
->rbr
);
3964 rp
->rbr_table_size
= MAX_RBR_RING_SIZE
;
3966 rp
->rbr_pending
= 0;
3971 static void niu_set_max_burst(struct niu
*np
, struct tx_ring_info
*rp
)
3973 int mtu
= np
->dev
->mtu
;
3975 /* These values are recommended by the HW designers for fair
3976 * utilization of DRR amongst the rings.
3978 rp
->max_burst
= mtu
+ 32;
3979 if (rp
->max_burst
> 4096)
3980 rp
->max_burst
= 4096;
3983 static int niu_alloc_tx_ring_info(struct niu
*np
,
3984 struct tx_ring_info
*rp
)
3986 BUILD_BUG_ON(sizeof(struct txdma_mailbox
) != 64);
3988 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
3989 sizeof(struct txdma_mailbox
),
3990 &rp
->mbox_dma
, GFP_KERNEL
);
3993 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
3994 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
3995 "TXDMA mailbox %p\n", np
->dev
->name
, rp
->mbox
);
3999 rp
->descr
= np
->ops
->alloc_coherent(np
->device
,
4000 MAX_TX_RING_SIZE
* sizeof(__le64
),
4001 &rp
->descr_dma
, GFP_KERNEL
);
4004 if ((unsigned long)rp
->descr
& (64UL - 1)) {
4005 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
4006 "TXDMA descr table %p\n", np
->dev
->name
, rp
->descr
);
4010 rp
->pending
= MAX_TX_RING_SIZE
;
4015 /* XXX make these configurable... XXX */
4016 rp
->mark_freq
= rp
->pending
/ 4;
4018 niu_set_max_burst(np
, rp
);
4023 static void niu_size_rbr(struct niu
*np
, struct rx_ring_info
*rp
)
4027 bss
= min(PAGE_SHIFT
, 15);
4029 rp
->rbr_block_size
= 1 << bss
;
4030 rp
->rbr_blocks_per_page
= 1 << (PAGE_SHIFT
-bss
);
4032 rp
->rbr_sizes
[0] = 256;
4033 rp
->rbr_sizes
[1] = 1024;
4034 if (np
->dev
->mtu
> ETH_DATA_LEN
) {
4035 switch (PAGE_SIZE
) {
4037 rp
->rbr_sizes
[2] = 4096;
4041 rp
->rbr_sizes
[2] = 8192;
4045 rp
->rbr_sizes
[2] = 2048;
4047 rp
->rbr_sizes
[3] = rp
->rbr_block_size
;
4050 static int niu_alloc_channels(struct niu
*np
)
4052 struct niu_parent
*parent
= np
->parent
;
4053 int first_rx_channel
, first_tx_channel
;
4057 first_rx_channel
= first_tx_channel
= 0;
4058 for (i
= 0; i
< port
; i
++) {
4059 first_rx_channel
+= parent
->rxchan_per_port
[i
];
4060 first_tx_channel
+= parent
->txchan_per_port
[i
];
4063 np
->num_rx_rings
= parent
->rxchan_per_port
[port
];
4064 np
->num_tx_rings
= parent
->txchan_per_port
[port
];
4066 np
->dev
->real_num_tx_queues
= np
->num_tx_rings
;
4068 np
->rx_rings
= kzalloc(np
->num_rx_rings
* sizeof(struct rx_ring_info
),
4074 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4075 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4078 rp
->rx_channel
= first_rx_channel
+ i
;
4080 err
= niu_alloc_rx_ring_info(np
, rp
);
4084 niu_size_rbr(np
, rp
);
4086 /* XXX better defaults, configurable, etc... XXX */
4087 rp
->nonsyn_window
= 64;
4088 rp
->nonsyn_threshold
= rp
->rcr_table_size
- 64;
4089 rp
->syn_window
= 64;
4090 rp
->syn_threshold
= rp
->rcr_table_size
- 64;
4091 rp
->rcr_pkt_threshold
= 16;
4092 rp
->rcr_timeout
= 8;
4093 rp
->rbr_kick_thresh
= RBR_REFILL_MIN
;
4094 if (rp
->rbr_kick_thresh
< rp
->rbr_blocks_per_page
)
4095 rp
->rbr_kick_thresh
= rp
->rbr_blocks_per_page
;
4097 err
= niu_rbr_fill(np
, rp
, GFP_KERNEL
);
4102 np
->tx_rings
= kzalloc(np
->num_tx_rings
* sizeof(struct tx_ring_info
),
4108 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4109 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4112 rp
->tx_channel
= first_tx_channel
+ i
;
4114 err
= niu_alloc_tx_ring_info(np
, rp
);
4122 niu_free_channels(np
);
4126 static int niu_tx_cs_sng_poll(struct niu
*np
, int channel
)
4130 while (--limit
> 0) {
4131 u64 val
= nr64(TX_CS(channel
));
4132 if (val
& TX_CS_SNG_STATE
)
4138 static int niu_tx_channel_stop(struct niu
*np
, int channel
)
4140 u64 val
= nr64(TX_CS(channel
));
4142 val
|= TX_CS_STOP_N_GO
;
4143 nw64(TX_CS(channel
), val
);
4145 return niu_tx_cs_sng_poll(np
, channel
);
4148 static int niu_tx_cs_reset_poll(struct niu
*np
, int channel
)
4152 while (--limit
> 0) {
4153 u64 val
= nr64(TX_CS(channel
));
4154 if (!(val
& TX_CS_RST
))
4160 static int niu_tx_channel_reset(struct niu
*np
, int channel
)
4162 u64 val
= nr64(TX_CS(channel
));
4166 nw64(TX_CS(channel
), val
);
4168 err
= niu_tx_cs_reset_poll(np
, channel
);
4170 nw64(TX_RING_KICK(channel
), 0);
4175 static int niu_tx_channel_lpage_init(struct niu
*np
, int channel
)
4179 nw64(TX_LOG_MASK1(channel
), 0);
4180 nw64(TX_LOG_VAL1(channel
), 0);
4181 nw64(TX_LOG_MASK2(channel
), 0);
4182 nw64(TX_LOG_VAL2(channel
), 0);
4183 nw64(TX_LOG_PAGE_RELO1(channel
), 0);
4184 nw64(TX_LOG_PAGE_RELO2(channel
), 0);
4185 nw64(TX_LOG_PAGE_HDL(channel
), 0);
4187 val
= (u64
)np
->port
<< TX_LOG_PAGE_VLD_FUNC_SHIFT
;
4188 val
|= (TX_LOG_PAGE_VLD_PAGE0
| TX_LOG_PAGE_VLD_PAGE1
);
4189 nw64(TX_LOG_PAGE_VLD(channel
), val
);
4191 /* XXX TXDMA 32bit mode? XXX */
4196 static void niu_txc_enable_port(struct niu
*np
, int on
)
4198 unsigned long flags
;
4201 niu_lock_parent(np
, flags
);
4202 val
= nr64(TXC_CONTROL
);
4203 mask
= (u64
)1 << np
->port
;
4205 val
|= TXC_CONTROL_ENABLE
| mask
;
4208 if ((val
& ~TXC_CONTROL_ENABLE
) == 0)
4209 val
&= ~TXC_CONTROL_ENABLE
;
4211 nw64(TXC_CONTROL
, val
);
4212 niu_unlock_parent(np
, flags
);
4215 static void niu_txc_set_imask(struct niu
*np
, u64 imask
)
4217 unsigned long flags
;
4220 niu_lock_parent(np
, flags
);
4221 val
= nr64(TXC_INT_MASK
);
4222 val
&= ~TXC_INT_MASK_VAL(np
->port
);
4223 val
|= (imask
<< TXC_INT_MASK_VAL_SHIFT(np
->port
));
4224 niu_unlock_parent(np
, flags
);
4227 static void niu_txc_port_dma_enable(struct niu
*np
, int on
)
4234 for (i
= 0; i
< np
->num_tx_rings
; i
++)
4235 val
|= (1 << np
->tx_rings
[i
].tx_channel
);
4237 nw64(TXC_PORT_DMA(np
->port
), val
);
4240 static int niu_init_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
4242 int err
, channel
= rp
->tx_channel
;
4245 err
= niu_tx_channel_stop(np
, channel
);
4249 err
= niu_tx_channel_reset(np
, channel
);
4253 err
= niu_tx_channel_lpage_init(np
, channel
);
4257 nw64(TXC_DMA_MAX(channel
), rp
->max_burst
);
4258 nw64(TX_ENT_MSK(channel
), 0);
4260 if (rp
->descr_dma
& ~(TX_RNG_CFIG_STADDR_BASE
|
4261 TX_RNG_CFIG_STADDR
)) {
4262 dev_err(np
->device
, PFX
"%s: TX ring channel %d "
4263 "DMA addr (%llx) is not aligned.\n",
4264 np
->dev
->name
, channel
,
4265 (unsigned long long) rp
->descr_dma
);
4269 /* The length field in TX_RNG_CFIG is measured in 64-byte
4270 * blocks. rp->pending is the number of TX descriptors in
4271 * our ring, 8 bytes each, thus we divide by 8 bytes more
4272 * to get the proper value the chip wants.
4274 ring_len
= (rp
->pending
/ 8);
4276 val
= ((ring_len
<< TX_RNG_CFIG_LEN_SHIFT
) |
4278 nw64(TX_RNG_CFIG(channel
), val
);
4280 if (((rp
->mbox_dma
>> 32) & ~TXDMA_MBH_MBADDR
) ||
4281 ((u32
)rp
->mbox_dma
& ~TXDMA_MBL_MBADDR
)) {
4282 dev_err(np
->device
, PFX
"%s: TX ring channel %d "
4283 "MBOX addr (%llx) is has illegal bits.\n",
4284 np
->dev
->name
, channel
,
4285 (unsigned long long) rp
->mbox_dma
);
4288 nw64(TXDMA_MBH(channel
), rp
->mbox_dma
>> 32);
4289 nw64(TXDMA_MBL(channel
), rp
->mbox_dma
& TXDMA_MBL_MBADDR
);
4291 nw64(TX_CS(channel
), 0);
4293 rp
->last_pkt_cnt
= 0;
4298 static void niu_init_rdc_groups(struct niu
*np
)
4300 struct niu_rdc_tables
*tp
= &np
->parent
->rdc_group_cfg
[np
->port
];
4301 int i
, first_table_num
= tp
->first_table_num
;
4303 for (i
= 0; i
< tp
->num_tables
; i
++) {
4304 struct rdc_table
*tbl
= &tp
->tables
[i
];
4305 int this_table
= first_table_num
+ i
;
4308 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++)
4309 nw64(RDC_TBL(this_table
, slot
),
4310 tbl
->rxdma_channel
[slot
]);
4313 nw64(DEF_RDC(np
->port
), np
->parent
->rdc_default
[np
->port
]);
4316 static void niu_init_drr_weight(struct niu
*np
)
4318 int type
= phy_decode(np
->parent
->port_phy
, np
->port
);
4323 val
= PT_DRR_WEIGHT_DEFAULT_10G
;
4328 val
= PT_DRR_WEIGHT_DEFAULT_1G
;
4331 nw64(PT_DRR_WT(np
->port
), val
);
4334 static int niu_init_hostinfo(struct niu
*np
)
4336 struct niu_parent
*parent
= np
->parent
;
4337 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
4338 int i
, err
, num_alt
= niu_num_alt_addr(np
);
4339 int first_rdc_table
= tp
->first_table_num
;
4341 err
= niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
4345 err
= niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
4349 for (i
= 0; i
< num_alt
; i
++) {
4350 err
= niu_set_alt_mac_rdc_table(np
, i
, first_rdc_table
, 1);
4358 static int niu_rx_channel_reset(struct niu
*np
, int channel
)
4360 return niu_set_and_wait_clear(np
, RXDMA_CFIG1(channel
),
4361 RXDMA_CFIG1_RST
, 1000, 10,
4365 static int niu_rx_channel_lpage_init(struct niu
*np
, int channel
)
4369 nw64(RX_LOG_MASK1(channel
), 0);
4370 nw64(RX_LOG_VAL1(channel
), 0);
4371 nw64(RX_LOG_MASK2(channel
), 0);
4372 nw64(RX_LOG_VAL2(channel
), 0);
4373 nw64(RX_LOG_PAGE_RELO1(channel
), 0);
4374 nw64(RX_LOG_PAGE_RELO2(channel
), 0);
4375 nw64(RX_LOG_PAGE_HDL(channel
), 0);
4377 val
= (u64
)np
->port
<< RX_LOG_PAGE_VLD_FUNC_SHIFT
;
4378 val
|= (RX_LOG_PAGE_VLD_PAGE0
| RX_LOG_PAGE_VLD_PAGE1
);
4379 nw64(RX_LOG_PAGE_VLD(channel
), val
);
4384 static void niu_rx_channel_wred_init(struct niu
*np
, struct rx_ring_info
*rp
)
4388 val
= (((u64
)rp
->nonsyn_window
<< RDC_RED_PARA_WIN_SHIFT
) |
4389 ((u64
)rp
->nonsyn_threshold
<< RDC_RED_PARA_THRE_SHIFT
) |
4390 ((u64
)rp
->syn_window
<< RDC_RED_PARA_WIN_SYN_SHIFT
) |
4391 ((u64
)rp
->syn_threshold
<< RDC_RED_PARA_THRE_SYN_SHIFT
));
4392 nw64(RDC_RED_PARA(rp
->rx_channel
), val
);
4395 static int niu_compute_rbr_cfig_b(struct rx_ring_info
*rp
, u64
*ret
)
4399 switch (rp
->rbr_block_size
) {
4401 val
|= (RBR_BLKSIZE_4K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4404 val
|= (RBR_BLKSIZE_8K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4407 val
|= (RBR_BLKSIZE_16K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4410 val
|= (RBR_BLKSIZE_32K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4415 val
|= RBR_CFIG_B_VLD2
;
4416 switch (rp
->rbr_sizes
[2]) {
4418 val
|= (RBR_BUFSZ2_2K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4421 val
|= (RBR_BUFSZ2_4K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4424 val
|= (RBR_BUFSZ2_8K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4427 val
|= (RBR_BUFSZ2_16K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4433 val
|= RBR_CFIG_B_VLD1
;
4434 switch (rp
->rbr_sizes
[1]) {
4436 val
|= (RBR_BUFSZ1_1K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4439 val
|= (RBR_BUFSZ1_2K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4442 val
|= (RBR_BUFSZ1_4K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4445 val
|= (RBR_BUFSZ1_8K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4451 val
|= RBR_CFIG_B_VLD0
;
4452 switch (rp
->rbr_sizes
[0]) {
4454 val
|= (RBR_BUFSZ0_256
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4457 val
|= (RBR_BUFSZ0_512
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4460 val
|= (RBR_BUFSZ0_1K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4463 val
|= (RBR_BUFSZ0_2K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4474 static int niu_enable_rx_channel(struct niu
*np
, int channel
, int on
)
4476 u64 val
= nr64(RXDMA_CFIG1(channel
));
4480 val
|= RXDMA_CFIG1_EN
;
4482 val
&= ~RXDMA_CFIG1_EN
;
4483 nw64(RXDMA_CFIG1(channel
), val
);
4486 while (--limit
> 0) {
4487 if (nr64(RXDMA_CFIG1(channel
)) & RXDMA_CFIG1_QST
)
4496 static int niu_init_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
4498 int err
, channel
= rp
->rx_channel
;
4501 err
= niu_rx_channel_reset(np
, channel
);
4505 err
= niu_rx_channel_lpage_init(np
, channel
);
4509 niu_rx_channel_wred_init(np
, rp
);
4511 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_RBR_EMPTY
);
4512 nw64(RX_DMA_CTL_STAT(channel
),
4513 (RX_DMA_CTL_STAT_MEX
|
4514 RX_DMA_CTL_STAT_RCRTHRES
|
4515 RX_DMA_CTL_STAT_RCRTO
|
4516 RX_DMA_CTL_STAT_RBR_EMPTY
));
4517 nw64(RXDMA_CFIG1(channel
), rp
->mbox_dma
>> 32);
4518 nw64(RXDMA_CFIG2(channel
), (rp
->mbox_dma
& 0x00000000ffffffc0));
4519 nw64(RBR_CFIG_A(channel
),
4520 ((u64
)rp
->rbr_table_size
<< RBR_CFIG_A_LEN_SHIFT
) |
4521 (rp
->rbr_dma
& (RBR_CFIG_A_STADDR_BASE
| RBR_CFIG_A_STADDR
)));
4522 err
= niu_compute_rbr_cfig_b(rp
, &val
);
4525 nw64(RBR_CFIG_B(channel
), val
);
4526 nw64(RCRCFIG_A(channel
),
4527 ((u64
)rp
->rcr_table_size
<< RCRCFIG_A_LEN_SHIFT
) |
4528 (rp
->rcr_dma
& (RCRCFIG_A_STADDR_BASE
| RCRCFIG_A_STADDR
)));
4529 nw64(RCRCFIG_B(channel
),
4530 ((u64
)rp
->rcr_pkt_threshold
<< RCRCFIG_B_PTHRES_SHIFT
) |
4532 ((u64
)rp
->rcr_timeout
<< RCRCFIG_B_TIMEOUT_SHIFT
));
4534 err
= niu_enable_rx_channel(np
, channel
, 1);
4538 nw64(RBR_KICK(channel
), rp
->rbr_index
);
4540 val
= nr64(RX_DMA_CTL_STAT(channel
));
4541 val
|= RX_DMA_CTL_STAT_RBR_EMPTY
;
4542 nw64(RX_DMA_CTL_STAT(channel
), val
);
4547 static int niu_init_rx_channels(struct niu
*np
)
4549 unsigned long flags
;
4550 u64 seed
= jiffies_64
;
4553 niu_lock_parent(np
, flags
);
4554 nw64(RX_DMA_CK_DIV
, np
->parent
->rxdma_clock_divider
);
4555 nw64(RED_RAN_INIT
, RED_RAN_INIT_OPMODE
| (seed
& RED_RAN_INIT_VAL
));
4556 niu_unlock_parent(np
, flags
);
4558 /* XXX RXDMA 32bit mode? XXX */
4560 niu_init_rdc_groups(np
);
4561 niu_init_drr_weight(np
);
4563 err
= niu_init_hostinfo(np
);
4567 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4568 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4570 err
= niu_init_one_rx_channel(np
, rp
);
4578 static int niu_set_ip_frag_rule(struct niu
*np
)
4580 struct niu_parent
*parent
= np
->parent
;
4581 struct niu_classifier
*cp
= &np
->clas
;
4582 struct niu_tcam_entry
*tp
;
4585 /* XXX fix this allocation scheme XXX */
4586 index
= cp
->tcam_index
;
4587 tp
= &parent
->tcam
[index
];
4589 /* Note that the noport bit is the same in both ipv4 and
4590 * ipv6 format TCAM entries.
4592 memset(tp
, 0, sizeof(*tp
));
4593 tp
->key
[1] = TCAM_V4KEY1_NOPORT
;
4594 tp
->key_mask
[1] = TCAM_V4KEY1_NOPORT
;
4595 tp
->assoc_data
= (TCAM_ASSOCDATA_TRES_USE_OFFSET
|
4596 ((u64
)0 << TCAM_ASSOCDATA_OFFSET_SHIFT
));
4597 err
= tcam_write(np
, index
, tp
->key
, tp
->key_mask
);
4600 err
= tcam_assoc_write(np
, index
, tp
->assoc_data
);
4607 static int niu_init_classifier_hw(struct niu
*np
)
4609 struct niu_parent
*parent
= np
->parent
;
4610 struct niu_classifier
*cp
= &np
->clas
;
4613 nw64(H1POLY
, cp
->h1_init
);
4614 nw64(H2POLY
, cp
->h2_init
);
4616 err
= niu_init_hostinfo(np
);
4620 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++) {
4621 struct niu_vlan_rdc
*vp
= &cp
->vlan_mappings
[i
];
4623 vlan_tbl_write(np
, i
, np
->port
,
4624 vp
->vlan_pref
, vp
->rdc_num
);
4627 for (i
= 0; i
< cp
->num_alt_mac_mappings
; i
++) {
4628 struct niu_altmac_rdc
*ap
= &cp
->alt_mac_mappings
[i
];
4630 err
= niu_set_alt_mac_rdc_table(np
, ap
->alt_mac_num
,
4631 ap
->rdc_num
, ap
->mac_pref
);
4636 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
4637 int index
= i
- CLASS_CODE_USER_PROG1
;
4639 err
= niu_set_tcam_key(np
, i
, parent
->tcam_key
[index
]);
4642 err
= niu_set_flow_key(np
, i
, parent
->flow_key
[index
]);
4647 err
= niu_set_ip_frag_rule(np
);
4656 static int niu_zcp_write(struct niu
*np
, int index
, u64
*data
)
4658 nw64(ZCP_RAM_DATA0
, data
[0]);
4659 nw64(ZCP_RAM_DATA1
, data
[1]);
4660 nw64(ZCP_RAM_DATA2
, data
[2]);
4661 nw64(ZCP_RAM_DATA3
, data
[3]);
4662 nw64(ZCP_RAM_DATA4
, data
[4]);
4663 nw64(ZCP_RAM_BE
, ZCP_RAM_BE_VAL
);
4665 (ZCP_RAM_ACC_WRITE
|
4666 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
4667 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
4669 return niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
4673 static int niu_zcp_read(struct niu
*np
, int index
, u64
*data
)
4677 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
4680 dev_err(np
->device
, PFX
"%s: ZCP read busy won't clear, "
4681 "ZCP_RAM_ACC[%llx]\n", np
->dev
->name
,
4682 (unsigned long long) nr64(ZCP_RAM_ACC
));
4688 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
4689 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
4691 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
4694 dev_err(np
->device
, PFX
"%s: ZCP read busy2 won't clear, "
4695 "ZCP_RAM_ACC[%llx]\n", np
->dev
->name
,
4696 (unsigned long long) nr64(ZCP_RAM_ACC
));
4700 data
[0] = nr64(ZCP_RAM_DATA0
);
4701 data
[1] = nr64(ZCP_RAM_DATA1
);
4702 data
[2] = nr64(ZCP_RAM_DATA2
);
4703 data
[3] = nr64(ZCP_RAM_DATA3
);
4704 data
[4] = nr64(ZCP_RAM_DATA4
);
4709 static void niu_zcp_cfifo_reset(struct niu
*np
)
4711 u64 val
= nr64(RESET_CFIFO
);
4713 val
|= RESET_CFIFO_RST(np
->port
);
4714 nw64(RESET_CFIFO
, val
);
4717 val
&= ~RESET_CFIFO_RST(np
->port
);
4718 nw64(RESET_CFIFO
, val
);
4721 static int niu_init_zcp(struct niu
*np
)
4723 u64 data
[5], rbuf
[5];
4726 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
4727 if (np
->port
== 0 || np
->port
== 1)
4728 max
= ATLAS_P0_P1_CFIFO_ENTRIES
;
4730 max
= ATLAS_P2_P3_CFIFO_ENTRIES
;
4732 max
= NIU_CFIFO_ENTRIES
;
4740 for (i
= 0; i
< max
; i
++) {
4741 err
= niu_zcp_write(np
, i
, data
);
4744 err
= niu_zcp_read(np
, i
, rbuf
);
4749 niu_zcp_cfifo_reset(np
);
4750 nw64(CFIFO_ECC(np
->port
), 0);
4751 nw64(ZCP_INT_STAT
, ZCP_INT_STAT_ALL
);
4752 (void) nr64(ZCP_INT_STAT
);
4753 nw64(ZCP_INT_MASK
, ZCP_INT_MASK_ALL
);
4758 static void niu_ipp_write(struct niu
*np
, int index
, u64
*data
)
4760 u64 val
= nr64_ipp(IPP_CFIG
);
4762 nw64_ipp(IPP_CFIG
, val
| IPP_CFIG_DFIFO_PIO_W
);
4763 nw64_ipp(IPP_DFIFO_WR_PTR
, index
);
4764 nw64_ipp(IPP_DFIFO_WR0
, data
[0]);
4765 nw64_ipp(IPP_DFIFO_WR1
, data
[1]);
4766 nw64_ipp(IPP_DFIFO_WR2
, data
[2]);
4767 nw64_ipp(IPP_DFIFO_WR3
, data
[3]);
4768 nw64_ipp(IPP_DFIFO_WR4
, data
[4]);
4769 nw64_ipp(IPP_CFIG
, val
& ~IPP_CFIG_DFIFO_PIO_W
);
4772 static void niu_ipp_read(struct niu
*np
, int index
, u64
*data
)
4774 nw64_ipp(IPP_DFIFO_RD_PTR
, index
);
4775 data
[0] = nr64_ipp(IPP_DFIFO_RD0
);
4776 data
[1] = nr64_ipp(IPP_DFIFO_RD1
);
4777 data
[2] = nr64_ipp(IPP_DFIFO_RD2
);
4778 data
[3] = nr64_ipp(IPP_DFIFO_RD3
);
4779 data
[4] = nr64_ipp(IPP_DFIFO_RD4
);
4782 static int niu_ipp_reset(struct niu
*np
)
4784 return niu_set_and_wait_clear_ipp(np
, IPP_CFIG
, IPP_CFIG_SOFT_RST
,
4785 1000, 100, "IPP_CFIG");
4788 static int niu_init_ipp(struct niu
*np
)
4790 u64 data
[5], rbuf
[5], val
;
4793 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
4794 if (np
->port
== 0 || np
->port
== 1)
4795 max
= ATLAS_P0_P1_DFIFO_ENTRIES
;
4797 max
= ATLAS_P2_P3_DFIFO_ENTRIES
;
4799 max
= NIU_DFIFO_ENTRIES
;
4807 for (i
= 0; i
< max
; i
++) {
4808 niu_ipp_write(np
, i
, data
);
4809 niu_ipp_read(np
, i
, rbuf
);
4812 (void) nr64_ipp(IPP_INT_STAT
);
4813 (void) nr64_ipp(IPP_INT_STAT
);
4815 err
= niu_ipp_reset(np
);
4819 (void) nr64_ipp(IPP_PKT_DIS
);
4820 (void) nr64_ipp(IPP_BAD_CS_CNT
);
4821 (void) nr64_ipp(IPP_ECC
);
4823 (void) nr64_ipp(IPP_INT_STAT
);
4825 nw64_ipp(IPP_MSK
, ~IPP_MSK_ALL
);
4827 val
= nr64_ipp(IPP_CFIG
);
4828 val
&= ~IPP_CFIG_IP_MAX_PKT
;
4829 val
|= (IPP_CFIG_IPP_ENABLE
|
4830 IPP_CFIG_DFIFO_ECC_EN
|
4831 IPP_CFIG_DROP_BAD_CRC
|
4833 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT
));
4834 nw64_ipp(IPP_CFIG
, val
);
4839 static void niu_handle_led(struct niu
*np
, int status
)
4842 val
= nr64_mac(XMAC_CONFIG
);
4844 if ((np
->flags
& NIU_FLAGS_10G
) != 0 &&
4845 (np
->flags
& NIU_FLAGS_FIBER
) != 0) {
4847 val
|= XMAC_CONFIG_LED_POLARITY
;
4848 val
&= ~XMAC_CONFIG_FORCE_LED_ON
;
4850 val
|= XMAC_CONFIG_FORCE_LED_ON
;
4851 val
&= ~XMAC_CONFIG_LED_POLARITY
;
4855 nw64_mac(XMAC_CONFIG
, val
);
4858 static void niu_init_xif_xmac(struct niu
*np
)
4860 struct niu_link_config
*lp
= &np
->link_config
;
4863 if (np
->flags
& NIU_FLAGS_XCVR_SERDES
) {
4864 val
= nr64(MIF_CONFIG
);
4865 val
|= MIF_CONFIG_ATCA_GE
;
4866 nw64(MIF_CONFIG
, val
);
4869 val
= nr64_mac(XMAC_CONFIG
);
4870 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
4872 val
|= XMAC_CONFIG_TX_OUTPUT_EN
;
4874 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
4875 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
4876 val
|= XMAC_CONFIG_LOOPBACK
;
4878 val
&= ~XMAC_CONFIG_LOOPBACK
;
4881 if (np
->flags
& NIU_FLAGS_10G
) {
4882 val
&= ~XMAC_CONFIG_LFS_DISABLE
;
4884 val
|= XMAC_CONFIG_LFS_DISABLE
;
4885 if (!(np
->flags
& NIU_FLAGS_FIBER
) &&
4886 !(np
->flags
& NIU_FLAGS_XCVR_SERDES
))
4887 val
|= XMAC_CONFIG_1G_PCS_BYPASS
;
4889 val
&= ~XMAC_CONFIG_1G_PCS_BYPASS
;
4892 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
4894 if (lp
->active_speed
== SPEED_100
)
4895 val
|= XMAC_CONFIG_SEL_CLK_25MHZ
;
4897 val
&= ~XMAC_CONFIG_SEL_CLK_25MHZ
;
4899 nw64_mac(XMAC_CONFIG
, val
);
4901 val
= nr64_mac(XMAC_CONFIG
);
4902 val
&= ~XMAC_CONFIG_MODE_MASK
;
4903 if (np
->flags
& NIU_FLAGS_10G
) {
4904 val
|= XMAC_CONFIG_MODE_XGMII
;
4906 if (lp
->active_speed
== SPEED_100
)
4907 val
|= XMAC_CONFIG_MODE_MII
;
4909 val
|= XMAC_CONFIG_MODE_GMII
;
4912 nw64_mac(XMAC_CONFIG
, val
);
4915 static void niu_init_xif_bmac(struct niu
*np
)
4917 struct niu_link_config
*lp
= &np
->link_config
;
4920 val
= BMAC_XIF_CONFIG_TX_OUTPUT_EN
;
4922 if (lp
->loopback_mode
== LOOPBACK_MAC
)
4923 val
|= BMAC_XIF_CONFIG_MII_LOOPBACK
;
4925 val
&= ~BMAC_XIF_CONFIG_MII_LOOPBACK
;
4927 if (lp
->active_speed
== SPEED_1000
)
4928 val
|= BMAC_XIF_CONFIG_GMII_MODE
;
4930 val
&= ~BMAC_XIF_CONFIG_GMII_MODE
;
4932 val
&= ~(BMAC_XIF_CONFIG_LINK_LED
|
4933 BMAC_XIF_CONFIG_LED_POLARITY
);
4935 if (!(np
->flags
& NIU_FLAGS_10G
) &&
4936 !(np
->flags
& NIU_FLAGS_FIBER
) &&
4937 lp
->active_speed
== SPEED_100
)
4938 val
|= BMAC_XIF_CONFIG_25MHZ_CLOCK
;
4940 val
&= ~BMAC_XIF_CONFIG_25MHZ_CLOCK
;
4942 nw64_mac(BMAC_XIF_CONFIG
, val
);
4945 static void niu_init_xif(struct niu
*np
)
4947 if (np
->flags
& NIU_FLAGS_XMAC
)
4948 niu_init_xif_xmac(np
);
4950 niu_init_xif_bmac(np
);
4953 static void niu_pcs_mii_reset(struct niu
*np
)
4956 u64 val
= nr64_pcs(PCS_MII_CTL
);
4957 val
|= PCS_MII_CTL_RST
;
4958 nw64_pcs(PCS_MII_CTL
, val
);
4959 while ((--limit
>= 0) && (val
& PCS_MII_CTL_RST
)) {
4961 val
= nr64_pcs(PCS_MII_CTL
);
4965 static void niu_xpcs_reset(struct niu
*np
)
4968 u64 val
= nr64_xpcs(XPCS_CONTROL1
);
4969 val
|= XPCS_CONTROL1_RESET
;
4970 nw64_xpcs(XPCS_CONTROL1
, val
);
4971 while ((--limit
>= 0) && (val
& XPCS_CONTROL1_RESET
)) {
4973 val
= nr64_xpcs(XPCS_CONTROL1
);
4977 static int niu_init_pcs(struct niu
*np
)
4979 struct niu_link_config
*lp
= &np
->link_config
;
4982 switch (np
->flags
& (NIU_FLAGS_10G
|
4984 NIU_FLAGS_XCVR_SERDES
)) {
4985 case NIU_FLAGS_FIBER
:
4987 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
4988 nw64_pcs(PCS_DPATH_MODE
, 0);
4989 niu_pcs_mii_reset(np
);
4993 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
4994 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
4996 if (!(np
->flags
& NIU_FLAGS_XMAC
))
4999 /* 10G copper or fiber */
5000 val
= nr64_mac(XMAC_CONFIG
);
5001 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
5002 nw64_mac(XMAC_CONFIG
, val
);
5006 val
= nr64_xpcs(XPCS_CONTROL1
);
5007 if (lp
->loopback_mode
== LOOPBACK_PHY
)
5008 val
|= XPCS_CONTROL1_LOOPBACK
;
5010 val
&= ~XPCS_CONTROL1_LOOPBACK
;
5011 nw64_xpcs(XPCS_CONTROL1
, val
);
5013 nw64_xpcs(XPCS_DESKEW_ERR_CNT
, 0);
5014 (void) nr64_xpcs(XPCS_SYMERR_CNT01
);
5015 (void) nr64_xpcs(XPCS_SYMERR_CNT23
);
5019 case NIU_FLAGS_XCVR_SERDES
:
5021 niu_pcs_mii_reset(np
);
5022 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
5023 nw64_pcs(PCS_DPATH_MODE
, 0);
5028 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
5029 /* 1G RGMII FIBER */
5030 nw64_pcs(PCS_DPATH_MODE
, PCS_DPATH_MODE_MII
);
5031 niu_pcs_mii_reset(np
);
5041 static int niu_reset_tx_xmac(struct niu
*np
)
5043 return niu_set_and_wait_clear_mac(np
, XTXMAC_SW_RST
,
5044 (XTXMAC_SW_RST_REG_RS
|
5045 XTXMAC_SW_RST_SOFT_RST
),
5046 1000, 100, "XTXMAC_SW_RST");
5049 static int niu_reset_tx_bmac(struct niu
*np
)
5053 nw64_mac(BTXMAC_SW_RST
, BTXMAC_SW_RST_RESET
);
5055 while (--limit
>= 0) {
5056 if (!(nr64_mac(BTXMAC_SW_RST
) & BTXMAC_SW_RST_RESET
))
5061 dev_err(np
->device
, PFX
"Port %u TX BMAC would not reset, "
5062 "BTXMAC_SW_RST[%llx]\n",
5064 (unsigned long long) nr64_mac(BTXMAC_SW_RST
));
5071 static int niu_reset_tx_mac(struct niu
*np
)
5073 if (np
->flags
& NIU_FLAGS_XMAC
)
5074 return niu_reset_tx_xmac(np
);
5076 return niu_reset_tx_bmac(np
);
5079 static void niu_init_tx_xmac(struct niu
*np
, u64 min
, u64 max
)
5083 val
= nr64_mac(XMAC_MIN
);
5084 val
&= ~(XMAC_MIN_TX_MIN_PKT_SIZE
|
5085 XMAC_MIN_RX_MIN_PKT_SIZE
);
5086 val
|= (min
<< XMAC_MIN_RX_MIN_PKT_SIZE_SHFT
);
5087 val
|= (min
<< XMAC_MIN_TX_MIN_PKT_SIZE_SHFT
);
5088 nw64_mac(XMAC_MIN
, val
);
5090 nw64_mac(XMAC_MAX
, max
);
5092 nw64_mac(XTXMAC_STAT_MSK
, ~(u64
)0);
5094 val
= nr64_mac(XMAC_IPG
);
5095 if (np
->flags
& NIU_FLAGS_10G
) {
5096 val
&= ~XMAC_IPG_IPG_XGMII
;
5097 val
|= (IPG_12_15_XGMII
<< XMAC_IPG_IPG_XGMII_SHIFT
);
5099 val
&= ~XMAC_IPG_IPG_MII_GMII
;
5100 val
|= (IPG_12_MII_GMII
<< XMAC_IPG_IPG_MII_GMII_SHIFT
);
5102 nw64_mac(XMAC_IPG
, val
);
5104 val
= nr64_mac(XMAC_CONFIG
);
5105 val
&= ~(XMAC_CONFIG_ALWAYS_NO_CRC
|
5106 XMAC_CONFIG_STRETCH_MODE
|
5107 XMAC_CONFIG_VAR_MIN_IPG_EN
|
5108 XMAC_CONFIG_TX_ENABLE
);
5109 nw64_mac(XMAC_CONFIG
, val
);
5111 nw64_mac(TXMAC_FRM_CNT
, 0);
5112 nw64_mac(TXMAC_BYTE_CNT
, 0);
5115 static void niu_init_tx_bmac(struct niu
*np
, u64 min
, u64 max
)
5119 nw64_mac(BMAC_MIN_FRAME
, min
);
5120 nw64_mac(BMAC_MAX_FRAME
, max
);
5122 nw64_mac(BTXMAC_STATUS_MASK
, ~(u64
)0);
5123 nw64_mac(BMAC_CTRL_TYPE
, 0x8808);
5124 nw64_mac(BMAC_PREAMBLE_SIZE
, 7);
5126 val
= nr64_mac(BTXMAC_CONFIG
);
5127 val
&= ~(BTXMAC_CONFIG_FCS_DISABLE
|
5128 BTXMAC_CONFIG_ENABLE
);
5129 nw64_mac(BTXMAC_CONFIG
, val
);
5132 static void niu_init_tx_mac(struct niu
*np
)
5137 if (np
->dev
->mtu
> ETH_DATA_LEN
)
5142 /* The XMAC_MIN register only accepts values for TX min which
5143 * have the low 3 bits cleared.
5145 BUILD_BUG_ON(min
& 0x7);
5147 if (np
->flags
& NIU_FLAGS_XMAC
)
5148 niu_init_tx_xmac(np
, min
, max
);
5150 niu_init_tx_bmac(np
, min
, max
);
5153 static int niu_reset_rx_xmac(struct niu
*np
)
5157 nw64_mac(XRXMAC_SW_RST
,
5158 XRXMAC_SW_RST_REG_RS
| XRXMAC_SW_RST_SOFT_RST
);
5160 while (--limit
>= 0) {
5161 if (!(nr64_mac(XRXMAC_SW_RST
) & (XRXMAC_SW_RST_REG_RS
|
5162 XRXMAC_SW_RST_SOFT_RST
)))
5167 dev_err(np
->device
, PFX
"Port %u RX XMAC would not reset, "
5168 "XRXMAC_SW_RST[%llx]\n",
5170 (unsigned long long) nr64_mac(XRXMAC_SW_RST
));
5177 static int niu_reset_rx_bmac(struct niu
*np
)
5181 nw64_mac(BRXMAC_SW_RST
, BRXMAC_SW_RST_RESET
);
5183 while (--limit
>= 0) {
5184 if (!(nr64_mac(BRXMAC_SW_RST
) & BRXMAC_SW_RST_RESET
))
5189 dev_err(np
->device
, PFX
"Port %u RX BMAC would not reset, "
5190 "BRXMAC_SW_RST[%llx]\n",
5192 (unsigned long long) nr64_mac(BRXMAC_SW_RST
));
5199 static int niu_reset_rx_mac(struct niu
*np
)
5201 if (np
->flags
& NIU_FLAGS_XMAC
)
5202 return niu_reset_rx_xmac(np
);
5204 return niu_reset_rx_bmac(np
);
5207 static void niu_init_rx_xmac(struct niu
*np
)
5209 struct niu_parent
*parent
= np
->parent
;
5210 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5211 int first_rdc_table
= tp
->first_table_num
;
5215 nw64_mac(XMAC_ADD_FILT0
, 0);
5216 nw64_mac(XMAC_ADD_FILT1
, 0);
5217 nw64_mac(XMAC_ADD_FILT2
, 0);
5218 nw64_mac(XMAC_ADD_FILT12_MASK
, 0);
5219 nw64_mac(XMAC_ADD_FILT00_MASK
, 0);
5220 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5221 nw64_mac(XMAC_HASH_TBL(i
), 0);
5222 nw64_mac(XRXMAC_STAT_MSK
, ~(u64
)0);
5223 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5224 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5226 val
= nr64_mac(XMAC_CONFIG
);
5227 val
&= ~(XMAC_CONFIG_RX_MAC_ENABLE
|
5228 XMAC_CONFIG_PROMISCUOUS
|
5229 XMAC_CONFIG_PROMISC_GROUP
|
5230 XMAC_CONFIG_ERR_CHK_DIS
|
5231 XMAC_CONFIG_RX_CRC_CHK_DIS
|
5232 XMAC_CONFIG_RESERVED_MULTICAST
|
5233 XMAC_CONFIG_RX_CODEV_CHK_DIS
|
5234 XMAC_CONFIG_ADDR_FILTER_EN
|
5235 XMAC_CONFIG_RCV_PAUSE_ENABLE
|
5236 XMAC_CONFIG_STRIP_CRC
|
5237 XMAC_CONFIG_PASS_FLOW_CTRL
|
5238 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN
);
5239 val
|= (XMAC_CONFIG_HASH_FILTER_EN
);
5240 nw64_mac(XMAC_CONFIG
, val
);
5242 nw64_mac(RXMAC_BT_CNT
, 0);
5243 nw64_mac(RXMAC_BC_FRM_CNT
, 0);
5244 nw64_mac(RXMAC_MC_FRM_CNT
, 0);
5245 nw64_mac(RXMAC_FRAG_CNT
, 0);
5246 nw64_mac(RXMAC_HIST_CNT1
, 0);
5247 nw64_mac(RXMAC_HIST_CNT2
, 0);
5248 nw64_mac(RXMAC_HIST_CNT3
, 0);
5249 nw64_mac(RXMAC_HIST_CNT4
, 0);
5250 nw64_mac(RXMAC_HIST_CNT5
, 0);
5251 nw64_mac(RXMAC_HIST_CNT6
, 0);
5252 nw64_mac(RXMAC_HIST_CNT7
, 0);
5253 nw64_mac(RXMAC_MPSZER_CNT
, 0);
5254 nw64_mac(RXMAC_CRC_ER_CNT
, 0);
5255 nw64_mac(RXMAC_CD_VIO_CNT
, 0);
5256 nw64_mac(LINK_FAULT_CNT
, 0);
5259 static void niu_init_rx_bmac(struct niu
*np
)
5261 struct niu_parent
*parent
= np
->parent
;
5262 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5263 int first_rdc_table
= tp
->first_table_num
;
5267 nw64_mac(BMAC_ADD_FILT0
, 0);
5268 nw64_mac(BMAC_ADD_FILT1
, 0);
5269 nw64_mac(BMAC_ADD_FILT2
, 0);
5270 nw64_mac(BMAC_ADD_FILT12_MASK
, 0);
5271 nw64_mac(BMAC_ADD_FILT00_MASK
, 0);
5272 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5273 nw64_mac(BMAC_HASH_TBL(i
), 0);
5274 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5275 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5276 nw64_mac(BRXMAC_STATUS_MASK
, ~(u64
)0);
5278 val
= nr64_mac(BRXMAC_CONFIG
);
5279 val
&= ~(BRXMAC_CONFIG_ENABLE
|
5280 BRXMAC_CONFIG_STRIP_PAD
|
5281 BRXMAC_CONFIG_STRIP_FCS
|
5282 BRXMAC_CONFIG_PROMISC
|
5283 BRXMAC_CONFIG_PROMISC_GRP
|
5284 BRXMAC_CONFIG_ADDR_FILT_EN
|
5285 BRXMAC_CONFIG_DISCARD_DIS
);
5286 val
|= (BRXMAC_CONFIG_HASH_FILT_EN
);
5287 nw64_mac(BRXMAC_CONFIG
, val
);
5289 val
= nr64_mac(BMAC_ADDR_CMPEN
);
5290 val
|= BMAC_ADDR_CMPEN_EN0
;
5291 nw64_mac(BMAC_ADDR_CMPEN
, val
);
5294 static void niu_init_rx_mac(struct niu
*np
)
5296 niu_set_primary_mac(np
, np
->dev
->dev_addr
);
5298 if (np
->flags
& NIU_FLAGS_XMAC
)
5299 niu_init_rx_xmac(np
);
5301 niu_init_rx_bmac(np
);
5304 static void niu_enable_tx_xmac(struct niu
*np
, int on
)
5306 u64 val
= nr64_mac(XMAC_CONFIG
);
5309 val
|= XMAC_CONFIG_TX_ENABLE
;
5311 val
&= ~XMAC_CONFIG_TX_ENABLE
;
5312 nw64_mac(XMAC_CONFIG
, val
);
5315 static void niu_enable_tx_bmac(struct niu
*np
, int on
)
5317 u64 val
= nr64_mac(BTXMAC_CONFIG
);
5320 val
|= BTXMAC_CONFIG_ENABLE
;
5322 val
&= ~BTXMAC_CONFIG_ENABLE
;
5323 nw64_mac(BTXMAC_CONFIG
, val
);
5326 static void niu_enable_tx_mac(struct niu
*np
, int on
)
5328 if (np
->flags
& NIU_FLAGS_XMAC
)
5329 niu_enable_tx_xmac(np
, on
);
5331 niu_enable_tx_bmac(np
, on
);
5334 static void niu_enable_rx_xmac(struct niu
*np
, int on
)
5336 u64 val
= nr64_mac(XMAC_CONFIG
);
5338 val
&= ~(XMAC_CONFIG_HASH_FILTER_EN
|
5339 XMAC_CONFIG_PROMISCUOUS
);
5341 if (np
->flags
& NIU_FLAGS_MCAST
)
5342 val
|= XMAC_CONFIG_HASH_FILTER_EN
;
5343 if (np
->flags
& NIU_FLAGS_PROMISC
)
5344 val
|= XMAC_CONFIG_PROMISCUOUS
;
5347 val
|= XMAC_CONFIG_RX_MAC_ENABLE
;
5349 val
&= ~XMAC_CONFIG_RX_MAC_ENABLE
;
5350 nw64_mac(XMAC_CONFIG
, val
);
5353 static void niu_enable_rx_bmac(struct niu
*np
, int on
)
5355 u64 val
= nr64_mac(BRXMAC_CONFIG
);
5357 val
&= ~(BRXMAC_CONFIG_HASH_FILT_EN
|
5358 BRXMAC_CONFIG_PROMISC
);
5360 if (np
->flags
& NIU_FLAGS_MCAST
)
5361 val
|= BRXMAC_CONFIG_HASH_FILT_EN
;
5362 if (np
->flags
& NIU_FLAGS_PROMISC
)
5363 val
|= BRXMAC_CONFIG_PROMISC
;
5366 val
|= BRXMAC_CONFIG_ENABLE
;
5368 val
&= ~BRXMAC_CONFIG_ENABLE
;
5369 nw64_mac(BRXMAC_CONFIG
, val
);
5372 static void niu_enable_rx_mac(struct niu
*np
, int on
)
5374 if (np
->flags
& NIU_FLAGS_XMAC
)
5375 niu_enable_rx_xmac(np
, on
);
5377 niu_enable_rx_bmac(np
, on
);
5380 static int niu_init_mac(struct niu
*np
)
5385 err
= niu_init_pcs(np
);
5389 err
= niu_reset_tx_mac(np
);
5392 niu_init_tx_mac(np
);
5393 err
= niu_reset_rx_mac(np
);
5396 niu_init_rx_mac(np
);
5398 /* This looks hookey but the RX MAC reset we just did will
5399 * undo some of the state we setup in niu_init_tx_mac() so we
5400 * have to call it again. In particular, the RX MAC reset will
5401 * set the XMAC_MAX register back to it's default value.
5403 niu_init_tx_mac(np
);
5404 niu_enable_tx_mac(np
, 1);
5406 niu_enable_rx_mac(np
, 1);
5411 static void niu_stop_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5413 (void) niu_tx_channel_stop(np
, rp
->tx_channel
);
5416 static void niu_stop_tx_channels(struct niu
*np
)
5420 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5421 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5423 niu_stop_one_tx_channel(np
, rp
);
5427 static void niu_reset_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5429 (void) niu_tx_channel_reset(np
, rp
->tx_channel
);
5432 static void niu_reset_tx_channels(struct niu
*np
)
5436 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5437 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5439 niu_reset_one_tx_channel(np
, rp
);
5443 static void niu_stop_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5445 (void) niu_enable_rx_channel(np
, rp
->rx_channel
, 0);
5448 static void niu_stop_rx_channels(struct niu
*np
)
5452 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5453 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5455 niu_stop_one_rx_channel(np
, rp
);
5459 static void niu_reset_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5461 int channel
= rp
->rx_channel
;
5463 (void) niu_rx_channel_reset(np
, channel
);
5464 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_ALL
);
5465 nw64(RX_DMA_CTL_STAT(channel
), 0);
5466 (void) niu_enable_rx_channel(np
, channel
, 0);
5469 static void niu_reset_rx_channels(struct niu
*np
)
5473 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5474 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5476 niu_reset_one_rx_channel(np
, rp
);
5480 static void niu_disable_ipp(struct niu
*np
)
5485 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5486 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5488 while (--limit
>= 0 && (rd
!= wr
)) {
5489 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5490 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5493 (rd
!= 0 && wr
!= 1)) {
5494 dev_err(np
->device
, PFX
"%s: IPP would not quiesce, "
5495 "rd_ptr[%llx] wr_ptr[%llx]\n",
5497 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR
),
5498 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR
));
5501 val
= nr64_ipp(IPP_CFIG
);
5502 val
&= ~(IPP_CFIG_IPP_ENABLE
|
5503 IPP_CFIG_DFIFO_ECC_EN
|
5504 IPP_CFIG_DROP_BAD_CRC
|
5506 nw64_ipp(IPP_CFIG
, val
);
5508 (void) niu_ipp_reset(np
);
5511 static int niu_init_hw(struct niu
*np
)
5515 niudbg(IFUP
, "%s: Initialize TXC\n", np
->dev
->name
);
5516 niu_txc_enable_port(np
, 1);
5517 niu_txc_port_dma_enable(np
, 1);
5518 niu_txc_set_imask(np
, 0);
5520 niudbg(IFUP
, "%s: Initialize TX channels\n", np
->dev
->name
);
5521 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5522 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5524 err
= niu_init_one_tx_channel(np
, rp
);
5529 niudbg(IFUP
, "%s: Initialize RX channels\n", np
->dev
->name
);
5530 err
= niu_init_rx_channels(np
);
5532 goto out_uninit_tx_channels
;
5534 niudbg(IFUP
, "%s: Initialize classifier\n", np
->dev
->name
);
5535 err
= niu_init_classifier_hw(np
);
5537 goto out_uninit_rx_channels
;
5539 niudbg(IFUP
, "%s: Initialize ZCP\n", np
->dev
->name
);
5540 err
= niu_init_zcp(np
);
5542 goto out_uninit_rx_channels
;
5544 niudbg(IFUP
, "%s: Initialize IPP\n", np
->dev
->name
);
5545 err
= niu_init_ipp(np
);
5547 goto out_uninit_rx_channels
;
5549 niudbg(IFUP
, "%s: Initialize MAC\n", np
->dev
->name
);
5550 err
= niu_init_mac(np
);
5552 goto out_uninit_ipp
;
5557 niudbg(IFUP
, "%s: Uninit IPP\n", np
->dev
->name
);
5558 niu_disable_ipp(np
);
5560 out_uninit_rx_channels
:
5561 niudbg(IFUP
, "%s: Uninit RX channels\n", np
->dev
->name
);
5562 niu_stop_rx_channels(np
);
5563 niu_reset_rx_channels(np
);
5565 out_uninit_tx_channels
:
5566 niudbg(IFUP
, "%s: Uninit TX channels\n", np
->dev
->name
);
5567 niu_stop_tx_channels(np
);
5568 niu_reset_tx_channels(np
);
5573 static void niu_stop_hw(struct niu
*np
)
5575 niudbg(IFDOWN
, "%s: Disable interrupts\n", np
->dev
->name
);
5576 niu_enable_interrupts(np
, 0);
5578 niudbg(IFDOWN
, "%s: Disable RX MAC\n", np
->dev
->name
);
5579 niu_enable_rx_mac(np
, 0);
5581 niudbg(IFDOWN
, "%s: Disable IPP\n", np
->dev
->name
);
5582 niu_disable_ipp(np
);
5584 niudbg(IFDOWN
, "%s: Stop TX channels\n", np
->dev
->name
);
5585 niu_stop_tx_channels(np
);
5587 niudbg(IFDOWN
, "%s: Stop RX channels\n", np
->dev
->name
);
5588 niu_stop_rx_channels(np
);
5590 niudbg(IFDOWN
, "%s: Reset TX channels\n", np
->dev
->name
);
5591 niu_reset_tx_channels(np
);
5593 niudbg(IFDOWN
, "%s: Reset RX channels\n", np
->dev
->name
);
5594 niu_reset_rx_channels(np
);
5597 static int niu_request_irq(struct niu
*np
)
5602 for (i
= 0; i
< np
->num_ldg
; i
++) {
5603 struct niu_ldg
*lp
= &np
->ldg
[i
];
5605 err
= request_irq(lp
->irq
, niu_interrupt
,
5606 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
,
5616 for (j
= 0; j
< i
; j
++) {
5617 struct niu_ldg
*lp
= &np
->ldg
[j
];
5619 free_irq(lp
->irq
, lp
);
5624 static void niu_free_irq(struct niu
*np
)
5628 for (i
= 0; i
< np
->num_ldg
; i
++) {
5629 struct niu_ldg
*lp
= &np
->ldg
[i
];
5631 free_irq(lp
->irq
, lp
);
5635 static void niu_enable_napi(struct niu
*np
)
5639 for (i
= 0; i
< np
->num_ldg
; i
++)
5640 napi_enable(&np
->ldg
[i
].napi
);
5643 static void niu_disable_napi(struct niu
*np
)
5647 for (i
= 0; i
< np
->num_ldg
; i
++)
5648 napi_disable(&np
->ldg
[i
].napi
);
5651 static int niu_open(struct net_device
*dev
)
5653 struct niu
*np
= netdev_priv(dev
);
5656 netif_carrier_off(dev
);
5658 err
= niu_alloc_channels(np
);
5662 err
= niu_enable_interrupts(np
, 0);
5664 goto out_free_channels
;
5666 err
= niu_request_irq(np
);
5668 goto out_free_channels
;
5670 niu_enable_napi(np
);
5672 spin_lock_irq(&np
->lock
);
5674 err
= niu_init_hw(np
);
5676 init_timer(&np
->timer
);
5677 np
->timer
.expires
= jiffies
+ HZ
;
5678 np
->timer
.data
= (unsigned long) np
;
5679 np
->timer
.function
= niu_timer
;
5681 err
= niu_enable_interrupts(np
, 1);
5686 spin_unlock_irq(&np
->lock
);
5689 niu_disable_napi(np
);
5693 netif_tx_start_all_queues(dev
);
5695 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
5696 netif_carrier_on(dev
);
5698 add_timer(&np
->timer
);
5706 niu_free_channels(np
);
5712 static void niu_full_shutdown(struct niu
*np
, struct net_device
*dev
)
5714 cancel_work_sync(&np
->reset_task
);
5716 niu_disable_napi(np
);
5717 netif_tx_stop_all_queues(dev
);
5719 del_timer_sync(&np
->timer
);
5721 spin_lock_irq(&np
->lock
);
5725 spin_unlock_irq(&np
->lock
);
5728 static int niu_close(struct net_device
*dev
)
5730 struct niu
*np
= netdev_priv(dev
);
5732 niu_full_shutdown(np
, dev
);
5736 niu_free_channels(np
);
5738 niu_handle_led(np
, 0);
5743 static void niu_sync_xmac_stats(struct niu
*np
)
5745 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
5747 mp
->tx_frames
+= nr64_mac(TXMAC_FRM_CNT
);
5748 mp
->tx_bytes
+= nr64_mac(TXMAC_BYTE_CNT
);
5750 mp
->rx_link_faults
+= nr64_mac(LINK_FAULT_CNT
);
5751 mp
->rx_align_errors
+= nr64_mac(RXMAC_ALIGN_ERR_CNT
);
5752 mp
->rx_frags
+= nr64_mac(RXMAC_FRAG_CNT
);
5753 mp
->rx_mcasts
+= nr64_mac(RXMAC_MC_FRM_CNT
);
5754 mp
->rx_bcasts
+= nr64_mac(RXMAC_BC_FRM_CNT
);
5755 mp
->rx_hist_cnt1
+= nr64_mac(RXMAC_HIST_CNT1
);
5756 mp
->rx_hist_cnt2
+= nr64_mac(RXMAC_HIST_CNT2
);
5757 mp
->rx_hist_cnt3
+= nr64_mac(RXMAC_HIST_CNT3
);
5758 mp
->rx_hist_cnt4
+= nr64_mac(RXMAC_HIST_CNT4
);
5759 mp
->rx_hist_cnt5
+= nr64_mac(RXMAC_HIST_CNT5
);
5760 mp
->rx_hist_cnt6
+= nr64_mac(RXMAC_HIST_CNT6
);
5761 mp
->rx_hist_cnt7
+= nr64_mac(RXMAC_HIST_CNT7
);
5762 mp
->rx_octets
+= nr64_mac(RXMAC_BT_CNT
);
5763 mp
->rx_code_violations
+= nr64_mac(RXMAC_CD_VIO_CNT
);
5764 mp
->rx_len_errors
+= nr64_mac(RXMAC_MPSZER_CNT
);
5765 mp
->rx_crc_errors
+= nr64_mac(RXMAC_CRC_ER_CNT
);
5768 static void niu_sync_bmac_stats(struct niu
*np
)
5770 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
5772 mp
->tx_bytes
+= nr64_mac(BTXMAC_BYTE_CNT
);
5773 mp
->tx_frames
+= nr64_mac(BTXMAC_FRM_CNT
);
5775 mp
->rx_frames
+= nr64_mac(BRXMAC_FRAME_CNT
);
5776 mp
->rx_align_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
5777 mp
->rx_crc_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
5778 mp
->rx_len_errors
+= nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT
);
5781 static void niu_sync_mac_stats(struct niu
*np
)
5783 if (np
->flags
& NIU_FLAGS_XMAC
)
5784 niu_sync_xmac_stats(np
);
5786 niu_sync_bmac_stats(np
);
5789 static void niu_get_rx_stats(struct niu
*np
)
5791 unsigned long pkts
, dropped
, errors
, bytes
;
5794 pkts
= dropped
= errors
= bytes
= 0;
5795 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5796 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5798 pkts
+= rp
->rx_packets
;
5799 bytes
+= rp
->rx_bytes
;
5800 dropped
+= rp
->rx_dropped
;
5801 errors
+= rp
->rx_errors
;
5803 np
->net_stats
.rx_packets
= pkts
;
5804 np
->net_stats
.rx_bytes
= bytes
;
5805 np
->net_stats
.rx_dropped
= dropped
;
5806 np
->net_stats
.rx_errors
= errors
;
5809 static void niu_get_tx_stats(struct niu
*np
)
5811 unsigned long pkts
, errors
, bytes
;
5814 pkts
= errors
= bytes
= 0;
5815 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5816 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5818 pkts
+= rp
->tx_packets
;
5819 bytes
+= rp
->tx_bytes
;
5820 errors
+= rp
->tx_errors
;
5822 np
->net_stats
.tx_packets
= pkts
;
5823 np
->net_stats
.tx_bytes
= bytes
;
5824 np
->net_stats
.tx_errors
= errors
;
5827 static struct net_device_stats
*niu_get_stats(struct net_device
*dev
)
5829 struct niu
*np
= netdev_priv(dev
);
5831 niu_get_rx_stats(np
);
5832 niu_get_tx_stats(np
);
5834 return &np
->net_stats
;
5837 static void niu_load_hash_xmac(struct niu
*np
, u16
*hash
)
5841 for (i
= 0; i
< 16; i
++)
5842 nw64_mac(XMAC_HASH_TBL(i
), hash
[i
]);
5845 static void niu_load_hash_bmac(struct niu
*np
, u16
*hash
)
5849 for (i
= 0; i
< 16; i
++)
5850 nw64_mac(BMAC_HASH_TBL(i
), hash
[i
]);
5853 static void niu_load_hash(struct niu
*np
, u16
*hash
)
5855 if (np
->flags
& NIU_FLAGS_XMAC
)
5856 niu_load_hash_xmac(np
, hash
);
5858 niu_load_hash_bmac(np
, hash
);
5861 static void niu_set_rx_mode(struct net_device
*dev
)
5863 struct niu
*np
= netdev_priv(dev
);
5864 int i
, alt_cnt
, err
;
5865 struct dev_addr_list
*addr
;
5866 unsigned long flags
;
5867 u16 hash
[16] = { 0, };
5869 spin_lock_irqsave(&np
->lock
, flags
);
5870 niu_enable_rx_mac(np
, 0);
5872 np
->flags
&= ~(NIU_FLAGS_MCAST
| NIU_FLAGS_PROMISC
);
5873 if (dev
->flags
& IFF_PROMISC
)
5874 np
->flags
|= NIU_FLAGS_PROMISC
;
5875 if ((dev
->flags
& IFF_ALLMULTI
) || (dev
->mc_count
> 0))
5876 np
->flags
|= NIU_FLAGS_MCAST
;
5878 alt_cnt
= dev
->uc_count
;
5879 if (alt_cnt
> niu_num_alt_addr(np
)) {
5881 np
->flags
|= NIU_FLAGS_PROMISC
;
5887 for (addr
= dev
->uc_list
; addr
; addr
= addr
->next
) {
5888 err
= niu_set_alt_mac(np
, index
,
5891 printk(KERN_WARNING PFX
"%s: Error %d "
5892 "adding alt mac %d\n",
5893 dev
->name
, err
, index
);
5894 err
= niu_enable_alt_mac(np
, index
, 1);
5896 printk(KERN_WARNING PFX
"%s: Error %d "
5897 "enabling alt mac %d\n",
5898 dev
->name
, err
, index
);
5904 if (np
->flags
& NIU_FLAGS_XMAC
)
5908 for (i
= alt_start
; i
< niu_num_alt_addr(np
); i
++) {
5909 err
= niu_enable_alt_mac(np
, i
, 0);
5911 printk(KERN_WARNING PFX
"%s: Error %d "
5912 "disabling alt mac %d\n",
5916 if (dev
->flags
& IFF_ALLMULTI
) {
5917 for (i
= 0; i
< 16; i
++)
5919 } else if (dev
->mc_count
> 0) {
5920 for (addr
= dev
->mc_list
; addr
; addr
= addr
->next
) {
5921 u32 crc
= ether_crc_le(ETH_ALEN
, addr
->da_addr
);
5924 hash
[crc
>> 4] |= (1 << (15 - (crc
& 0xf)));
5928 if (np
->flags
& NIU_FLAGS_MCAST
)
5929 niu_load_hash(np
, hash
);
5931 niu_enable_rx_mac(np
, 1);
5932 spin_unlock_irqrestore(&np
->lock
, flags
);
5935 static int niu_set_mac_addr(struct net_device
*dev
, void *p
)
5937 struct niu
*np
= netdev_priv(dev
);
5938 struct sockaddr
*addr
= p
;
5939 unsigned long flags
;
5941 if (!is_valid_ether_addr(addr
->sa_data
))
5944 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
5946 if (!netif_running(dev
))
5949 spin_lock_irqsave(&np
->lock
, flags
);
5950 niu_enable_rx_mac(np
, 0);
5951 niu_set_primary_mac(np
, dev
->dev_addr
);
5952 niu_enable_rx_mac(np
, 1);
5953 spin_unlock_irqrestore(&np
->lock
, flags
);
5958 static int niu_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
5963 static void niu_netif_stop(struct niu
*np
)
5965 np
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
5967 niu_disable_napi(np
);
5969 netif_tx_disable(np
->dev
);
5972 static void niu_netif_start(struct niu
*np
)
5974 /* NOTE: unconditional netif_wake_queue is only appropriate
5975 * so long as all callers are assured to have free tx slots
5976 * (such as after niu_init_hw).
5978 netif_tx_wake_all_queues(np
->dev
);
5980 niu_enable_napi(np
);
5982 niu_enable_interrupts(np
, 1);
5985 static void niu_reset_buffers(struct niu
*np
)
5990 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5991 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5993 for (j
= 0, k
= 0; j
< MAX_RBR_RING_SIZE
; j
++) {
5996 page
= rp
->rxhash
[j
];
5999 (struct page
*) page
->mapping
;
6000 u64 base
= page
->index
;
6001 base
= base
>> RBR_DESCR_ADDR_SHIFT
;
6002 rp
->rbr
[k
++] = cpu_to_le32(base
);
6006 for (; k
< MAX_RBR_RING_SIZE
; k
++) {
6007 err
= niu_rbr_add_page(np
, rp
, GFP_ATOMIC
, k
);
6012 rp
->rbr_index
= rp
->rbr_table_size
- 1;
6014 rp
->rbr_pending
= 0;
6015 rp
->rbr_refill_pending
= 0;
6019 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6020 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
6022 for (j
= 0; j
< MAX_TX_RING_SIZE
; j
++) {
6023 if (rp
->tx_buffs
[j
].skb
)
6024 (void) release_tx_packet(np
, rp
, j
);
6027 rp
->pending
= MAX_TX_RING_SIZE
;
6035 static void niu_reset_task(struct work_struct
*work
)
6037 struct niu
*np
= container_of(work
, struct niu
, reset_task
);
6038 unsigned long flags
;
6041 spin_lock_irqsave(&np
->lock
, flags
);
6042 if (!netif_running(np
->dev
)) {
6043 spin_unlock_irqrestore(&np
->lock
, flags
);
6047 spin_unlock_irqrestore(&np
->lock
, flags
);
6049 del_timer_sync(&np
->timer
);
6053 spin_lock_irqsave(&np
->lock
, flags
);
6057 spin_unlock_irqrestore(&np
->lock
, flags
);
6059 niu_reset_buffers(np
);
6061 spin_lock_irqsave(&np
->lock
, flags
);
6063 err
= niu_init_hw(np
);
6065 np
->timer
.expires
= jiffies
+ HZ
;
6066 add_timer(&np
->timer
);
6067 niu_netif_start(np
);
6070 spin_unlock_irqrestore(&np
->lock
, flags
);
6073 static void niu_tx_timeout(struct net_device
*dev
)
6075 struct niu
*np
= netdev_priv(dev
);
6077 dev_err(np
->device
, PFX
"%s: Transmit timed out, resetting\n",
6080 schedule_work(&np
->reset_task
);
6083 static void niu_set_txd(struct tx_ring_info
*rp
, int index
,
6084 u64 mapping
, u64 len
, u64 mark
,
6087 __le64
*desc
= &rp
->descr
[index
];
6089 *desc
= cpu_to_le64(mark
|
6090 (n_frags
<< TX_DESC_NUM_PTR_SHIFT
) |
6091 (len
<< TX_DESC_TR_LEN_SHIFT
) |
6092 (mapping
& TX_DESC_SAD
));
6095 static u64
niu_compute_tx_flags(struct sk_buff
*skb
, struct ethhdr
*ehdr
,
6096 u64 pad_bytes
, u64 len
)
6098 u16 eth_proto
, eth_proto_inner
;
6099 u64 csum_bits
, l3off
, ihl
, ret
;
6103 eth_proto
= be16_to_cpu(ehdr
->h_proto
);
6104 eth_proto_inner
= eth_proto
;
6105 if (eth_proto
== ETH_P_8021Q
) {
6106 struct vlan_ethhdr
*vp
= (struct vlan_ethhdr
*) ehdr
;
6107 __be16 val
= vp
->h_vlan_encapsulated_proto
;
6109 eth_proto_inner
= be16_to_cpu(val
);
6113 switch (skb
->protocol
) {
6114 case __constant_htons(ETH_P_IP
):
6115 ip_proto
= ip_hdr(skb
)->protocol
;
6116 ihl
= ip_hdr(skb
)->ihl
;
6118 case __constant_htons(ETH_P_IPV6
):
6119 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
6128 csum_bits
= TXHDR_CSUM_NONE
;
6129 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6132 csum_bits
= (ip_proto
== IPPROTO_TCP
?
6134 (ip_proto
== IPPROTO_UDP
?
6135 TXHDR_CSUM_UDP
: TXHDR_CSUM_SCTP
));
6137 start
= skb_transport_offset(skb
) -
6138 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6139 stuff
= start
+ skb
->csum_offset
;
6141 csum_bits
|= (start
/ 2) << TXHDR_L4START_SHIFT
;
6142 csum_bits
|= (stuff
/ 2) << TXHDR_L4STUFF_SHIFT
;
6145 l3off
= skb_network_offset(skb
) -
6146 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6148 ret
= (((pad_bytes
/ 2) << TXHDR_PAD_SHIFT
) |
6149 (len
<< TXHDR_LEN_SHIFT
) |
6150 ((l3off
/ 2) << TXHDR_L3START_SHIFT
) |
6151 (ihl
<< TXHDR_IHL_SHIFT
) |
6152 ((eth_proto_inner
< 1536) ? TXHDR_LLC
: 0) |
6153 ((eth_proto
== ETH_P_8021Q
) ? TXHDR_VLAN
: 0) |
6154 (ipv6
? TXHDR_IP_VER
: 0) |
6160 static int niu_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
6162 struct niu
*np
= netdev_priv(dev
);
6163 unsigned long align
, headroom
;
6164 struct netdev_queue
*txq
;
6165 struct tx_ring_info
*rp
;
6166 struct tx_pkt_hdr
*tp
;
6167 unsigned int len
, nfg
;
6168 struct ethhdr
*ehdr
;
6172 i
= skb_get_queue_mapping(skb
);
6173 rp
= &np
->tx_rings
[i
];
6174 txq
= netdev_get_tx_queue(dev
, i
);
6176 if (niu_tx_avail(rp
) <= (skb_shinfo(skb
)->nr_frags
+ 1)) {
6177 netif_tx_stop_queue(txq
);
6178 dev_err(np
->device
, PFX
"%s: BUG! Tx ring full when "
6179 "queue awake!\n", dev
->name
);
6181 return NETDEV_TX_BUSY
;
6184 if (skb
->len
< ETH_ZLEN
) {
6185 unsigned int pad_bytes
= ETH_ZLEN
- skb
->len
;
6187 if (skb_pad(skb
, pad_bytes
))
6189 skb_put(skb
, pad_bytes
);
6192 len
= sizeof(struct tx_pkt_hdr
) + 15;
6193 if (skb_headroom(skb
) < len
) {
6194 struct sk_buff
*skb_new
;
6196 skb_new
= skb_realloc_headroom(skb
, len
);
6206 align
= ((unsigned long) skb
->data
& (16 - 1));
6207 headroom
= align
+ sizeof(struct tx_pkt_hdr
);
6209 ehdr
= (struct ethhdr
*) skb
->data
;
6210 tp
= (struct tx_pkt_hdr
*) skb_push(skb
, headroom
);
6212 len
= skb
->len
- sizeof(struct tx_pkt_hdr
);
6213 tp
->flags
= cpu_to_le64(niu_compute_tx_flags(skb
, ehdr
, align
, len
));
6216 len
= skb_headlen(skb
);
6217 mapping
= np
->ops
->map_single(np
->device
, skb
->data
,
6218 len
, DMA_TO_DEVICE
);
6222 rp
->tx_buffs
[prod
].skb
= skb
;
6223 rp
->tx_buffs
[prod
].mapping
= mapping
;
6226 if (++rp
->mark_counter
== rp
->mark_freq
) {
6227 rp
->mark_counter
= 0;
6228 mrk
|= TX_DESC_MARK
;
6233 nfg
= skb_shinfo(skb
)->nr_frags
;
6235 tlen
-= MAX_TX_DESC_LEN
;
6240 unsigned int this_len
= len
;
6242 if (this_len
> MAX_TX_DESC_LEN
)
6243 this_len
= MAX_TX_DESC_LEN
;
6245 niu_set_txd(rp
, prod
, mapping
, this_len
, mrk
, nfg
);
6248 prod
= NEXT_TX(rp
, prod
);
6249 mapping
+= this_len
;
6253 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
6254 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6257 mapping
= np
->ops
->map_page(np
->device
, frag
->page
,
6258 frag
->page_offset
, len
,
6261 rp
->tx_buffs
[prod
].skb
= NULL
;
6262 rp
->tx_buffs
[prod
].mapping
= mapping
;
6264 niu_set_txd(rp
, prod
, mapping
, len
, 0, 0);
6266 prod
= NEXT_TX(rp
, prod
);
6269 if (prod
< rp
->prod
)
6270 rp
->wrap_bit
^= TX_RING_KICK_WRAP
;
6273 nw64(TX_RING_KICK(rp
->tx_channel
), rp
->wrap_bit
| (prod
<< 3));
6275 if (unlikely(niu_tx_avail(rp
) <= (MAX_SKB_FRAGS
+ 1))) {
6276 netif_tx_stop_queue(txq
);
6277 if (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
))
6278 netif_tx_wake_queue(txq
);
6281 dev
->trans_start
= jiffies
;
6284 return NETDEV_TX_OK
;
6292 static int niu_change_mtu(struct net_device
*dev
, int new_mtu
)
6294 struct niu
*np
= netdev_priv(dev
);
6295 int err
, orig_jumbo
, new_jumbo
;
6297 if (new_mtu
< 68 || new_mtu
> NIU_MAX_MTU
)
6300 orig_jumbo
= (dev
->mtu
> ETH_DATA_LEN
);
6301 new_jumbo
= (new_mtu
> ETH_DATA_LEN
);
6305 if (!netif_running(dev
) ||
6306 (orig_jumbo
== new_jumbo
))
6309 niu_full_shutdown(np
, dev
);
6311 niu_free_channels(np
);
6313 niu_enable_napi(np
);
6315 err
= niu_alloc_channels(np
);
6319 spin_lock_irq(&np
->lock
);
6321 err
= niu_init_hw(np
);
6323 init_timer(&np
->timer
);
6324 np
->timer
.expires
= jiffies
+ HZ
;
6325 np
->timer
.data
= (unsigned long) np
;
6326 np
->timer
.function
= niu_timer
;
6328 err
= niu_enable_interrupts(np
, 1);
6333 spin_unlock_irq(&np
->lock
);
6336 netif_tx_start_all_queues(dev
);
6337 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
6338 netif_carrier_on(dev
);
6340 add_timer(&np
->timer
);
6346 static void niu_get_drvinfo(struct net_device
*dev
,
6347 struct ethtool_drvinfo
*info
)
6349 struct niu
*np
= netdev_priv(dev
);
6350 struct niu_vpd
*vpd
= &np
->vpd
;
6352 strcpy(info
->driver
, DRV_MODULE_NAME
);
6353 strcpy(info
->version
, DRV_MODULE_VERSION
);
6354 sprintf(info
->fw_version
, "%d.%d",
6355 vpd
->fcode_major
, vpd
->fcode_minor
);
6356 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
)
6357 strcpy(info
->bus_info
, pci_name(np
->pdev
));
6360 static int niu_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6362 struct niu
*np
= netdev_priv(dev
);
6363 struct niu_link_config
*lp
;
6365 lp
= &np
->link_config
;
6367 memset(cmd
, 0, sizeof(*cmd
));
6368 cmd
->phy_address
= np
->phy_addr
;
6369 cmd
->supported
= lp
->supported
;
6370 cmd
->advertising
= lp
->advertising
;
6371 cmd
->autoneg
= lp
->autoneg
;
6372 cmd
->speed
= lp
->active_speed
;
6373 cmd
->duplex
= lp
->active_duplex
;
6378 static int niu_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6383 static u32
niu_get_msglevel(struct net_device
*dev
)
6385 struct niu
*np
= netdev_priv(dev
);
6386 return np
->msg_enable
;
6389 static void niu_set_msglevel(struct net_device
*dev
, u32 value
)
6391 struct niu
*np
= netdev_priv(dev
);
6392 np
->msg_enable
= value
;
6395 static int niu_get_eeprom_len(struct net_device
*dev
)
6397 struct niu
*np
= netdev_priv(dev
);
6399 return np
->eeprom_len
;
6402 static int niu_get_eeprom(struct net_device
*dev
,
6403 struct ethtool_eeprom
*eeprom
, u8
*data
)
6405 struct niu
*np
= netdev_priv(dev
);
6406 u32 offset
, len
, val
;
6408 offset
= eeprom
->offset
;
6411 if (offset
+ len
< offset
)
6413 if (offset
>= np
->eeprom_len
)
6415 if (offset
+ len
> np
->eeprom_len
)
6416 len
= eeprom
->len
= np
->eeprom_len
- offset
;
6419 u32 b_offset
, b_count
;
6421 b_offset
= offset
& 3;
6422 b_count
= 4 - b_offset
;
6426 val
= nr64(ESPC_NCR((offset
- b_offset
) / 4));
6427 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
6433 val
= nr64(ESPC_NCR(offset
/ 4));
6434 memcpy(data
, &val
, 4);
6440 val
= nr64(ESPC_NCR(offset
/ 4));
6441 memcpy(data
, &val
, len
);
6446 static int niu_ethflow_to_class(int flow_type
, u64
*class)
6448 switch (flow_type
) {
6450 *class = CLASS_CODE_TCP_IPV4
;
6453 *class = CLASS_CODE_UDP_IPV4
;
6455 case AH_ESP_V4_FLOW
:
6456 *class = CLASS_CODE_AH_ESP_IPV4
;
6459 *class = CLASS_CODE_SCTP_IPV4
;
6462 *class = CLASS_CODE_TCP_IPV6
;
6465 *class = CLASS_CODE_UDP_IPV6
;
6467 case AH_ESP_V6_FLOW
:
6468 *class = CLASS_CODE_AH_ESP_IPV6
;
6471 *class = CLASS_CODE_SCTP_IPV6
;
6480 static u64
niu_flowkey_to_ethflow(u64 flow_key
)
6484 if (flow_key
& FLOW_KEY_PORT
)
6485 ethflow
|= RXH_DEV_PORT
;
6486 if (flow_key
& FLOW_KEY_L2DA
)
6487 ethflow
|= RXH_L2DA
;
6488 if (flow_key
& FLOW_KEY_VLAN
)
6489 ethflow
|= RXH_VLAN
;
6490 if (flow_key
& FLOW_KEY_IPSA
)
6491 ethflow
|= RXH_IP_SRC
;
6492 if (flow_key
& FLOW_KEY_IPDA
)
6493 ethflow
|= RXH_IP_DST
;
6494 if (flow_key
& FLOW_KEY_PROTO
)
6495 ethflow
|= RXH_L3_PROTO
;
6496 if (flow_key
& (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_0_SHIFT
))
6497 ethflow
|= RXH_L4_B_0_1
;
6498 if (flow_key
& (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_1_SHIFT
))
6499 ethflow
|= RXH_L4_B_2_3
;
6505 static int niu_ethflow_to_flowkey(u64 ethflow
, u64
*flow_key
)
6509 if (ethflow
& RXH_DEV_PORT
)
6510 key
|= FLOW_KEY_PORT
;
6511 if (ethflow
& RXH_L2DA
)
6512 key
|= FLOW_KEY_L2DA
;
6513 if (ethflow
& RXH_VLAN
)
6514 key
|= FLOW_KEY_VLAN
;
6515 if (ethflow
& RXH_IP_SRC
)
6516 key
|= FLOW_KEY_IPSA
;
6517 if (ethflow
& RXH_IP_DST
)
6518 key
|= FLOW_KEY_IPDA
;
6519 if (ethflow
& RXH_L3_PROTO
)
6520 key
|= FLOW_KEY_PROTO
;
6521 if (ethflow
& RXH_L4_B_0_1
)
6522 key
|= (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_0_SHIFT
);
6523 if (ethflow
& RXH_L4_B_2_3
)
6524 key
|= (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_1_SHIFT
);
6532 static int niu_get_hash_opts(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
)
6534 struct niu
*np
= netdev_priv(dev
);
6539 if (!niu_ethflow_to_class(cmd
->flow_type
, &class))
6542 if (np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] &
6544 cmd
->data
= RXH_DISCARD
;
6547 cmd
->data
= niu_flowkey_to_ethflow(np
->parent
->flow_key
[class -
6548 CLASS_CODE_USER_PROG1
]);
6552 static int niu_set_hash_opts(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
)
6554 struct niu
*np
= netdev_priv(dev
);
6557 unsigned long flags
;
6559 if (!niu_ethflow_to_class(cmd
->flow_type
, &class))
6562 if (class < CLASS_CODE_USER_PROG1
||
6563 class > CLASS_CODE_SCTP_IPV6
)
6566 if (cmd
->data
& RXH_DISCARD
) {
6567 niu_lock_parent(np
, flags
);
6568 flow_key
= np
->parent
->tcam_key
[class -
6569 CLASS_CODE_USER_PROG1
];
6570 flow_key
|= TCAM_KEY_DISC
;
6571 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1
), flow_key
);
6572 np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] = flow_key
;
6573 niu_unlock_parent(np
, flags
);
6576 /* Discard was set before, but is not set now */
6577 if (np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] &
6579 niu_lock_parent(np
, flags
);
6580 flow_key
= np
->parent
->tcam_key
[class -
6581 CLASS_CODE_USER_PROG1
];
6582 flow_key
&= ~TCAM_KEY_DISC
;
6583 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1
),
6585 np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] =
6587 niu_unlock_parent(np
, flags
);
6591 if (!niu_ethflow_to_flowkey(cmd
->data
, &flow_key
))
6594 niu_lock_parent(np
, flags
);
6595 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1
), flow_key
);
6596 np
->parent
->flow_key
[class - CLASS_CODE_USER_PROG1
] = flow_key
;
6597 niu_unlock_parent(np
, flags
);
6602 static const struct {
6603 const char string
[ETH_GSTRING_LEN
];
6604 } niu_xmac_stat_keys
[] = {
6607 { "tx_fifo_errors" },
6608 { "tx_overflow_errors" },
6609 { "tx_max_pkt_size_errors" },
6610 { "tx_underflow_errors" },
6611 { "rx_local_faults" },
6612 { "rx_remote_faults" },
6613 { "rx_link_faults" },
6614 { "rx_align_errors" },
6626 { "rx_code_violations" },
6627 { "rx_len_errors" },
6628 { "rx_crc_errors" },
6629 { "rx_underflows" },
6631 { "pause_off_state" },
6632 { "pause_on_state" },
6633 { "pause_received" },
6636 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
6638 static const struct {
6639 const char string
[ETH_GSTRING_LEN
];
6640 } niu_bmac_stat_keys
[] = {
6641 { "tx_underflow_errors" },
6642 { "tx_max_pkt_size_errors" },
6647 { "rx_align_errors" },
6648 { "rx_crc_errors" },
6649 { "rx_len_errors" },
6650 { "pause_off_state" },
6651 { "pause_on_state" },
6652 { "pause_received" },
6655 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
6657 static const struct {
6658 const char string
[ETH_GSTRING_LEN
];
6659 } niu_rxchan_stat_keys
[] = {
6667 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
6669 static const struct {
6670 const char string
[ETH_GSTRING_LEN
];
6671 } niu_txchan_stat_keys
[] = {
6678 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
6680 static void niu_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
6682 struct niu
*np
= netdev_priv(dev
);
6685 if (stringset
!= ETH_SS_STATS
)
6688 if (np
->flags
& NIU_FLAGS_XMAC
) {
6689 memcpy(data
, niu_xmac_stat_keys
,
6690 sizeof(niu_xmac_stat_keys
));
6691 data
+= sizeof(niu_xmac_stat_keys
);
6693 memcpy(data
, niu_bmac_stat_keys
,
6694 sizeof(niu_bmac_stat_keys
));
6695 data
+= sizeof(niu_bmac_stat_keys
);
6697 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6698 memcpy(data
, niu_rxchan_stat_keys
,
6699 sizeof(niu_rxchan_stat_keys
));
6700 data
+= sizeof(niu_rxchan_stat_keys
);
6702 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6703 memcpy(data
, niu_txchan_stat_keys
,
6704 sizeof(niu_txchan_stat_keys
));
6705 data
+= sizeof(niu_txchan_stat_keys
);
6709 static int niu_get_stats_count(struct net_device
*dev
)
6711 struct niu
*np
= netdev_priv(dev
);
6713 return ((np
->flags
& NIU_FLAGS_XMAC
?
6714 NUM_XMAC_STAT_KEYS
:
6715 NUM_BMAC_STAT_KEYS
) +
6716 (np
->num_rx_rings
* NUM_RXCHAN_STAT_KEYS
) +
6717 (np
->num_tx_rings
* NUM_TXCHAN_STAT_KEYS
));
6720 static void niu_get_ethtool_stats(struct net_device
*dev
,
6721 struct ethtool_stats
*stats
, u64
*data
)
6723 struct niu
*np
= netdev_priv(dev
);
6726 niu_sync_mac_stats(np
);
6727 if (np
->flags
& NIU_FLAGS_XMAC
) {
6728 memcpy(data
, &np
->mac_stats
.xmac
,
6729 sizeof(struct niu_xmac_stats
));
6730 data
+= (sizeof(struct niu_xmac_stats
) / sizeof(u64
));
6732 memcpy(data
, &np
->mac_stats
.bmac
,
6733 sizeof(struct niu_bmac_stats
));
6734 data
+= (sizeof(struct niu_bmac_stats
) / sizeof(u64
));
6736 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6737 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
6739 data
[0] = rp
->rx_channel
;
6740 data
[1] = rp
->rx_packets
;
6741 data
[2] = rp
->rx_bytes
;
6742 data
[3] = rp
->rx_dropped
;
6743 data
[4] = rp
->rx_errors
;
6746 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6747 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
6749 data
[0] = rp
->tx_channel
;
6750 data
[1] = rp
->tx_packets
;
6751 data
[2] = rp
->tx_bytes
;
6752 data
[3] = rp
->tx_errors
;
6757 static u64
niu_led_state_save(struct niu
*np
)
6759 if (np
->flags
& NIU_FLAGS_XMAC
)
6760 return nr64_mac(XMAC_CONFIG
);
6762 return nr64_mac(BMAC_XIF_CONFIG
);
6765 static void niu_led_state_restore(struct niu
*np
, u64 val
)
6767 if (np
->flags
& NIU_FLAGS_XMAC
)
6768 nw64_mac(XMAC_CONFIG
, val
);
6770 nw64_mac(BMAC_XIF_CONFIG
, val
);
6773 static void niu_force_led(struct niu
*np
, int on
)
6777 if (np
->flags
& NIU_FLAGS_XMAC
) {
6779 bit
= XMAC_CONFIG_FORCE_LED_ON
;
6781 reg
= BMAC_XIF_CONFIG
;
6782 bit
= BMAC_XIF_CONFIG_LINK_LED
;
6785 val
= nr64_mac(reg
);
6793 static int niu_phys_id(struct net_device
*dev
, u32 data
)
6795 struct niu
*np
= netdev_priv(dev
);
6799 if (!netif_running(dev
))
6805 orig_led_state
= niu_led_state_save(np
);
6806 for (i
= 0; i
< (data
* 2); i
++) {
6807 int on
= ((i
% 2) == 0);
6809 niu_force_led(np
, on
);
6811 if (msleep_interruptible(500))
6814 niu_led_state_restore(np
, orig_led_state
);
6819 static const struct ethtool_ops niu_ethtool_ops
= {
6820 .get_drvinfo
= niu_get_drvinfo
,
6821 .get_link
= ethtool_op_get_link
,
6822 .get_msglevel
= niu_get_msglevel
,
6823 .set_msglevel
= niu_set_msglevel
,
6824 .get_eeprom_len
= niu_get_eeprom_len
,
6825 .get_eeprom
= niu_get_eeprom
,
6826 .get_settings
= niu_get_settings
,
6827 .set_settings
= niu_set_settings
,
6828 .get_strings
= niu_get_strings
,
6829 .get_stats_count
= niu_get_stats_count
,
6830 .get_ethtool_stats
= niu_get_ethtool_stats
,
6831 .phys_id
= niu_phys_id
,
6832 .get_rxhash
= niu_get_hash_opts
,
6833 .set_rxhash
= niu_set_hash_opts
,
6836 static int niu_ldg_assign_ldn(struct niu
*np
, struct niu_parent
*parent
,
6839 if (ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
)
6841 if (ldn
< 0 || ldn
> LDN_MAX
)
6844 parent
->ldg_map
[ldn
] = ldg
;
6846 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
) {
6847 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
6848 * the firmware, and we're not supposed to change them.
6849 * Validate the mapping, because if it's wrong we probably
6850 * won't get any interrupts and that's painful to debug.
6852 if (nr64(LDG_NUM(ldn
)) != ldg
) {
6853 dev_err(np
->device
, PFX
"Port %u, mis-matched "
6855 "for ldn %d, should be %d is %llu\n",
6857 (unsigned long long) nr64(LDG_NUM(ldn
)));
6861 nw64(LDG_NUM(ldn
), ldg
);
6866 static int niu_set_ldg_timer_res(struct niu
*np
, int res
)
6868 if (res
< 0 || res
> LDG_TIMER_RES_VAL
)
6872 nw64(LDG_TIMER_RES
, res
);
6877 static int niu_set_ldg_sid(struct niu
*np
, int ldg
, int func
, int vector
)
6879 if ((ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
) ||
6880 (func
< 0 || func
> 3) ||
6881 (vector
< 0 || vector
> 0x1f))
6884 nw64(SID(ldg
), (func
<< SID_FUNC_SHIFT
) | vector
);
6889 static int __devinit
niu_pci_eeprom_read(struct niu
*np
, u32 addr
)
6891 u64 frame
, frame_base
= (ESPC_PIO_STAT_READ_START
|
6892 (addr
<< ESPC_PIO_STAT_ADDR_SHIFT
));
6895 if (addr
> (ESPC_PIO_STAT_ADDR
>> ESPC_PIO_STAT_ADDR_SHIFT
))
6899 nw64(ESPC_PIO_STAT
, frame
);
6903 frame
= nr64(ESPC_PIO_STAT
);
6904 if (frame
& ESPC_PIO_STAT_READ_END
)
6907 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
6908 dev_err(np
->device
, PFX
"EEPROM read timeout frame[%llx]\n",
6909 (unsigned long long) frame
);
6914 nw64(ESPC_PIO_STAT
, frame
);
6918 frame
= nr64(ESPC_PIO_STAT
);
6919 if (frame
& ESPC_PIO_STAT_READ_END
)
6922 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
6923 dev_err(np
->device
, PFX
"EEPROM read timeout frame[%llx]\n",
6924 (unsigned long long) frame
);
6928 frame
= nr64(ESPC_PIO_STAT
);
6929 return (frame
& ESPC_PIO_STAT_DATA
) >> ESPC_PIO_STAT_DATA_SHIFT
;
6932 static int __devinit
niu_pci_eeprom_read16(struct niu
*np
, u32 off
)
6934 int err
= niu_pci_eeprom_read(np
, off
);
6940 err
= niu_pci_eeprom_read(np
, off
+ 1);
6943 val
|= (err
& 0xff);
6948 static int __devinit
niu_pci_eeprom_read16_swp(struct niu
*np
, u32 off
)
6950 int err
= niu_pci_eeprom_read(np
, off
);
6957 err
= niu_pci_eeprom_read(np
, off
+ 1);
6961 val
|= (err
& 0xff) << 8;
6966 static int __devinit
niu_pci_vpd_get_propname(struct niu
*np
,
6973 for (i
= 0; i
< namebuf_len
; i
++) {
6974 int err
= niu_pci_eeprom_read(np
, off
+ i
);
6981 if (i
>= namebuf_len
)
6987 static void __devinit
niu_vpd_parse_version(struct niu
*np
)
6989 struct niu_vpd
*vpd
= &np
->vpd
;
6990 int len
= strlen(vpd
->version
) + 1;
6991 const char *s
= vpd
->version
;
6994 for (i
= 0; i
< len
- 5; i
++) {
6995 if (!strncmp(s
+ i
, "FCode ", 5))
7002 sscanf(s
, "%d.%d", &vpd
->fcode_major
, &vpd
->fcode_minor
);
7004 niudbg(PROBE
, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
7005 vpd
->fcode_major
, vpd
->fcode_minor
);
7006 if (vpd
->fcode_major
> NIU_VPD_MIN_MAJOR
||
7007 (vpd
->fcode_major
== NIU_VPD_MIN_MAJOR
&&
7008 vpd
->fcode_minor
>= NIU_VPD_MIN_MINOR
))
7009 np
->flags
|= NIU_FLAGS_VPD_VALID
;
7012 /* ESPC_PIO_EN_ENABLE must be set */
7013 static int __devinit
niu_pci_vpd_scan_props(struct niu
*np
,
7016 unsigned int found_mask
= 0;
7017 #define FOUND_MASK_MODEL 0x00000001
7018 #define FOUND_MASK_BMODEL 0x00000002
7019 #define FOUND_MASK_VERS 0x00000004
7020 #define FOUND_MASK_MAC 0x00000008
7021 #define FOUND_MASK_NMAC 0x00000010
7022 #define FOUND_MASK_PHY 0x00000020
7023 #define FOUND_MASK_ALL 0x0000003f
7025 niudbg(PROBE
, "VPD_SCAN: start[%x] end[%x]\n",
7027 while (start
< end
) {
7028 int len
, err
, instance
, type
, prop_len
;
7033 if (found_mask
== FOUND_MASK_ALL
) {
7034 niu_vpd_parse_version(np
);
7038 err
= niu_pci_eeprom_read(np
, start
+ 2);
7044 instance
= niu_pci_eeprom_read(np
, start
);
7045 type
= niu_pci_eeprom_read(np
, start
+ 3);
7046 prop_len
= niu_pci_eeprom_read(np
, start
+ 4);
7047 err
= niu_pci_vpd_get_propname(np
, start
+ 5, namebuf
, 64);
7053 if (!strcmp(namebuf
, "model")) {
7054 prop_buf
= np
->vpd
.model
;
7055 max_len
= NIU_VPD_MODEL_MAX
;
7056 found_mask
|= FOUND_MASK_MODEL
;
7057 } else if (!strcmp(namebuf
, "board-model")) {
7058 prop_buf
= np
->vpd
.board_model
;
7059 max_len
= NIU_VPD_BD_MODEL_MAX
;
7060 found_mask
|= FOUND_MASK_BMODEL
;
7061 } else if (!strcmp(namebuf
, "version")) {
7062 prop_buf
= np
->vpd
.version
;
7063 max_len
= NIU_VPD_VERSION_MAX
;
7064 found_mask
|= FOUND_MASK_VERS
;
7065 } else if (!strcmp(namebuf
, "local-mac-address")) {
7066 prop_buf
= np
->vpd
.local_mac
;
7068 found_mask
|= FOUND_MASK_MAC
;
7069 } else if (!strcmp(namebuf
, "num-mac-addresses")) {
7070 prop_buf
= &np
->vpd
.mac_num
;
7072 found_mask
|= FOUND_MASK_NMAC
;
7073 } else if (!strcmp(namebuf
, "phy-type")) {
7074 prop_buf
= np
->vpd
.phy_type
;
7075 max_len
= NIU_VPD_PHY_TYPE_MAX
;
7076 found_mask
|= FOUND_MASK_PHY
;
7079 if (max_len
&& prop_len
> max_len
) {
7080 dev_err(np
->device
, PFX
"Property '%s' length (%d) is "
7081 "too long.\n", namebuf
, prop_len
);
7086 u32 off
= start
+ 5 + err
;
7089 niudbg(PROBE
, "VPD_SCAN: Reading in property [%s] "
7090 "len[%d]\n", namebuf
, prop_len
);
7091 for (i
= 0; i
< prop_len
; i
++)
7092 *prop_buf
++ = niu_pci_eeprom_read(np
, off
+ i
);
7101 /* ESPC_PIO_EN_ENABLE must be set */
7102 static void __devinit
niu_pci_vpd_fetch(struct niu
*np
, u32 start
)
7107 err
= niu_pci_eeprom_read16_swp(np
, start
+ 1);
7113 while (start
+ offset
< ESPC_EEPROM_SIZE
) {
7114 u32 here
= start
+ offset
;
7117 err
= niu_pci_eeprom_read(np
, here
);
7121 err
= niu_pci_eeprom_read16_swp(np
, here
+ 1);
7125 here
= start
+ offset
+ 3;
7126 end
= start
+ offset
+ err
;
7130 err
= niu_pci_vpd_scan_props(np
, here
, end
);
7131 if (err
< 0 || err
== 1)
7136 /* ESPC_PIO_EN_ENABLE must be set */
7137 static u32 __devinit
niu_pci_vpd_offset(struct niu
*np
)
7139 u32 start
= 0, end
= ESPC_EEPROM_SIZE
, ret
;
7142 while (start
< end
) {
7145 /* ROM header signature? */
7146 err
= niu_pci_eeprom_read16(np
, start
+ 0);
7150 /* Apply offset to PCI data structure. */
7151 err
= niu_pci_eeprom_read16(np
, start
+ 23);
7156 /* Check for "PCIR" signature. */
7157 err
= niu_pci_eeprom_read16(np
, start
+ 0);
7160 err
= niu_pci_eeprom_read16(np
, start
+ 2);
7164 /* Check for OBP image type. */
7165 err
= niu_pci_eeprom_read(np
, start
+ 20);
7169 err
= niu_pci_eeprom_read(np
, ret
+ 2);
7173 start
= ret
+ (err
* 512);
7177 err
= niu_pci_eeprom_read16_swp(np
, start
+ 8);
7182 err
= niu_pci_eeprom_read(np
, ret
+ 0);
7192 static int __devinit
niu_phy_type_prop_decode(struct niu
*np
,
7193 const char *phy_prop
)
7195 if (!strcmp(phy_prop
, "mif")) {
7196 /* 1G copper, MII */
7197 np
->flags
&= ~(NIU_FLAGS_FIBER
|
7199 np
->mac_xcvr
= MAC_XCVR_MII
;
7200 } else if (!strcmp(phy_prop
, "xgf")) {
7201 /* 10G fiber, XPCS */
7202 np
->flags
|= (NIU_FLAGS_10G
|
7204 np
->mac_xcvr
= MAC_XCVR_XPCS
;
7205 } else if (!strcmp(phy_prop
, "pcs")) {
7207 np
->flags
&= ~NIU_FLAGS_10G
;
7208 np
->flags
|= NIU_FLAGS_FIBER
;
7209 np
->mac_xcvr
= MAC_XCVR_PCS
;
7210 } else if (!strcmp(phy_prop
, "xgc")) {
7211 /* 10G copper, XPCS */
7212 np
->flags
|= NIU_FLAGS_10G
;
7213 np
->flags
&= ~NIU_FLAGS_FIBER
;
7214 np
->mac_xcvr
= MAC_XCVR_XPCS
;
7221 static int niu_pci_vpd_get_nports(struct niu
*np
)
7225 if ((!strcmp(np
->vpd
.model
, NIU_QGC_LP_MDL_STR
)) ||
7226 (!strcmp(np
->vpd
.model
, NIU_QGC_PEM_MDL_STR
)) ||
7227 (!strcmp(np
->vpd
.model
, NIU_MARAMBA_MDL_STR
)) ||
7228 (!strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) ||
7229 (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
))) {
7231 } else if ((!strcmp(np
->vpd
.model
, NIU_2XGF_LP_MDL_STR
)) ||
7232 (!strcmp(np
->vpd
.model
, NIU_2XGF_PEM_MDL_STR
)) ||
7233 (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) ||
7234 (!strcmp(np
->vpd
.model
, NIU_2XGF_MRVL_MDL_STR
))) {
7241 static void __devinit
niu_pci_vpd_validate(struct niu
*np
)
7243 struct net_device
*dev
= np
->dev
;
7244 struct niu_vpd
*vpd
= &np
->vpd
;
7247 if (!is_valid_ether_addr(&vpd
->local_mac
[0])) {
7248 dev_err(np
->device
, PFX
"VPD MAC invalid, "
7249 "falling back to SPROM.\n");
7251 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
7255 if (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
) ||
7256 !strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) {
7257 np
->flags
|= NIU_FLAGS_10G
;
7258 np
->flags
&= ~NIU_FLAGS_FIBER
;
7259 np
->flags
|= NIU_FLAGS_XCVR_SERDES
;
7260 np
->mac_xcvr
= MAC_XCVR_PCS
;
7262 np
->flags
|= NIU_FLAGS_FIBER
;
7263 np
->flags
&= ~NIU_FLAGS_10G
;
7265 if (np
->flags
& NIU_FLAGS_10G
)
7266 np
->mac_xcvr
= MAC_XCVR_XPCS
;
7267 } else if (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) {
7268 np
->flags
|= (NIU_FLAGS_10G
| NIU_FLAGS_FIBER
|
7269 NIU_FLAGS_HOTPLUG_PHY
);
7270 } else if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
7271 dev_err(np
->device
, PFX
"Illegal phy string [%s].\n",
7273 dev_err(np
->device
, PFX
"Falling back to SPROM.\n");
7274 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
7278 memcpy(dev
->perm_addr
, vpd
->local_mac
, ETH_ALEN
);
7280 val8
= dev
->perm_addr
[5];
7281 dev
->perm_addr
[5] += np
->port
;
7282 if (dev
->perm_addr
[5] < val8
)
7283 dev
->perm_addr
[4]++;
7285 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
7288 static int __devinit
niu_pci_probe_sprom(struct niu
*np
)
7290 struct net_device
*dev
= np
->dev
;
7295 val
= (nr64(ESPC_VER_IMGSZ
) & ESPC_VER_IMGSZ_IMGSZ
);
7296 val
>>= ESPC_VER_IMGSZ_IMGSZ_SHIFT
;
7299 np
->eeprom_len
= len
;
7301 niudbg(PROBE
, "SPROM: Image size %llu\n", (unsigned long long) val
);
7304 for (i
= 0; i
< len
; i
++) {
7305 val
= nr64(ESPC_NCR(i
));
7306 sum
+= (val
>> 0) & 0xff;
7307 sum
+= (val
>> 8) & 0xff;
7308 sum
+= (val
>> 16) & 0xff;
7309 sum
+= (val
>> 24) & 0xff;
7311 niudbg(PROBE
, "SPROM: Checksum %x\n", (int)(sum
& 0xff));
7312 if ((sum
& 0xff) != 0xab) {
7313 dev_err(np
->device
, PFX
"Bad SPROM checksum "
7314 "(%x, should be 0xab)\n", (int) (sum
& 0xff));
7318 val
= nr64(ESPC_PHY_TYPE
);
7321 val8
= (val
& ESPC_PHY_TYPE_PORT0
) >>
7322 ESPC_PHY_TYPE_PORT0_SHIFT
;
7325 val8
= (val
& ESPC_PHY_TYPE_PORT1
) >>
7326 ESPC_PHY_TYPE_PORT1_SHIFT
;
7329 val8
= (val
& ESPC_PHY_TYPE_PORT2
) >>
7330 ESPC_PHY_TYPE_PORT2_SHIFT
;
7333 val8
= (val
& ESPC_PHY_TYPE_PORT3
) >>
7334 ESPC_PHY_TYPE_PORT3_SHIFT
;
7337 dev_err(np
->device
, PFX
"Bogus port number %u\n",
7341 niudbg(PROBE
, "SPROM: PHY type %x\n", val8
);
7344 case ESPC_PHY_TYPE_1G_COPPER
:
7345 /* 1G copper, MII */
7346 np
->flags
&= ~(NIU_FLAGS_FIBER
|
7348 np
->mac_xcvr
= MAC_XCVR_MII
;
7351 case ESPC_PHY_TYPE_1G_FIBER
:
7353 np
->flags
&= ~NIU_FLAGS_10G
;
7354 np
->flags
|= NIU_FLAGS_FIBER
;
7355 np
->mac_xcvr
= MAC_XCVR_PCS
;
7358 case ESPC_PHY_TYPE_10G_COPPER
:
7359 /* 10G copper, XPCS */
7360 np
->flags
|= NIU_FLAGS_10G
;
7361 np
->flags
&= ~NIU_FLAGS_FIBER
;
7362 np
->mac_xcvr
= MAC_XCVR_XPCS
;
7365 case ESPC_PHY_TYPE_10G_FIBER
:
7366 /* 10G fiber, XPCS */
7367 np
->flags
|= (NIU_FLAGS_10G
|
7369 np
->mac_xcvr
= MAC_XCVR_XPCS
;
7373 dev_err(np
->device
, PFX
"Bogus SPROM phy type %u\n", val8
);
7377 val
= nr64(ESPC_MAC_ADDR0
);
7378 niudbg(PROBE
, "SPROM: MAC_ADDR0[%08llx]\n",
7379 (unsigned long long) val
);
7380 dev
->perm_addr
[0] = (val
>> 0) & 0xff;
7381 dev
->perm_addr
[1] = (val
>> 8) & 0xff;
7382 dev
->perm_addr
[2] = (val
>> 16) & 0xff;
7383 dev
->perm_addr
[3] = (val
>> 24) & 0xff;
7385 val
= nr64(ESPC_MAC_ADDR1
);
7386 niudbg(PROBE
, "SPROM: MAC_ADDR1[%08llx]\n",
7387 (unsigned long long) val
);
7388 dev
->perm_addr
[4] = (val
>> 0) & 0xff;
7389 dev
->perm_addr
[5] = (val
>> 8) & 0xff;
7391 if (!is_valid_ether_addr(&dev
->perm_addr
[0])) {
7392 dev_err(np
->device
, PFX
"SPROM MAC address invalid\n");
7393 dev_err(np
->device
, PFX
"[ \n");
7394 for (i
= 0; i
< 6; i
++)
7395 printk("%02x ", dev
->perm_addr
[i
]);
7400 val8
= dev
->perm_addr
[5];
7401 dev
->perm_addr
[5] += np
->port
;
7402 if (dev
->perm_addr
[5] < val8
)
7403 dev
->perm_addr
[4]++;
7405 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
7407 val
= nr64(ESPC_MOD_STR_LEN
);
7408 niudbg(PROBE
, "SPROM: MOD_STR_LEN[%llu]\n",
7409 (unsigned long long) val
);
7413 for (i
= 0; i
< val
; i
+= 4) {
7414 u64 tmp
= nr64(ESPC_NCR(5 + (i
/ 4)));
7416 np
->vpd
.model
[i
+ 3] = (tmp
>> 0) & 0xff;
7417 np
->vpd
.model
[i
+ 2] = (tmp
>> 8) & 0xff;
7418 np
->vpd
.model
[i
+ 1] = (tmp
>> 16) & 0xff;
7419 np
->vpd
.model
[i
+ 0] = (tmp
>> 24) & 0xff;
7421 np
->vpd
.model
[val
] = '\0';
7423 val
= nr64(ESPC_BD_MOD_STR_LEN
);
7424 niudbg(PROBE
, "SPROM: BD_MOD_STR_LEN[%llu]\n",
7425 (unsigned long long) val
);
7429 for (i
= 0; i
< val
; i
+= 4) {
7430 u64 tmp
= nr64(ESPC_NCR(14 + (i
/ 4)));
7432 np
->vpd
.board_model
[i
+ 3] = (tmp
>> 0) & 0xff;
7433 np
->vpd
.board_model
[i
+ 2] = (tmp
>> 8) & 0xff;
7434 np
->vpd
.board_model
[i
+ 1] = (tmp
>> 16) & 0xff;
7435 np
->vpd
.board_model
[i
+ 0] = (tmp
>> 24) & 0xff;
7437 np
->vpd
.board_model
[val
] = '\0';
7440 nr64(ESPC_NUM_PORTS_MACS
) & ESPC_NUM_PORTS_MACS_VAL
;
7441 niudbg(PROBE
, "SPROM: NUM_PORTS_MACS[%d]\n",
7447 static int __devinit
niu_get_and_validate_port(struct niu
*np
)
7449 struct niu_parent
*parent
= np
->parent
;
7452 np
->flags
|= NIU_FLAGS_XMAC
;
7454 if (!parent
->num_ports
) {
7455 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
7456 parent
->num_ports
= 2;
7458 parent
->num_ports
= niu_pci_vpd_get_nports(np
);
7459 if (!parent
->num_ports
) {
7460 /* Fall back to SPROM as last resort.
7461 * This will fail on most cards.
7463 parent
->num_ports
= nr64(ESPC_NUM_PORTS_MACS
) &
7464 ESPC_NUM_PORTS_MACS_VAL
;
7466 /* All of the current probing methods fail on
7467 * Maramba on-board parts.
7469 if (!parent
->num_ports
)
7470 parent
->num_ports
= 4;
7475 niudbg(PROBE
, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
7476 np
->port
, parent
->num_ports
);
7477 if (np
->port
>= parent
->num_ports
)
7483 static int __devinit
phy_record(struct niu_parent
*parent
,
7484 struct phy_probe_info
*p
,
7485 int dev_id_1
, int dev_id_2
, u8 phy_port
,
7488 u32 id
= (dev_id_1
<< 16) | dev_id_2
;
7491 if (dev_id_1
< 0 || dev_id_2
< 0)
7493 if (type
== PHY_TYPE_PMA_PMD
|| type
== PHY_TYPE_PCS
) {
7494 if (((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM8704
) &&
7495 ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_MRVL88X2011
) &&
7496 ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM8706
))
7499 if ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM5464R
)
7503 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
7505 (type
== PHY_TYPE_PMA_PMD
?
7507 (type
== PHY_TYPE_PCS
?
7511 if (p
->cur
[type
] >= NIU_MAX_PORTS
) {
7512 printk(KERN_ERR PFX
"Too many PHY ports.\n");
7516 p
->phy_id
[type
][idx
] = id
;
7517 p
->phy_port
[type
][idx
] = phy_port
;
7518 p
->cur
[type
] = idx
+ 1;
7522 static int __devinit
port_has_10g(struct phy_probe_info
*p
, int port
)
7526 for (i
= 0; i
< p
->cur
[PHY_TYPE_PMA_PMD
]; i
++) {
7527 if (p
->phy_port
[PHY_TYPE_PMA_PMD
][i
] == port
)
7530 for (i
= 0; i
< p
->cur
[PHY_TYPE_PCS
]; i
++) {
7531 if (p
->phy_port
[PHY_TYPE_PCS
][i
] == port
)
7538 static int __devinit
count_10g_ports(struct phy_probe_info
*p
, int *lowest
)
7544 for (port
= 8; port
< 32; port
++) {
7545 if (port_has_10g(p
, port
)) {
7555 static int __devinit
count_1g_ports(struct phy_probe_info
*p
, int *lowest
)
7558 if (p
->cur
[PHY_TYPE_MII
])
7559 *lowest
= p
->phy_port
[PHY_TYPE_MII
][0];
7561 return p
->cur
[PHY_TYPE_MII
];
7564 static void __devinit
niu_n2_divide_channels(struct niu_parent
*parent
)
7566 int num_ports
= parent
->num_ports
;
7569 for (i
= 0; i
< num_ports
; i
++) {
7570 parent
->rxchan_per_port
[i
] = (16 / num_ports
);
7571 parent
->txchan_per_port
[i
] = (16 / num_ports
);
7573 pr_info(PFX
"niu%d: Port %u [%u RX chans] "
7576 parent
->rxchan_per_port
[i
],
7577 parent
->txchan_per_port
[i
]);
7581 static void __devinit
niu_divide_channels(struct niu_parent
*parent
,
7582 int num_10g
, int num_1g
)
7584 int num_ports
= parent
->num_ports
;
7585 int rx_chans_per_10g
, rx_chans_per_1g
;
7586 int tx_chans_per_10g
, tx_chans_per_1g
;
7587 int i
, tot_rx
, tot_tx
;
7589 if (!num_10g
|| !num_1g
) {
7590 rx_chans_per_10g
= rx_chans_per_1g
=
7591 (NIU_NUM_RXCHAN
/ num_ports
);
7592 tx_chans_per_10g
= tx_chans_per_1g
=
7593 (NIU_NUM_TXCHAN
/ num_ports
);
7595 rx_chans_per_1g
= NIU_NUM_RXCHAN
/ 8;
7596 rx_chans_per_10g
= (NIU_NUM_RXCHAN
-
7597 (rx_chans_per_1g
* num_1g
)) /
7600 tx_chans_per_1g
= NIU_NUM_TXCHAN
/ 6;
7601 tx_chans_per_10g
= (NIU_NUM_TXCHAN
-
7602 (tx_chans_per_1g
* num_1g
)) /
7606 tot_rx
= tot_tx
= 0;
7607 for (i
= 0; i
< num_ports
; i
++) {
7608 int type
= phy_decode(parent
->port_phy
, i
);
7610 if (type
== PORT_TYPE_10G
) {
7611 parent
->rxchan_per_port
[i
] = rx_chans_per_10g
;
7612 parent
->txchan_per_port
[i
] = tx_chans_per_10g
;
7614 parent
->rxchan_per_port
[i
] = rx_chans_per_1g
;
7615 parent
->txchan_per_port
[i
] = tx_chans_per_1g
;
7617 pr_info(PFX
"niu%d: Port %u [%u RX chans] "
7620 parent
->rxchan_per_port
[i
],
7621 parent
->txchan_per_port
[i
]);
7622 tot_rx
+= parent
->rxchan_per_port
[i
];
7623 tot_tx
+= parent
->txchan_per_port
[i
];
7626 if (tot_rx
> NIU_NUM_RXCHAN
) {
7627 printk(KERN_ERR PFX
"niu%d: Too many RX channels (%d), "
7628 "resetting to one per port.\n",
7629 parent
->index
, tot_rx
);
7630 for (i
= 0; i
< num_ports
; i
++)
7631 parent
->rxchan_per_port
[i
] = 1;
7633 if (tot_tx
> NIU_NUM_TXCHAN
) {
7634 printk(KERN_ERR PFX
"niu%d: Too many TX channels (%d), "
7635 "resetting to one per port.\n",
7636 parent
->index
, tot_tx
);
7637 for (i
= 0; i
< num_ports
; i
++)
7638 parent
->txchan_per_port
[i
] = 1;
7640 if (tot_rx
< NIU_NUM_RXCHAN
|| tot_tx
< NIU_NUM_TXCHAN
) {
7641 printk(KERN_WARNING PFX
"niu%d: Driver bug, wasted channels, "
7643 parent
->index
, tot_rx
, tot_tx
);
7647 static void __devinit
niu_divide_rdc_groups(struct niu_parent
*parent
,
7648 int num_10g
, int num_1g
)
7650 int i
, num_ports
= parent
->num_ports
;
7651 int rdc_group
, rdc_groups_per_port
;
7652 int rdc_channel_base
;
7655 rdc_groups_per_port
= NIU_NUM_RDC_TABLES
/ num_ports
;
7657 rdc_channel_base
= 0;
7659 for (i
= 0; i
< num_ports
; i
++) {
7660 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[i
];
7661 int grp
, num_channels
= parent
->rxchan_per_port
[i
];
7662 int this_channel_offset
;
7664 tp
->first_table_num
= rdc_group
;
7665 tp
->num_tables
= rdc_groups_per_port
;
7666 this_channel_offset
= 0;
7667 for (grp
= 0; grp
< tp
->num_tables
; grp
++) {
7668 struct rdc_table
*rt
= &tp
->tables
[grp
];
7671 pr_info(PFX
"niu%d: Port %d RDC tbl(%d) [ ",
7672 parent
->index
, i
, tp
->first_table_num
+ grp
);
7673 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++) {
7674 rt
->rxdma_channel
[slot
] =
7675 rdc_channel_base
+ this_channel_offset
;
7677 printk("%d ", rt
->rxdma_channel
[slot
]);
7679 if (++this_channel_offset
== num_channels
)
7680 this_channel_offset
= 0;
7685 parent
->rdc_default
[i
] = rdc_channel_base
;
7687 rdc_channel_base
+= num_channels
;
7688 rdc_group
+= rdc_groups_per_port
;
7692 static int __devinit
fill_phy_probe_info(struct niu
*np
,
7693 struct niu_parent
*parent
,
7694 struct phy_probe_info
*info
)
7696 unsigned long flags
;
7699 memset(info
, 0, sizeof(*info
));
7701 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
7702 niu_lock_parent(np
, flags
);
7704 for (port
= 8; port
< 32; port
++) {
7705 int dev_id_1
, dev_id_2
;
7707 dev_id_1
= mdio_read(np
, port
,
7708 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID1
);
7709 dev_id_2
= mdio_read(np
, port
,
7710 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID2
);
7711 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
7715 dev_id_1
= mdio_read(np
, port
,
7716 NIU_PCS_DEV_ADDR
, MII_PHYSID1
);
7717 dev_id_2
= mdio_read(np
, port
,
7718 NIU_PCS_DEV_ADDR
, MII_PHYSID2
);
7719 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
7723 dev_id_1
= mii_read(np
, port
, MII_PHYSID1
);
7724 dev_id_2
= mii_read(np
, port
, MII_PHYSID2
);
7725 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
7730 niu_unlock_parent(np
, flags
);
7735 static int __devinit
walk_phys(struct niu
*np
, struct niu_parent
*parent
)
7737 struct phy_probe_info
*info
= &parent
->phy_probe_info
;
7738 int lowest_10g
, lowest_1g
;
7739 int num_10g
, num_1g
;
7743 if (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
) ||
7744 !strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) {
7747 parent
->plat_type
= PLAT_TYPE_ATCA_CP3220
;
7748 parent
->num_ports
= 4;
7749 val
= (phy_encode(PORT_TYPE_1G
, 0) |
7750 phy_encode(PORT_TYPE_1G
, 1) |
7751 phy_encode(PORT_TYPE_1G
, 2) |
7752 phy_encode(PORT_TYPE_1G
, 3));
7753 } else if (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) {
7756 parent
->num_ports
= 2;
7757 val
= (phy_encode(PORT_TYPE_10G
, 0) |
7758 phy_encode(PORT_TYPE_10G
, 1));
7760 err
= fill_phy_probe_info(np
, parent
, info
);
7764 num_10g
= count_10g_ports(info
, &lowest_10g
);
7765 num_1g
= count_1g_ports(info
, &lowest_1g
);
7767 switch ((num_10g
<< 4) | num_1g
) {
7769 if (lowest_1g
== 10)
7770 parent
->plat_type
= PLAT_TYPE_VF_P0
;
7771 else if (lowest_1g
== 26)
7772 parent
->plat_type
= PLAT_TYPE_VF_P1
;
7774 goto unknown_vg_1g_port
;
7778 val
= (phy_encode(PORT_TYPE_10G
, 0) |
7779 phy_encode(PORT_TYPE_10G
, 1) |
7780 phy_encode(PORT_TYPE_1G
, 2) |
7781 phy_encode(PORT_TYPE_1G
, 3));
7785 val
= (phy_encode(PORT_TYPE_10G
, 0) |
7786 phy_encode(PORT_TYPE_10G
, 1));
7790 val
= phy_encode(PORT_TYPE_10G
, np
->port
);
7794 if (lowest_1g
== 10)
7795 parent
->plat_type
= PLAT_TYPE_VF_P0
;
7796 else if (lowest_1g
== 26)
7797 parent
->plat_type
= PLAT_TYPE_VF_P1
;
7799 goto unknown_vg_1g_port
;
7803 if ((lowest_10g
& 0x7) == 0)
7804 val
= (phy_encode(PORT_TYPE_10G
, 0) |
7805 phy_encode(PORT_TYPE_1G
, 1) |
7806 phy_encode(PORT_TYPE_1G
, 2) |
7807 phy_encode(PORT_TYPE_1G
, 3));
7809 val
= (phy_encode(PORT_TYPE_1G
, 0) |
7810 phy_encode(PORT_TYPE_10G
, 1) |
7811 phy_encode(PORT_TYPE_1G
, 2) |
7812 phy_encode(PORT_TYPE_1G
, 3));
7816 if (lowest_1g
== 10)
7817 parent
->plat_type
= PLAT_TYPE_VF_P0
;
7818 else if (lowest_1g
== 26)
7819 parent
->plat_type
= PLAT_TYPE_VF_P1
;
7821 goto unknown_vg_1g_port
;
7823 val
= (phy_encode(PORT_TYPE_1G
, 0) |
7824 phy_encode(PORT_TYPE_1G
, 1) |
7825 phy_encode(PORT_TYPE_1G
, 2) |
7826 phy_encode(PORT_TYPE_1G
, 3));
7830 printk(KERN_ERR PFX
"Unsupported port config "
7837 parent
->port_phy
= val
;
7839 if (parent
->plat_type
== PLAT_TYPE_NIU
)
7840 niu_n2_divide_channels(parent
);
7842 niu_divide_channels(parent
, num_10g
, num_1g
);
7844 niu_divide_rdc_groups(parent
, num_10g
, num_1g
);
7849 printk(KERN_ERR PFX
"Cannot identify platform type, 1gport=%d\n",
7854 static int __devinit
niu_probe_ports(struct niu
*np
)
7856 struct niu_parent
*parent
= np
->parent
;
7859 niudbg(PROBE
, "niu_probe_ports(): port_phy[%08x]\n",
7862 if (parent
->port_phy
== PORT_PHY_UNKNOWN
) {
7863 err
= walk_phys(np
, parent
);
7867 niu_set_ldg_timer_res(np
, 2);
7868 for (i
= 0; i
<= LDN_MAX
; i
++)
7869 niu_ldn_irq_enable(np
, i
, 0);
7872 if (parent
->port_phy
== PORT_PHY_INVALID
)
7878 static int __devinit
niu_classifier_swstate_init(struct niu
*np
)
7880 struct niu_classifier
*cp
= &np
->clas
;
7882 niudbg(PROBE
, "niu_classifier_swstate_init: num_tcam(%d)\n",
7883 np
->parent
->tcam_num_entries
);
7885 cp
->tcam_index
= (u16
) np
->port
;
7886 cp
->h1_init
= 0xffffffff;
7887 cp
->h2_init
= 0xffff;
7889 return fflp_early_init(np
);
7892 static void __devinit
niu_link_config_init(struct niu
*np
)
7894 struct niu_link_config
*lp
= &np
->link_config
;
7896 lp
->advertising
= (ADVERTISED_10baseT_Half
|
7897 ADVERTISED_10baseT_Full
|
7898 ADVERTISED_100baseT_Half
|
7899 ADVERTISED_100baseT_Full
|
7900 ADVERTISED_1000baseT_Half
|
7901 ADVERTISED_1000baseT_Full
|
7902 ADVERTISED_10000baseT_Full
|
7903 ADVERTISED_Autoneg
);
7904 lp
->speed
= lp
->active_speed
= SPEED_INVALID
;
7905 lp
->duplex
= lp
->active_duplex
= DUPLEX_INVALID
;
7907 lp
->loopback_mode
= LOOPBACK_MAC
;
7908 lp
->active_speed
= SPEED_10000
;
7909 lp
->active_duplex
= DUPLEX_FULL
;
7911 lp
->loopback_mode
= LOOPBACK_DISABLED
;
7915 static int __devinit
niu_init_mac_ipp_pcs_base(struct niu
*np
)
7919 np
->mac_regs
= np
->regs
+ XMAC_PORT0_OFF
;
7920 np
->ipp_off
= 0x00000;
7921 np
->pcs_off
= 0x04000;
7922 np
->xpcs_off
= 0x02000;
7926 np
->mac_regs
= np
->regs
+ XMAC_PORT1_OFF
;
7927 np
->ipp_off
= 0x08000;
7928 np
->pcs_off
= 0x0a000;
7929 np
->xpcs_off
= 0x08000;
7933 np
->mac_regs
= np
->regs
+ BMAC_PORT2_OFF
;
7934 np
->ipp_off
= 0x04000;
7935 np
->pcs_off
= 0x0e000;
7936 np
->xpcs_off
= ~0UL;
7940 np
->mac_regs
= np
->regs
+ BMAC_PORT3_OFF
;
7941 np
->ipp_off
= 0x0c000;
7942 np
->pcs_off
= 0x12000;
7943 np
->xpcs_off
= ~0UL;
7947 dev_err(np
->device
, PFX
"Port %u is invalid, cannot "
7948 "compute MAC block offset.\n", np
->port
);
7955 static void __devinit
niu_try_msix(struct niu
*np
, u8
*ldg_num_map
)
7957 struct msix_entry msi_vec
[NIU_NUM_LDG
];
7958 struct niu_parent
*parent
= np
->parent
;
7959 struct pci_dev
*pdev
= np
->pdev
;
7960 int i
, num_irqs
, err
;
7963 first_ldg
= (NIU_NUM_LDG
/ parent
->num_ports
) * np
->port
;
7964 for (i
= 0; i
< (NIU_NUM_LDG
/ parent
->num_ports
); i
++)
7965 ldg_num_map
[i
] = first_ldg
+ i
;
7967 num_irqs
= (parent
->rxchan_per_port
[np
->port
] +
7968 parent
->txchan_per_port
[np
->port
] +
7969 (np
->port
== 0 ? 3 : 1));
7970 BUG_ON(num_irqs
> (NIU_NUM_LDG
/ parent
->num_ports
));
7973 for (i
= 0; i
< num_irqs
; i
++) {
7974 msi_vec
[i
].vector
= 0;
7975 msi_vec
[i
].entry
= i
;
7978 err
= pci_enable_msix(pdev
, msi_vec
, num_irqs
);
7980 np
->flags
&= ~NIU_FLAGS_MSIX
;
7988 np
->flags
|= NIU_FLAGS_MSIX
;
7989 for (i
= 0; i
< num_irqs
; i
++)
7990 np
->ldg
[i
].irq
= msi_vec
[i
].vector
;
7991 np
->num_ldg
= num_irqs
;
7994 static int __devinit
niu_n2_irq_init(struct niu
*np
, u8
*ldg_num_map
)
7996 #ifdef CONFIG_SPARC64
7997 struct of_device
*op
= np
->op
;
7998 const u32
*int_prop
;
8001 int_prop
= of_get_property(op
->node
, "interrupts", NULL
);
8005 for (i
= 0; i
< op
->num_irqs
; i
++) {
8006 ldg_num_map
[i
] = int_prop
[i
];
8007 np
->ldg
[i
].irq
= op
->irqs
[i
];
8010 np
->num_ldg
= op
->num_irqs
;
8018 static int __devinit
niu_ldg_init(struct niu
*np
)
8020 struct niu_parent
*parent
= np
->parent
;
8021 u8 ldg_num_map
[NIU_NUM_LDG
];
8022 int first_chan
, num_chan
;
8023 int i
, err
, ldg_rotor
;
8027 np
->ldg
[0].irq
= np
->dev
->irq
;
8028 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
8029 err
= niu_n2_irq_init(np
, ldg_num_map
);
8033 niu_try_msix(np
, ldg_num_map
);
8036 for (i
= 0; i
< np
->num_ldg
; i
++) {
8037 struct niu_ldg
*lp
= &np
->ldg
[i
];
8039 netif_napi_add(np
->dev
, &lp
->napi
, niu_poll
, 64);
8042 lp
->ldg_num
= ldg_num_map
[i
];
8043 lp
->timer
= 2; /* XXX */
8045 /* On N2 NIU the firmware has setup the SID mappings so they go
8046 * to the correct values that will route the LDG to the proper
8047 * interrupt in the NCU interrupt table.
8049 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
8050 err
= niu_set_ldg_sid(np
, lp
->ldg_num
, port
, i
);
8056 /* We adopt the LDG assignment ordering used by the N2 NIU
8057 * 'interrupt' properties because that simplifies a lot of
8058 * things. This ordering is:
8061 * MIF (if port zero)
8062 * SYSERR (if port zero)
8069 err
= niu_ldg_assign_ldn(np
, parent
, ldg_num_map
[ldg_rotor
],
8075 if (ldg_rotor
== np
->num_ldg
)
8079 err
= niu_ldg_assign_ldn(np
, parent
,
8080 ldg_num_map
[ldg_rotor
],
8086 if (ldg_rotor
== np
->num_ldg
)
8089 err
= niu_ldg_assign_ldn(np
, parent
,
8090 ldg_num_map
[ldg_rotor
],
8096 if (ldg_rotor
== np
->num_ldg
)
8102 for (i
= 0; i
< port
; i
++)
8103 first_chan
+= parent
->rxchan_per_port
[port
];
8104 num_chan
= parent
->rxchan_per_port
[port
];
8106 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
8107 err
= niu_ldg_assign_ldn(np
, parent
,
8108 ldg_num_map
[ldg_rotor
],
8113 if (ldg_rotor
== np
->num_ldg
)
8118 for (i
= 0; i
< port
; i
++)
8119 first_chan
+= parent
->txchan_per_port
[port
];
8120 num_chan
= parent
->txchan_per_port
[port
];
8121 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
8122 err
= niu_ldg_assign_ldn(np
, parent
,
8123 ldg_num_map
[ldg_rotor
],
8128 if (ldg_rotor
== np
->num_ldg
)
8135 static void __devexit
niu_ldg_free(struct niu
*np
)
8137 if (np
->flags
& NIU_FLAGS_MSIX
)
8138 pci_disable_msix(np
->pdev
);
8141 static int __devinit
niu_get_of_props(struct niu
*np
)
8143 #ifdef CONFIG_SPARC64
8144 struct net_device
*dev
= np
->dev
;
8145 struct device_node
*dp
;
8146 const char *phy_type
;
8151 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
8154 dp
= pci_device_to_OF_node(np
->pdev
);
8156 phy_type
= of_get_property(dp
, "phy-type", &prop_len
);
8158 dev_err(np
->device
, PFX
"%s: OF node lacks "
8159 "phy-type property\n",
8164 if (!strcmp(phy_type
, "none"))
8167 strcpy(np
->vpd
.phy_type
, phy_type
);
8169 if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
8170 dev_err(np
->device
, PFX
"%s: Illegal phy string [%s].\n",
8171 dp
->full_name
, np
->vpd
.phy_type
);
8175 mac_addr
= of_get_property(dp
, "local-mac-address", &prop_len
);
8177 dev_err(np
->device
, PFX
"%s: OF node lacks "
8178 "local-mac-address property\n",
8182 if (prop_len
!= dev
->addr_len
) {
8183 dev_err(np
->device
, PFX
"%s: OF MAC address prop len (%d) "
8185 dp
->full_name
, prop_len
);
8187 memcpy(dev
->perm_addr
, mac_addr
, dev
->addr_len
);
8188 if (!is_valid_ether_addr(&dev
->perm_addr
[0])) {
8191 dev_err(np
->device
, PFX
"%s: OF MAC address is invalid\n",
8193 dev_err(np
->device
, PFX
"%s: [ \n",
8195 for (i
= 0; i
< 6; i
++)
8196 printk("%02x ", dev
->perm_addr
[i
]);
8201 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
8203 model
= of_get_property(dp
, "model", &prop_len
);
8206 strcpy(np
->vpd
.model
, model
);
8214 static int __devinit
niu_get_invariants(struct niu
*np
)
8216 int err
, have_props
;
8219 err
= niu_get_of_props(np
);
8225 err
= niu_init_mac_ipp_pcs_base(np
);
8230 err
= niu_get_and_validate_port(np
);
8235 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
8238 nw64(ESPC_PIO_EN
, ESPC_PIO_EN_ENABLE
);
8239 offset
= niu_pci_vpd_offset(np
);
8240 niudbg(PROBE
, "niu_get_invariants: VPD offset [%08x]\n",
8243 niu_pci_vpd_fetch(np
, offset
);
8244 nw64(ESPC_PIO_EN
, 0);
8246 if (np
->flags
& NIU_FLAGS_VPD_VALID
) {
8247 niu_pci_vpd_validate(np
);
8248 err
= niu_get_and_validate_port(np
);
8253 if (!(np
->flags
& NIU_FLAGS_VPD_VALID
)) {
8254 err
= niu_get_and_validate_port(np
);
8257 err
= niu_pci_probe_sprom(np
);
8263 err
= niu_probe_ports(np
);
8269 niu_classifier_swstate_init(np
);
8270 niu_link_config_init(np
);
8272 err
= niu_determine_phy_disposition(np
);
8274 err
= niu_init_link(np
);
8279 static LIST_HEAD(niu_parent_list
);
8280 static DEFINE_MUTEX(niu_parent_lock
);
8281 static int niu_parent_index
;
8283 static ssize_t
show_port_phy(struct device
*dev
,
8284 struct device_attribute
*attr
, char *buf
)
8286 struct platform_device
*plat_dev
= to_platform_device(dev
);
8287 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
8288 u32 port_phy
= p
->port_phy
;
8289 char *orig_buf
= buf
;
8292 if (port_phy
== PORT_PHY_UNKNOWN
||
8293 port_phy
== PORT_PHY_INVALID
)
8296 for (i
= 0; i
< p
->num_ports
; i
++) {
8297 const char *type_str
;
8300 type
= phy_decode(port_phy
, i
);
8301 if (type
== PORT_TYPE_10G
)
8306 (i
== 0) ? "%s" : " %s",
8309 buf
+= sprintf(buf
, "\n");
8310 return buf
- orig_buf
;
8313 static ssize_t
show_plat_type(struct device
*dev
,
8314 struct device_attribute
*attr
, char *buf
)
8316 struct platform_device
*plat_dev
= to_platform_device(dev
);
8317 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
8318 const char *type_str
;
8320 switch (p
->plat_type
) {
8321 case PLAT_TYPE_ATLAS
:
8327 case PLAT_TYPE_VF_P0
:
8330 case PLAT_TYPE_VF_P1
:
8334 type_str
= "unknown";
8338 return sprintf(buf
, "%s\n", type_str
);
8341 static ssize_t
__show_chan_per_port(struct device
*dev
,
8342 struct device_attribute
*attr
, char *buf
,
8345 struct platform_device
*plat_dev
= to_platform_device(dev
);
8346 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
8347 char *orig_buf
= buf
;
8351 arr
= (rx
? p
->rxchan_per_port
: p
->txchan_per_port
);
8353 for (i
= 0; i
< p
->num_ports
; i
++) {
8355 (i
== 0) ? "%d" : " %d",
8358 buf
+= sprintf(buf
, "\n");
8360 return buf
- orig_buf
;
8363 static ssize_t
show_rxchan_per_port(struct device
*dev
,
8364 struct device_attribute
*attr
, char *buf
)
8366 return __show_chan_per_port(dev
, attr
, buf
, 1);
8369 static ssize_t
show_txchan_per_port(struct device
*dev
,
8370 struct device_attribute
*attr
, char *buf
)
8372 return __show_chan_per_port(dev
, attr
, buf
, 1);
8375 static ssize_t
show_num_ports(struct device
*dev
,
8376 struct device_attribute
*attr
, char *buf
)
8378 struct platform_device
*plat_dev
= to_platform_device(dev
);
8379 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
8381 return sprintf(buf
, "%d\n", p
->num_ports
);
8384 static struct device_attribute niu_parent_attributes
[] = {
8385 __ATTR(port_phy
, S_IRUGO
, show_port_phy
, NULL
),
8386 __ATTR(plat_type
, S_IRUGO
, show_plat_type
, NULL
),
8387 __ATTR(rxchan_per_port
, S_IRUGO
, show_rxchan_per_port
, NULL
),
8388 __ATTR(txchan_per_port
, S_IRUGO
, show_txchan_per_port
, NULL
),
8389 __ATTR(num_ports
, S_IRUGO
, show_num_ports
, NULL
),
8393 static struct niu_parent
* __devinit
niu_new_parent(struct niu
*np
,
8394 union niu_parent_id
*id
,
8397 struct platform_device
*plat_dev
;
8398 struct niu_parent
*p
;
8401 niudbg(PROBE
, "niu_new_parent: Creating new parent.\n");
8403 plat_dev
= platform_device_register_simple("niu", niu_parent_index
,
8408 for (i
= 0; attr_name(niu_parent_attributes
[i
]); i
++) {
8409 int err
= device_create_file(&plat_dev
->dev
,
8410 &niu_parent_attributes
[i
]);
8412 goto fail_unregister
;
8415 p
= kzalloc(sizeof(*p
), GFP_KERNEL
);
8417 goto fail_unregister
;
8419 p
->index
= niu_parent_index
++;
8421 plat_dev
->dev
.platform_data
= p
;
8422 p
->plat_dev
= plat_dev
;
8424 memcpy(&p
->id
, id
, sizeof(*id
));
8425 p
->plat_type
= ptype
;
8426 INIT_LIST_HEAD(&p
->list
);
8427 atomic_set(&p
->refcnt
, 0);
8428 list_add(&p
->list
, &niu_parent_list
);
8429 spin_lock_init(&p
->lock
);
8431 p
->rxdma_clock_divider
= 7500;
8433 p
->tcam_num_entries
= NIU_PCI_TCAM_ENTRIES
;
8434 if (p
->plat_type
== PLAT_TYPE_NIU
)
8435 p
->tcam_num_entries
= NIU_NONPCI_TCAM_ENTRIES
;
8437 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
8438 int index
= i
- CLASS_CODE_USER_PROG1
;
8440 p
->tcam_key
[index
] = TCAM_KEY_TSEL
;
8441 p
->flow_key
[index
] = (FLOW_KEY_IPSA
|
8444 (FLOW_KEY_L4_BYTE12
<<
8445 FLOW_KEY_L4_0_SHIFT
) |
8446 (FLOW_KEY_L4_BYTE12
<<
8447 FLOW_KEY_L4_1_SHIFT
));
8450 for (i
= 0; i
< LDN_MAX
+ 1; i
++)
8451 p
->ldg_map
[i
] = LDG_INVALID
;
8456 platform_device_unregister(plat_dev
);
8460 static struct niu_parent
* __devinit
niu_get_parent(struct niu
*np
,
8461 union niu_parent_id
*id
,
8464 struct niu_parent
*p
, *tmp
;
8465 int port
= np
->port
;
8467 niudbg(PROBE
, "niu_get_parent: platform_type[%u] port[%u]\n",
8470 mutex_lock(&niu_parent_lock
);
8472 list_for_each_entry(tmp
, &niu_parent_list
, list
) {
8473 if (!memcmp(id
, &tmp
->id
, sizeof(*id
))) {
8479 p
= niu_new_parent(np
, id
, ptype
);
8485 sprintf(port_name
, "port%d", port
);
8486 err
= sysfs_create_link(&p
->plat_dev
->dev
.kobj
,
8490 p
->ports
[port
] = np
;
8491 atomic_inc(&p
->refcnt
);
8494 mutex_unlock(&niu_parent_lock
);
8499 static void niu_put_parent(struct niu
*np
)
8501 struct niu_parent
*p
= np
->parent
;
8505 BUG_ON(!p
|| p
->ports
[port
] != np
);
8507 niudbg(PROBE
, "niu_put_parent: port[%u]\n", port
);
8509 sprintf(port_name
, "port%d", port
);
8511 mutex_lock(&niu_parent_lock
);
8513 sysfs_remove_link(&p
->plat_dev
->dev
.kobj
, port_name
);
8515 p
->ports
[port
] = NULL
;
8518 if (atomic_dec_and_test(&p
->refcnt
)) {
8520 platform_device_unregister(p
->plat_dev
);
8523 mutex_unlock(&niu_parent_lock
);
8526 static void *niu_pci_alloc_coherent(struct device
*dev
, size_t size
,
8527 u64
*handle
, gfp_t flag
)
8532 ret
= dma_alloc_coherent(dev
, size
, &dh
, flag
);
8538 static void niu_pci_free_coherent(struct device
*dev
, size_t size
,
8539 void *cpu_addr
, u64 handle
)
8541 dma_free_coherent(dev
, size
, cpu_addr
, handle
);
8544 static u64
niu_pci_map_page(struct device
*dev
, struct page
*page
,
8545 unsigned long offset
, size_t size
,
8546 enum dma_data_direction direction
)
8548 return dma_map_page(dev
, page
, offset
, size
, direction
);
8551 static void niu_pci_unmap_page(struct device
*dev
, u64 dma_address
,
8552 size_t size
, enum dma_data_direction direction
)
8554 return dma_unmap_page(dev
, dma_address
, size
, direction
);
8557 static u64
niu_pci_map_single(struct device
*dev
, void *cpu_addr
,
8559 enum dma_data_direction direction
)
8561 return dma_map_single(dev
, cpu_addr
, size
, direction
);
8564 static void niu_pci_unmap_single(struct device
*dev
, u64 dma_address
,
8566 enum dma_data_direction direction
)
8568 dma_unmap_single(dev
, dma_address
, size
, direction
);
8571 static const struct niu_ops niu_pci_ops
= {
8572 .alloc_coherent
= niu_pci_alloc_coherent
,
8573 .free_coherent
= niu_pci_free_coherent
,
8574 .map_page
= niu_pci_map_page
,
8575 .unmap_page
= niu_pci_unmap_page
,
8576 .map_single
= niu_pci_map_single
,
8577 .unmap_single
= niu_pci_unmap_single
,
8580 static void __devinit
niu_driver_version(void)
8582 static int niu_version_printed
;
8584 if (niu_version_printed
++ == 0)
8585 pr_info("%s", version
);
8588 static struct net_device
* __devinit
niu_alloc_and_init(
8589 struct device
*gen_dev
, struct pci_dev
*pdev
,
8590 struct of_device
*op
, const struct niu_ops
*ops
,
8593 struct net_device
*dev
;
8596 dev
= alloc_etherdev_mq(sizeof(struct niu
), NIU_NUM_TXCHAN
);
8598 dev_err(gen_dev
, PFX
"Etherdev alloc failed, aborting.\n");
8602 SET_NETDEV_DEV(dev
, gen_dev
);
8604 np
= netdev_priv(dev
);
8608 np
->device
= gen_dev
;
8611 np
->msg_enable
= niu_debug
;
8613 spin_lock_init(&np
->lock
);
8614 INIT_WORK(&np
->reset_task
, niu_reset_task
);
8621 static void __devinit
niu_assign_netdev_ops(struct net_device
*dev
)
8623 dev
->open
= niu_open
;
8624 dev
->stop
= niu_close
;
8625 dev
->get_stats
= niu_get_stats
;
8626 dev
->set_multicast_list
= niu_set_rx_mode
;
8627 dev
->set_mac_address
= niu_set_mac_addr
;
8628 dev
->do_ioctl
= niu_ioctl
;
8629 dev
->tx_timeout
= niu_tx_timeout
;
8630 dev
->hard_start_xmit
= niu_start_xmit
;
8631 dev
->ethtool_ops
= &niu_ethtool_ops
;
8632 dev
->watchdog_timeo
= NIU_TX_TIMEOUT
;
8633 dev
->change_mtu
= niu_change_mtu
;
8636 static void __devinit
niu_device_announce(struct niu
*np
)
8638 struct net_device
*dev
= np
->dev
;
8640 pr_info("%s: NIU Ethernet %pM\n", dev
->name
, dev
->dev_addr
);
8642 if (np
->parent
->plat_type
== PLAT_TYPE_ATCA_CP3220
) {
8643 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8645 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
8646 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
8647 (np
->flags
& NIU_FLAGS_FIBER
? "RGMII FIBER" : "SERDES"),
8648 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
8649 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
8652 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8654 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
8655 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
8656 (np
->flags
& NIU_FLAGS_FIBER
? "FIBER" : "COPPER"),
8657 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
8658 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
8663 static int __devinit
niu_pci_init_one(struct pci_dev
*pdev
,
8664 const struct pci_device_id
*ent
)
8666 union niu_parent_id parent_id
;
8667 struct net_device
*dev
;
8673 niu_driver_version();
8675 err
= pci_enable_device(pdev
);
8677 dev_err(&pdev
->dev
, PFX
"Cannot enable PCI device, "
8682 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
) ||
8683 !(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
8684 dev_err(&pdev
->dev
, PFX
"Cannot find proper PCI device "
8685 "base addresses, aborting.\n");
8687 goto err_out_disable_pdev
;
8690 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
8692 dev_err(&pdev
->dev
, PFX
"Cannot obtain PCI resources, "
8694 goto err_out_disable_pdev
;
8697 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
8699 dev_err(&pdev
->dev
, PFX
"Cannot find PCI Express capability, "
8701 goto err_out_free_res
;
8704 dev
= niu_alloc_and_init(&pdev
->dev
, pdev
, NULL
,
8705 &niu_pci_ops
, PCI_FUNC(pdev
->devfn
));
8708 goto err_out_free_res
;
8710 np
= netdev_priv(dev
);
8712 memset(&parent_id
, 0, sizeof(parent_id
));
8713 parent_id
.pci
.domain
= pci_domain_nr(pdev
->bus
);
8714 parent_id
.pci
.bus
= pdev
->bus
->number
;
8715 parent_id
.pci
.device
= PCI_SLOT(pdev
->devfn
);
8717 np
->parent
= niu_get_parent(np
, &parent_id
,
8721 goto err_out_free_dev
;
8724 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, &val16
);
8725 val16
&= ~PCI_EXP_DEVCTL_NOSNOOP_EN
;
8726 val16
|= (PCI_EXP_DEVCTL_CERE
|
8727 PCI_EXP_DEVCTL_NFERE
|
8728 PCI_EXP_DEVCTL_FERE
|
8729 PCI_EXP_DEVCTL_URRE
|
8730 PCI_EXP_DEVCTL_RELAX_EN
);
8731 pci_write_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, val16
);
8733 dma_mask
= DMA_44BIT_MASK
;
8734 err
= pci_set_dma_mask(pdev
, dma_mask
);
8736 dev
->features
|= NETIF_F_HIGHDMA
;
8737 err
= pci_set_consistent_dma_mask(pdev
, dma_mask
);
8739 dev_err(&pdev
->dev
, PFX
"Unable to obtain 44 bit "
8740 "DMA for consistent allocations, "
8742 goto err_out_release_parent
;
8745 if (err
|| dma_mask
== DMA_32BIT_MASK
) {
8746 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
8748 dev_err(&pdev
->dev
, PFX
"No usable DMA configuration, "
8750 goto err_out_release_parent
;
8754 dev
->features
|= (NETIF_F_SG
| NETIF_F_HW_CSUM
);
8756 np
->regs
= pci_ioremap_bar(pdev
, 0);
8758 dev_err(&pdev
->dev
, PFX
"Cannot map device registers, "
8761 goto err_out_release_parent
;
8764 pci_set_master(pdev
);
8765 pci_save_state(pdev
);
8767 dev
->irq
= pdev
->irq
;
8769 niu_assign_netdev_ops(dev
);
8771 err
= niu_get_invariants(np
);
8774 dev_err(&pdev
->dev
, PFX
"Problem fetching invariants "
8775 "of chip, aborting.\n");
8776 goto err_out_iounmap
;
8779 err
= register_netdev(dev
);
8781 dev_err(&pdev
->dev
, PFX
"Cannot register net device, "
8783 goto err_out_iounmap
;
8786 pci_set_drvdata(pdev
, dev
);
8788 niu_device_announce(np
);
8798 err_out_release_parent
:
8805 pci_release_regions(pdev
);
8807 err_out_disable_pdev
:
8808 pci_disable_device(pdev
);
8809 pci_set_drvdata(pdev
, NULL
);
8814 static void __devexit
niu_pci_remove_one(struct pci_dev
*pdev
)
8816 struct net_device
*dev
= pci_get_drvdata(pdev
);
8819 struct niu
*np
= netdev_priv(dev
);
8821 unregister_netdev(dev
);
8832 pci_release_regions(pdev
);
8833 pci_disable_device(pdev
);
8834 pci_set_drvdata(pdev
, NULL
);
8838 static int niu_suspend(struct pci_dev
*pdev
, pm_message_t state
)
8840 struct net_device
*dev
= pci_get_drvdata(pdev
);
8841 struct niu
*np
= netdev_priv(dev
);
8842 unsigned long flags
;
8844 if (!netif_running(dev
))
8847 flush_scheduled_work();
8850 del_timer_sync(&np
->timer
);
8852 spin_lock_irqsave(&np
->lock
, flags
);
8853 niu_enable_interrupts(np
, 0);
8854 spin_unlock_irqrestore(&np
->lock
, flags
);
8856 netif_device_detach(dev
);
8858 spin_lock_irqsave(&np
->lock
, flags
);
8860 spin_unlock_irqrestore(&np
->lock
, flags
);
8862 pci_save_state(pdev
);
8867 static int niu_resume(struct pci_dev
*pdev
)
8869 struct net_device
*dev
= pci_get_drvdata(pdev
);
8870 struct niu
*np
= netdev_priv(dev
);
8871 unsigned long flags
;
8874 if (!netif_running(dev
))
8877 pci_restore_state(pdev
);
8879 netif_device_attach(dev
);
8881 spin_lock_irqsave(&np
->lock
, flags
);
8883 err
= niu_init_hw(np
);
8885 np
->timer
.expires
= jiffies
+ HZ
;
8886 add_timer(&np
->timer
);
8887 niu_netif_start(np
);
8890 spin_unlock_irqrestore(&np
->lock
, flags
);
8895 static struct pci_driver niu_pci_driver
= {
8896 .name
= DRV_MODULE_NAME
,
8897 .id_table
= niu_pci_tbl
,
8898 .probe
= niu_pci_init_one
,
8899 .remove
= __devexit_p(niu_pci_remove_one
),
8900 .suspend
= niu_suspend
,
8901 .resume
= niu_resume
,
8904 #ifdef CONFIG_SPARC64
8905 static void *niu_phys_alloc_coherent(struct device
*dev
, size_t size
,
8906 u64
*dma_addr
, gfp_t flag
)
8908 unsigned long order
= get_order(size
);
8909 unsigned long page
= __get_free_pages(flag
, order
);
8913 memset((char *)page
, 0, PAGE_SIZE
<< order
);
8914 *dma_addr
= __pa(page
);
8916 return (void *) page
;
8919 static void niu_phys_free_coherent(struct device
*dev
, size_t size
,
8920 void *cpu_addr
, u64 handle
)
8922 unsigned long order
= get_order(size
);
8924 free_pages((unsigned long) cpu_addr
, order
);
8927 static u64
niu_phys_map_page(struct device
*dev
, struct page
*page
,
8928 unsigned long offset
, size_t size
,
8929 enum dma_data_direction direction
)
8931 return page_to_phys(page
) + offset
;
8934 static void niu_phys_unmap_page(struct device
*dev
, u64 dma_address
,
8935 size_t size
, enum dma_data_direction direction
)
8937 /* Nothing to do. */
8940 static u64
niu_phys_map_single(struct device
*dev
, void *cpu_addr
,
8942 enum dma_data_direction direction
)
8944 return __pa(cpu_addr
);
8947 static void niu_phys_unmap_single(struct device
*dev
, u64 dma_address
,
8949 enum dma_data_direction direction
)
8951 /* Nothing to do. */
8954 static const struct niu_ops niu_phys_ops
= {
8955 .alloc_coherent
= niu_phys_alloc_coherent
,
8956 .free_coherent
= niu_phys_free_coherent
,
8957 .map_page
= niu_phys_map_page
,
8958 .unmap_page
= niu_phys_unmap_page
,
8959 .map_single
= niu_phys_map_single
,
8960 .unmap_single
= niu_phys_unmap_single
,
8963 static unsigned long res_size(struct resource
*r
)
8965 return r
->end
- r
->start
+ 1UL;
8968 static int __devinit
niu_of_probe(struct of_device
*op
,
8969 const struct of_device_id
*match
)
8971 union niu_parent_id parent_id
;
8972 struct net_device
*dev
;
8977 niu_driver_version();
8979 reg
= of_get_property(op
->node
, "reg", NULL
);
8981 dev_err(&op
->dev
, PFX
"%s: No 'reg' property, aborting.\n",
8982 op
->node
->full_name
);
8986 dev
= niu_alloc_and_init(&op
->dev
, NULL
, op
,
8987 &niu_phys_ops
, reg
[0] & 0x1);
8992 np
= netdev_priv(dev
);
8994 memset(&parent_id
, 0, sizeof(parent_id
));
8995 parent_id
.of
= of_get_parent(op
->node
);
8997 np
->parent
= niu_get_parent(np
, &parent_id
,
9001 goto err_out_free_dev
;
9004 dev
->features
|= (NETIF_F_SG
| NETIF_F_HW_CSUM
);
9006 np
->regs
= of_ioremap(&op
->resource
[1], 0,
9007 res_size(&op
->resource
[1]),
9010 dev_err(&op
->dev
, PFX
"Cannot map device registers, "
9013 goto err_out_release_parent
;
9016 np
->vir_regs_1
= of_ioremap(&op
->resource
[2], 0,
9017 res_size(&op
->resource
[2]),
9019 if (!np
->vir_regs_1
) {
9020 dev_err(&op
->dev
, PFX
"Cannot map device vir registers 1, "
9023 goto err_out_iounmap
;
9026 np
->vir_regs_2
= of_ioremap(&op
->resource
[3], 0,
9027 res_size(&op
->resource
[3]),
9029 if (!np
->vir_regs_2
) {
9030 dev_err(&op
->dev
, PFX
"Cannot map device vir registers 2, "
9033 goto err_out_iounmap
;
9036 niu_assign_netdev_ops(dev
);
9038 err
= niu_get_invariants(np
);
9041 dev_err(&op
->dev
, PFX
"Problem fetching invariants "
9042 "of chip, aborting.\n");
9043 goto err_out_iounmap
;
9046 err
= register_netdev(dev
);
9048 dev_err(&op
->dev
, PFX
"Cannot register net device, "
9050 goto err_out_iounmap
;
9053 dev_set_drvdata(&op
->dev
, dev
);
9055 niu_device_announce(np
);
9060 if (np
->vir_regs_1
) {
9061 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
9062 res_size(&op
->resource
[2]));
9063 np
->vir_regs_1
= NULL
;
9066 if (np
->vir_regs_2
) {
9067 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
9068 res_size(&op
->resource
[3]));
9069 np
->vir_regs_2
= NULL
;
9073 of_iounmap(&op
->resource
[1], np
->regs
,
9074 res_size(&op
->resource
[1]));
9078 err_out_release_parent
:
9088 static int __devexit
niu_of_remove(struct of_device
*op
)
9090 struct net_device
*dev
= dev_get_drvdata(&op
->dev
);
9093 struct niu
*np
= netdev_priv(dev
);
9095 unregister_netdev(dev
);
9097 if (np
->vir_regs_1
) {
9098 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
9099 res_size(&op
->resource
[2]));
9100 np
->vir_regs_1
= NULL
;
9103 if (np
->vir_regs_2
) {
9104 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
9105 res_size(&op
->resource
[3]));
9106 np
->vir_regs_2
= NULL
;
9110 of_iounmap(&op
->resource
[1], np
->regs
,
9111 res_size(&op
->resource
[1]));
9120 dev_set_drvdata(&op
->dev
, NULL
);
9125 static const struct of_device_id niu_match
[] = {
9128 .compatible
= "SUNW,niusl",
9132 MODULE_DEVICE_TABLE(of
, niu_match
);
9134 static struct of_platform_driver niu_of_driver
= {
9136 .match_table
= niu_match
,
9137 .probe
= niu_of_probe
,
9138 .remove
= __devexit_p(niu_of_remove
),
9141 #endif /* CONFIG_SPARC64 */
9143 static int __init
niu_init(void)
9147 BUILD_BUG_ON(PAGE_SIZE
< 4 * 1024);
9149 niu_debug
= netif_msg_init(debug
, NIU_MSG_DEFAULT
);
9151 #ifdef CONFIG_SPARC64
9152 err
= of_register_driver(&niu_of_driver
, &of_bus_type
);
9156 err
= pci_register_driver(&niu_pci_driver
);
9157 #ifdef CONFIG_SPARC64
9159 of_unregister_driver(&niu_of_driver
);
9166 static void __exit
niu_exit(void)
9168 pci_unregister_driver(&niu_pci_driver
);
9169 #ifdef CONFIG_SPARC64
9170 of_unregister_driver(&niu_of_driver
);
9174 module_init(niu_init
);
9175 module_exit(niu_exit
);