2 /* ns83820.c by Benjamin LaHaise with contributions.
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
6 * $Revision: 1.34.2.23 $
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
11 * Mmmm, chocolate vanilla mocha...
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
63 * - fix missed txok introduced during performance
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
86 * Cameo SOHO-GA2000T SOHO-GA2500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
92 * Special thanks to SMC for providing hardware to test this driver on.
94 * Reports of success or failure would be greatly appreciated.
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
99 #include <linux/module.h>
100 #include <linux/moduleparam.h>
101 #include <linux/types.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/delay.h>
107 #include <linux/smp_lock.h>
108 #include <linux/workqueue.h>
109 #include <linux/init.h>
110 #include <linux/ip.h> /* for iph */
111 #include <linux/in.h> /* for IPPROTO_... */
112 #include <linux/compiler.h>
113 #include <linux/prefetch.h>
114 #include <linux/ethtool.h>
115 #include <linux/timer.h>
116 #include <linux/if_vlan.h>
117 #include <linux/rtnetlink.h>
118 #include <linux/jiffies.h>
121 #include <asm/uaccess.h>
122 #include <asm/system.h>
124 #define DRV_NAME "ns83820"
126 /* Global parameters. See module_param near the bottom. */
128 static int reset_phy
= 0;
129 static int lnksts
= 0; /* CFG_LNKSTS bit polarity */
131 /* Dprintk is used for more interesting debug events */
133 #define Dprintk dprintk
136 #define RX_BUF_SIZE 1500 /* 8192 */
137 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
138 #define NS83820_VLAN_ACCEL_SUPPORT
141 /* Must not exceed ~65000. */
142 #define NR_RX_DESC 64
143 #define NR_TX_DESC 128
146 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
148 #define MIN_TX_DESC_FREE 8
150 /* register defines */
153 #define CR_TXE 0x00000001
154 #define CR_TXD 0x00000002
155 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
156 * The Receive engine skips one descriptor and moves
157 * onto the next one!! */
158 #define CR_RXE 0x00000004
159 #define CR_RXD 0x00000008
160 #define CR_TXR 0x00000010
161 #define CR_RXR 0x00000020
162 #define CR_SWI 0x00000080
163 #define CR_RST 0x00000100
165 #define PTSCR_EEBIST_FAIL 0x00000001
166 #define PTSCR_EEBIST_EN 0x00000002
167 #define PTSCR_EELOAD_EN 0x00000004
168 #define PTSCR_RBIST_FAIL 0x000001b8
169 #define PTSCR_RBIST_DONE 0x00000200
170 #define PTSCR_RBIST_EN 0x00000400
171 #define PTSCR_RBIST_RST 0x00002000
173 #define MEAR_EEDI 0x00000001
174 #define MEAR_EEDO 0x00000002
175 #define MEAR_EECLK 0x00000004
176 #define MEAR_EESEL 0x00000008
177 #define MEAR_MDIO 0x00000010
178 #define MEAR_MDDIR 0x00000020
179 #define MEAR_MDC 0x00000040
181 #define ISR_TXDESC3 0x40000000
182 #define ISR_TXDESC2 0x20000000
183 #define ISR_TXDESC1 0x10000000
184 #define ISR_TXDESC0 0x08000000
185 #define ISR_RXDESC3 0x04000000
186 #define ISR_RXDESC2 0x02000000
187 #define ISR_RXDESC1 0x01000000
188 #define ISR_RXDESC0 0x00800000
189 #define ISR_TXRCMP 0x00400000
190 #define ISR_RXRCMP 0x00200000
191 #define ISR_DPERR 0x00100000
192 #define ISR_SSERR 0x00080000
193 #define ISR_RMABT 0x00040000
194 #define ISR_RTABT 0x00020000
195 #define ISR_RXSOVR 0x00010000
196 #define ISR_HIBINT 0x00008000
197 #define ISR_PHY 0x00004000
198 #define ISR_PME 0x00002000
199 #define ISR_SWI 0x00001000
200 #define ISR_MIB 0x00000800
201 #define ISR_TXURN 0x00000400
202 #define ISR_TXIDLE 0x00000200
203 #define ISR_TXERR 0x00000100
204 #define ISR_TXDESC 0x00000080
205 #define ISR_TXOK 0x00000040
206 #define ISR_RXORN 0x00000020
207 #define ISR_RXIDLE 0x00000010
208 #define ISR_RXEARLY 0x00000008
209 #define ISR_RXERR 0x00000004
210 #define ISR_RXDESC 0x00000002
211 #define ISR_RXOK 0x00000001
213 #define TXCFG_CSI 0x80000000
214 #define TXCFG_HBI 0x40000000
215 #define TXCFG_MLB 0x20000000
216 #define TXCFG_ATP 0x10000000
217 #define TXCFG_ECRETRY 0x00800000
218 #define TXCFG_BRST_DIS 0x00080000
219 #define TXCFG_MXDMA1024 0x00000000
220 #define TXCFG_MXDMA512 0x00700000
221 #define TXCFG_MXDMA256 0x00600000
222 #define TXCFG_MXDMA128 0x00500000
223 #define TXCFG_MXDMA64 0x00400000
224 #define TXCFG_MXDMA32 0x00300000
225 #define TXCFG_MXDMA16 0x00200000
226 #define TXCFG_MXDMA8 0x00100000
228 #define CFG_LNKSTS 0x80000000
229 #define CFG_SPDSTS 0x60000000
230 #define CFG_SPDSTS1 0x40000000
231 #define CFG_SPDSTS0 0x20000000
232 #define CFG_DUPSTS 0x10000000
233 #define CFG_TBI_EN 0x01000000
234 #define CFG_MODE_1000 0x00400000
235 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
236 * Read the Phy response and then configure the MAC accordingly */
237 #define CFG_AUTO_1000 0x00200000
238 #define CFG_PINT_CTL 0x001c0000
239 #define CFG_PINT_DUPSTS 0x00100000
240 #define CFG_PINT_LNKSTS 0x00080000
241 #define CFG_PINT_SPDSTS 0x00040000
242 #define CFG_TMRTEST 0x00020000
243 #define CFG_MRM_DIS 0x00010000
244 #define CFG_MWI_DIS 0x00008000
245 #define CFG_T64ADDR 0x00004000
246 #define CFG_PCI64_DET 0x00002000
247 #define CFG_DATA64_EN 0x00001000
248 #define CFG_M64ADDR 0x00000800
249 #define CFG_PHY_RST 0x00000400
250 #define CFG_PHY_DIS 0x00000200
251 #define CFG_EXTSTS_EN 0x00000100
252 #define CFG_REQALG 0x00000080
253 #define CFG_SB 0x00000040
254 #define CFG_POW 0x00000020
255 #define CFG_EXD 0x00000010
256 #define CFG_PESEL 0x00000008
257 #define CFG_BROM_DIS 0x00000004
258 #define CFG_EXT_125 0x00000002
259 #define CFG_BEM 0x00000001
261 #define EXTSTS_UDPPKT 0x00200000
262 #define EXTSTS_TCPPKT 0x00080000
263 #define EXTSTS_IPPKT 0x00020000
264 #define EXTSTS_VPKT 0x00010000
265 #define EXTSTS_VTG_MASK 0x0000ffff
267 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
269 #define MIBC_MIBS 0x00000008
270 #define MIBC_ACLR 0x00000004
271 #define MIBC_FRZ 0x00000002
272 #define MIBC_WRN 0x00000001
274 #define PCR_PSEN (1 << 31)
275 #define PCR_PS_MCAST (1 << 30)
276 #define PCR_PS_DA (1 << 29)
277 #define PCR_STHI_8 (3 << 23)
278 #define PCR_STLO_4 (1 << 23)
279 #define PCR_FFHI_8K (3 << 21)
280 #define PCR_FFLO_4K (1 << 21)
281 #define PCR_PAUSE_CNT 0xFFFE
283 #define RXCFG_AEP 0x80000000
284 #define RXCFG_ARP 0x40000000
285 #define RXCFG_STRIPCRC 0x20000000
286 #define RXCFG_RX_FD 0x10000000
287 #define RXCFG_ALP 0x08000000
288 #define RXCFG_AIRL 0x04000000
289 #define RXCFG_MXDMA512 0x00700000
290 #define RXCFG_DRTH 0x0000003e
291 #define RXCFG_DRTH0 0x00000002
293 #define RFCR_RFEN 0x80000000
294 #define RFCR_AAB 0x40000000
295 #define RFCR_AAM 0x20000000
296 #define RFCR_AAU 0x10000000
297 #define RFCR_APM 0x08000000
298 #define RFCR_APAT 0x07800000
299 #define RFCR_APAT3 0x04000000
300 #define RFCR_APAT2 0x02000000
301 #define RFCR_APAT1 0x01000000
302 #define RFCR_APAT0 0x00800000
303 #define RFCR_AARP 0x00400000
304 #define RFCR_MHEN 0x00200000
305 #define RFCR_UHEN 0x00100000
306 #define RFCR_ULM 0x00080000
308 #define VRCR_RUDPE 0x00000080
309 #define VRCR_RTCPE 0x00000040
310 #define VRCR_RIPE 0x00000020
311 #define VRCR_IPEN 0x00000010
312 #define VRCR_DUTF 0x00000008
313 #define VRCR_DVTF 0x00000004
314 #define VRCR_VTREN 0x00000002
315 #define VRCR_VTDEN 0x00000001
317 #define VTCR_PPCHK 0x00000008
318 #define VTCR_GCHK 0x00000004
319 #define VTCR_VPPTI 0x00000002
320 #define VTCR_VGTI 0x00000001
357 #define TBICR_MR_AN_ENABLE 0x00001000
358 #define TBICR_MR_RESTART_AN 0x00000200
360 #define TBISR_MR_LINK_STATUS 0x00000020
361 #define TBISR_MR_AN_COMPLETE 0x00000004
363 #define TANAR_PS2 0x00000100
364 #define TANAR_PS1 0x00000080
365 #define TANAR_HALF_DUP 0x00000040
366 #define TANAR_FULL_DUP 0x00000020
368 #define GPIOR_GP5_OE 0x00000200
369 #define GPIOR_GP4_OE 0x00000100
370 #define GPIOR_GP3_OE 0x00000080
371 #define GPIOR_GP2_OE 0x00000040
372 #define GPIOR_GP1_OE 0x00000020
373 #define GPIOR_GP3_OUT 0x00000004
374 #define GPIOR_GP1_OUT 0x00000001
376 #define LINK_AUTONEGOTIATE 0x01
377 #define LINK_DOWN 0x02
380 #define HW_ADDR_LEN sizeof(dma_addr_t)
381 #define desc_addr_set(desc, addr) \
383 ((desc)[0] = cpu_to_le32(addr)); \
384 if (HW_ADDR_LEN == 8) \
385 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
387 #define desc_addr_get(desc) \
388 (le32_to_cpu((desc)[0]) | \
389 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
392 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
393 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
394 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
396 #define CMDSTS_OWN 0x80000000
397 #define CMDSTS_MORE 0x40000000
398 #define CMDSTS_INTR 0x20000000
399 #define CMDSTS_ERR 0x10000000
400 #define CMDSTS_OK 0x08000000
401 #define CMDSTS_RUNT 0x00200000
402 #define CMDSTS_LEN_MASK 0x0000ffff
404 #define CMDSTS_DEST_MASK 0x01800000
405 #define CMDSTS_DEST_SELF 0x00800000
406 #define CMDSTS_DEST_MULTI 0x01000000
408 #define DESC_SIZE 8 /* Should be cache line sized */
415 struct sk_buff
*skbs
[NR_RX_DESC
];
418 u16 next_rx
, next_empty
;
421 dma_addr_t phy_descs
;
426 struct net_device_stats stats
;
429 struct pci_dev
*pci_dev
;
431 #ifdef NS83820_VLAN_ACCEL_SUPPORT
432 struct vlan_group
*vlgrp
;
435 struct rx_info rx_info
;
436 struct tasklet_struct rx_tasklet
;
439 struct work_struct tq_refill
;
441 /* protects everything below. irqsave when using. */
442 spinlock_t misc_lock
;
455 volatile u16 tx_free_idx
; /* idx of free desc chain */
459 struct sk_buff
*tx_skbs
[NR_TX_DESC
];
461 char pad
[16] __attribute__((aligned(16)));
463 dma_addr_t tx_phy_descs
;
465 struct timer_list tx_watchdog
;
468 static inline struct ns83820
*PRIV(struct net_device
*dev
)
470 return netdev_priv(dev
);
473 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
475 static inline void kick_rx(struct net_device
*ndev
)
477 struct ns83820
*dev
= PRIV(ndev
);
478 dprintk("kick_rx: maybe kicking\n");
479 if (test_and_clear_bit(0, &dev
->rx_info
.idle
)) {
480 dprintk("actually kicking\n");
481 writel(dev
->rx_info
.phy_descs
+
482 (4 * DESC_SIZE
* dev
->rx_info
.next_rx
),
484 if (dev
->rx_info
.next_rx
== dev
->rx_info
.next_empty
)
485 printk(KERN_DEBUG
"%s: uh-oh: next_rx == next_empty???\n",
491 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
492 #define start_tx_okay(dev) \
493 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
496 #ifdef NS83820_VLAN_ACCEL_SUPPORT
497 static void ns83820_vlan_rx_register(struct net_device
*ndev
, struct vlan_group
*grp
)
499 struct ns83820
*dev
= PRIV(ndev
);
501 spin_lock_irq(&dev
->misc_lock
);
502 spin_lock(&dev
->tx_lock
);
506 spin_unlock(&dev
->tx_lock
);
507 spin_unlock_irq(&dev
->misc_lock
);
510 static void ns83820_vlan_rx_kill_vid(struct net_device
*ndev
, unsigned short vid
)
512 struct ns83820
*dev
= PRIV(ndev
);
514 spin_lock_irq(&dev
->misc_lock
);
515 spin_lock(&dev
->tx_lock
);
517 dev
->vlgrp
->vlan_devices
[vid
] = NULL
;
518 spin_unlock(&dev
->tx_lock
);
519 spin_unlock_irq(&dev
->misc_lock
);
525 * The hardware supports linked lists of receive descriptors for
526 * which ownership is transfered back and forth by means of an
527 * ownership bit. While the hardware does support the use of a
528 * ring for receive descriptors, we only make use of a chain in
529 * an attempt to reduce bus traffic under heavy load scenarios.
530 * This will also make bugs a bit more obvious. The current code
531 * only makes use of a single rx chain; I hope to implement
532 * priority based rx for version 1.0. Goal: even under overload
533 * conditions, still route realtime traffic with as low jitter as
536 static inline void build_rx_desc(struct ns83820
*dev
, u32
*desc
, dma_addr_t link
, dma_addr_t buf
, u32 cmdsts
, u32 extsts
)
538 desc_addr_set(desc
+ DESC_LINK
, link
);
539 desc_addr_set(desc
+ DESC_BUFPTR
, buf
);
540 desc
[DESC_EXTSTS
] = cpu_to_le32(extsts
);
542 desc
[DESC_CMDSTS
] = cpu_to_le32(cmdsts
);
545 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
546 static inline int ns83820_add_rx_skb(struct ns83820
*dev
, struct sk_buff
*skb
)
553 next_empty
= dev
->rx_info
.next_empty
;
555 /* don't overrun last rx marker */
556 if (unlikely(nr_rx_empty(dev
) <= 2)) {
562 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
563 dev
->rx_info
.next_empty
,
564 dev
->rx_info
.nr_used
,
569 sg
= dev
->rx_info
.descs
+ (next_empty
* DESC_SIZE
);
570 BUG_ON(NULL
!= dev
->rx_info
.skbs
[next_empty
]);
571 dev
->rx_info
.skbs
[next_empty
] = skb
;
573 dev
->rx_info
.next_empty
= (next_empty
+ 1) % NR_RX_DESC
;
574 cmdsts
= REAL_RX_BUF_SIZE
| CMDSTS_INTR
;
575 buf
= pci_map_single(dev
->pci_dev
, skb
->data
,
576 REAL_RX_BUF_SIZE
, PCI_DMA_FROMDEVICE
);
577 build_rx_desc(dev
, sg
, 0, buf
, cmdsts
, 0);
578 /* update link of previous rx */
579 if (likely(next_empty
!= dev
->rx_info
.next_rx
))
580 dev
->rx_info
.descs
[((NR_RX_DESC
+ next_empty
- 1) % NR_RX_DESC
) * DESC_SIZE
] = cpu_to_le32(dev
->rx_info
.phy_descs
+ (next_empty
* DESC_SIZE
* 4));
585 static inline int rx_refill(struct net_device
*ndev
, gfp_t gfp
)
587 struct ns83820
*dev
= PRIV(ndev
);
589 unsigned long flags
= 0;
591 if (unlikely(nr_rx_empty(dev
) <= 2))
594 dprintk("rx_refill(%p)\n", ndev
);
595 if (gfp
== GFP_ATOMIC
)
596 spin_lock_irqsave(&dev
->rx_info
.lock
, flags
);
597 for (i
=0; i
<NR_RX_DESC
; i
++) {
600 /* extra 16 bytes for alignment */
601 skb
= __dev_alloc_skb(REAL_RX_BUF_SIZE
+16, gfp
);
605 res
= (long)skb
->data
& 0xf;
608 skb_reserve(skb
, res
);
611 if (gfp
!= GFP_ATOMIC
)
612 spin_lock_irqsave(&dev
->rx_info
.lock
, flags
);
613 res
= ns83820_add_rx_skb(dev
, skb
);
614 if (gfp
!= GFP_ATOMIC
)
615 spin_unlock_irqrestore(&dev
->rx_info
.lock
, flags
);
621 if (gfp
== GFP_ATOMIC
)
622 spin_unlock_irqrestore(&dev
->rx_info
.lock
, flags
);
624 return i
? 0 : -ENOMEM
;
627 static void FASTCALL(rx_refill_atomic(struct net_device
*ndev
));
628 static void fastcall
rx_refill_atomic(struct net_device
*ndev
)
630 rx_refill(ndev
, GFP_ATOMIC
);
634 static inline void queue_refill(void *_dev
)
636 struct net_device
*ndev
= _dev
;
637 struct ns83820
*dev
= PRIV(ndev
);
639 rx_refill(ndev
, GFP_KERNEL
);
644 static inline void clear_rx_desc(struct ns83820
*dev
, unsigned i
)
646 build_rx_desc(dev
, dev
->rx_info
.descs
+ (DESC_SIZE
* i
), 0, 0, CMDSTS_OWN
, 0);
649 static void FASTCALL(phy_intr(struct net_device
*ndev
));
650 static void fastcall
phy_intr(struct net_device
*ndev
)
652 struct ns83820
*dev
= PRIV(ndev
);
653 static const char *speeds
[] = { "10", "100", "1000", "1000(?)", "1000F" };
655 u32 tbisr
, tanar
, tanlpar
;
656 int speed
, fullduplex
, newlinkstate
;
658 cfg
= readl(dev
->base
+ CFG
) ^ SPDSTS_POLARITY
;
660 if (dev
->CFG_cache
& CFG_TBI_EN
) {
661 /* we have an optical transceiver */
662 tbisr
= readl(dev
->base
+ TBISR
);
663 tanar
= readl(dev
->base
+ TANAR
);
664 tanlpar
= readl(dev
->base
+ TANLPAR
);
665 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
666 tbisr
, tanar
, tanlpar
);
668 if ( (fullduplex
= (tanlpar
& TANAR_FULL_DUP
)
669 && (tanar
& TANAR_FULL_DUP
)) ) {
671 /* both of us are full duplex */
672 writel(readl(dev
->base
+ TXCFG
)
673 | TXCFG_CSI
| TXCFG_HBI
| TXCFG_ATP
,
675 writel(readl(dev
->base
+ RXCFG
) | RXCFG_RX_FD
,
677 /* Light up full duplex LED */
678 writel(readl(dev
->base
+ GPIOR
) | GPIOR_GP1_OUT
,
681 } else if(((tanlpar
& TANAR_HALF_DUP
)
682 && (tanar
& TANAR_HALF_DUP
))
683 || ((tanlpar
& TANAR_FULL_DUP
)
684 && (tanar
& TANAR_HALF_DUP
))
685 || ((tanlpar
& TANAR_HALF_DUP
)
686 && (tanar
& TANAR_FULL_DUP
))) {
688 /* one or both of us are half duplex */
689 writel((readl(dev
->base
+ TXCFG
)
690 & ~(TXCFG_CSI
| TXCFG_HBI
)) | TXCFG_ATP
,
692 writel(readl(dev
->base
+ RXCFG
) & ~RXCFG_RX_FD
,
694 /* Turn off full duplex LED */
695 writel(readl(dev
->base
+ GPIOR
) & ~GPIOR_GP1_OUT
,
699 speed
= 4; /* 1000F */
702 /* we have a copper transceiver */
703 new_cfg
= dev
->CFG_cache
& ~(CFG_SB
| CFG_MODE_1000
| CFG_SPDSTS
);
705 if (cfg
& CFG_SPDSTS1
)
706 new_cfg
|= CFG_MODE_1000
;
708 new_cfg
&= ~CFG_MODE_1000
;
710 speed
= ((cfg
/ CFG_SPDSTS0
) & 3);
711 fullduplex
= (cfg
& CFG_DUPSTS
);
715 writel(readl(dev
->base
+ TXCFG
)
716 | TXCFG_CSI
| TXCFG_HBI
,
718 writel(readl(dev
->base
+ RXCFG
) | RXCFG_RX_FD
,
721 writel(readl(dev
->base
+ TXCFG
)
722 & ~(TXCFG_CSI
| TXCFG_HBI
),
724 writel(readl(dev
->base
+ RXCFG
) & ~(RXCFG_RX_FD
),
728 if ((cfg
& CFG_LNKSTS
) &&
729 ((new_cfg
^ dev
->CFG_cache
) != 0)) {
730 writel(new_cfg
, dev
->base
+ CFG
);
731 dev
->CFG_cache
= new_cfg
;
734 dev
->CFG_cache
&= ~CFG_SPDSTS
;
735 dev
->CFG_cache
|= cfg
& CFG_SPDSTS
;
738 newlinkstate
= (cfg
& CFG_LNKSTS
) ? LINK_UP
: LINK_DOWN
;
740 if (newlinkstate
& LINK_UP
741 && dev
->linkstate
!= newlinkstate
) {
742 netif_start_queue(ndev
);
743 netif_wake_queue(ndev
);
744 printk(KERN_INFO
"%s: link now %s mbps, %s duplex and up.\n",
747 fullduplex
? "full" : "half");
748 } else if (newlinkstate
& LINK_DOWN
749 && dev
->linkstate
!= newlinkstate
) {
750 netif_stop_queue(ndev
);
751 printk(KERN_INFO
"%s: link now down.\n", ndev
->name
);
754 dev
->linkstate
= newlinkstate
;
757 static int ns83820_setup_rx(struct net_device
*ndev
)
759 struct ns83820
*dev
= PRIV(ndev
);
763 dprintk("ns83820_setup_rx(%p)\n", ndev
);
765 dev
->rx_info
.idle
= 1;
766 dev
->rx_info
.next_rx
= 0;
767 dev
->rx_info
.next_rx_desc
= dev
->rx_info
.descs
;
768 dev
->rx_info
.next_empty
= 0;
770 for (i
=0; i
<NR_RX_DESC
; i
++)
771 clear_rx_desc(dev
, i
);
773 writel(0, dev
->base
+ RXDP_HI
);
774 writel(dev
->rx_info
.phy_descs
, dev
->base
+ RXDP
);
776 ret
= rx_refill(ndev
, GFP_KERNEL
);
778 dprintk("starting receiver\n");
779 /* prevent the interrupt handler from stomping on us */
780 spin_lock_irq(&dev
->rx_info
.lock
);
782 writel(0x0001, dev
->base
+ CCSR
);
783 writel(0, dev
->base
+ RFCR
);
784 writel(0x7fc00000, dev
->base
+ RFCR
);
785 writel(0xffc00000, dev
->base
+ RFCR
);
791 /* Okay, let it rip */
792 spin_lock_irq(&dev
->misc_lock
);
793 dev
->IMR_cache
|= ISR_PHY
;
794 dev
->IMR_cache
|= ISR_RXRCMP
;
795 //dev->IMR_cache |= ISR_RXERR;
796 //dev->IMR_cache |= ISR_RXOK;
797 dev
->IMR_cache
|= ISR_RXORN
;
798 dev
->IMR_cache
|= ISR_RXSOVR
;
799 dev
->IMR_cache
|= ISR_RXDESC
;
800 dev
->IMR_cache
|= ISR_RXIDLE
;
801 dev
->IMR_cache
|= ISR_TXDESC
;
802 dev
->IMR_cache
|= ISR_TXIDLE
;
804 writel(dev
->IMR_cache
, dev
->base
+ IMR
);
805 writel(1, dev
->base
+ IER
);
806 spin_unlock_irq(&dev
->misc_lock
);
810 spin_unlock_irq(&dev
->rx_info
.lock
);
815 static void ns83820_cleanup_rx(struct ns83820
*dev
)
820 dprintk("ns83820_cleanup_rx(%p)\n", dev
);
822 /* disable receive interrupts */
823 spin_lock_irqsave(&dev
->misc_lock
, flags
);
824 dev
->IMR_cache
&= ~(ISR_RXOK
| ISR_RXDESC
| ISR_RXERR
| ISR_RXEARLY
| ISR_RXIDLE
);
825 writel(dev
->IMR_cache
, dev
->base
+ IMR
);
826 spin_unlock_irqrestore(&dev
->misc_lock
, flags
);
828 /* synchronize with the interrupt handler and kill it */
830 synchronize_irq(dev
->pci_dev
->irq
);
832 /* touch the pci bus... */
833 readl(dev
->base
+ IMR
);
835 /* assumes the transmitter is already disabled and reset */
836 writel(0, dev
->base
+ RXDP_HI
);
837 writel(0, dev
->base
+ RXDP
);
839 for (i
=0; i
<NR_RX_DESC
; i
++) {
840 struct sk_buff
*skb
= dev
->rx_info
.skbs
[i
];
841 dev
->rx_info
.skbs
[i
] = NULL
;
842 clear_rx_desc(dev
, i
);
848 static void FASTCALL(ns83820_rx_kick(struct net_device
*ndev
));
849 static void fastcall
ns83820_rx_kick(struct net_device
*ndev
)
851 struct ns83820
*dev
= PRIV(ndev
);
852 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
853 if (dev
->rx_info
.up
) {
854 rx_refill_atomic(ndev
);
859 if (dev
->rx_info
.up
&& nr_rx_empty(dev
) > NR_RX_DESC
*3/4)
860 schedule_work(&dev
->tq_refill
);
863 if (dev
->rx_info
.idle
)
864 printk(KERN_DEBUG
"%s: BAD\n", ndev
->name
);
870 static void FASTCALL(rx_irq(struct net_device
*ndev
));
871 static void fastcall
rx_irq(struct net_device
*ndev
)
873 struct ns83820
*dev
= PRIV(ndev
);
874 struct rx_info
*info
= &dev
->rx_info
;
881 dprintk("rx_irq(%p)\n", ndev
);
882 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
883 readl(dev
->base
+ RXDP
),
884 (long)(dev
->rx_info
.phy_descs
),
885 (int)dev
->rx_info
.next_rx
,
886 (dev
->rx_info
.descs
+ (DESC_SIZE
* dev
->rx_info
.next_rx
)),
887 (int)dev
->rx_info
.next_empty
,
888 (dev
->rx_info
.descs
+ (DESC_SIZE
* dev
->rx_info
.next_empty
))
891 spin_lock_irqsave(&info
->lock
, flags
);
895 dprintk("walking descs\n");
896 next_rx
= info
->next_rx
;
897 desc
= info
->next_rx_desc
;
898 while ((CMDSTS_OWN
& (cmdsts
= le32_to_cpu(desc
[DESC_CMDSTS
]))) &&
899 (cmdsts
!= CMDSTS_OWN
)) {
901 u32 extsts
= le32_to_cpu(desc
[DESC_EXTSTS
]);
902 dma_addr_t bufptr
= desc_addr_get(desc
+ DESC_BUFPTR
);
904 dprintk("cmdsts: %08x\n", cmdsts
);
905 dprintk("link: %08x\n", cpu_to_le32(desc
[DESC_LINK
]));
906 dprintk("extsts: %08x\n", extsts
);
908 skb
= info
->skbs
[next_rx
];
909 info
->skbs
[next_rx
] = NULL
;
910 info
->next_rx
= (next_rx
+ 1) % NR_RX_DESC
;
913 clear_rx_desc(dev
, next_rx
);
915 pci_unmap_single(dev
->pci_dev
, bufptr
,
916 RX_BUF_SIZE
, PCI_DMA_FROMDEVICE
);
917 len
= cmdsts
& CMDSTS_LEN_MASK
;
918 #ifdef NS83820_VLAN_ACCEL_SUPPORT
919 /* NH: As was mentioned below, this chip is kinda
920 * brain dead about vlan tag stripping. Frames
921 * that are 64 bytes with a vlan header appended
922 * like arp frames, or pings, are flagged as Runts
923 * when the tag is stripped and hardware. This
924 * also means that the OK bit in the descriptor
925 * is cleared when the frame comes in so we have
926 * to do a specific length check here to make sure
927 * the frame would have been ok, had we not stripped
930 if (likely((CMDSTS_OK
& cmdsts
) ||
931 ((cmdsts
& CMDSTS_RUNT
) && len
>= 56))) {
933 if (likely(CMDSTS_OK
& cmdsts
)) {
937 goto netdev_mangle_me_harder_failed
;
938 if (cmdsts
& CMDSTS_DEST_MULTI
)
939 dev
->stats
.multicast
++;
940 dev
->stats
.rx_packets
++;
941 dev
->stats
.rx_bytes
+= len
;
942 if ((extsts
& 0x002a0000) && !(extsts
& 0x00540000)) {
943 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
945 skb
->ip_summed
= CHECKSUM_NONE
;
947 skb
->protocol
= eth_type_trans(skb
, ndev
);
948 #ifdef NS83820_VLAN_ACCEL_SUPPORT
949 if(extsts
& EXTSTS_VPKT
) {
951 tag
= ntohs(extsts
& EXTSTS_VTG_MASK
);
952 rx_rc
= vlan_hwaccel_rx(skb
,dev
->vlgrp
,tag
);
954 rx_rc
= netif_rx(skb
);
957 rx_rc
= netif_rx(skb
);
959 if (NET_RX_DROP
== rx_rc
) {
960 netdev_mangle_me_harder_failed
:
961 dev
->stats
.rx_dropped
++;
968 next_rx
= info
->next_rx
;
969 desc
= info
->descs
+ (DESC_SIZE
* next_rx
);
971 info
->next_rx
= next_rx
;
972 info
->next_rx_desc
= info
->descs
+ (DESC_SIZE
* next_rx
);
976 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts
);
979 spin_unlock_irqrestore(&info
->lock
, flags
);
982 static void rx_action(unsigned long _dev
)
984 struct net_device
*ndev
= (void *)_dev
;
985 struct ns83820
*dev
= PRIV(ndev
);
987 writel(ihr
, dev
->base
+ IHR
);
989 spin_lock_irq(&dev
->misc_lock
);
990 dev
->IMR_cache
|= ISR_RXDESC
;
991 writel(dev
->IMR_cache
, dev
->base
+ IMR
);
992 spin_unlock_irq(&dev
->misc_lock
);
995 ns83820_rx_kick(ndev
);
998 /* Packet Transmit code
1000 static inline void kick_tx(struct ns83820
*dev
)
1002 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
1003 dev
, dev
->tx_idx
, dev
->tx_free_idx
);
1004 writel(CR_TXE
, dev
->base
+ CR
);
1007 /* No spinlock needed on the transmit irq path as the interrupt handler is
1010 static void do_tx_done(struct net_device
*ndev
)
1012 struct ns83820
*dev
= PRIV(ndev
);
1013 u32 cmdsts
, tx_done_idx
, *desc
;
1015 spin_lock_irq(&dev
->tx_lock
);
1017 dprintk("do_tx_done(%p)\n", ndev
);
1018 tx_done_idx
= dev
->tx_done_idx
;
1019 desc
= dev
->tx_descs
+ (tx_done_idx
* DESC_SIZE
);
1021 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1022 tx_done_idx
, dev
->tx_free_idx
, le32_to_cpu(desc
[DESC_CMDSTS
]));
1023 while ((tx_done_idx
!= dev
->tx_free_idx
) &&
1024 !(CMDSTS_OWN
& (cmdsts
= le32_to_cpu(desc
[DESC_CMDSTS
]))) ) {
1025 struct sk_buff
*skb
;
1029 if (cmdsts
& CMDSTS_ERR
)
1030 dev
->stats
.tx_errors
++;
1031 if (cmdsts
& CMDSTS_OK
)
1032 dev
->stats
.tx_packets
++;
1033 if (cmdsts
& CMDSTS_OK
)
1034 dev
->stats
.tx_bytes
+= cmdsts
& 0xffff;
1036 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1037 tx_done_idx
, dev
->tx_free_idx
, cmdsts
);
1038 skb
= dev
->tx_skbs
[tx_done_idx
];
1039 dev
->tx_skbs
[tx_done_idx
] = NULL
;
1040 dprintk("done(%p)\n", skb
);
1042 len
= cmdsts
& CMDSTS_LEN_MASK
;
1043 addr
= desc_addr_get(desc
+ DESC_BUFPTR
);
1045 pci_unmap_single(dev
->pci_dev
,
1049 dev_kfree_skb_irq(skb
);
1050 atomic_dec(&dev
->nr_tx_skbs
);
1052 pci_unmap_page(dev
->pci_dev
,
1057 tx_done_idx
= (tx_done_idx
+ 1) % NR_TX_DESC
;
1058 dev
->tx_done_idx
= tx_done_idx
;
1059 desc
[DESC_CMDSTS
] = cpu_to_le32(0);
1061 desc
= dev
->tx_descs
+ (tx_done_idx
* DESC_SIZE
);
1064 /* Allow network stack to resume queueing packets after we've
1065 * finished transmitting at least 1/4 of the packets in the queue.
1067 if (netif_queue_stopped(ndev
) && start_tx_okay(dev
)) {
1068 dprintk("start_queue(%p)\n", ndev
);
1069 netif_start_queue(ndev
);
1070 netif_wake_queue(ndev
);
1072 spin_unlock_irq(&dev
->tx_lock
);
1075 static void ns83820_cleanup_tx(struct ns83820
*dev
)
1079 for (i
=0; i
<NR_TX_DESC
; i
++) {
1080 struct sk_buff
*skb
= dev
->tx_skbs
[i
];
1081 dev
->tx_skbs
[i
] = NULL
;
1083 u32
*desc
= dev
->tx_descs
+ (i
* DESC_SIZE
);
1084 pci_unmap_single(dev
->pci_dev
,
1085 desc_addr_get(desc
+ DESC_BUFPTR
),
1086 le32_to_cpu(desc
[DESC_CMDSTS
]) & CMDSTS_LEN_MASK
,
1088 dev_kfree_skb_irq(skb
);
1089 atomic_dec(&dev
->nr_tx_skbs
);
1093 memset(dev
->tx_descs
, 0, NR_TX_DESC
* DESC_SIZE
* 4);
1096 /* transmit routine. This code relies on the network layer serializing
1097 * its calls in, but will run happily in parallel with the interrupt
1098 * handler. This code currently has provisions for fragmenting tx buffers
1099 * while trying to track down a bug in either the zero copy code or
1100 * the tx fifo (hence the MAX_FRAG_LEN).
1102 static int ns83820_hard_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
1104 struct ns83820
*dev
= PRIV(ndev
);
1105 u32 free_idx
, cmdsts
, extsts
;
1106 int nr_free
, nr_frags
;
1107 unsigned tx_done_idx
, last_idx
;
1113 volatile u32
*first_desc
;
1115 dprintk("ns83820_hard_start_xmit\n");
1117 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1119 if (unlikely(dev
->CFG_cache
& CFG_LNKSTS
)) {
1120 netif_stop_queue(ndev
);
1121 if (unlikely(dev
->CFG_cache
& CFG_LNKSTS
))
1123 netif_start_queue(ndev
);
1126 last_idx
= free_idx
= dev
->tx_free_idx
;
1127 tx_done_idx
= dev
->tx_done_idx
;
1128 nr_free
= (tx_done_idx
+ NR_TX_DESC
-2 - free_idx
) % NR_TX_DESC
;
1130 if (nr_free
<= nr_frags
) {
1131 dprintk("stop_queue - not enough(%p)\n", ndev
);
1132 netif_stop_queue(ndev
);
1134 /* Check again: we may have raced with a tx done irq */
1135 if (dev
->tx_done_idx
!= tx_done_idx
) {
1136 dprintk("restart queue(%p)\n", ndev
);
1137 netif_start_queue(ndev
);
1143 if (free_idx
== dev
->tx_intr_idx
) {
1145 dev
->tx_intr_idx
= (dev
->tx_intr_idx
+ NR_TX_DESC
/4) % NR_TX_DESC
;
1148 nr_free
-= nr_frags
;
1149 if (nr_free
< MIN_TX_DESC_FREE
) {
1150 dprintk("stop_queue - last entry(%p)\n", ndev
);
1151 netif_stop_queue(ndev
);
1155 frag
= skb_shinfo(skb
)->frags
;
1159 if (skb
->ip_summed
== CHECKSUM_HW
) {
1160 extsts
|= EXTSTS_IPPKT
;
1161 if (IPPROTO_TCP
== skb
->nh
.iph
->protocol
)
1162 extsts
|= EXTSTS_TCPPKT
;
1163 else if (IPPROTO_UDP
== skb
->nh
.iph
->protocol
)
1164 extsts
|= EXTSTS_UDPPKT
;
1167 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1168 if(vlan_tx_tag_present(skb
)) {
1169 /* fetch the vlan tag info out of the
1170 * ancilliary data if the vlan code
1171 * is using hw vlan acceleration
1173 short tag
= vlan_tx_tag_get(skb
);
1174 extsts
|= (EXTSTS_VPKT
| htons(tag
));
1180 len
-= skb
->data_len
;
1181 buf
= pci_map_single(dev
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1183 first_desc
= dev
->tx_descs
+ (free_idx
* DESC_SIZE
);
1186 volatile u32
*desc
= dev
->tx_descs
+ (free_idx
* DESC_SIZE
);
1188 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx
, len
,
1189 (unsigned long long)buf
);
1190 last_idx
= free_idx
;
1191 free_idx
= (free_idx
+ 1) % NR_TX_DESC
;
1192 desc
[DESC_LINK
] = cpu_to_le32(dev
->tx_phy_descs
+ (free_idx
* DESC_SIZE
* 4));
1193 desc_addr_set(desc
+ DESC_BUFPTR
, buf
);
1194 desc
[DESC_EXTSTS
] = cpu_to_le32(extsts
);
1196 cmdsts
= ((nr_frags
) ? CMDSTS_MORE
: do_intr
? CMDSTS_INTR
: 0);
1197 cmdsts
|= (desc
== first_desc
) ? 0 : CMDSTS_OWN
;
1199 desc
[DESC_CMDSTS
] = cpu_to_le32(cmdsts
);
1204 buf
= pci_map_page(dev
->pci_dev
, frag
->page
,
1206 frag
->size
, PCI_DMA_TODEVICE
);
1207 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1208 (long long)buf
, (long) page_to_pfn(frag
->page
),
1214 dprintk("done pkt\n");
1216 spin_lock_irq(&dev
->tx_lock
);
1217 dev
->tx_skbs
[last_idx
] = skb
;
1218 first_desc
[DESC_CMDSTS
] |= cpu_to_le32(CMDSTS_OWN
);
1219 dev
->tx_free_idx
= free_idx
;
1220 atomic_inc(&dev
->nr_tx_skbs
);
1221 spin_unlock_irq(&dev
->tx_lock
);
1225 /* Check again: we may have raced with a tx done irq */
1226 if (stopped
&& (dev
->tx_done_idx
!= tx_done_idx
) && start_tx_okay(dev
))
1227 netif_start_queue(ndev
);
1229 /* set the transmit start time to catch transmit timeouts */
1230 ndev
->trans_start
= jiffies
;
1234 static void ns83820_update_stats(struct ns83820
*dev
)
1236 u8 __iomem
*base
= dev
->base
;
1238 /* the DP83820 will freeze counters, so we need to read all of them */
1239 dev
->stats
.rx_errors
+= readl(base
+ 0x60) & 0xffff;
1240 dev
->stats
.rx_crc_errors
+= readl(base
+ 0x64) & 0xffff;
1241 dev
->stats
.rx_missed_errors
+= readl(base
+ 0x68) & 0xffff;
1242 dev
->stats
.rx_frame_errors
+= readl(base
+ 0x6c) & 0xffff;
1243 /*dev->stats.rx_symbol_errors +=*/ readl(base
+ 0x70);
1244 dev
->stats
.rx_length_errors
+= readl(base
+ 0x74) & 0xffff;
1245 dev
->stats
.rx_length_errors
+= readl(base
+ 0x78) & 0xffff;
1246 /*dev->stats.rx_badopcode_errors += */ readl(base
+ 0x7c);
1247 /*dev->stats.rx_pause_count += */ readl(base
+ 0x80);
1248 /*dev->stats.tx_pause_count += */ readl(base
+ 0x84);
1249 dev
->stats
.tx_carrier_errors
+= readl(base
+ 0x88) & 0xff;
1252 static struct net_device_stats
*ns83820_get_stats(struct net_device
*ndev
)
1254 struct ns83820
*dev
= PRIV(ndev
);
1256 /* somewhat overkill */
1257 spin_lock_irq(&dev
->misc_lock
);
1258 ns83820_update_stats(dev
);
1259 spin_unlock_irq(&dev
->misc_lock
);
1264 static void ns83820_get_drvinfo(struct net_device
*ndev
, struct ethtool_drvinfo
*info
)
1266 struct ns83820
*dev
= PRIV(ndev
);
1267 strcpy(info
->driver
, "ns83820");
1268 strcpy(info
->version
, VERSION
);
1269 strcpy(info
->bus_info
, pci_name(dev
->pci_dev
));
1272 static u32
ns83820_get_link(struct net_device
*ndev
)
1274 struct ns83820
*dev
= PRIV(ndev
);
1275 u32 cfg
= readl(dev
->base
+ CFG
) ^ SPDSTS_POLARITY
;
1276 return cfg
& CFG_LNKSTS
? 1 : 0;
1279 static struct ethtool_ops ops
= {
1280 .get_drvinfo
= ns83820_get_drvinfo
,
1281 .get_link
= ns83820_get_link
1284 static void ns83820_mib_isr(struct ns83820
*dev
)
1286 spin_lock(&dev
->misc_lock
);
1287 ns83820_update_stats(dev
);
1288 spin_unlock(&dev
->misc_lock
);
1291 static void ns83820_do_isr(struct net_device
*ndev
, u32 isr
);
1292 static irqreturn_t
ns83820_irq(int foo
, void *data
, struct pt_regs
*regs
)
1294 struct net_device
*ndev
= data
;
1295 struct ns83820
*dev
= PRIV(ndev
);
1297 dprintk("ns83820_irq(%p)\n", ndev
);
1301 isr
= readl(dev
->base
+ ISR
);
1302 dprintk("irq: %08x\n", isr
);
1303 ns83820_do_isr(ndev
, isr
);
1307 static void ns83820_do_isr(struct net_device
*ndev
, u32 isr
)
1309 struct ns83820
*dev
= PRIV(ndev
);
1311 if (isr
& ~(ISR_PHY
| ISR_RXDESC
| ISR_RXEARLY
| ISR_RXOK
| ISR_RXERR
| ISR_TXIDLE
| ISR_TXOK
| ISR_TXDESC
))
1312 Dprintk("odd isr? 0x%08x\n", isr
);
1315 if (ISR_RXIDLE
& isr
) {
1316 dev
->rx_info
.idle
= 1;
1317 Dprintk("oh dear, we are idle\n");
1318 ns83820_rx_kick(ndev
);
1321 if ((ISR_RXDESC
| ISR_RXOK
) & isr
) {
1322 prefetch(dev
->rx_info
.next_rx_desc
);
1324 spin_lock_irq(&dev
->misc_lock
);
1325 dev
->IMR_cache
&= ~(ISR_RXDESC
| ISR_RXOK
);
1326 writel(dev
->IMR_cache
, dev
->base
+ IMR
);
1327 spin_unlock_irq(&dev
->misc_lock
);
1329 tasklet_schedule(&dev
->rx_tasklet
);
1331 //writel(4, dev->base + IHR);
1334 if ((ISR_RXIDLE
| ISR_RXORN
| ISR_RXDESC
| ISR_RXOK
| ISR_RXERR
) & isr
)
1335 ns83820_rx_kick(ndev
);
1337 if (unlikely(ISR_RXSOVR
& isr
)) {
1338 //printk("overrun: rxsovr\n");
1339 dev
->stats
.rx_fifo_errors
++;
1342 if (unlikely(ISR_RXORN
& isr
)) {
1343 //printk("overrun: rxorn\n");
1344 dev
->stats
.rx_fifo_errors
++;
1347 if ((ISR_RXRCMP
& isr
) && dev
->rx_info
.up
)
1348 writel(CR_RXE
, dev
->base
+ CR
);
1350 if (ISR_TXIDLE
& isr
) {
1352 txdp
= readl(dev
->base
+ TXDP
);
1353 dprintk("txdp: %08x\n", txdp
);
1354 txdp
-= dev
->tx_phy_descs
;
1355 dev
->tx_idx
= txdp
/ (DESC_SIZE
* 4);
1356 if (dev
->tx_idx
>= NR_TX_DESC
) {
1357 printk(KERN_ALERT
"%s: BUG -- txdp out of range\n", ndev
->name
);
1360 /* The may have been a race between a pci originated read
1361 * and the descriptor update from the cpu. Just in case,
1362 * kick the transmitter if the hardware thinks it is on a
1363 * different descriptor than we are.
1365 if (dev
->tx_idx
!= dev
->tx_free_idx
)
1369 /* Defer tx ring processing until more than a minimum amount of
1370 * work has accumulated
1372 if ((ISR_TXDESC
| ISR_TXIDLE
| ISR_TXOK
| ISR_TXERR
) & isr
) {
1375 /* Disable TxOk if there are no outstanding tx packets.
1377 if ((dev
->tx_done_idx
== dev
->tx_free_idx
) &&
1378 (dev
->IMR_cache
& ISR_TXOK
)) {
1379 spin_lock_irq(&dev
->misc_lock
);
1380 dev
->IMR_cache
&= ~ISR_TXOK
;
1381 writel(dev
->IMR_cache
, dev
->base
+ IMR
);
1382 spin_unlock_irq(&dev
->misc_lock
);
1386 /* The TxIdle interrupt can come in before the transmit has
1387 * completed. Normally we reap packets off of the combination
1388 * of TxDesc and TxIdle and leave TxOk disabled (since it
1389 * occurs on every packet), but when no further irqs of this
1390 * nature are expected, we must enable TxOk.
1392 if ((ISR_TXIDLE
& isr
) && (dev
->tx_done_idx
!= dev
->tx_free_idx
)) {
1393 spin_lock_irq(&dev
->misc_lock
);
1394 dev
->IMR_cache
|= ISR_TXOK
;
1395 writel(dev
->IMR_cache
, dev
->base
+ IMR
);
1396 spin_unlock_irq(&dev
->misc_lock
);
1399 /* MIB interrupt: one of the statistics counters is about to overflow */
1400 if (unlikely(ISR_MIB
& isr
))
1401 ns83820_mib_isr(dev
);
1403 /* PHY: Link up/down/negotiation state change */
1404 if (unlikely(ISR_PHY
& isr
))
1407 #if 0 /* Still working on the interrupt mitigation strategy */
1409 writel(dev
->ihr
, dev
->base
+ IHR
);
1413 static void ns83820_do_reset(struct ns83820
*dev
, u32 which
)
1415 Dprintk("resetting chip...\n");
1416 writel(which
, dev
->base
+ CR
);
1419 } while (readl(dev
->base
+ CR
) & which
);
1423 static int ns83820_stop(struct net_device
*ndev
)
1425 struct ns83820
*dev
= PRIV(ndev
);
1427 /* FIXME: protect against interrupt handler? */
1428 del_timer_sync(&dev
->tx_watchdog
);
1430 /* disable interrupts */
1431 writel(0, dev
->base
+ IMR
);
1432 writel(0, dev
->base
+ IER
);
1433 readl(dev
->base
+ IER
);
1435 dev
->rx_info
.up
= 0;
1436 synchronize_irq(dev
->pci_dev
->irq
);
1438 ns83820_do_reset(dev
, CR_RST
);
1440 synchronize_irq(dev
->pci_dev
->irq
);
1442 spin_lock_irq(&dev
->misc_lock
);
1443 dev
->IMR_cache
&= ~(ISR_TXURN
| ISR_TXIDLE
| ISR_TXERR
| ISR_TXDESC
| ISR_TXOK
);
1444 spin_unlock_irq(&dev
->misc_lock
);
1446 ns83820_cleanup_rx(dev
);
1447 ns83820_cleanup_tx(dev
);
1452 static void ns83820_tx_timeout(struct net_device
*ndev
)
1454 struct ns83820
*dev
= PRIV(ndev
);
1455 u32 tx_done_idx
, *desc
;
1456 unsigned long flags
;
1458 local_irq_save(flags
);
1460 tx_done_idx
= dev
->tx_done_idx
;
1461 desc
= dev
->tx_descs
+ (tx_done_idx
* DESC_SIZE
);
1463 printk(KERN_INFO
"%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1465 tx_done_idx
, dev
->tx_free_idx
, le32_to_cpu(desc
[DESC_CMDSTS
]));
1470 isr
= readl(dev
->base
+ ISR
);
1471 printk("irq: %08x imr: %08x\n", isr
, dev
->IMR_cache
);
1472 ns83820_do_isr(ndev
, isr
);
1478 tx_done_idx
= dev
->tx_done_idx
;
1479 desc
= dev
->tx_descs
+ (tx_done_idx
* DESC_SIZE
);
1481 printk(KERN_INFO
"%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1483 tx_done_idx
, dev
->tx_free_idx
, le32_to_cpu(desc
[DESC_CMDSTS
]));
1485 local_irq_restore(flags
);
1488 static void ns83820_tx_watch(unsigned long data
)
1490 struct net_device
*ndev
= (void *)data
;
1491 struct ns83820
*dev
= PRIV(ndev
);
1494 printk("ns83820_tx_watch: %u %u %d\n",
1495 dev
->tx_done_idx
, dev
->tx_free_idx
, atomic_read(&dev
->nr_tx_skbs
)
1499 if (time_after(jiffies
, ndev
->trans_start
+ 1*HZ
) &&
1500 dev
->tx_done_idx
!= dev
->tx_free_idx
) {
1501 printk(KERN_DEBUG
"%s: ns83820_tx_watch: %u %u %d\n",
1503 dev
->tx_done_idx
, dev
->tx_free_idx
,
1504 atomic_read(&dev
->nr_tx_skbs
));
1505 ns83820_tx_timeout(ndev
);
1508 mod_timer(&dev
->tx_watchdog
, jiffies
+ 2*HZ
);
1511 static int ns83820_open(struct net_device
*ndev
)
1513 struct ns83820
*dev
= PRIV(ndev
);
1518 dprintk("ns83820_open\n");
1520 writel(0, dev
->base
+ PQCR
);
1522 ret
= ns83820_setup_rx(ndev
);
1526 memset(dev
->tx_descs
, 0, 4 * NR_TX_DESC
* DESC_SIZE
);
1527 for (i
=0; i
<NR_TX_DESC
; i
++) {
1528 dev
->tx_descs
[(i
* DESC_SIZE
) + DESC_LINK
]
1531 + ((i
+1) % NR_TX_DESC
) * DESC_SIZE
* 4);
1535 dev
->tx_done_idx
= 0;
1536 desc
= dev
->tx_phy_descs
;
1537 writel(0, dev
->base
+ TXDP_HI
);
1538 writel(desc
, dev
->base
+ TXDP
);
1540 init_timer(&dev
->tx_watchdog
);
1541 dev
->tx_watchdog
.data
= (unsigned long)ndev
;
1542 dev
->tx_watchdog
.function
= ns83820_tx_watch
;
1543 mod_timer(&dev
->tx_watchdog
, jiffies
+ 2*HZ
);
1545 netif_start_queue(ndev
); /* FIXME: wait for phy to come up */
1554 static void ns83820_getmac(struct ns83820
*dev
, u8
*mac
)
1557 for (i
=0; i
<3; i
++) {
1560 /* Read from the perfect match memory: this is loaded by
1561 * the chip from the EEPROM via the EELOAD self test.
1563 writel(i
*2, dev
->base
+ RFCR
);
1564 data
= readl(dev
->base
+ RFDR
);
1571 static int ns83820_change_mtu(struct net_device
*ndev
, int new_mtu
)
1573 if (new_mtu
> RX_BUF_SIZE
)
1575 ndev
->mtu
= new_mtu
;
1579 static void ns83820_set_multicast(struct net_device
*ndev
)
1581 struct ns83820
*dev
= PRIV(ndev
);
1582 u8 __iomem
*rfcr
= dev
->base
+ RFCR
;
1583 u32 and_mask
= 0xffffffff;
1587 if (ndev
->flags
& IFF_PROMISC
)
1588 or_mask
|= RFCR_AAU
| RFCR_AAM
;
1590 and_mask
&= ~(RFCR_AAU
| RFCR_AAM
);
1592 if (ndev
->flags
& IFF_ALLMULTI
)
1593 or_mask
|= RFCR_AAM
;
1595 and_mask
&= ~RFCR_AAM
;
1597 spin_lock_irq(&dev
->misc_lock
);
1598 val
= (readl(rfcr
) & and_mask
) | or_mask
;
1599 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1600 writel(val
& ~RFCR_RFEN
, rfcr
);
1602 spin_unlock_irq(&dev
->misc_lock
);
1605 static void ns83820_run_bist(struct net_device
*ndev
, const char *name
, u32 enable
, u32 done
, u32 fail
)
1607 struct ns83820
*dev
= PRIV(ndev
);
1609 unsigned long start
;
1613 dprintk("%s: start %s\n", ndev
->name
, name
);
1617 writel(enable
, dev
->base
+ PTSCR
);
1620 status
= readl(dev
->base
+ PTSCR
);
1621 if (!(status
& enable
))
1627 if (time_after_eq(jiffies
, start
+ HZ
)) {
1631 schedule_timeout_uninterruptible(1);
1635 printk(KERN_INFO
"%s: %s failed! (0x%08x & 0x%08x)\n",
1636 ndev
->name
, name
, status
, fail
);
1638 printk(KERN_INFO
"%s: run_bist %s timed out! (%08x)\n",
1639 ndev
->name
, name
, status
);
1641 dprintk("%s: done %s in %d loops\n", ndev
->name
, name
, loops
);
1644 #ifdef PHY_CODE_IS_FINISHED
1645 static void ns83820_mii_write_bit(struct ns83820
*dev
, int bit
)
1648 dev
->MEAR_cache
&= ~MEAR_MDC
;
1649 writel(dev
->MEAR_cache
, dev
->base
+ MEAR
);
1650 readl(dev
->base
+ MEAR
);
1652 /* enable output, set bit */
1653 dev
->MEAR_cache
|= MEAR_MDDIR
;
1655 dev
->MEAR_cache
|= MEAR_MDIO
;
1657 dev
->MEAR_cache
&= ~MEAR_MDIO
;
1659 /* set the output bit */
1660 writel(dev
->MEAR_cache
, dev
->base
+ MEAR
);
1661 readl(dev
->base
+ MEAR
);
1663 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1666 /* drive MDC high causing the data bit to be latched */
1667 dev
->MEAR_cache
|= MEAR_MDC
;
1668 writel(dev
->MEAR_cache
, dev
->base
+ MEAR
);
1669 readl(dev
->base
+ MEAR
);
1675 static int ns83820_mii_read_bit(struct ns83820
*dev
)
1679 /* drive MDC low, disable output */
1680 dev
->MEAR_cache
&= ~MEAR_MDC
;
1681 dev
->MEAR_cache
&= ~MEAR_MDDIR
;
1682 writel(dev
->MEAR_cache
, dev
->base
+ MEAR
);
1683 readl(dev
->base
+ MEAR
);
1685 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1688 /* drive MDC high causing the data bit to be latched */
1689 bit
= (readl(dev
->base
+ MEAR
) & MEAR_MDIO
) ? 1 : 0;
1690 dev
->MEAR_cache
|= MEAR_MDC
;
1691 writel(dev
->MEAR_cache
, dev
->base
+ MEAR
);
1699 static unsigned ns83820_mii_read_reg(struct ns83820
*dev
, unsigned phy
, unsigned reg
)
1704 /* read some garbage so that we eventually sync up */
1705 for (i
=0; i
<64; i
++)
1706 ns83820_mii_read_bit(dev
);
1708 ns83820_mii_write_bit(dev
, 0); /* start */
1709 ns83820_mii_write_bit(dev
, 1);
1710 ns83820_mii_write_bit(dev
, 1); /* opcode read */
1711 ns83820_mii_write_bit(dev
, 0);
1713 /* write out the phy address: 5 bits, msb first */
1715 ns83820_mii_write_bit(dev
, phy
& (0x10 >> i
));
1717 /* write out the register address, 5 bits, msb first */
1719 ns83820_mii_write_bit(dev
, reg
& (0x10 >> i
));
1721 ns83820_mii_read_bit(dev
); /* turn around cycles */
1722 ns83820_mii_read_bit(dev
);
1724 /* read in the register data, 16 bits msb first */
1725 for (i
=0; i
<16; i
++) {
1727 data
|= ns83820_mii_read_bit(dev
);
1733 static unsigned ns83820_mii_write_reg(struct ns83820
*dev
, unsigned phy
, unsigned reg
, unsigned data
)
1737 /* read some garbage so that we eventually sync up */
1738 for (i
=0; i
<64; i
++)
1739 ns83820_mii_read_bit(dev
);
1741 ns83820_mii_write_bit(dev
, 0); /* start */
1742 ns83820_mii_write_bit(dev
, 1);
1743 ns83820_mii_write_bit(dev
, 0); /* opcode read */
1744 ns83820_mii_write_bit(dev
, 1);
1746 /* write out the phy address: 5 bits, msb first */
1748 ns83820_mii_write_bit(dev
, phy
& (0x10 >> i
));
1750 /* write out the register address, 5 bits, msb first */
1752 ns83820_mii_write_bit(dev
, reg
& (0x10 >> i
));
1754 ns83820_mii_read_bit(dev
); /* turn around cycles */
1755 ns83820_mii_read_bit(dev
);
1757 /* read in the register data, 16 bits msb first */
1758 for (i
=0; i
<16; i
++)
1759 ns83820_mii_write_bit(dev
, (data
>> (15 - i
)) & 1);
1764 static void ns83820_probe_phy(struct net_device
*ndev
)
1766 struct ns83820
*dev
= PRIV(ndev
);
1769 #define MII_PHYIDR1 0x02
1770 #define MII_PHYIDR2 0x03
1775 ns83820_mii_read_reg(dev
, 1, 0x09);
1776 ns83820_mii_write_reg(dev
, 1, 0x10, 0x0d3e);
1778 tmp
= ns83820_mii_read_reg(dev
, 1, 0x00);
1779 ns83820_mii_write_reg(dev
, 1, 0x00, tmp
| 0x8000);
1781 ns83820_mii_read_reg(dev
, 1, 0x09);
1786 for (i
=1; i
<2; i
++) {
1789 a
= ns83820_mii_read_reg(dev
, i
, MII_PHYIDR1
);
1790 b
= ns83820_mii_read_reg(dev
, i
, MII_PHYIDR2
);
1792 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1793 // ndev->name, i, a, b);
1795 for (j
=0; j
<0x16; j
+=4) {
1796 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1798 ns83820_mii_read_reg(dev
, i
, 0 + j
),
1799 ns83820_mii_read_reg(dev
, i
, 1 + j
),
1800 ns83820_mii_read_reg(dev
, i
, 2 + j
),
1801 ns83820_mii_read_reg(dev
, i
, 3 + j
)
1807 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1808 ns83820_mii_write_reg(dev
, 1, 0x16, 0x000d);
1809 ns83820_mii_write_reg(dev
, 1, 0x1e, 0x810e);
1810 a
= ns83820_mii_read_reg(dev
, 1, 0x1d);
1812 ns83820_mii_write_reg(dev
, 1, 0x16, 0x000d);
1813 ns83820_mii_write_reg(dev
, 1, 0x1e, 0x810e);
1814 b
= ns83820_mii_read_reg(dev
, 1, 0x1d);
1815 dprintk("version: 0x%04x 0x%04x\n", a
, b
);
1820 static int __devinit
ns83820_init_one(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
1822 struct net_device
*ndev
;
1823 struct ns83820
*dev
;
1828 /* See if we can set the dma mask early on; failure is fatal. */
1829 if (sizeof(dma_addr_t
) == 8 &&
1830 !pci_set_dma_mask(pci_dev
, DMA_64BIT_MASK
)) {
1832 } else if (!pci_set_dma_mask(pci_dev
, DMA_32BIT_MASK
)) {
1835 printk(KERN_WARNING
"ns83820.c: pci_set_dma_mask failed!\n");
1839 ndev
= alloc_etherdev(sizeof(struct ns83820
));
1845 spin_lock_init(&dev
->rx_info
.lock
);
1846 spin_lock_init(&dev
->tx_lock
);
1847 spin_lock_init(&dev
->misc_lock
);
1848 dev
->pci_dev
= pci_dev
;
1850 SET_MODULE_OWNER(ndev
);
1851 SET_NETDEV_DEV(ndev
, &pci_dev
->dev
);
1853 INIT_WORK(&dev
->tq_refill
, queue_refill
, ndev
);
1854 tasklet_init(&dev
->rx_tasklet
, rx_action
, (unsigned long)ndev
);
1856 err
= pci_enable_device(pci_dev
);
1858 printk(KERN_INFO
"ns83820: pci_enable_dev failed: %d\n", err
);
1862 pci_set_master(pci_dev
);
1863 addr
= pci_resource_start(pci_dev
, 1);
1864 dev
->base
= ioremap_nocache(addr
, PAGE_SIZE
);
1865 dev
->tx_descs
= pci_alloc_consistent(pci_dev
,
1866 4 * DESC_SIZE
* NR_TX_DESC
, &dev
->tx_phy_descs
);
1867 dev
->rx_info
.descs
= pci_alloc_consistent(pci_dev
,
1868 4 * DESC_SIZE
* NR_RX_DESC
, &dev
->rx_info
.phy_descs
);
1870 if (!dev
->base
|| !dev
->tx_descs
|| !dev
->rx_info
.descs
)
1873 dprintk("%p: %08lx %p: %08lx\n",
1874 dev
->tx_descs
, (long)dev
->tx_phy_descs
,
1875 dev
->rx_info
.descs
, (long)dev
->rx_info
.phy_descs
);
1877 /* disable interrupts */
1878 writel(0, dev
->base
+ IMR
);
1879 writel(0, dev
->base
+ IER
);
1880 readl(dev
->base
+ IER
);
1884 err
= request_irq(pci_dev
->irq
, ns83820_irq
, IRQF_SHARED
,
1887 printk(KERN_INFO
"ns83820: unable to register irq %d\n",
1893 * FIXME: we are holding rtnl_lock() over obscenely long area only
1894 * because some of the setup code uses dev->name. It's Wrong(tm) -
1895 * we should be using driver-specific names for all that stuff.
1896 * For now that will do, but we really need to come back and kill
1897 * most of the dev_alloc_name() users later.
1900 err
= dev_alloc_name(ndev
, ndev
->name
);
1902 printk(KERN_INFO
"ns83820: unable to get netdev name: %d\n", err
);
1906 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1907 ndev
->name
, le32_to_cpu(readl(dev
->base
+ 0x22c)),
1908 pci_dev
->subsystem_vendor
, pci_dev
->subsystem_device
);
1910 ndev
->open
= ns83820_open
;
1911 ndev
->stop
= ns83820_stop
;
1912 ndev
->hard_start_xmit
= ns83820_hard_start_xmit
;
1913 ndev
->get_stats
= ns83820_get_stats
;
1914 ndev
->change_mtu
= ns83820_change_mtu
;
1915 ndev
->set_multicast_list
= ns83820_set_multicast
;
1916 SET_ETHTOOL_OPS(ndev
, &ops
);
1917 ndev
->tx_timeout
= ns83820_tx_timeout
;
1918 ndev
->watchdog_timeo
= 5 * HZ
;
1919 pci_set_drvdata(pci_dev
, ndev
);
1921 ns83820_do_reset(dev
, CR_RST
);
1923 /* Must reset the ram bist before running it */
1924 writel(PTSCR_RBIST_RST
, dev
->base
+ PTSCR
);
1925 ns83820_run_bist(ndev
, "sram bist", PTSCR_RBIST_EN
,
1926 PTSCR_RBIST_DONE
, PTSCR_RBIST_FAIL
);
1927 ns83820_run_bist(ndev
, "eeprom bist", PTSCR_EEBIST_EN
, 0,
1929 ns83820_run_bist(ndev
, "eeprom load", PTSCR_EELOAD_EN
, 0, 0);
1931 /* I love config registers */
1932 dev
->CFG_cache
= readl(dev
->base
+ CFG
);
1934 if ((dev
->CFG_cache
& CFG_PCI64_DET
)) {
1935 printk(KERN_INFO
"%s: detected 64 bit PCI data bus.\n",
1937 /*dev->CFG_cache |= CFG_DATA64_EN;*/
1938 if (!(dev
->CFG_cache
& CFG_DATA64_EN
))
1939 printk(KERN_INFO
"%s: EEPROM did not enable 64 bit bus. Disabled.\n",
1942 dev
->CFG_cache
&= ~(CFG_DATA64_EN
);
1944 dev
->CFG_cache
&= (CFG_TBI_EN
| CFG_MRM_DIS
| CFG_MWI_DIS
|
1945 CFG_T64ADDR
| CFG_DATA64_EN
| CFG_EXT_125
|
1947 dev
->CFG_cache
|= CFG_PINT_DUPSTS
| CFG_PINT_LNKSTS
| CFG_PINT_SPDSTS
|
1948 CFG_EXTSTS_EN
| CFG_EXD
| CFG_PESEL
;
1949 dev
->CFG_cache
|= CFG_REQALG
;
1950 dev
->CFG_cache
|= CFG_POW
;
1951 dev
->CFG_cache
|= CFG_TMRTEST
;
1953 /* When compiled with 64 bit addressing, we must always enable
1954 * the 64 bit descriptor format.
1956 if (sizeof(dma_addr_t
) == 8)
1957 dev
->CFG_cache
|= CFG_M64ADDR
;
1959 dev
->CFG_cache
|= CFG_T64ADDR
;
1961 /* Big endian mode does not seem to do what the docs suggest */
1962 dev
->CFG_cache
&= ~CFG_BEM
;
1964 /* setup optical transceiver if we have one */
1965 if (dev
->CFG_cache
& CFG_TBI_EN
) {
1966 printk(KERN_INFO
"%s: enabling optical transceiver\n",
1968 writel(readl(dev
->base
+ GPIOR
) | 0x3e8, dev
->base
+ GPIOR
);
1970 /* setup auto negotiation feature advertisement */
1971 writel(readl(dev
->base
+ TANAR
)
1972 | TANAR_HALF_DUP
| TANAR_FULL_DUP
,
1975 /* start auto negotiation */
1976 writel(TBICR_MR_AN_ENABLE
| TBICR_MR_RESTART_AN
,
1978 writel(TBICR_MR_AN_ENABLE
, dev
->base
+ TBICR
);
1979 dev
->linkstate
= LINK_AUTONEGOTIATE
;
1981 dev
->CFG_cache
|= CFG_MODE_1000
;
1984 writel(dev
->CFG_cache
, dev
->base
+ CFG
);
1985 dprintk("CFG: %08x\n", dev
->CFG_cache
);
1988 printk(KERN_INFO
"%s: resetting phy\n", ndev
->name
);
1989 writel(dev
->CFG_cache
| CFG_PHY_RST
, dev
->base
+ CFG
);
1991 writel(dev
->CFG_cache
, dev
->base
+ CFG
);
1994 #if 0 /* Huh? This sets the PCI latency register. Should be done via
1995 * the PCI layer. FIXME.
1997 if (readl(dev
->base
+ SRR
))
1998 writel(readl(dev
->base
+0x20c) | 0xfe00, dev
->base
+ 0x20c);
2001 /* Note! The DMA burst size interacts with packet
2002 * transmission, such that the largest packet that
2003 * can be transmitted is 8192 - FLTH - burst size.
2004 * If only the transmit fifo was larger...
2006 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2007 * some DELL and COMPAQ SMP systems */
2008 writel(TXCFG_CSI
| TXCFG_HBI
| TXCFG_ATP
| TXCFG_MXDMA512
2009 | ((1600 / 32) * 0x100),
2012 /* Flush the interrupt holdoff timer */
2013 writel(0x000, dev
->base
+ IHR
);
2014 writel(0x100, dev
->base
+ IHR
);
2015 writel(0x000, dev
->base
+ IHR
);
2017 /* Set Rx to full duplex, don't accept runt, errored, long or length
2018 * range errored packets. Use 512 byte DMA.
2020 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2021 * some DELL and COMPAQ SMP systems
2022 * Turn on ALP, only we are accpeting Jumbo Packets */
2023 writel(RXCFG_AEP
| RXCFG_ARP
| RXCFG_AIRL
| RXCFG_RX_FD
2026 | (RXCFG_MXDMA512
) | 0, dev
->base
+ RXCFG
);
2028 /* Disable priority queueing */
2029 writel(0, dev
->base
+ PQCR
);
2031 /* Enable IP checksum validation and detetion of VLAN headers.
2032 * Note: do not set the reject options as at least the 0x102
2033 * revision of the chip does not properly accept IP fragments
2036 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2037 * the MAC it calculates the packetsize AFTER stripping the VLAN
2038 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2039 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2040 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2041 * it discrards it!. These guys......
2042 * also turn on tag stripping if hardware acceleration is enabled
2044 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2045 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2047 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2049 writel(VRCR_INIT_VALUE
, dev
->base
+ VRCR
);
2051 /* Enable per-packet TCP/UDP/IP checksumming
2052 * and per packet vlan tag insertion if
2053 * vlan hardware acceleration is enabled
2055 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2056 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2058 #define VTCR_INIT_VALUE VTCR_PPCHK
2060 writel(VTCR_INIT_VALUE
, dev
->base
+ VTCR
);
2062 /* Ramit : Enable async and sync pause frames */
2063 /* writel(0, dev->base + PCR); */
2064 writel((PCR_PS_MCAST
| PCR_PS_DA
| PCR_PSEN
| PCR_FFLO_4K
|
2065 PCR_FFHI_8K
| PCR_STLO_4
| PCR_STHI_8
| PCR_PAUSE_CNT
),
2068 /* Disable Wake On Lan */
2069 writel(0, dev
->base
+ WCSR
);
2071 ns83820_getmac(dev
, ndev
->dev_addr
);
2073 /* Yes, we support dumb IP checksum on transmit */
2074 ndev
->features
|= NETIF_F_SG
;
2075 ndev
->features
|= NETIF_F_IP_CSUM
;
2077 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2078 /* We also support hardware vlan acceleration */
2079 ndev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
2080 ndev
->vlan_rx_register
= ns83820_vlan_rx_register
;
2081 ndev
->vlan_rx_kill_vid
= ns83820_vlan_rx_kill_vid
;
2085 printk(KERN_INFO
"%s: using 64 bit addressing.\n",
2087 ndev
->features
|= NETIF_F_HIGHDMA
;
2090 printk(KERN_INFO
"%s: ns83820 v" VERSION
": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
2092 (unsigned)readl(dev
->base
+ SRR
) >> 8,
2093 (unsigned)readl(dev
->base
+ SRR
) & 0xff,
2094 ndev
->dev_addr
[0], ndev
->dev_addr
[1],
2095 ndev
->dev_addr
[2], ndev
->dev_addr
[3],
2096 ndev
->dev_addr
[4], ndev
->dev_addr
[5],
2098 (ndev
->features
& NETIF_F_HIGHDMA
) ? "h,sg" : "sg"
2101 #ifdef PHY_CODE_IS_FINISHED
2102 ns83820_probe_phy(ndev
);
2105 err
= register_netdevice(ndev
);
2107 printk(KERN_INFO
"ns83820: unable to register netdev: %d\n", err
);
2115 writel(0, dev
->base
+ IMR
); /* paranoia */
2116 writel(0, dev
->base
+ IER
);
2117 readl(dev
->base
+ IER
);
2120 free_irq(pci_dev
->irq
, ndev
);
2124 pci_free_consistent(pci_dev
, 4 * DESC_SIZE
* NR_TX_DESC
, dev
->tx_descs
, dev
->tx_phy_descs
);
2125 pci_free_consistent(pci_dev
, 4 * DESC_SIZE
* NR_RX_DESC
, dev
->rx_info
.descs
, dev
->rx_info
.phy_descs
);
2126 pci_disable_device(pci_dev
);
2129 pci_set_drvdata(pci_dev
, NULL
);
2134 static void __devexit
ns83820_remove_one(struct pci_dev
*pci_dev
)
2136 struct net_device
*ndev
= pci_get_drvdata(pci_dev
);
2137 struct ns83820
*dev
= PRIV(ndev
); /* ok even if NULL */
2139 if (!ndev
) /* paranoia */
2142 writel(0, dev
->base
+ IMR
); /* paranoia */
2143 writel(0, dev
->base
+ IER
);
2144 readl(dev
->base
+ IER
);
2146 unregister_netdev(ndev
);
2147 free_irq(dev
->pci_dev
->irq
, ndev
);
2149 pci_free_consistent(dev
->pci_dev
, 4 * DESC_SIZE
* NR_TX_DESC
,
2150 dev
->tx_descs
, dev
->tx_phy_descs
);
2151 pci_free_consistent(dev
->pci_dev
, 4 * DESC_SIZE
* NR_RX_DESC
,
2152 dev
->rx_info
.descs
, dev
->rx_info
.phy_descs
);
2153 pci_disable_device(dev
->pci_dev
);
2155 pci_set_drvdata(pci_dev
, NULL
);
2158 static struct pci_device_id ns83820_pci_tbl
[] = {
2159 { 0x100b, 0x0022, PCI_ANY_ID
, PCI_ANY_ID
, 0, .driver_data
= 0, },
2163 static struct pci_driver driver
= {
2165 .id_table
= ns83820_pci_tbl
,
2166 .probe
= ns83820_init_one
,
2167 .remove
= __devexit_p(ns83820_remove_one
),
2168 #if 0 /* FIXME: implement */
2175 static int __init
ns83820_init(void)
2177 printk(KERN_INFO
"ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2178 return pci_module_init(&driver
);
2181 static void __exit
ns83820_exit(void)
2183 pci_unregister_driver(&driver
);
2186 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2187 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2188 MODULE_LICENSE("GPL");
2190 MODULE_DEVICE_TABLE(pci
, ns83820_pci_tbl
);
2192 module_param(lnksts
, int, 0);
2193 MODULE_PARM_DESC(lnksts
, "Polarity of LNKSTS bit");
2195 module_param(ihr
, int, 0);
2196 MODULE_PARM_DESC(ihr
, "Time in 100 us increments to delay interrupts (range 0-127)");
2198 module_param(reset_phy
, int, 0);
2199 MODULE_PARM_DESC(reset_phy
, "Set to 1 to reset the PHY on startup");
2201 module_init(ns83820_init
);
2202 module_exit(ns83820_exit
);