drivers/net/pasemi_mac.h

   1 /*
   2  * Copyright (C) 2006 PA Semi, Inc
   3  *
   4  * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
   5  * hardware register layouts.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  */
  20
  21 #ifndef PASEMI_MAC_H
  22 #define PASEMI_MAC_H
  23
  24 #include <linux/ethtool.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/phy.h>
  28
  29 struct pasemi_mac_txring {
  30         spinlock_t       lock;
  31         u64             *status; /* Ptr to cacheable status area */
  32         u64             *ring;
  33         dma_addr_t       dma;
  34         unsigned int     size;
  35         unsigned int     next_to_fill;
  36         unsigned int     next_to_clean;
  37         struct pasemi_mac_buffer *ring_info;
  38         int              chan;
  39         struct pasemi_mac *mac; /* Needed in intr handler */
  40 };
  41
  42 struct pasemi_mac_rxring {
  43         spinlock_t       lock;
  44         u64             *status; /* Ptr to cacheable status area */
  45         u64             *ring;  /* RX channel descriptor ring */
  46         dma_addr_t       dma;
  47         u64             *buffers;       /* RX interface buffer ring */
  48         dma_addr_t       buf_dma;
  49         unsigned int     size;
  50         unsigned int     next_to_fill;
  51         unsigned int     next_to_clean;
  52         struct pasemi_mac_buffer *ring_info;
  53         struct pasemi_mac *mac; /* Needed in intr handler */
  54 };
  55
  56 struct pasemi_mac {
  57         struct net_device *netdev;
  58         void __iomem *regs;
  59         void __iomem *dma_regs;
  60         void __iomem *iob_regs;
  61         struct pci_dev *pdev;
  62         struct pci_dev *dma_pdev;
  63         struct pci_dev *iob_pdev;
  64         struct phy_device *phydev;
  65         struct napi_struct napi;
  66
  67         u8              type;
  68 #define MAC_TYPE_GMAC   1
  69 #define MAC_TYPE_XAUI   2
  70         u32     dma_txch;
  71         u32     dma_rxch;
  72         u32     dma_if;
  73
  74         u8              mac_addr[6];
  75
  76         struct timer_list       rxtimer;
  77
  78         struct pasemi_mac_txring *tx;
  79         struct pasemi_mac_rxring *rx;
  80         unsigned int    tx_irq;
  81         unsigned int    rx_irq;
  82         char            tx_irq_name[10];                /* "eth%d tx" */
  83         char            rx_irq_name[10];                /* "eth%d rx" */
  84         int     link;
  85         int     speed;
  86         int     duplex;
  87
  88         unsigned int    msg_enable;
  89         char    phy_id[BUS_ID_SIZE];
  90 };
  91
  92 /* Software status descriptor (ring_info) */
  93 struct pasemi_mac_buffer {
  94         struct sk_buff *skb;
  95         dma_addr_t      dma;
  96 };
  97
  98
  99 /* PCI register offsets and formats */
 100
 101
 102 /* MAC CFG register offsets */
 103 enum {
 104         PAS_MAC_CFG_PCFG = 0x80,
 105         PAS_MAC_CFG_TXP = 0x98,
 106         PAS_MAC_IPC_CHNL = 0x208,
 107 };
 108
 109 /* MAC CFG register fields */
 110 #define PAS_MAC_CFG_PCFG_PE             0x80000000
 111 #define PAS_MAC_CFG_PCFG_CE             0x40000000
 112 #define PAS_MAC_CFG_PCFG_BU             0x20000000
 113 #define PAS_MAC_CFG_PCFG_TT             0x10000000
 114 #define PAS_MAC_CFG_PCFG_TSR_M          0x0c000000
 115 #define PAS_MAC_CFG_PCFG_TSR_10M        0x00000000
 116 #define PAS_MAC_CFG_PCFG_TSR_100M       0x04000000
 117 #define PAS_MAC_CFG_PCFG_TSR_1G         0x08000000
 118 #define PAS_MAC_CFG_PCFG_TSR_10G        0x0c000000
 119 #define PAS_MAC_CFG_PCFG_T24            0x02000000
 120 #define PAS_MAC_CFG_PCFG_PR             0x01000000
 121 #define PAS_MAC_CFG_PCFG_CRO_M          0x00ff0000
 122 #define PAS_MAC_CFG_PCFG_CRO_S  16
 123 #define PAS_MAC_CFG_PCFG_IPO_M          0x0000ff00
 124 #define PAS_MAC_CFG_PCFG_IPO_S  8
 125 #define PAS_MAC_CFG_PCFG_S1             0x00000080
 126 #define PAS_MAC_CFG_PCFG_IO_M           0x00000060
 127 #define PAS_MAC_CFG_PCFG_IO_MAC         0x00000000
 128 #define PAS_MAC_CFG_PCFG_IO_OFF         0x00000020
 129 #define PAS_MAC_CFG_PCFG_IO_IND_ETH     0x00000040
 130 #define PAS_MAC_CFG_PCFG_IO_IND_IP      0x00000060
 131 #define PAS_MAC_CFG_PCFG_LP             0x00000010
 132 #define PAS_MAC_CFG_PCFG_TS             0x00000008
 133 #define PAS_MAC_CFG_PCFG_HD             0x00000004
 134 #define PAS_MAC_CFG_PCFG_SPD_M          0x00000003
 135 #define PAS_MAC_CFG_PCFG_SPD_10M        0x00000000
 136 #define PAS_MAC_CFG_PCFG_SPD_100M       0x00000001
 137 #define PAS_MAC_CFG_PCFG_SPD_1G         0x00000002
 138 #define PAS_MAC_CFG_PCFG_SPD_10G        0x00000003
 139 #define PAS_MAC_CFG_TXP_FCF             0x01000000
 140 #define PAS_MAC_CFG_TXP_FCE             0x00800000
 141 #define PAS_MAC_CFG_TXP_FC              0x00400000
 142 #define PAS_MAC_CFG_TXP_FPC_M           0x00300000
 143 #define PAS_MAC_CFG_TXP_FPC_S           20
 144 #define PAS_MAC_CFG_TXP_FPC(x)          (((x) << PAS_MAC_CFG_TXP_FPC_S) & \
 145                                          PAS_MAC_CFG_TXP_FPC_M)
 146 #define PAS_MAC_CFG_TXP_RT              0x00080000
 147 #define PAS_MAC_CFG_TXP_BL              0x00040000
 148 #define PAS_MAC_CFG_TXP_SL_M            0x00030000
 149 #define PAS_MAC_CFG_TXP_SL_S            16
 150 #define PAS_MAC_CFG_TXP_SL(x)           (((x) << PAS_MAC_CFG_TXP_SL_S) & \
 151                                          PAS_MAC_CFG_TXP_SL_M)
 152 #define PAS_MAC_CFG_TXP_COB_M           0x0000f000
 153 #define PAS_MAC_CFG_TXP_COB_S           12
 154 #define PAS_MAC_CFG_TXP_COB(x)          (((x) << PAS_MAC_CFG_TXP_COB_S) & \
 155                                          PAS_MAC_CFG_TXP_COB_M)
 156 #define PAS_MAC_CFG_TXP_TIFT_M          0x00000f00
 157 #define PAS_MAC_CFG_TXP_TIFT_S          8
 158 #define PAS_MAC_CFG_TXP_TIFT(x)         (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
 159                                          PAS_MAC_CFG_TXP_TIFT_M)
 160 #define PAS_MAC_CFG_TXP_TIFG_M          0x000000ff
 161 #define PAS_MAC_CFG_TXP_TIFG_S          0
 162 #define PAS_MAC_CFG_TXP_TIFG(x)         (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
 163                                          PAS_MAC_CFG_TXP_TIFG_M)
 164
 165 #define PAS_MAC_IPC_CHNL_DCHNO_M        0x003f0000
 166 #define PAS_MAC_IPC_CHNL_DCHNO_S        16
 167 #define PAS_MAC_IPC_CHNL_DCHNO(x)       (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
 168                                          PAS_MAC_IPC_CHNL_DCHNO_M)
 169 #define PAS_MAC_IPC_CHNL_BCH_M          0x0000003f
 170 #define PAS_MAC_IPC_CHNL_BCH_S          0
 171 #define PAS_MAC_IPC_CHNL_BCH(x)         (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
 172                                          PAS_MAC_IPC_CHNL_BCH_M)
 173
 174 #endif /* PASEMI_MAC_H */