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[mirror_ubuntu-artful-kernel.git] / drivers / net / pcmcia / nmclan_cs.c
1 /* ----------------------------------------------------------------------------
2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9 Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003
12
13 This software may be used and distributed according to the terms of
14 the GNU General Public License.
15
16 Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi>
18
19 References
20
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
26
27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net>
33
34 The Linux client driver is based on the 3c589_cs.c client driver by
35 David Hinds.
36
37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are
39 by Donald Becker.
40
41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
43
44 Special thanks for testing and help in debugging this driver goes
45 to Ken Lesniak.
46
47 -------------------------------------------------------------------------------
48 Driver Notes and Issues
49 -------------------------------------------------------------------------------
50
51 1. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
54
55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values.
59
60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
61 before extraction.
62
63 4. There is a bad slow-down problem in this driver.
64
65 5. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled.
67
68 -------------------------------------------------------------------------------
69 History
70 -------------------------------------------------------------------------------
71 Log: nmclan_cs.c,v
72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking.
75 *
76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly.
78 *
79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling.
81 *
82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
86 *
87 * Revision 0.13 1995/05/18 05:56:34 rpao
88 * Statistics changes.
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
91 *
92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul.
94 *
95
96 95/05/13 rpao V0.10a
97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending.
100 95/05/11 rpao V0.10
101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible.
103 95/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104 *Released
105 95/05/10 rpao V0.08
106 Bug fix: Make all non-exported functions private by using
107 static keyword.
108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
109 95/05/10 rpao V0.07 Statistics.
110 95/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111
112 ---------------------------------------------------------------------------- */
113
114 #define DRV_NAME "nmclan_cs"
115 #define DRV_VERSION "0.16"
116
117
118 /* ----------------------------------------------------------------------------
119 Conditional Compilation Options
120 ---------------------------------------------------------------------------- */
121
122 #define MULTI_TX 0
123 #define RESET_ON_TIMEOUT 1
124 #define TX_INTERRUPTABLE 1
125 #define RESET_XILINX 0
126
127 /* ----------------------------------------------------------------------------
128 Include Files
129 ---------------------------------------------------------------------------- */
130
131 #include <linux/module.h>
132 #include <linux/kernel.h>
133 #include <linux/init.h>
134 #include <linux/ptrace.h>
135 #include <linux/slab.h>
136 #include <linux/string.h>
137 #include <linux/timer.h>
138 #include <linux/interrupt.h>
139 #include <linux/in.h>
140 #include <linux/delay.h>
141 #include <linux/ethtool.h>
142 #include <linux/netdevice.h>
143 #include <linux/etherdevice.h>
144 #include <linux/skbuff.h>
145 #include <linux/if_arp.h>
146 #include <linux/ioport.h>
147 #include <linux/bitops.h>
148
149 #include <pcmcia/cisreg.h>
150 #include <pcmcia/cistpl.h>
151 #include <pcmcia/ds.h>
152
153 #include <asm/uaccess.h>
154 #include <asm/io.h>
155 #include <asm/system.h>
156
157 /* ----------------------------------------------------------------------------
158 Defines
159 ---------------------------------------------------------------------------- */
160
161 #define ETHER_ADDR_LEN ETH_ALEN
162 /* 6 bytes in an Ethernet Address */
163 #define MACE_LADRF_LEN 8
164 /* 8 bytes in Logical Address Filter */
165
166 /* Loop Control Defines */
167 #define MACE_MAX_IR_ITERATIONS 10
168 #define MACE_MAX_RX_ITERATIONS 12
169 /*
170 TBD: Dean brought this up, and I assumed the hardware would
171 handle it:
172
173 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
174 non-zero when the isr exits. We may not get another interrupt
175 to process the remaining packets for some time.
176 */
177
178 /*
179 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
180 which manages the interface between the MACE and the PCMCIA bus. It
181 also includes buffer management for the 32K x 8 SRAM to control up to
182 four transmit and 12 receive frames at a time.
183 */
184 #define AM2150_MAX_TX_FRAMES 4
185 #define AM2150_MAX_RX_FRAMES 12
186
187 /* Am2150 Ethernet Card I/O Mapping */
188 #define AM2150_RCV 0x00
189 #define AM2150_XMT 0x04
190 #define AM2150_XMT_SKIP 0x09
191 #define AM2150_RCV_NEXT 0x0A
192 #define AM2150_RCV_FRAME_COUNT 0x0B
193 #define AM2150_MACE_BANK 0x0C
194 #define AM2150_MACE_BASE 0x10
195
196 /* MACE Registers */
197 #define MACE_RCVFIFO 0
198 #define MACE_XMTFIFO 1
199 #define MACE_XMTFC 2
200 #define MACE_XMTFS 3
201 #define MACE_XMTRC 4
202 #define MACE_RCVFC 5
203 #define MACE_RCVFS 6
204 #define MACE_FIFOFC 7
205 #define MACE_IR 8
206 #define MACE_IMR 9
207 #define MACE_PR 10
208 #define MACE_BIUCC 11
209 #define MACE_FIFOCC 12
210 #define MACE_MACCC 13
211 #define MACE_PLSCC 14
212 #define MACE_PHYCC 15
213 #define MACE_CHIPIDL 16
214 #define MACE_CHIPIDH 17
215 #define MACE_IAC 18
216 /* Reserved */
217 #define MACE_LADRF 20
218 #define MACE_PADR 21
219 /* Reserved */
220 /* Reserved */
221 #define MACE_MPC 24
222 /* Reserved */
223 #define MACE_RNTPC 26
224 #define MACE_RCVCC 27
225 /* Reserved */
226 #define MACE_UTR 29
227 #define MACE_RTR1 30
228 #define MACE_RTR2 31
229
230 /* MACE Bit Masks */
231 #define MACE_XMTRC_EXDEF 0x80
232 #define MACE_XMTRC_XMTRC 0x0F
233
234 #define MACE_XMTFS_XMTSV 0x80
235 #define MACE_XMTFS_UFLO 0x40
236 #define MACE_XMTFS_LCOL 0x20
237 #define MACE_XMTFS_MORE 0x10
238 #define MACE_XMTFS_ONE 0x08
239 #define MACE_XMTFS_DEFER 0x04
240 #define MACE_XMTFS_LCAR 0x02
241 #define MACE_XMTFS_RTRY 0x01
242
243 #define MACE_RCVFS_RCVSTS 0xF000
244 #define MACE_RCVFS_OFLO 0x8000
245 #define MACE_RCVFS_CLSN 0x4000
246 #define MACE_RCVFS_FRAM 0x2000
247 #define MACE_RCVFS_FCS 0x1000
248
249 #define MACE_FIFOFC_RCVFC 0xF0
250 #define MACE_FIFOFC_XMTFC 0x0F
251
252 #define MACE_IR_JAB 0x80
253 #define MACE_IR_BABL 0x40
254 #define MACE_IR_CERR 0x20
255 #define MACE_IR_RCVCCO 0x10
256 #define MACE_IR_RNTPCO 0x08
257 #define MACE_IR_MPCO 0x04
258 #define MACE_IR_RCVINT 0x02
259 #define MACE_IR_XMTINT 0x01
260
261 #define MACE_MACCC_PROM 0x80
262 #define MACE_MACCC_DXMT2PD 0x40
263 #define MACE_MACCC_EMBA 0x20
264 #define MACE_MACCC_RESERVED 0x10
265 #define MACE_MACCC_DRCVPA 0x08
266 #define MACE_MACCC_DRCVBC 0x04
267 #define MACE_MACCC_ENXMT 0x02
268 #define MACE_MACCC_ENRCV 0x01
269
270 #define MACE_PHYCC_LNKFL 0x80
271 #define MACE_PHYCC_DLNKTST 0x40
272 #define MACE_PHYCC_REVPOL 0x20
273 #define MACE_PHYCC_DAPC 0x10
274 #define MACE_PHYCC_LRT 0x08
275 #define MACE_PHYCC_ASEL 0x04
276 #define MACE_PHYCC_RWAKE 0x02
277 #define MACE_PHYCC_AWAKE 0x01
278
279 #define MACE_IAC_ADDRCHG 0x80
280 #define MACE_IAC_PHYADDR 0x04
281 #define MACE_IAC_LOGADDR 0x02
282
283 #define MACE_UTR_RTRE 0x80
284 #define MACE_UTR_RTRD 0x40
285 #define MACE_UTR_RPA 0x20
286 #define MACE_UTR_FCOLL 0x10
287 #define MACE_UTR_RCVFCSE 0x08
288 #define MACE_UTR_LOOP_INCL_MENDEC 0x06
289 #define MACE_UTR_LOOP_NO_MENDEC 0x04
290 #define MACE_UTR_LOOP_EXTERNAL 0x02
291 #define MACE_UTR_LOOP_NONE 0x00
292 #define MACE_UTR_RESERVED 0x01
293
294 /* Switch MACE register bank (only 0 and 1 are valid) */
295 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
296
297 #define MACE_IMR_DEFAULT \
298 (0xFF - \
299 ( \
300 MACE_IR_CERR | \
301 MACE_IR_RCVCCO | \
302 MACE_IR_RNTPCO | \
303 MACE_IR_MPCO | \
304 MACE_IR_RCVINT | \
305 MACE_IR_XMTINT \
306 ) \
307 )
308 #undef MACE_IMR_DEFAULT
309 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
310
311 #define TX_TIMEOUT ((400*HZ)/1000)
312
313 /* ----------------------------------------------------------------------------
314 Type Definitions
315 ---------------------------------------------------------------------------- */
316
317 typedef struct _mace_statistics {
318 /* MACE_XMTFS */
319 int xmtsv;
320 int uflo;
321 int lcol;
322 int more;
323 int one;
324 int defer;
325 int lcar;
326 int rtry;
327
328 /* MACE_XMTRC */
329 int exdef;
330 int xmtrc;
331
332 /* RFS1--Receive Status (RCVSTS) */
333 int oflo;
334 int clsn;
335 int fram;
336 int fcs;
337
338 /* RFS2--Runt Packet Count (RNTPC) */
339 int rfs_rntpc;
340
341 /* RFS3--Receive Collision Count (RCVCC) */
342 int rfs_rcvcc;
343
344 /* MACE_IR */
345 int jab;
346 int babl;
347 int cerr;
348 int rcvcco;
349 int rntpco;
350 int mpco;
351
352 /* MACE_MPC */
353 int mpc;
354
355 /* MACE_RNTPC */
356 int rntpc;
357
358 /* MACE_RCVCC */
359 int rcvcc;
360 } mace_statistics;
361
362 typedef struct _mace_private {
363 struct pcmcia_device *p_dev;
364 struct net_device_stats linux_stats; /* Linux statistics counters */
365 mace_statistics mace_stats; /* MACE chip statistics counters */
366
367 /* restore_multicast_list() state variables */
368 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
369 int multicast_num_addrs;
370
371 char tx_free_frames; /* Number of free transmit frame buffers */
372 char tx_irq_disabled; /* MACE TX interrupt disabled */
373
374 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
375 } mace_private;
376
377 /* ----------------------------------------------------------------------------
378 Private Global Variables
379 ---------------------------------------------------------------------------- */
380
381 static const char *if_names[]={
382 "Auto", "10baseT", "BNC",
383 };
384
385 /* ----------------------------------------------------------------------------
386 Parameters
387 These are the parameters that can be set during loading with
388 'insmod'.
389 ---------------------------------------------------------------------------- */
390
391 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
392 MODULE_LICENSE("GPL");
393
394 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
395
396 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
397 INT_MODULE_PARM(if_port, 0);
398
399
400 /* ----------------------------------------------------------------------------
401 Function Prototypes
402 ---------------------------------------------------------------------------- */
403
404 static int nmclan_config(struct pcmcia_device *link);
405 static void nmclan_release(struct pcmcia_device *link);
406
407 static void nmclan_reset(struct net_device *dev);
408 static int mace_config(struct net_device *dev, struct ifmap *map);
409 static int mace_open(struct net_device *dev);
410 static int mace_close(struct net_device *dev);
411 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
412 struct net_device *dev);
413 static void mace_tx_timeout(struct net_device *dev);
414 static irqreturn_t mace_interrupt(int irq, void *dev_id);
415 static struct net_device_stats *mace_get_stats(struct net_device *dev);
416 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
417 static void restore_multicast_list(struct net_device *dev);
418 static void set_multicast_list(struct net_device *dev);
419 static const struct ethtool_ops netdev_ethtool_ops;
420
421
422 static void nmclan_detach(struct pcmcia_device *p_dev);
423
424 static const struct net_device_ops mace_netdev_ops = {
425 .ndo_open = mace_open,
426 .ndo_stop = mace_close,
427 .ndo_start_xmit = mace_start_xmit,
428 .ndo_tx_timeout = mace_tx_timeout,
429 .ndo_set_config = mace_config,
430 .ndo_get_stats = mace_get_stats,
431 .ndo_set_multicast_list = set_multicast_list,
432 .ndo_change_mtu = eth_change_mtu,
433 .ndo_set_mac_address = eth_mac_addr,
434 .ndo_validate_addr = eth_validate_addr,
435 };
436
437 /* ----------------------------------------------------------------------------
438 nmclan_attach
439 Creates an "instance" of the driver, allocating local data
440 structures for one device. The device is registered with Card
441 Services.
442 ---------------------------------------------------------------------------- */
443
444 static int nmclan_probe(struct pcmcia_device *link)
445 {
446 mace_private *lp;
447 struct net_device *dev;
448
449 dev_dbg(&link->dev, "nmclan_attach()\n");
450
451 /* Create new ethernet device */
452 dev = alloc_etherdev(sizeof(mace_private));
453 if (!dev)
454 return -ENOMEM;
455 lp = netdev_priv(dev);
456 lp->p_dev = link;
457 link->priv = dev;
458
459 spin_lock_init(&lp->bank_lock);
460 link->resource[0]->end = 32;
461 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
462 link->config_flags |= CONF_ENABLE_IRQ;
463 link->config_index = 1;
464 link->config_regs = PRESENT_OPTION;
465
466 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
467
468 dev->netdev_ops = &mace_netdev_ops;
469 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
470 dev->watchdog_timeo = TX_TIMEOUT;
471
472 return nmclan_config(link);
473 } /* nmclan_attach */
474
475 /* ----------------------------------------------------------------------------
476 nmclan_detach
477 This deletes a driver "instance". The device is de-registered
478 with Card Services. If it has been released, all local data
479 structures are freed. Otherwise, the structures will be freed
480 when the device is released.
481 ---------------------------------------------------------------------------- */
482
483 static void nmclan_detach(struct pcmcia_device *link)
484 {
485 struct net_device *dev = link->priv;
486
487 dev_dbg(&link->dev, "nmclan_detach\n");
488
489 unregister_netdev(dev);
490
491 nmclan_release(link);
492
493 free_netdev(dev);
494 } /* nmclan_detach */
495
496 /* ----------------------------------------------------------------------------
497 mace_read
498 Reads a MACE register. This is bank independent; however, the
499 caller must ensure that this call is not interruptable. We are
500 assuming that during normal operation, the MACE is always in
501 bank 0.
502 ---------------------------------------------------------------------------- */
503 static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
504 {
505 int data = 0xFF;
506 unsigned long flags;
507
508 switch (reg >> 4) {
509 case 0: /* register 0-15 */
510 data = inb(ioaddr + AM2150_MACE_BASE + reg);
511 break;
512 case 1: /* register 16-31 */
513 spin_lock_irqsave(&lp->bank_lock, flags);
514 MACEBANK(1);
515 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
516 MACEBANK(0);
517 spin_unlock_irqrestore(&lp->bank_lock, flags);
518 break;
519 }
520 return (data & 0xFF);
521 } /* mace_read */
522
523 /* ----------------------------------------------------------------------------
524 mace_write
525 Writes to a MACE register. This is bank independent; however,
526 the caller must ensure that this call is not interruptable. We
527 are assuming that during normal operation, the MACE is always in
528 bank 0.
529 ---------------------------------------------------------------------------- */
530 static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
531 int data)
532 {
533 unsigned long flags;
534
535 switch (reg >> 4) {
536 case 0: /* register 0-15 */
537 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
538 break;
539 case 1: /* register 16-31 */
540 spin_lock_irqsave(&lp->bank_lock, flags);
541 MACEBANK(1);
542 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
543 MACEBANK(0);
544 spin_unlock_irqrestore(&lp->bank_lock, flags);
545 break;
546 }
547 } /* mace_write */
548
549 /* ----------------------------------------------------------------------------
550 mace_init
551 Resets the MACE chip.
552 ---------------------------------------------------------------------------- */
553 static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
554 {
555 int i;
556 int ct = 0;
557
558 /* MACE Software reset */
559 mace_write(lp, ioaddr, MACE_BIUCC, 1);
560 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
561 /* Wait for reset bit to be cleared automatically after <= 200ns */;
562 if(++ct > 500)
563 {
564 printk(KERN_ERR "mace: reset failed, card removed ?\n");
565 return -1;
566 }
567 udelay(1);
568 }
569 mace_write(lp, ioaddr, MACE_BIUCC, 0);
570
571 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
572 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
573
574 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
575 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
576
577 /*
578 * Bit 2-1 PORTSEL[1-0] Port Select.
579 * 00 AUI/10Base-2
580 * 01 10Base-T
581 * 10 DAI Port (reserved in Am2150)
582 * 11 GPSI
583 * For this card, only the first two are valid.
584 * So, PLSCC should be set to
585 * 0x00 for 10Base-2
586 * 0x02 for 10Base-T
587 * Or just set ASEL in PHYCC below!
588 */
589 switch (if_port) {
590 case 1:
591 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
592 break;
593 case 2:
594 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
595 break;
596 default:
597 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
598 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
599 and the MACE device will automatically select the operating media
600 interface port. */
601 break;
602 }
603
604 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
605 /* Poll ADDRCHG bit */
606 ct = 0;
607 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
608 {
609 if(++ ct > 500)
610 {
611 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
612 return -1;
613 }
614 }
615 /* Set PADR register */
616 for (i = 0; i < ETHER_ADDR_LEN; i++)
617 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
618
619 /* MAC Configuration Control Register should be written last */
620 /* Let set_multicast_list set this. */
621 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
622 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
623 return 0;
624 } /* mace_init */
625
626 /* ----------------------------------------------------------------------------
627 nmclan_config
628 This routine is scheduled to run after a CARD_INSERTION event
629 is received, to configure the PCMCIA socket, and to make the
630 ethernet device available to the system.
631 ---------------------------------------------------------------------------- */
632
633 static int nmclan_config(struct pcmcia_device *link)
634 {
635 struct net_device *dev = link->priv;
636 mace_private *lp = netdev_priv(dev);
637 u8 *buf;
638 size_t len;
639 int i, ret;
640 unsigned int ioaddr;
641
642 dev_dbg(&link->dev, "nmclan_config\n");
643
644 link->io_lines = 5;
645 ret = pcmcia_request_io(link);
646 if (ret)
647 goto failed;
648 ret = pcmcia_request_exclusive_irq(link, mace_interrupt);
649 if (ret)
650 goto failed;
651 ret = pcmcia_enable_device(link);
652 if (ret)
653 goto failed;
654
655 dev->irq = link->irq;
656 dev->base_addr = link->resource[0]->start;
657
658 ioaddr = dev->base_addr;
659
660 /* Read the ethernet address from the CIS. */
661 len = pcmcia_get_tuple(link, 0x80, &buf);
662 if (!buf || len < ETHER_ADDR_LEN) {
663 kfree(buf);
664 goto failed;
665 }
666 memcpy(dev->dev_addr, buf, ETHER_ADDR_LEN);
667 kfree(buf);
668
669 /* Verify configuration by reading the MACE ID. */
670 {
671 char sig[2];
672
673 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
674 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
675 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
676 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
677 sig[0], sig[1]);
678 } else {
679 printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
680 " be 0x40 0x?9\n", sig[0], sig[1]);
681 return -ENODEV;
682 }
683 }
684
685 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
686 goto failed;
687
688 /* The if_port symbol can be set when the module is loaded */
689 if (if_port <= 2)
690 dev->if_port = if_port;
691 else
692 printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
693
694 SET_NETDEV_DEV(dev, &link->dev);
695
696 i = register_netdev(dev);
697 if (i != 0) {
698 printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
699 goto failed;
700 }
701
702 printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port,"
703 " hw_addr %pM\n",
704 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port],
705 dev->dev_addr);
706 return 0;
707
708 failed:
709 nmclan_release(link);
710 return -ENODEV;
711 } /* nmclan_config */
712
713 /* ----------------------------------------------------------------------------
714 nmclan_release
715 After a card is removed, nmclan_release() will unregister the
716 net device, and release the PCMCIA configuration. If the device
717 is still open, this will be postponed until it is closed.
718 ---------------------------------------------------------------------------- */
719 static void nmclan_release(struct pcmcia_device *link)
720 {
721 dev_dbg(&link->dev, "nmclan_release\n");
722 pcmcia_disable_device(link);
723 }
724
725 static int nmclan_suspend(struct pcmcia_device *link)
726 {
727 struct net_device *dev = link->priv;
728
729 if (link->open)
730 netif_device_detach(dev);
731
732 return 0;
733 }
734
735 static int nmclan_resume(struct pcmcia_device *link)
736 {
737 struct net_device *dev = link->priv;
738
739 if (link->open) {
740 nmclan_reset(dev);
741 netif_device_attach(dev);
742 }
743
744 return 0;
745 }
746
747
748 /* ----------------------------------------------------------------------------
749 nmclan_reset
750 Reset and restore all of the Xilinx and MACE registers.
751 ---------------------------------------------------------------------------- */
752 static void nmclan_reset(struct net_device *dev)
753 {
754 mace_private *lp = netdev_priv(dev);
755
756 #if RESET_XILINX
757 struct pcmcia_device *link = &lp->link;
758 u8 OrigCorValue;
759
760 /* Save original COR value */
761 pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue);
762
763 /* Reset Xilinx */
764 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n",
765 OrigCorValue);
766 pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET);
767 /* Need to wait for 20 ms for PCMCIA to finish reset. */
768
769 /* Restore original COR configuration index */
770 pcmcia_write_config_byte(link, CISREG_COR,
771 (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK)));
772 /* Xilinx is now completely reset along with the MACE chip. */
773 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
774
775 #endif /* #if RESET_XILINX */
776
777 /* Xilinx is now completely reset along with the MACE chip. */
778 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
779
780 /* Reinitialize the MACE chip for operation. */
781 mace_init(lp, dev->base_addr, dev->dev_addr);
782 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
783
784 /* Restore the multicast list and enable TX and RX. */
785 restore_multicast_list(dev);
786 } /* nmclan_reset */
787
788 /* ----------------------------------------------------------------------------
789 mace_config
790 [Someone tell me what this is supposed to do? Is if_port a defined
791 standard? If so, there should be defines to indicate 1=10Base-T,
792 2=10Base-2, etc. including limited automatic detection.]
793 ---------------------------------------------------------------------------- */
794 static int mace_config(struct net_device *dev, struct ifmap *map)
795 {
796 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
797 if (map->port <= 2) {
798 dev->if_port = map->port;
799 printk(KERN_INFO "%s: switched to %s port\n", dev->name,
800 if_names[dev->if_port]);
801 } else
802 return -EINVAL;
803 }
804 return 0;
805 } /* mace_config */
806
807 /* ----------------------------------------------------------------------------
808 mace_open
809 Open device driver.
810 ---------------------------------------------------------------------------- */
811 static int mace_open(struct net_device *dev)
812 {
813 unsigned int ioaddr = dev->base_addr;
814 mace_private *lp = netdev_priv(dev);
815 struct pcmcia_device *link = lp->p_dev;
816
817 if (!pcmcia_dev_present(link))
818 return -ENODEV;
819
820 link->open++;
821
822 MACEBANK(0);
823
824 netif_start_queue(dev);
825 nmclan_reset(dev);
826
827 return 0; /* Always succeed */
828 } /* mace_open */
829
830 /* ----------------------------------------------------------------------------
831 mace_close
832 Closes device driver.
833 ---------------------------------------------------------------------------- */
834 static int mace_close(struct net_device *dev)
835 {
836 unsigned int ioaddr = dev->base_addr;
837 mace_private *lp = netdev_priv(dev);
838 struct pcmcia_device *link = lp->p_dev;
839
840 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
841
842 /* Mask off all interrupts from the MACE chip. */
843 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
844
845 link->open--;
846 netif_stop_queue(dev);
847
848 return 0;
849 } /* mace_close */
850
851 static void netdev_get_drvinfo(struct net_device *dev,
852 struct ethtool_drvinfo *info)
853 {
854 strcpy(info->driver, DRV_NAME);
855 strcpy(info->version, DRV_VERSION);
856 sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
857 }
858
859 static const struct ethtool_ops netdev_ethtool_ops = {
860 .get_drvinfo = netdev_get_drvinfo,
861 };
862
863 /* ----------------------------------------------------------------------------
864 mace_start_xmit
865 This routine begins the packet transmit function. When completed,
866 it will generate a transmit interrupt.
867
868 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
869 returns 0, the "packet is now solely the responsibility of the
870 driver." If _start_xmit returns non-zero, the "transmission
871 failed, put skb back into a list."
872 ---------------------------------------------------------------------------- */
873
874 static void mace_tx_timeout(struct net_device *dev)
875 {
876 mace_private *lp = netdev_priv(dev);
877 struct pcmcia_device *link = lp->p_dev;
878
879 printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
880 #if RESET_ON_TIMEOUT
881 printk("resetting card\n");
882 pcmcia_reset_card(link->socket);
883 #else /* #if RESET_ON_TIMEOUT */
884 printk("NOT resetting card\n");
885 #endif /* #if RESET_ON_TIMEOUT */
886 dev->trans_start = jiffies; /* prevent tx timeout */
887 netif_wake_queue(dev);
888 }
889
890 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
891 struct net_device *dev)
892 {
893 mace_private *lp = netdev_priv(dev);
894 unsigned int ioaddr = dev->base_addr;
895
896 netif_stop_queue(dev);
897
898 pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
899 dev->name, (long)skb->len);
900
901 #if (!TX_INTERRUPTABLE)
902 /* Disable MACE TX interrupts. */
903 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
904 ioaddr + AM2150_MACE_BASE + MACE_IMR);
905 lp->tx_irq_disabled=1;
906 #endif /* #if (!TX_INTERRUPTABLE) */
907
908 {
909 /* This block must not be interrupted by another transmit request!
910 mace_tx_timeout will take care of timer-based retransmissions from
911 the upper layers. The interrupt handler is guaranteed never to
912 service a transmit interrupt while we are in here.
913 */
914
915 lp->linux_stats.tx_bytes += skb->len;
916 lp->tx_free_frames--;
917
918 /* WARNING: Write the _exact_ number of bytes written in the header! */
919 /* Put out the word header [must be an outw()] . . . */
920 outw(skb->len, ioaddr + AM2150_XMT);
921 /* . . . and the packet [may be any combination of outw() and outb()] */
922 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
923 if (skb->len & 1) {
924 /* Odd byte transfer */
925 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
926 }
927
928 #if MULTI_TX
929 if (lp->tx_free_frames > 0)
930 netif_start_queue(dev);
931 #endif /* #if MULTI_TX */
932 }
933
934 #if (!TX_INTERRUPTABLE)
935 /* Re-enable MACE TX interrupts. */
936 lp->tx_irq_disabled=0;
937 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
938 #endif /* #if (!TX_INTERRUPTABLE) */
939
940 dev_kfree_skb(skb);
941
942 return NETDEV_TX_OK;
943 } /* mace_start_xmit */
944
945 /* ----------------------------------------------------------------------------
946 mace_interrupt
947 The interrupt handler.
948 ---------------------------------------------------------------------------- */
949 static irqreturn_t mace_interrupt(int irq, void *dev_id)
950 {
951 struct net_device *dev = (struct net_device *) dev_id;
952 mace_private *lp = netdev_priv(dev);
953 unsigned int ioaddr;
954 int status;
955 int IntrCnt = MACE_MAX_IR_ITERATIONS;
956
957 if (dev == NULL) {
958 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
959 irq);
960 return IRQ_NONE;
961 }
962
963 ioaddr = dev->base_addr;
964
965 if (lp->tx_irq_disabled) {
966 printk(
967 (lp->tx_irq_disabled?
968 KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
969 "[isr=%02X, imr=%02X]\n":
970 KERN_NOTICE "%s: Re-entering the interrupt handler "
971 "[isr=%02X, imr=%02X]\n"),
972 dev->name,
973 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
974 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
975 );
976 /* WARNING: MACE_IR has been read! */
977 return IRQ_NONE;
978 }
979
980 if (!netif_device_present(dev)) {
981 pr_debug("%s: interrupt from dead card\n", dev->name);
982 return IRQ_NONE;
983 }
984
985 do {
986 /* WARNING: MACE_IR is a READ/CLEAR port! */
987 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
988
989 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
990
991 if (status & MACE_IR_RCVINT) {
992 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
993 }
994
995 if (status & MACE_IR_XMTINT) {
996 unsigned char fifofc;
997 unsigned char xmtrc;
998 unsigned char xmtfs;
999
1000 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1001 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1002 lp->linux_stats.tx_errors++;
1003 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1004 }
1005
1006 /* Transmit Retry Count (XMTRC, reg 4) */
1007 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1008 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1009 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1010
1011 if (
1012 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1013 MACE_XMTFS_XMTSV /* Transmit Status Valid */
1014 ) {
1015 lp->mace_stats.xmtsv++;
1016
1017 if (xmtfs & ~MACE_XMTFS_XMTSV) {
1018 if (xmtfs & MACE_XMTFS_UFLO) {
1019 /* Underflow. Indicates that the Transmit FIFO emptied before
1020 the end of frame was reached. */
1021 lp->mace_stats.uflo++;
1022 }
1023 if (xmtfs & MACE_XMTFS_LCOL) {
1024 /* Late Collision */
1025 lp->mace_stats.lcol++;
1026 }
1027 if (xmtfs & MACE_XMTFS_MORE) {
1028 /* MORE than one retry was needed */
1029 lp->mace_stats.more++;
1030 }
1031 if (xmtfs & MACE_XMTFS_ONE) {
1032 /* Exactly ONE retry occurred */
1033 lp->mace_stats.one++;
1034 }
1035 if (xmtfs & MACE_XMTFS_DEFER) {
1036 /* Transmission was defered */
1037 lp->mace_stats.defer++;
1038 }
1039 if (xmtfs & MACE_XMTFS_LCAR) {
1040 /* Loss of carrier */
1041 lp->mace_stats.lcar++;
1042 }
1043 if (xmtfs & MACE_XMTFS_RTRY) {
1044 /* Retry error: transmit aborted after 16 attempts */
1045 lp->mace_stats.rtry++;
1046 }
1047 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1048
1049 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1050
1051 lp->linux_stats.tx_packets++;
1052 lp->tx_free_frames++;
1053 netif_wake_queue(dev);
1054 } /* if (status & MACE_IR_XMTINT) */
1055
1056 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1057 if (status & MACE_IR_JAB) {
1058 /* Jabber Error. Excessive transmit duration (20-150ms). */
1059 lp->mace_stats.jab++;
1060 }
1061 if (status & MACE_IR_BABL) {
1062 /* Babble Error. >1518 bytes transmitted. */
1063 lp->mace_stats.babl++;
1064 }
1065 if (status & MACE_IR_CERR) {
1066 /* Collision Error. CERR indicates the absence of the
1067 Signal Quality Error Test message after a packet
1068 transmission. */
1069 lp->mace_stats.cerr++;
1070 }
1071 if (status & MACE_IR_RCVCCO) {
1072 /* Receive Collision Count Overflow; */
1073 lp->mace_stats.rcvcco++;
1074 }
1075 if (status & MACE_IR_RNTPCO) {
1076 /* Runt Packet Count Overflow */
1077 lp->mace_stats.rntpco++;
1078 }
1079 if (status & MACE_IR_MPCO) {
1080 /* Missed Packet Count Overflow */
1081 lp->mace_stats.mpco++;
1082 }
1083 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1084
1085 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1086
1087 return IRQ_HANDLED;
1088 } /* mace_interrupt */
1089
1090 /* ----------------------------------------------------------------------------
1091 mace_rx
1092 Receives packets.
1093 ---------------------------------------------------------------------------- */
1094 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1095 {
1096 mace_private *lp = netdev_priv(dev);
1097 unsigned int ioaddr = dev->base_addr;
1098 unsigned char rx_framecnt;
1099 unsigned short rx_status;
1100
1101 while (
1102 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1103 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1104 (RxCnt--)
1105 ) {
1106 rx_status = inw(ioaddr + AM2150_RCV);
1107
1108 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1109 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1110
1111 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1112 lp->linux_stats.rx_errors++;
1113 if (rx_status & MACE_RCVFS_OFLO) {
1114 lp->mace_stats.oflo++;
1115 }
1116 if (rx_status & MACE_RCVFS_CLSN) {
1117 lp->mace_stats.clsn++;
1118 }
1119 if (rx_status & MACE_RCVFS_FRAM) {
1120 lp->mace_stats.fram++;
1121 }
1122 if (rx_status & MACE_RCVFS_FCS) {
1123 lp->mace_stats.fcs++;
1124 }
1125 } else {
1126 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1127 /* Auto Strip is off, always subtract 4 */
1128 struct sk_buff *skb;
1129
1130 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1131 /* runt packet count */
1132 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1133 /* rcv collision count */
1134
1135 pr_debug(" receiving packet size 0x%X rx_status"
1136 " 0x%X.\n", pkt_len, rx_status);
1137
1138 skb = dev_alloc_skb(pkt_len+2);
1139
1140 if (skb != NULL) {
1141 skb_reserve(skb, 2);
1142 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1143 if (pkt_len & 1)
1144 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1145 skb->protocol = eth_type_trans(skb, dev);
1146
1147 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1148
1149 lp->linux_stats.rx_packets++;
1150 lp->linux_stats.rx_bytes += pkt_len;
1151 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1152 continue;
1153 } else {
1154 pr_debug("%s: couldn't allocate a sk_buff of size"
1155 " %d.\n", dev->name, pkt_len);
1156 lp->linux_stats.rx_dropped++;
1157 }
1158 }
1159 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1160 } /* while */
1161
1162 return 0;
1163 } /* mace_rx */
1164
1165 /* ----------------------------------------------------------------------------
1166 pr_linux_stats
1167 ---------------------------------------------------------------------------- */
1168 static void pr_linux_stats(struct net_device_stats *pstats)
1169 {
1170 pr_debug("pr_linux_stats\n");
1171 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n",
1172 (long)pstats->rx_packets, (long)pstats->tx_packets);
1173 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n",
1174 (long)pstats->rx_errors, (long)pstats->tx_errors);
1175 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n",
1176 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1177 pr_debug(" multicast=%-7ld collisions=%ld\n",
1178 (long)pstats->multicast, (long)pstats->collisions);
1179
1180 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n",
1181 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1182 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1183 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1184 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1185 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1186
1187 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1188 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1189 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1190 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1191 pr_debug(" tx_window_errors=%ld\n",
1192 (long)pstats->tx_window_errors);
1193 } /* pr_linux_stats */
1194
1195 /* ----------------------------------------------------------------------------
1196 pr_mace_stats
1197 ---------------------------------------------------------------------------- */
1198 static void pr_mace_stats(mace_statistics *pstats)
1199 {
1200 pr_debug("pr_mace_stats\n");
1201
1202 pr_debug(" xmtsv=%-7d uflo=%d\n",
1203 pstats->xmtsv, pstats->uflo);
1204 pr_debug(" lcol=%-7d more=%d\n",
1205 pstats->lcol, pstats->more);
1206 pr_debug(" one=%-7d defer=%d\n",
1207 pstats->one, pstats->defer);
1208 pr_debug(" lcar=%-7d rtry=%d\n",
1209 pstats->lcar, pstats->rtry);
1210
1211 /* MACE_XMTRC */
1212 pr_debug(" exdef=%-7d xmtrc=%d\n",
1213 pstats->exdef, pstats->xmtrc);
1214
1215 /* RFS1--Receive Status (RCVSTS) */
1216 pr_debug(" oflo=%-7d clsn=%d\n",
1217 pstats->oflo, pstats->clsn);
1218 pr_debug(" fram=%-7d fcs=%d\n",
1219 pstats->fram, pstats->fcs);
1220
1221 /* RFS2--Runt Packet Count (RNTPC) */
1222 /* RFS3--Receive Collision Count (RCVCC) */
1223 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1224 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1225
1226 /* MACE_IR */
1227 pr_debug(" jab=%-7d babl=%d\n",
1228 pstats->jab, pstats->babl);
1229 pr_debug(" cerr=%-7d rcvcco=%d\n",
1230 pstats->cerr, pstats->rcvcco);
1231 pr_debug(" rntpco=%-7d mpco=%d\n",
1232 pstats->rntpco, pstats->mpco);
1233
1234 /* MACE_MPC */
1235 pr_debug(" mpc=%d\n", pstats->mpc);
1236
1237 /* MACE_RNTPC */
1238 pr_debug(" rntpc=%d\n", pstats->rntpc);
1239
1240 /* MACE_RCVCC */
1241 pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1242
1243 } /* pr_mace_stats */
1244
1245 /* ----------------------------------------------------------------------------
1246 update_stats
1247 Update statistics. We change to register window 1, so this
1248 should be run single-threaded if the device is active. This is
1249 expected to be a rare operation, and it's simpler for the rest
1250 of the driver to assume that window 0 is always valid rather
1251 than use a special window-state variable.
1252
1253 oflo & uflo should _never_ occur since it would mean the Xilinx
1254 was not able to transfer data between the MACE FIFO and the
1255 card's SRAM fast enough. If this happens, something is
1256 seriously wrong with the hardware.
1257 ---------------------------------------------------------------------------- */
1258 static void update_stats(unsigned int ioaddr, struct net_device *dev)
1259 {
1260 mace_private *lp = netdev_priv(dev);
1261
1262 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1263 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1264 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1265 /* At this point, mace_stats is fully updated for this call.
1266 We may now update the linux_stats. */
1267
1268 /* The MACE has no equivalent for linux_stats field which are commented
1269 out. */
1270
1271 /* lp->linux_stats.multicast; */
1272 lp->linux_stats.collisions =
1273 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1274 /* Collision: The MACE may retry sending a packet 15 times
1275 before giving up. The retry count is in XMTRC.
1276 Does each retry constitute a collision?
1277 If so, why doesn't the RCVCC record these collisions? */
1278
1279 /* detailed rx_errors: */
1280 lp->linux_stats.rx_length_errors =
1281 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1282 /* lp->linux_stats.rx_over_errors */
1283 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1284 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1285 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1286 lp->linux_stats.rx_missed_errors =
1287 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1288
1289 /* detailed tx_errors */
1290 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1291 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1292 /* LCAR usually results from bad cabling. */
1293 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1294 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1295 /* lp->linux_stats.tx_window_errors; */
1296 } /* update_stats */
1297
1298 /* ----------------------------------------------------------------------------
1299 mace_get_stats
1300 Gathers ethernet statistics from the MACE chip.
1301 ---------------------------------------------------------------------------- */
1302 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1303 {
1304 mace_private *lp = netdev_priv(dev);
1305
1306 update_stats(dev->base_addr, dev);
1307
1308 pr_debug("%s: updating the statistics.\n", dev->name);
1309 pr_linux_stats(&lp->linux_stats);
1310 pr_mace_stats(&lp->mace_stats);
1311
1312 return &lp->linux_stats;
1313 } /* net_device_stats */
1314
1315 /* ----------------------------------------------------------------------------
1316 updateCRC
1317 Modified from Am79C90 data sheet.
1318 ---------------------------------------------------------------------------- */
1319
1320 #ifdef BROKEN_MULTICAST
1321
1322 static void updateCRC(int *CRC, int bit)
1323 {
1324 int poly[]={
1325 1,1,1,0, 1,1,0,1,
1326 1,0,1,1, 1,0,0,0,
1327 1,0,0,0, 0,0,1,1,
1328 0,0,1,0, 0,0,0,0
1329 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1330 CRC generator polynomial. */
1331
1332 int j;
1333
1334 /* shift CRC and control bit (CRC[32]) */
1335 for (j = 32; j > 0; j--)
1336 CRC[j] = CRC[j-1];
1337 CRC[0] = 0;
1338
1339 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1340 if (bit ^ CRC[32])
1341 for (j = 0; j < 32; j++)
1342 CRC[j] ^= poly[j];
1343 } /* updateCRC */
1344
1345 /* ----------------------------------------------------------------------------
1346 BuildLAF
1347 Build logical address filter.
1348 Modified from Am79C90 data sheet.
1349
1350 Input
1351 ladrf: logical address filter (contents initialized to 0)
1352 adr: ethernet address
1353 ---------------------------------------------------------------------------- */
1354 static void BuildLAF(int *ladrf, int *adr)
1355 {
1356 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1357
1358 int i, byte; /* temporary array indices */
1359 int hashcode; /* the output object */
1360
1361 CRC[32]=0;
1362
1363 for (byte = 0; byte < 6; byte++)
1364 for (i = 0; i < 8; i++)
1365 updateCRC(CRC, (adr[byte] >> i) & 1);
1366
1367 hashcode = 0;
1368 for (i = 0; i < 6; i++)
1369 hashcode = (hashcode << 1) + CRC[i];
1370
1371 byte = hashcode >> 3;
1372 ladrf[byte] |= (1 << (hashcode & 7));
1373
1374 #ifdef PCMCIA_DEBUG
1375 if (0)
1376 printk(KERN_DEBUG " adr =%pM\n", adr);
1377 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1378 for (i = 0; i < 8; i++)
1379 printk(KERN_CONT " %02X", ladrf[i]);
1380 printk(KERN_CONT "\n");
1381 #endif
1382 } /* BuildLAF */
1383
1384 /* ----------------------------------------------------------------------------
1385 restore_multicast_list
1386 Restores the multicast filter for MACE chip to the last
1387 set_multicast_list() call.
1388
1389 Input
1390 multicast_num_addrs
1391 multicast_ladrf[]
1392 ---------------------------------------------------------------------------- */
1393 static void restore_multicast_list(struct net_device *dev)
1394 {
1395 mace_private *lp = netdev_priv(dev);
1396 int num_addrs = lp->multicast_num_addrs;
1397 int *ladrf = lp->multicast_ladrf;
1398 unsigned int ioaddr = dev->base_addr;
1399 int i;
1400
1401 pr_debug("%s: restoring Rx mode to %d addresses.\n",
1402 dev->name, num_addrs);
1403
1404 if (num_addrs > 0) {
1405
1406 pr_debug("Attempt to restore multicast list detected.\n");
1407
1408 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1409 /* Poll ADDRCHG bit */
1410 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1411 ;
1412 /* Set LADRF register */
1413 for (i = 0; i < MACE_LADRF_LEN; i++)
1414 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1415
1416 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1417 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1418
1419 } else if (num_addrs < 0) {
1420
1421 /* Promiscuous mode: receive all packets */
1422 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1423 mace_write(lp, ioaddr, MACE_MACCC,
1424 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1425 );
1426
1427 } else {
1428
1429 /* Normal mode */
1430 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1431 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1432
1433 }
1434 } /* restore_multicast_list */
1435
1436 /* ----------------------------------------------------------------------------
1437 set_multicast_list
1438 Set or clear the multicast filter for this adaptor.
1439
1440 Input
1441 num_addrs == -1 Promiscuous mode, receive all packets
1442 num_addrs == 0 Normal mode, clear multicast list
1443 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1444 best-effort filtering.
1445 Output
1446 multicast_num_addrs
1447 multicast_ladrf[]
1448 ---------------------------------------------------------------------------- */
1449
1450 static void set_multicast_list(struct net_device *dev)
1451 {
1452 mace_private *lp = netdev_priv(dev);
1453 int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1454 struct netdev_hw_addr *ha;
1455
1456 #ifdef PCMCIA_DEBUG
1457 {
1458 static int old;
1459 if (netdev_mc_count(dev) != old) {
1460 old = netdev_mc_count(dev);
1461 pr_debug("%s: setting Rx mode to %d addresses.\n",
1462 dev->name, old);
1463 }
1464 }
1465 #endif
1466
1467 /* Set multicast_num_addrs. */
1468 lp->multicast_num_addrs = netdev_mc_count(dev);
1469
1470 /* Set multicast_ladrf. */
1471 if (num_addrs > 0) {
1472 /* Calculate multicast logical address filter */
1473 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1474 netdev_for_each_mc_addr(ha, dev) {
1475 memcpy(adr, ha->addr, ETHER_ADDR_LEN);
1476 BuildLAF(lp->multicast_ladrf, adr);
1477 }
1478 }
1479
1480 restore_multicast_list(dev);
1481
1482 } /* set_multicast_list */
1483
1484 #endif /* BROKEN_MULTICAST */
1485
1486 static void restore_multicast_list(struct net_device *dev)
1487 {
1488 unsigned int ioaddr = dev->base_addr;
1489 mace_private *lp = netdev_priv(dev);
1490
1491 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1492 lp->multicast_num_addrs);
1493
1494 if (dev->flags & IFF_PROMISC) {
1495 /* Promiscuous mode: receive all packets */
1496 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1497 mace_write(lp, ioaddr, MACE_MACCC,
1498 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1499 );
1500 } else {
1501 /* Normal mode */
1502 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1503 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1504 }
1505 } /* restore_multicast_list */
1506
1507 static void set_multicast_list(struct net_device *dev)
1508 {
1509 mace_private *lp = netdev_priv(dev);
1510
1511 #ifdef PCMCIA_DEBUG
1512 {
1513 static int old;
1514 if (netdev_mc_count(dev) != old) {
1515 old = netdev_mc_count(dev);
1516 pr_debug("%s: setting Rx mode to %d addresses.\n",
1517 dev->name, old);
1518 }
1519 }
1520 #endif
1521
1522 lp->multicast_num_addrs = netdev_mc_count(dev);
1523 restore_multicast_list(dev);
1524
1525 } /* set_multicast_list */
1526
1527 static struct pcmcia_device_id nmclan_ids[] = {
1528 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1529 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1530 PCMCIA_DEVICE_NULL,
1531 };
1532 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1533
1534 static struct pcmcia_driver nmclan_cs_driver = {
1535 .owner = THIS_MODULE,
1536 .drv = {
1537 .name = "nmclan_cs",
1538 },
1539 .probe = nmclan_probe,
1540 .remove = nmclan_detach,
1541 .id_table = nmclan_ids,
1542 .suspend = nmclan_suspend,
1543 .resume = nmclan_resume,
1544 };
1545
1546 static int __init init_nmclan_cs(void)
1547 {
1548 return pcmcia_register_driver(&nmclan_cs_driver);
1549 }
1550
1551 static void __exit exit_nmclan_cs(void)
1552 {
1553 pcmcia_unregister_driver(&nmclan_cs_driver);
1554 }
1555
1556 module_init(init_nmclan_cs);
1557 module_exit(exit_nmclan_cs);
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