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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland...
[mirror_ubuntu-artful-kernel.git] / drivers / net / pcnet32.c
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24 #define DRV_NAME "pcnet32"
25 #ifdef CONFIG_PCNET32_NAPI
26 #define DRV_VERSION "1.34-NAPI"
27 #else
28 #define DRV_VERSION "1.34"
29 #endif
30 #define DRV_RELDATE "14.Aug.2007"
31 #define PFX DRV_NAME ": "
32
33 static const char *const version =
34 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/string.h>
39 #include <linux/errno.h>
40 #include <linux/ioport.h>
41 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/delay.h>
45 #include <linux/init.h>
46 #include <linux/ethtool.h>
47 #include <linux/mii.h>
48 #include <linux/crc32.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/skbuff.h>
52 #include <linux/spinlock.h>
53 #include <linux/moduleparam.h>
54 #include <linux/bitops.h>
55
56 #include <asm/dma.h>
57 #include <asm/io.h>
58 #include <asm/uaccess.h>
59 #include <asm/irq.h>
60
61 /*
62 * PCI device identifiers for "new style" Linux PCI Device Drivers
63 */
64 static struct pci_device_id pcnet32_pci_tbl[] = {
65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
67
68 /*
69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
70 * the incorrect vendor id.
71 */
72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
74
75 { } /* terminate list */
76 };
77
78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
79
80 static int cards_found;
81
82 /*
83 * VLB I/O addresses
84 */
85 static unsigned int pcnet32_portlist[] __initdata =
86 { 0x300, 0x320, 0x340, 0x360, 0 };
87
88 static int pcnet32_debug = 0;
89 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
90 static int pcnet32vlb; /* check for VLB cards ? */
91
92 static struct net_device *pcnet32_dev;
93
94 static int max_interrupt_work = 2;
95 static int rx_copybreak = 200;
96
97 #define PCNET32_PORT_AUI 0x00
98 #define PCNET32_PORT_10BT 0x01
99 #define PCNET32_PORT_GPSI 0x02
100 #define PCNET32_PORT_MII 0x03
101
102 #define PCNET32_PORT_PORTSEL 0x03
103 #define PCNET32_PORT_ASEL 0x04
104 #define PCNET32_PORT_100 0x40
105 #define PCNET32_PORT_FD 0x80
106
107 #define PCNET32_DMA_MASK 0xffffffff
108
109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
110 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
111
112 /*
113 * table to translate option values from tulip
114 * to internal options
115 */
116 static const unsigned char options_mapping[] = {
117 PCNET32_PORT_ASEL, /* 0 Auto-select */
118 PCNET32_PORT_AUI, /* 1 BNC/AUI */
119 PCNET32_PORT_AUI, /* 2 AUI/BNC */
120 PCNET32_PORT_ASEL, /* 3 not supported */
121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
122 PCNET32_PORT_ASEL, /* 5 not supported */
123 PCNET32_PORT_ASEL, /* 6 not supported */
124 PCNET32_PORT_ASEL, /* 7 not supported */
125 PCNET32_PORT_ASEL, /* 8 not supported */
126 PCNET32_PORT_MII, /* 9 MII 10baseT */
127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
128 PCNET32_PORT_MII, /* 11 MII (autosel) */
129 PCNET32_PORT_10BT, /* 12 10BaseT */
130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
131 /* 14 MII 100BaseTx-FD */
132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
133 PCNET32_PORT_ASEL /* 15 not supported */
134 };
135
136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
137 "Loopback test (offline)"
138 };
139
140 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
141
142 #define PCNET32_NUM_REGS 136
143
144 #define MAX_UNITS 8 /* More are supported, limit only on options */
145 static int options[MAX_UNITS];
146 static int full_duplex[MAX_UNITS];
147 static int homepna[MAX_UNITS];
148
149 /*
150 * Theory of Operation
151 *
152 * This driver uses the same software structure as the normal lance
153 * driver. So look for a verbose description in lance.c. The differences
154 * to the normal lance driver is the use of the 32bit mode of PCnet32
155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
156 * 16MB limitation and we don't need bounce buffers.
157 */
158
159 /*
160 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
163 */
164 #ifndef PCNET32_LOG_TX_BUFFERS
165 #define PCNET32_LOG_TX_BUFFERS 4
166 #define PCNET32_LOG_RX_BUFFERS 5
167 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
168 #define PCNET32_LOG_MAX_RX_BUFFERS 9
169 #endif
170
171 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
172 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
173
174 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
175 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
176
177 #define PKT_BUF_SZ 1544
178
179 /* Offsets from base I/O address. */
180 #define PCNET32_WIO_RDP 0x10
181 #define PCNET32_WIO_RAP 0x12
182 #define PCNET32_WIO_RESET 0x14
183 #define PCNET32_WIO_BDP 0x16
184
185 #define PCNET32_DWIO_RDP 0x10
186 #define PCNET32_DWIO_RAP 0x14
187 #define PCNET32_DWIO_RESET 0x18
188 #define PCNET32_DWIO_BDP 0x1C
189
190 #define PCNET32_TOTAL_SIZE 0x20
191
192 #define CSR0 0
193 #define CSR0_INIT 0x1
194 #define CSR0_START 0x2
195 #define CSR0_STOP 0x4
196 #define CSR0_TXPOLL 0x8
197 #define CSR0_INTEN 0x40
198 #define CSR0_IDON 0x0100
199 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
200 #define PCNET32_INIT_LOW 1
201 #define PCNET32_INIT_HIGH 2
202 #define CSR3 3
203 #define CSR4 4
204 #define CSR5 5
205 #define CSR5_SUSPEND 0x0001
206 #define CSR15 15
207 #define PCNET32_MC_FILTER 8
208
209 #define PCNET32_79C970A 0x2621
210
211 /* The PCNET32 Rx and Tx ring descriptors. */
212 struct pcnet32_rx_head {
213 __le32 base;
214 __le16 buf_length; /* two`s complement of length */
215 __le16 status;
216 __le32 msg_length;
217 __le32 reserved;
218 };
219
220 struct pcnet32_tx_head {
221 __le32 base;
222 __le16 length; /* two`s complement of length */
223 __le16 status;
224 __le32 misc;
225 __le32 reserved;
226 };
227
228 /* The PCNET32 32-Bit initialization block, described in databook. */
229 struct pcnet32_init_block {
230 __le16 mode;
231 __le16 tlen_rlen;
232 u8 phys_addr[6];
233 __le16 reserved;
234 __le32 filter[2];
235 /* Receive and transmit ring base, along with extra bits. */
236 __le32 rx_ring;
237 __le32 tx_ring;
238 };
239
240 /* PCnet32 access functions */
241 struct pcnet32_access {
242 u16 (*read_csr) (unsigned long, int);
243 void (*write_csr) (unsigned long, int, u16);
244 u16 (*read_bcr) (unsigned long, int);
245 void (*write_bcr) (unsigned long, int, u16);
246 u16 (*read_rap) (unsigned long);
247 void (*write_rap) (unsigned long, u16);
248 void (*reset) (unsigned long);
249 };
250
251 /*
252 * The first field of pcnet32_private is read by the ethernet device
253 * so the structure should be allocated using pci_alloc_consistent().
254 */
255 struct pcnet32_private {
256 struct pcnet32_init_block *init_block;
257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
258 struct pcnet32_rx_head *rx_ring;
259 struct pcnet32_tx_head *tx_ring;
260 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
261 returned by pci_alloc_consistent */
262 struct pci_dev *pci_dev;
263 const char *name;
264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
265 struct sk_buff **tx_skbuff;
266 struct sk_buff **rx_skbuff;
267 dma_addr_t *tx_dma_addr;
268 dma_addr_t *rx_dma_addr;
269 struct pcnet32_access a;
270 spinlock_t lock; /* Guard lock */
271 unsigned int cur_rx, cur_tx; /* The next free ring entry */
272 unsigned int rx_ring_size; /* current rx ring size */
273 unsigned int tx_ring_size; /* current tx ring size */
274 unsigned int rx_mod_mask; /* rx ring modular mask */
275 unsigned int tx_mod_mask; /* tx ring modular mask */
276 unsigned short rx_len_bits;
277 unsigned short tx_len_bits;
278 dma_addr_t rx_ring_dma_addr;
279 dma_addr_t tx_ring_dma_addr;
280 unsigned int dirty_rx, /* ring entries to be freed. */
281 dirty_tx;
282
283 struct net_device *dev;
284 struct napi_struct napi;
285 struct net_device_stats stats;
286 char tx_full;
287 char phycount; /* number of phys found */
288 int options;
289 unsigned int shared_irq:1, /* shared irq possible */
290 dxsuflo:1, /* disable transmit stop on uflo */
291 mii:1; /* mii port available */
292 struct net_device *next;
293 struct mii_if_info mii_if;
294 struct timer_list watchdog_timer;
295 struct timer_list blink_timer;
296 u32 msg_enable; /* debug message level */
297
298 /* each bit indicates an available PHY */
299 u32 phymask;
300 unsigned short chip_version; /* which variant this is */
301 };
302
303 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
304 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
305 static int pcnet32_open(struct net_device *);
306 static int pcnet32_init_ring(struct net_device *);
307 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
308 static void pcnet32_tx_timeout(struct net_device *dev);
309 static irqreturn_t pcnet32_interrupt(int, void *);
310 static int pcnet32_close(struct net_device *);
311 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
312 static void pcnet32_load_multicast(struct net_device *dev);
313 static void pcnet32_set_multicast_list(struct net_device *);
314 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
315 static void pcnet32_watchdog(struct net_device *);
316 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
317 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
318 int val);
319 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
320 static void pcnet32_ethtool_test(struct net_device *dev,
321 struct ethtool_test *eth_test, u64 * data);
322 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
323 static int pcnet32_phys_id(struct net_device *dev, u32 data);
324 static void pcnet32_led_blink_callback(struct net_device *dev);
325 static int pcnet32_get_regs_len(struct net_device *dev);
326 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
327 void *ptr);
328 static void pcnet32_purge_tx_ring(struct net_device *dev);
329 static int pcnet32_alloc_ring(struct net_device *dev, char *name);
330 static void pcnet32_free_ring(struct net_device *dev);
331 static void pcnet32_check_media(struct net_device *dev, int verbose);
332
333 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
334 {
335 outw(index, addr + PCNET32_WIO_RAP);
336 return inw(addr + PCNET32_WIO_RDP);
337 }
338
339 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
340 {
341 outw(index, addr + PCNET32_WIO_RAP);
342 outw(val, addr + PCNET32_WIO_RDP);
343 }
344
345 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
346 {
347 outw(index, addr + PCNET32_WIO_RAP);
348 return inw(addr + PCNET32_WIO_BDP);
349 }
350
351 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
352 {
353 outw(index, addr + PCNET32_WIO_RAP);
354 outw(val, addr + PCNET32_WIO_BDP);
355 }
356
357 static u16 pcnet32_wio_read_rap(unsigned long addr)
358 {
359 return inw(addr + PCNET32_WIO_RAP);
360 }
361
362 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
363 {
364 outw(val, addr + PCNET32_WIO_RAP);
365 }
366
367 static void pcnet32_wio_reset(unsigned long addr)
368 {
369 inw(addr + PCNET32_WIO_RESET);
370 }
371
372 static int pcnet32_wio_check(unsigned long addr)
373 {
374 outw(88, addr + PCNET32_WIO_RAP);
375 return (inw(addr + PCNET32_WIO_RAP) == 88);
376 }
377
378 static struct pcnet32_access pcnet32_wio = {
379 .read_csr = pcnet32_wio_read_csr,
380 .write_csr = pcnet32_wio_write_csr,
381 .read_bcr = pcnet32_wio_read_bcr,
382 .write_bcr = pcnet32_wio_write_bcr,
383 .read_rap = pcnet32_wio_read_rap,
384 .write_rap = pcnet32_wio_write_rap,
385 .reset = pcnet32_wio_reset
386 };
387
388 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
389 {
390 outl(index, addr + PCNET32_DWIO_RAP);
391 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
392 }
393
394 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
395 {
396 outl(index, addr + PCNET32_DWIO_RAP);
397 outl(val, addr + PCNET32_DWIO_RDP);
398 }
399
400 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
401 {
402 outl(index, addr + PCNET32_DWIO_RAP);
403 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
404 }
405
406 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
407 {
408 outl(index, addr + PCNET32_DWIO_RAP);
409 outl(val, addr + PCNET32_DWIO_BDP);
410 }
411
412 static u16 pcnet32_dwio_read_rap(unsigned long addr)
413 {
414 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
415 }
416
417 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
418 {
419 outl(val, addr + PCNET32_DWIO_RAP);
420 }
421
422 static void pcnet32_dwio_reset(unsigned long addr)
423 {
424 inl(addr + PCNET32_DWIO_RESET);
425 }
426
427 static int pcnet32_dwio_check(unsigned long addr)
428 {
429 outl(88, addr + PCNET32_DWIO_RAP);
430 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
431 }
432
433 static struct pcnet32_access pcnet32_dwio = {
434 .read_csr = pcnet32_dwio_read_csr,
435 .write_csr = pcnet32_dwio_write_csr,
436 .read_bcr = pcnet32_dwio_read_bcr,
437 .write_bcr = pcnet32_dwio_write_bcr,
438 .read_rap = pcnet32_dwio_read_rap,
439 .write_rap = pcnet32_dwio_write_rap,
440 .reset = pcnet32_dwio_reset
441 };
442
443 static void pcnet32_netif_stop(struct net_device *dev)
444 {
445 struct pcnet32_private *lp = netdev_priv(dev);
446 dev->trans_start = jiffies;
447 #ifdef CONFIG_PCNET32_NAPI
448 napi_disable(&lp->napi);
449 #endif
450 netif_tx_disable(dev);
451 }
452
453 static void pcnet32_netif_start(struct net_device *dev)
454 {
455 struct pcnet32_private *lp = netdev_priv(dev);
456 netif_wake_queue(dev);
457 #ifdef CONFIG_PCNET32_NAPI
458 napi_enable(&lp->napi);
459 #endif
460 }
461
462 /*
463 * Allocate space for the new sized tx ring.
464 * Free old resources
465 * Save new resources.
466 * Any failure keeps old resources.
467 * Must be called with lp->lock held.
468 */
469 static void pcnet32_realloc_tx_ring(struct net_device *dev,
470 struct pcnet32_private *lp,
471 unsigned int size)
472 {
473 dma_addr_t new_ring_dma_addr;
474 dma_addr_t *new_dma_addr_list;
475 struct pcnet32_tx_head *new_tx_ring;
476 struct sk_buff **new_skb_list;
477
478 pcnet32_purge_tx_ring(dev);
479
480 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
481 sizeof(struct pcnet32_tx_head) *
482 (1 << size),
483 &new_ring_dma_addr);
484 if (new_tx_ring == NULL) {
485 if (netif_msg_drv(lp))
486 printk("\n" KERN_ERR
487 "%s: Consistent memory allocation failed.\n",
488 dev->name);
489 return;
490 }
491 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
492
493 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
494 GFP_ATOMIC);
495 if (!new_dma_addr_list) {
496 if (netif_msg_drv(lp))
497 printk("\n" KERN_ERR
498 "%s: Memory allocation failed.\n", dev->name);
499 goto free_new_tx_ring;
500 }
501
502 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
503 GFP_ATOMIC);
504 if (!new_skb_list) {
505 if (netif_msg_drv(lp))
506 printk("\n" KERN_ERR
507 "%s: Memory allocation failed.\n", dev->name);
508 goto free_new_lists;
509 }
510
511 kfree(lp->tx_skbuff);
512 kfree(lp->tx_dma_addr);
513 pci_free_consistent(lp->pci_dev,
514 sizeof(struct pcnet32_tx_head) *
515 lp->tx_ring_size, lp->tx_ring,
516 lp->tx_ring_dma_addr);
517
518 lp->tx_ring_size = (1 << size);
519 lp->tx_mod_mask = lp->tx_ring_size - 1;
520 lp->tx_len_bits = (size << 12);
521 lp->tx_ring = new_tx_ring;
522 lp->tx_ring_dma_addr = new_ring_dma_addr;
523 lp->tx_dma_addr = new_dma_addr_list;
524 lp->tx_skbuff = new_skb_list;
525 return;
526
527 free_new_lists:
528 kfree(new_dma_addr_list);
529 free_new_tx_ring:
530 pci_free_consistent(lp->pci_dev,
531 sizeof(struct pcnet32_tx_head) *
532 (1 << size),
533 new_tx_ring,
534 new_ring_dma_addr);
535 return;
536 }
537
538 /*
539 * Allocate space for the new sized rx ring.
540 * Re-use old receive buffers.
541 * alloc extra buffers
542 * free unneeded buffers
543 * free unneeded buffers
544 * Save new resources.
545 * Any failure keeps old resources.
546 * Must be called with lp->lock held.
547 */
548 static void pcnet32_realloc_rx_ring(struct net_device *dev,
549 struct pcnet32_private *lp,
550 unsigned int size)
551 {
552 dma_addr_t new_ring_dma_addr;
553 dma_addr_t *new_dma_addr_list;
554 struct pcnet32_rx_head *new_rx_ring;
555 struct sk_buff **new_skb_list;
556 int new, overlap;
557
558 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
559 sizeof(struct pcnet32_rx_head) *
560 (1 << size),
561 &new_ring_dma_addr);
562 if (new_rx_ring == NULL) {
563 if (netif_msg_drv(lp))
564 printk("\n" KERN_ERR
565 "%s: Consistent memory allocation failed.\n",
566 dev->name);
567 return;
568 }
569 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
570
571 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
572 GFP_ATOMIC);
573 if (!new_dma_addr_list) {
574 if (netif_msg_drv(lp))
575 printk("\n" KERN_ERR
576 "%s: Memory allocation failed.\n", dev->name);
577 goto free_new_rx_ring;
578 }
579
580 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
581 GFP_ATOMIC);
582 if (!new_skb_list) {
583 if (netif_msg_drv(lp))
584 printk("\n" KERN_ERR
585 "%s: Memory allocation failed.\n", dev->name);
586 goto free_new_lists;
587 }
588
589 /* first copy the current receive buffers */
590 overlap = min(size, lp->rx_ring_size);
591 for (new = 0; new < overlap; new++) {
592 new_rx_ring[new] = lp->rx_ring[new];
593 new_dma_addr_list[new] = lp->rx_dma_addr[new];
594 new_skb_list[new] = lp->rx_skbuff[new];
595 }
596 /* now allocate any new buffers needed */
597 for (; new < size; new++ ) {
598 struct sk_buff *rx_skbuff;
599 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
600 if (!(rx_skbuff = new_skb_list[new])) {
601 /* keep the original lists and buffers */
602 if (netif_msg_drv(lp))
603 printk(KERN_ERR
604 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
605 dev->name);
606 goto free_all_new;
607 }
608 skb_reserve(rx_skbuff, 2);
609
610 new_dma_addr_list[new] =
611 pci_map_single(lp->pci_dev, rx_skbuff->data,
612 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
613 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
614 new_rx_ring[new].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
615 new_rx_ring[new].status = cpu_to_le16(0x8000);
616 }
617 /* and free any unneeded buffers */
618 for (; new < lp->rx_ring_size; new++) {
619 if (lp->rx_skbuff[new]) {
620 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
621 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
622 dev_kfree_skb(lp->rx_skbuff[new]);
623 }
624 }
625
626 kfree(lp->rx_skbuff);
627 kfree(lp->rx_dma_addr);
628 pci_free_consistent(lp->pci_dev,
629 sizeof(struct pcnet32_rx_head) *
630 lp->rx_ring_size, lp->rx_ring,
631 lp->rx_ring_dma_addr);
632
633 lp->rx_ring_size = (1 << size);
634 lp->rx_mod_mask = lp->rx_ring_size - 1;
635 lp->rx_len_bits = (size << 4);
636 lp->rx_ring = new_rx_ring;
637 lp->rx_ring_dma_addr = new_ring_dma_addr;
638 lp->rx_dma_addr = new_dma_addr_list;
639 lp->rx_skbuff = new_skb_list;
640 return;
641
642 free_all_new:
643 for (; --new >= lp->rx_ring_size; ) {
644 if (new_skb_list[new]) {
645 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
646 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
647 dev_kfree_skb(new_skb_list[new]);
648 }
649 }
650 kfree(new_skb_list);
651 free_new_lists:
652 kfree(new_dma_addr_list);
653 free_new_rx_ring:
654 pci_free_consistent(lp->pci_dev,
655 sizeof(struct pcnet32_rx_head) *
656 (1 << size),
657 new_rx_ring,
658 new_ring_dma_addr);
659 return;
660 }
661
662 static void pcnet32_purge_rx_ring(struct net_device *dev)
663 {
664 struct pcnet32_private *lp = netdev_priv(dev);
665 int i;
666
667 /* free all allocated skbuffs */
668 for (i = 0; i < lp->rx_ring_size; i++) {
669 lp->rx_ring[i].status = 0; /* CPU owns buffer */
670 wmb(); /* Make sure adapter sees owner change */
671 if (lp->rx_skbuff[i]) {
672 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
673 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
674 dev_kfree_skb_any(lp->rx_skbuff[i]);
675 }
676 lp->rx_skbuff[i] = NULL;
677 lp->rx_dma_addr[i] = 0;
678 }
679 }
680
681 #ifdef CONFIG_NET_POLL_CONTROLLER
682 static void pcnet32_poll_controller(struct net_device *dev)
683 {
684 disable_irq(dev->irq);
685 pcnet32_interrupt(0, dev);
686 enable_irq(dev->irq);
687 }
688 #endif
689
690 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
691 {
692 struct pcnet32_private *lp = netdev_priv(dev);
693 unsigned long flags;
694 int r = -EOPNOTSUPP;
695
696 if (lp->mii) {
697 spin_lock_irqsave(&lp->lock, flags);
698 mii_ethtool_gset(&lp->mii_if, cmd);
699 spin_unlock_irqrestore(&lp->lock, flags);
700 r = 0;
701 }
702 return r;
703 }
704
705 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
706 {
707 struct pcnet32_private *lp = netdev_priv(dev);
708 unsigned long flags;
709 int r = -EOPNOTSUPP;
710
711 if (lp->mii) {
712 spin_lock_irqsave(&lp->lock, flags);
713 r = mii_ethtool_sset(&lp->mii_if, cmd);
714 spin_unlock_irqrestore(&lp->lock, flags);
715 }
716 return r;
717 }
718
719 static void pcnet32_get_drvinfo(struct net_device *dev,
720 struct ethtool_drvinfo *info)
721 {
722 struct pcnet32_private *lp = netdev_priv(dev);
723
724 strcpy(info->driver, DRV_NAME);
725 strcpy(info->version, DRV_VERSION);
726 if (lp->pci_dev)
727 strcpy(info->bus_info, pci_name(lp->pci_dev));
728 else
729 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
730 }
731
732 static u32 pcnet32_get_link(struct net_device *dev)
733 {
734 struct pcnet32_private *lp = netdev_priv(dev);
735 unsigned long flags;
736 int r;
737
738 spin_lock_irqsave(&lp->lock, flags);
739 if (lp->mii) {
740 r = mii_link_ok(&lp->mii_if);
741 } else if (lp->chip_version >= PCNET32_79C970A) {
742 ulong ioaddr = dev->base_addr; /* card base I/O address */
743 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
744 } else { /* can not detect link on really old chips */
745 r = 1;
746 }
747 spin_unlock_irqrestore(&lp->lock, flags);
748
749 return r;
750 }
751
752 static u32 pcnet32_get_msglevel(struct net_device *dev)
753 {
754 struct pcnet32_private *lp = netdev_priv(dev);
755 return lp->msg_enable;
756 }
757
758 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
759 {
760 struct pcnet32_private *lp = netdev_priv(dev);
761 lp->msg_enable = value;
762 }
763
764 static int pcnet32_nway_reset(struct net_device *dev)
765 {
766 struct pcnet32_private *lp = netdev_priv(dev);
767 unsigned long flags;
768 int r = -EOPNOTSUPP;
769
770 if (lp->mii) {
771 spin_lock_irqsave(&lp->lock, flags);
772 r = mii_nway_restart(&lp->mii_if);
773 spin_unlock_irqrestore(&lp->lock, flags);
774 }
775 return r;
776 }
777
778 static void pcnet32_get_ringparam(struct net_device *dev,
779 struct ethtool_ringparam *ering)
780 {
781 struct pcnet32_private *lp = netdev_priv(dev);
782
783 ering->tx_max_pending = TX_MAX_RING_SIZE;
784 ering->tx_pending = lp->tx_ring_size;
785 ering->rx_max_pending = RX_MAX_RING_SIZE;
786 ering->rx_pending = lp->rx_ring_size;
787 }
788
789 static int pcnet32_set_ringparam(struct net_device *dev,
790 struct ethtool_ringparam *ering)
791 {
792 struct pcnet32_private *lp = netdev_priv(dev);
793 unsigned long flags;
794 unsigned int size;
795 ulong ioaddr = dev->base_addr;
796 int i;
797
798 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
799 return -EINVAL;
800
801 if (netif_running(dev))
802 pcnet32_netif_stop(dev);
803
804 spin_lock_irqsave(&lp->lock, flags);
805 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
806
807 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
808
809 /* set the minimum ring size to 4, to allow the loopback test to work
810 * unchanged.
811 */
812 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
813 if (size <= (1 << i))
814 break;
815 }
816 if ((1 << i) != lp->tx_ring_size)
817 pcnet32_realloc_tx_ring(dev, lp, i);
818
819 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
820 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
821 if (size <= (1 << i))
822 break;
823 }
824 if ((1 << i) != lp->rx_ring_size)
825 pcnet32_realloc_rx_ring(dev, lp, i);
826
827 lp->napi.weight = lp->rx_ring_size / 2;
828
829 if (netif_running(dev)) {
830 pcnet32_netif_start(dev);
831 pcnet32_restart(dev, CSR0_NORMAL);
832 }
833
834 spin_unlock_irqrestore(&lp->lock, flags);
835
836 if (netif_msg_drv(lp))
837 printk(KERN_INFO
838 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
839 lp->rx_ring_size, lp->tx_ring_size);
840
841 return 0;
842 }
843
844 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
845 u8 * data)
846 {
847 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
848 }
849
850 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
851 {
852 switch (sset) {
853 case ETH_SS_TEST:
854 return PCNET32_TEST_LEN;
855 default:
856 return -EOPNOTSUPP;
857 }
858 }
859
860 static void pcnet32_ethtool_test(struct net_device *dev,
861 struct ethtool_test *test, u64 * data)
862 {
863 struct pcnet32_private *lp = netdev_priv(dev);
864 int rc;
865
866 if (test->flags == ETH_TEST_FL_OFFLINE) {
867 rc = pcnet32_loopback_test(dev, data);
868 if (rc) {
869 if (netif_msg_hw(lp))
870 printk(KERN_DEBUG "%s: Loopback test failed.\n",
871 dev->name);
872 test->flags |= ETH_TEST_FL_FAILED;
873 } else if (netif_msg_hw(lp))
874 printk(KERN_DEBUG "%s: Loopback test passed.\n",
875 dev->name);
876 } else if (netif_msg_hw(lp))
877 printk(KERN_DEBUG
878 "%s: No tests to run (specify 'Offline' on ethtool).",
879 dev->name);
880 } /* end pcnet32_ethtool_test */
881
882 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
883 {
884 struct pcnet32_private *lp = netdev_priv(dev);
885 struct pcnet32_access *a = &lp->a; /* access to registers */
886 ulong ioaddr = dev->base_addr; /* card base I/O address */
887 struct sk_buff *skb; /* sk buff */
888 int x, i; /* counters */
889 int numbuffs = 4; /* number of TX/RX buffers and descs */
890 u16 status = 0x8300; /* TX ring status */
891 __le16 teststatus; /* test of ring status */
892 int rc; /* return code */
893 int size; /* size of packets */
894 unsigned char *packet; /* source packet data */
895 static const int data_len = 60; /* length of source packets */
896 unsigned long flags;
897 unsigned long ticks;
898
899 rc = 1; /* default to fail */
900
901 if (netif_running(dev))
902 #ifdef CONFIG_PCNET32_NAPI
903 pcnet32_netif_stop(dev);
904 #else
905 pcnet32_close(dev);
906 #endif
907
908 spin_lock_irqsave(&lp->lock, flags);
909 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
910
911 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
912
913 /* Reset the PCNET32 */
914 lp->a.reset(ioaddr);
915 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
916
917 /* switch pcnet32 to 32bit mode */
918 lp->a.write_bcr(ioaddr, 20, 2);
919
920 /* purge & init rings but don't actually restart */
921 pcnet32_restart(dev, 0x0000);
922
923 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
924
925 /* Initialize Transmit buffers. */
926 size = data_len + 15;
927 for (x = 0; x < numbuffs; x++) {
928 if (!(skb = dev_alloc_skb(size))) {
929 if (netif_msg_hw(lp))
930 printk(KERN_DEBUG
931 "%s: Cannot allocate skb at line: %d!\n",
932 dev->name, __LINE__);
933 goto clean_up;
934 } else {
935 packet = skb->data;
936 skb_put(skb, size); /* create space for data */
937 lp->tx_skbuff[x] = skb;
938 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
939 lp->tx_ring[x].misc = 0;
940
941 /* put DA and SA into the skb */
942 for (i = 0; i < 6; i++)
943 *packet++ = dev->dev_addr[i];
944 for (i = 0; i < 6; i++)
945 *packet++ = dev->dev_addr[i];
946 /* type */
947 *packet++ = 0x08;
948 *packet++ = 0x06;
949 /* packet number */
950 *packet++ = x;
951 /* fill packet with data */
952 for (i = 0; i < data_len; i++)
953 *packet++ = i;
954
955 lp->tx_dma_addr[x] =
956 pci_map_single(lp->pci_dev, skb->data, skb->len,
957 PCI_DMA_TODEVICE);
958 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
959 wmb(); /* Make sure owner changes after all others are visible */
960 lp->tx_ring[x].status = cpu_to_le16(status);
961 }
962 }
963
964 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
965 a->write_bcr(ioaddr, 32, x | 0x0002);
966
967 /* set int loopback in CSR15 */
968 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
969 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
970
971 teststatus = cpu_to_le16(0x8000);
972 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
973
974 /* Check status of descriptors */
975 for (x = 0; x < numbuffs; x++) {
976 ticks = 0;
977 rmb();
978 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
979 spin_unlock_irqrestore(&lp->lock, flags);
980 msleep(1);
981 spin_lock_irqsave(&lp->lock, flags);
982 rmb();
983 ticks++;
984 }
985 if (ticks == 200) {
986 if (netif_msg_hw(lp))
987 printk("%s: Desc %d failed to reset!\n",
988 dev->name, x);
989 break;
990 }
991 }
992
993 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
994 wmb();
995 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
996 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
997
998 for (x = 0; x < numbuffs; x++) {
999 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
1000 skb = lp->rx_skbuff[x];
1001 for (i = 0; i < size; i++) {
1002 printk("%02x ", *(skb->data + i));
1003 }
1004 printk("\n");
1005 }
1006 }
1007
1008 x = 0;
1009 rc = 0;
1010 while (x < numbuffs && !rc) {
1011 skb = lp->rx_skbuff[x];
1012 packet = lp->tx_skbuff[x]->data;
1013 for (i = 0; i < size; i++) {
1014 if (*(skb->data + i) != packet[i]) {
1015 if (netif_msg_hw(lp))
1016 printk(KERN_DEBUG
1017 "%s: Error in compare! %2x - %02x %02x\n",
1018 dev->name, i, *(skb->data + i),
1019 packet[i]);
1020 rc = 1;
1021 break;
1022 }
1023 }
1024 x++;
1025 }
1026
1027 clean_up:
1028 *data1 = rc;
1029 pcnet32_purge_tx_ring(dev);
1030
1031 x = a->read_csr(ioaddr, CSR15);
1032 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1033
1034 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1035 a->write_bcr(ioaddr, 32, (x & ~0x0002));
1036
1037 #ifdef CONFIG_PCNET32_NAPI
1038 if (netif_running(dev)) {
1039 pcnet32_netif_start(dev);
1040 pcnet32_restart(dev, CSR0_NORMAL);
1041 } else {
1042 pcnet32_purge_rx_ring(dev);
1043 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1044 }
1045 spin_unlock_irqrestore(&lp->lock, flags);
1046 #else
1047 if (netif_running(dev)) {
1048 spin_unlock_irqrestore(&lp->lock, flags);
1049 pcnet32_open(dev);
1050 } else {
1051 pcnet32_purge_rx_ring(dev);
1052 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1053 spin_unlock_irqrestore(&lp->lock, flags);
1054 }
1055 #endif
1056
1057 return (rc);
1058 } /* end pcnet32_loopback_test */
1059
1060 static void pcnet32_led_blink_callback(struct net_device *dev)
1061 {
1062 struct pcnet32_private *lp = netdev_priv(dev);
1063 struct pcnet32_access *a = &lp->a;
1064 ulong ioaddr = dev->base_addr;
1065 unsigned long flags;
1066 int i;
1067
1068 spin_lock_irqsave(&lp->lock, flags);
1069 for (i = 4; i < 8; i++) {
1070 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1071 }
1072 spin_unlock_irqrestore(&lp->lock, flags);
1073
1074 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1075 }
1076
1077 static int pcnet32_phys_id(struct net_device *dev, u32 data)
1078 {
1079 struct pcnet32_private *lp = netdev_priv(dev);
1080 struct pcnet32_access *a = &lp->a;
1081 ulong ioaddr = dev->base_addr;
1082 unsigned long flags;
1083 int i, regs[4];
1084
1085 if (!lp->blink_timer.function) {
1086 init_timer(&lp->blink_timer);
1087 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1088 lp->blink_timer.data = (unsigned long)dev;
1089 }
1090
1091 /* Save the current value of the bcrs */
1092 spin_lock_irqsave(&lp->lock, flags);
1093 for (i = 4; i < 8; i++) {
1094 regs[i - 4] = a->read_bcr(ioaddr, i);
1095 }
1096 spin_unlock_irqrestore(&lp->lock, flags);
1097
1098 mod_timer(&lp->blink_timer, jiffies);
1099 set_current_state(TASK_INTERRUPTIBLE);
1100
1101 /* AV: the limit here makes no sense whatsoever */
1102 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1103 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1104
1105 msleep_interruptible(data * 1000);
1106 del_timer_sync(&lp->blink_timer);
1107
1108 /* Restore the original value of the bcrs */
1109 spin_lock_irqsave(&lp->lock, flags);
1110 for (i = 4; i < 8; i++) {
1111 a->write_bcr(ioaddr, i, regs[i - 4]);
1112 }
1113 spin_unlock_irqrestore(&lp->lock, flags);
1114
1115 return 0;
1116 }
1117
1118 /*
1119 * lp->lock must be held.
1120 */
1121 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1122 int can_sleep)
1123 {
1124 int csr5;
1125 struct pcnet32_private *lp = netdev_priv(dev);
1126 struct pcnet32_access *a = &lp->a;
1127 ulong ioaddr = dev->base_addr;
1128 int ticks;
1129
1130 /* really old chips have to be stopped. */
1131 if (lp->chip_version < PCNET32_79C970A)
1132 return 0;
1133
1134 /* set SUSPEND (SPND) - CSR5 bit 0 */
1135 csr5 = a->read_csr(ioaddr, CSR5);
1136 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1137
1138 /* poll waiting for bit to be set */
1139 ticks = 0;
1140 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1141 spin_unlock_irqrestore(&lp->lock, *flags);
1142 if (can_sleep)
1143 msleep(1);
1144 else
1145 mdelay(1);
1146 spin_lock_irqsave(&lp->lock, *flags);
1147 ticks++;
1148 if (ticks > 200) {
1149 if (netif_msg_hw(lp))
1150 printk(KERN_DEBUG
1151 "%s: Error getting into suspend!\n",
1152 dev->name);
1153 return 0;
1154 }
1155 }
1156 return 1;
1157 }
1158
1159 /*
1160 * process one receive descriptor entry
1161 */
1162
1163 static void pcnet32_rx_entry(struct net_device *dev,
1164 struct pcnet32_private *lp,
1165 struct pcnet32_rx_head *rxp,
1166 int entry)
1167 {
1168 int status = (short)le16_to_cpu(rxp->status) >> 8;
1169 int rx_in_place = 0;
1170 struct sk_buff *skb;
1171 short pkt_len;
1172
1173 if (status != 0x03) { /* There was an error. */
1174 /*
1175 * There is a tricky error noted by John Murphy,
1176 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1177 * buffers it's possible for a jabber packet to use two
1178 * buffers, with only the last correctly noting the error.
1179 */
1180 if (status & 0x01) /* Only count a general error at the */
1181 lp->stats.rx_errors++; /* end of a packet. */
1182 if (status & 0x20)
1183 lp->stats.rx_frame_errors++;
1184 if (status & 0x10)
1185 lp->stats.rx_over_errors++;
1186 if (status & 0x08)
1187 lp->stats.rx_crc_errors++;
1188 if (status & 0x04)
1189 lp->stats.rx_fifo_errors++;
1190 return;
1191 }
1192
1193 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1194
1195 /* Discard oversize frames. */
1196 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
1197 if (netif_msg_drv(lp))
1198 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1199 dev->name, pkt_len);
1200 lp->stats.rx_errors++;
1201 return;
1202 }
1203 if (pkt_len < 60) {
1204 if (netif_msg_rx_err(lp))
1205 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1206 lp->stats.rx_errors++;
1207 return;
1208 }
1209
1210 if (pkt_len > rx_copybreak) {
1211 struct sk_buff *newskb;
1212
1213 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
1214 skb_reserve(newskb, 2);
1215 skb = lp->rx_skbuff[entry];
1216 pci_unmap_single(lp->pci_dev,
1217 lp->rx_dma_addr[entry],
1218 PKT_BUF_SZ - 2,
1219 PCI_DMA_FROMDEVICE);
1220 skb_put(skb, pkt_len);
1221 lp->rx_skbuff[entry] = newskb;
1222 lp->rx_dma_addr[entry] =
1223 pci_map_single(lp->pci_dev,
1224 newskb->data,
1225 PKT_BUF_SZ - 2,
1226 PCI_DMA_FROMDEVICE);
1227 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
1228 rx_in_place = 1;
1229 } else
1230 skb = NULL;
1231 } else {
1232 skb = dev_alloc_skb(pkt_len + 2);
1233 }
1234
1235 if (skb == NULL) {
1236 if (netif_msg_drv(lp))
1237 printk(KERN_ERR
1238 "%s: Memory squeeze, dropping packet.\n",
1239 dev->name);
1240 lp->stats.rx_dropped++;
1241 return;
1242 }
1243 skb->dev = dev;
1244 if (!rx_in_place) {
1245 skb_reserve(skb, 2); /* 16 byte align */
1246 skb_put(skb, pkt_len); /* Make room */
1247 pci_dma_sync_single_for_cpu(lp->pci_dev,
1248 lp->rx_dma_addr[entry],
1249 pkt_len,
1250 PCI_DMA_FROMDEVICE);
1251 skb_copy_to_linear_data(skb,
1252 (unsigned char *)(lp->rx_skbuff[entry]->data),
1253 pkt_len);
1254 pci_dma_sync_single_for_device(lp->pci_dev,
1255 lp->rx_dma_addr[entry],
1256 pkt_len,
1257 PCI_DMA_FROMDEVICE);
1258 }
1259 lp->stats.rx_bytes += skb->len;
1260 skb->protocol = eth_type_trans(skb, dev);
1261 #ifdef CONFIG_PCNET32_NAPI
1262 netif_receive_skb(skb);
1263 #else
1264 netif_rx(skb);
1265 #endif
1266 dev->last_rx = jiffies;
1267 lp->stats.rx_packets++;
1268 return;
1269 }
1270
1271 static int pcnet32_rx(struct net_device *dev, int budget)
1272 {
1273 struct pcnet32_private *lp = netdev_priv(dev);
1274 int entry = lp->cur_rx & lp->rx_mod_mask;
1275 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1276 int npackets = 0;
1277
1278 /* If we own the next entry, it's a new packet. Send it up. */
1279 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1280 pcnet32_rx_entry(dev, lp, rxp, entry);
1281 npackets += 1;
1282 /*
1283 * The docs say that the buffer length isn't touched, but Andrew
1284 * Boyd of QNX reports that some revs of the 79C965 clear it.
1285 */
1286 rxp->buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
1287 wmb(); /* Make sure owner changes after others are visible */
1288 rxp->status = cpu_to_le16(0x8000);
1289 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1290 rxp = &lp->rx_ring[entry];
1291 }
1292
1293 return npackets;
1294 }
1295
1296 static int pcnet32_tx(struct net_device *dev)
1297 {
1298 struct pcnet32_private *lp = netdev_priv(dev);
1299 unsigned int dirty_tx = lp->dirty_tx;
1300 int delta;
1301 int must_restart = 0;
1302
1303 while (dirty_tx != lp->cur_tx) {
1304 int entry = dirty_tx & lp->tx_mod_mask;
1305 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1306
1307 if (status < 0)
1308 break; /* It still hasn't been Txed */
1309
1310 lp->tx_ring[entry].base = 0;
1311
1312 if (status & 0x4000) {
1313 /* There was a major error, log it. */
1314 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1315 lp->stats.tx_errors++;
1316 if (netif_msg_tx_err(lp))
1317 printk(KERN_ERR
1318 "%s: Tx error status=%04x err_status=%08x\n",
1319 dev->name, status,
1320 err_status);
1321 if (err_status & 0x04000000)
1322 lp->stats.tx_aborted_errors++;
1323 if (err_status & 0x08000000)
1324 lp->stats.tx_carrier_errors++;
1325 if (err_status & 0x10000000)
1326 lp->stats.tx_window_errors++;
1327 #ifndef DO_DXSUFLO
1328 if (err_status & 0x40000000) {
1329 lp->stats.tx_fifo_errors++;
1330 /* Ackk! On FIFO errors the Tx unit is turned off! */
1331 /* Remove this verbosity later! */
1332 if (netif_msg_tx_err(lp))
1333 printk(KERN_ERR
1334 "%s: Tx FIFO error!\n",
1335 dev->name);
1336 must_restart = 1;
1337 }
1338 #else
1339 if (err_status & 0x40000000) {
1340 lp->stats.tx_fifo_errors++;
1341 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1342 /* Ackk! On FIFO errors the Tx unit is turned off! */
1343 /* Remove this verbosity later! */
1344 if (netif_msg_tx_err(lp))
1345 printk(KERN_ERR
1346 "%s: Tx FIFO error!\n",
1347 dev->name);
1348 must_restart = 1;
1349 }
1350 }
1351 #endif
1352 } else {
1353 if (status & 0x1800)
1354 lp->stats.collisions++;
1355 lp->stats.tx_packets++;
1356 }
1357
1358 /* We must free the original skb */
1359 if (lp->tx_skbuff[entry]) {
1360 pci_unmap_single(lp->pci_dev,
1361 lp->tx_dma_addr[entry],
1362 lp->tx_skbuff[entry]->
1363 len, PCI_DMA_TODEVICE);
1364 dev_kfree_skb_any(lp->tx_skbuff[entry]);
1365 lp->tx_skbuff[entry] = NULL;
1366 lp->tx_dma_addr[entry] = 0;
1367 }
1368 dirty_tx++;
1369 }
1370
1371 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1372 if (delta > lp->tx_ring_size) {
1373 if (netif_msg_drv(lp))
1374 printk(KERN_ERR
1375 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1376 dev->name, dirty_tx, lp->cur_tx,
1377 lp->tx_full);
1378 dirty_tx += lp->tx_ring_size;
1379 delta -= lp->tx_ring_size;
1380 }
1381
1382 if (lp->tx_full &&
1383 netif_queue_stopped(dev) &&
1384 delta < lp->tx_ring_size - 2) {
1385 /* The ring is no longer full, clear tbusy. */
1386 lp->tx_full = 0;
1387 netif_wake_queue(dev);
1388 }
1389 lp->dirty_tx = dirty_tx;
1390
1391 return must_restart;
1392 }
1393
1394 #ifdef CONFIG_PCNET32_NAPI
1395 static int pcnet32_poll(struct napi_struct *napi, int budget)
1396 {
1397 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1398 struct net_device *dev = lp->dev;
1399 unsigned long ioaddr = dev->base_addr;
1400 unsigned long flags;
1401 int work_done;
1402 u16 val;
1403
1404 work_done = pcnet32_rx(dev, budget);
1405
1406 spin_lock_irqsave(&lp->lock, flags);
1407 if (pcnet32_tx(dev)) {
1408 /* reset the chip to clear the error condition, then restart */
1409 lp->a.reset(ioaddr);
1410 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1411 pcnet32_restart(dev, CSR0_START);
1412 netif_wake_queue(dev);
1413 }
1414 spin_unlock_irqrestore(&lp->lock, flags);
1415
1416 if (work_done < budget) {
1417 spin_lock_irqsave(&lp->lock, flags);
1418
1419 __netif_rx_complete(dev, napi);
1420
1421 /* clear interrupt masks */
1422 val = lp->a.read_csr(ioaddr, CSR3);
1423 val &= 0x00ff;
1424 lp->a.write_csr(ioaddr, CSR3, val);
1425
1426 /* Set interrupt enable. */
1427 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1428 mmiowb();
1429 spin_unlock_irqrestore(&lp->lock, flags);
1430 }
1431 return work_done;
1432 }
1433 #endif
1434
1435 #define PCNET32_REGS_PER_PHY 32
1436 #define PCNET32_MAX_PHYS 32
1437 static int pcnet32_get_regs_len(struct net_device *dev)
1438 {
1439 struct pcnet32_private *lp = netdev_priv(dev);
1440 int j = lp->phycount * PCNET32_REGS_PER_PHY;
1441
1442 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1443 }
1444
1445 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1446 void *ptr)
1447 {
1448 int i, csr0;
1449 u16 *buff = ptr;
1450 struct pcnet32_private *lp = netdev_priv(dev);
1451 struct pcnet32_access *a = &lp->a;
1452 ulong ioaddr = dev->base_addr;
1453 unsigned long flags;
1454
1455 spin_lock_irqsave(&lp->lock, flags);
1456
1457 csr0 = a->read_csr(ioaddr, CSR0);
1458 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1459 pcnet32_suspend(dev, &flags, 1);
1460
1461 /* read address PROM */
1462 for (i = 0; i < 16; i += 2)
1463 *buff++ = inw(ioaddr + i);
1464
1465 /* read control and status registers */
1466 for (i = 0; i < 90; i++) {
1467 *buff++ = a->read_csr(ioaddr, i);
1468 }
1469
1470 *buff++ = a->read_csr(ioaddr, 112);
1471 *buff++ = a->read_csr(ioaddr, 114);
1472
1473 /* read bus configuration registers */
1474 for (i = 0; i < 30; i++) {
1475 *buff++ = a->read_bcr(ioaddr, i);
1476 }
1477 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1478 for (i = 31; i < 36; i++) {
1479 *buff++ = a->read_bcr(ioaddr, i);
1480 }
1481
1482 /* read mii phy registers */
1483 if (lp->mii) {
1484 int j;
1485 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1486 if (lp->phymask & (1 << j)) {
1487 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1488 lp->a.write_bcr(ioaddr, 33,
1489 (j << 5) | i);
1490 *buff++ = lp->a.read_bcr(ioaddr, 34);
1491 }
1492 }
1493 }
1494 }
1495
1496 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1497 int csr5;
1498
1499 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1500 csr5 = a->read_csr(ioaddr, CSR5);
1501 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1502 }
1503
1504 spin_unlock_irqrestore(&lp->lock, flags);
1505 }
1506
1507 static const struct ethtool_ops pcnet32_ethtool_ops = {
1508 .get_settings = pcnet32_get_settings,
1509 .set_settings = pcnet32_set_settings,
1510 .get_drvinfo = pcnet32_get_drvinfo,
1511 .get_msglevel = pcnet32_get_msglevel,
1512 .set_msglevel = pcnet32_set_msglevel,
1513 .nway_reset = pcnet32_nway_reset,
1514 .get_link = pcnet32_get_link,
1515 .get_ringparam = pcnet32_get_ringparam,
1516 .set_ringparam = pcnet32_set_ringparam,
1517 .get_strings = pcnet32_get_strings,
1518 .self_test = pcnet32_ethtool_test,
1519 .phys_id = pcnet32_phys_id,
1520 .get_regs_len = pcnet32_get_regs_len,
1521 .get_regs = pcnet32_get_regs,
1522 .get_sset_count = pcnet32_get_sset_count,
1523 };
1524
1525 /* only probes for non-PCI devices, the rest are handled by
1526 * pci_register_driver via pcnet32_probe_pci */
1527
1528 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1529 {
1530 unsigned int *port, ioaddr;
1531
1532 /* search for PCnet32 VLB cards at known addresses */
1533 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1534 if (request_region
1535 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1536 /* check if there is really a pcnet chip on that ioaddr */
1537 if ((inb(ioaddr + 14) == 0x57)
1538 && (inb(ioaddr + 15) == 0x57)) {
1539 pcnet32_probe1(ioaddr, 0, NULL);
1540 } else {
1541 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1542 }
1543 }
1544 }
1545 }
1546
1547 static int __devinit
1548 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1549 {
1550 unsigned long ioaddr;
1551 int err;
1552
1553 err = pci_enable_device(pdev);
1554 if (err < 0) {
1555 if (pcnet32_debug & NETIF_MSG_PROBE)
1556 printk(KERN_ERR PFX
1557 "failed to enable device -- err=%d\n", err);
1558 return err;
1559 }
1560 pci_set_master(pdev);
1561
1562 ioaddr = pci_resource_start(pdev, 0);
1563 if (!ioaddr) {
1564 if (pcnet32_debug & NETIF_MSG_PROBE)
1565 printk(KERN_ERR PFX
1566 "card has no PCI IO resources, aborting\n");
1567 return -ENODEV;
1568 }
1569
1570 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1571 if (pcnet32_debug & NETIF_MSG_PROBE)
1572 printk(KERN_ERR PFX
1573 "architecture does not support 32bit PCI busmaster DMA\n");
1574 return -ENODEV;
1575 }
1576 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1577 NULL) {
1578 if (pcnet32_debug & NETIF_MSG_PROBE)
1579 printk(KERN_ERR PFX
1580 "io address range already allocated\n");
1581 return -EBUSY;
1582 }
1583
1584 err = pcnet32_probe1(ioaddr, 1, pdev);
1585 if (err < 0) {
1586 pci_disable_device(pdev);
1587 }
1588 return err;
1589 }
1590
1591 /* pcnet32_probe1
1592 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1593 * pdev will be NULL when called from pcnet32_probe_vlbus.
1594 */
1595 static int __devinit
1596 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1597 {
1598 struct pcnet32_private *lp;
1599 int i, media;
1600 int fdx, mii, fset, dxsuflo;
1601 int chip_version;
1602 char *chipname;
1603 struct net_device *dev;
1604 struct pcnet32_access *a = NULL;
1605 u8 promaddr[6];
1606 int ret = -ENODEV;
1607
1608 /* reset the chip */
1609 pcnet32_wio_reset(ioaddr);
1610
1611 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1612 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1613 a = &pcnet32_wio;
1614 } else {
1615 pcnet32_dwio_reset(ioaddr);
1616 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1617 && pcnet32_dwio_check(ioaddr)) {
1618 a = &pcnet32_dwio;
1619 } else
1620 goto err_release_region;
1621 }
1622
1623 chip_version =
1624 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1625 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1626 printk(KERN_INFO " PCnet chip version is %#x.\n",
1627 chip_version);
1628 if ((chip_version & 0xfff) != 0x003) {
1629 if (pcnet32_debug & NETIF_MSG_PROBE)
1630 printk(KERN_INFO PFX "Unsupported chip version.\n");
1631 goto err_release_region;
1632 }
1633
1634 /* initialize variables */
1635 fdx = mii = fset = dxsuflo = 0;
1636 chip_version = (chip_version >> 12) & 0xffff;
1637
1638 switch (chip_version) {
1639 case 0x2420:
1640 chipname = "PCnet/PCI 79C970"; /* PCI */
1641 break;
1642 case 0x2430:
1643 if (shared)
1644 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1645 else
1646 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1647 break;
1648 case 0x2621:
1649 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1650 fdx = 1;
1651 break;
1652 case 0x2623:
1653 chipname = "PCnet/FAST 79C971"; /* PCI */
1654 fdx = 1;
1655 mii = 1;
1656 fset = 1;
1657 break;
1658 case 0x2624:
1659 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1660 fdx = 1;
1661 mii = 1;
1662 fset = 1;
1663 break;
1664 case 0x2625:
1665 chipname = "PCnet/FAST III 79C973"; /* PCI */
1666 fdx = 1;
1667 mii = 1;
1668 break;
1669 case 0x2626:
1670 chipname = "PCnet/Home 79C978"; /* PCI */
1671 fdx = 1;
1672 /*
1673 * This is based on specs published at www.amd.com. This section
1674 * assumes that a card with a 79C978 wants to go into standard
1675 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1676 * and the module option homepna=1 can select this instead.
1677 */
1678 media = a->read_bcr(ioaddr, 49);
1679 media &= ~3; /* default to 10Mb ethernet */
1680 if (cards_found < MAX_UNITS && homepna[cards_found])
1681 media |= 1; /* switch to home wiring mode */
1682 if (pcnet32_debug & NETIF_MSG_PROBE)
1683 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1684 (media & 1) ? "1" : "10");
1685 a->write_bcr(ioaddr, 49, media);
1686 break;
1687 case 0x2627:
1688 chipname = "PCnet/FAST III 79C975"; /* PCI */
1689 fdx = 1;
1690 mii = 1;
1691 break;
1692 case 0x2628:
1693 chipname = "PCnet/PRO 79C976";
1694 fdx = 1;
1695 mii = 1;
1696 break;
1697 default:
1698 if (pcnet32_debug & NETIF_MSG_PROBE)
1699 printk(KERN_INFO PFX
1700 "PCnet version %#x, no PCnet32 chip.\n",
1701 chip_version);
1702 goto err_release_region;
1703 }
1704
1705 /*
1706 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1707 * starting until the packet is loaded. Strike one for reliability, lose
1708 * one for latency - although on PCI this isnt a big loss. Older chips
1709 * have FIFO's smaller than a packet, so you can't do this.
1710 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1711 */
1712
1713 if (fset) {
1714 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1715 a->write_csr(ioaddr, 80,
1716 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1717 dxsuflo = 1;
1718 }
1719
1720 dev = alloc_etherdev(sizeof(*lp));
1721 if (!dev) {
1722 if (pcnet32_debug & NETIF_MSG_PROBE)
1723 printk(KERN_ERR PFX "Memory allocation failed.\n");
1724 ret = -ENOMEM;
1725 goto err_release_region;
1726 }
1727 SET_NETDEV_DEV(dev, &pdev->dev);
1728
1729 if (pcnet32_debug & NETIF_MSG_PROBE)
1730 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1731
1732 /* In most chips, after a chip reset, the ethernet address is read from the
1733 * station address PROM at the base address and programmed into the
1734 * "Physical Address Registers" CSR12-14.
1735 * As a precautionary measure, we read the PROM values and complain if
1736 * they disagree with the CSRs. If they miscompare, and the PROM addr
1737 * is valid, then the PROM addr is used.
1738 */
1739 for (i = 0; i < 3; i++) {
1740 unsigned int val;
1741 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1742 /* There may be endianness issues here. */
1743 dev->dev_addr[2 * i] = val & 0x0ff;
1744 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1745 }
1746
1747 /* read PROM address and compare with CSR address */
1748 for (i = 0; i < 6; i++)
1749 promaddr[i] = inb(ioaddr + i);
1750
1751 if (memcmp(promaddr, dev->dev_addr, 6)
1752 || !is_valid_ether_addr(dev->dev_addr)) {
1753 if (is_valid_ether_addr(promaddr)) {
1754 if (pcnet32_debug & NETIF_MSG_PROBE) {
1755 printk(" warning: CSR address invalid,\n");
1756 printk(KERN_INFO
1757 " using instead PROM address of");
1758 }
1759 memcpy(dev->dev_addr, promaddr, 6);
1760 }
1761 }
1762 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1763
1764 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1765 if (!is_valid_ether_addr(dev->perm_addr))
1766 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1767
1768 if (pcnet32_debug & NETIF_MSG_PROBE) {
1769 for (i = 0; i < 6; i++)
1770 printk(" %2.2x", dev->dev_addr[i]);
1771
1772 /* Version 0x2623 and 0x2624 */
1773 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1774 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1775 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1776 switch (i >> 10) {
1777 case 0:
1778 printk(" 20 bytes,");
1779 break;
1780 case 1:
1781 printk(" 64 bytes,");
1782 break;
1783 case 2:
1784 printk(" 128 bytes,");
1785 break;
1786 case 3:
1787 printk("~220 bytes,");
1788 break;
1789 }
1790 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1791 printk(" BCR18(%x):", i & 0xffff);
1792 if (i & (1 << 5))
1793 printk("BurstWrEn ");
1794 if (i & (1 << 6))
1795 printk("BurstRdEn ");
1796 if (i & (1 << 7))
1797 printk("DWordIO ");
1798 if (i & (1 << 11))
1799 printk("NoUFlow ");
1800 i = a->read_bcr(ioaddr, 25);
1801 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1802 i = a->read_bcr(ioaddr, 26);
1803 printk(" SRAM_BND=0x%04x,", i << 8);
1804 i = a->read_bcr(ioaddr, 27);
1805 if (i & (1 << 14))
1806 printk("LowLatRx");
1807 }
1808 }
1809
1810 dev->base_addr = ioaddr;
1811 lp = netdev_priv(dev);
1812 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1813 if ((lp->init_block =
1814 pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
1815 if (pcnet32_debug & NETIF_MSG_PROBE)
1816 printk(KERN_ERR PFX
1817 "Consistent memory allocation failed.\n");
1818 ret = -ENOMEM;
1819 goto err_free_netdev;
1820 }
1821 lp->pci_dev = pdev;
1822
1823 lp->dev = dev;
1824
1825 spin_lock_init(&lp->lock);
1826
1827 SET_NETDEV_DEV(dev, &pdev->dev);
1828 lp->name = chipname;
1829 lp->shared_irq = shared;
1830 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1831 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1832 lp->tx_mod_mask = lp->tx_ring_size - 1;
1833 lp->rx_mod_mask = lp->rx_ring_size - 1;
1834 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1835 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1836 lp->mii_if.full_duplex = fdx;
1837 lp->mii_if.phy_id_mask = 0x1f;
1838 lp->mii_if.reg_num_mask = 0x1f;
1839 lp->dxsuflo = dxsuflo;
1840 lp->mii = mii;
1841 lp->chip_version = chip_version;
1842 lp->msg_enable = pcnet32_debug;
1843 if ((cards_found >= MAX_UNITS)
1844 || (options[cards_found] > sizeof(options_mapping)))
1845 lp->options = PCNET32_PORT_ASEL;
1846 else
1847 lp->options = options_mapping[options[cards_found]];
1848 lp->mii_if.dev = dev;
1849 lp->mii_if.mdio_read = mdio_read;
1850 lp->mii_if.mdio_write = mdio_write;
1851
1852 #ifdef CONFIG_PCNET32_NAPI
1853 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1854 #endif
1855
1856 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1857 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1858 lp->options |= PCNET32_PORT_FD;
1859
1860 if (!a) {
1861 if (pcnet32_debug & NETIF_MSG_PROBE)
1862 printk(KERN_ERR PFX "No access methods\n");
1863 ret = -ENODEV;
1864 goto err_free_consistent;
1865 }
1866 lp->a = *a;
1867
1868 /* prior to register_netdev, dev->name is not yet correct */
1869 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1870 ret = -ENOMEM;
1871 goto err_free_ring;
1872 }
1873 /* detect special T1/E1 WAN card by checking for MAC address */
1874 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1875 && dev->dev_addr[2] == 0x75)
1876 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1877
1878 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
1879 lp->init_block->tlen_rlen =
1880 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1881 for (i = 0; i < 6; i++)
1882 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1883 lp->init_block->filter[0] = 0x00000000;
1884 lp->init_block->filter[1] = 0x00000000;
1885 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1886 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1887
1888 /* switch pcnet32 to 32bit mode */
1889 a->write_bcr(ioaddr, 20, 2);
1890
1891 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1892 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1893
1894 if (pdev) { /* use the IRQ provided by PCI */
1895 dev->irq = pdev->irq;
1896 if (pcnet32_debug & NETIF_MSG_PROBE)
1897 printk(" assigned IRQ %d.\n", dev->irq);
1898 } else {
1899 unsigned long irq_mask = probe_irq_on();
1900
1901 /*
1902 * To auto-IRQ we enable the initialization-done and DMA error
1903 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1904 * boards will work.
1905 */
1906 /* Trigger an initialization just for the interrupt. */
1907 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1908 mdelay(1);
1909
1910 dev->irq = probe_irq_off(irq_mask);
1911 if (!dev->irq) {
1912 if (pcnet32_debug & NETIF_MSG_PROBE)
1913 printk(", failed to detect IRQ line.\n");
1914 ret = -ENODEV;
1915 goto err_free_ring;
1916 }
1917 if (pcnet32_debug & NETIF_MSG_PROBE)
1918 printk(", probed IRQ %d.\n", dev->irq);
1919 }
1920
1921 /* Set the mii phy_id so that we can query the link state */
1922 if (lp->mii) {
1923 /* lp->phycount and lp->phymask are set to 0 by memset above */
1924
1925 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1926 /* scan for PHYs */
1927 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1928 unsigned short id1, id2;
1929
1930 id1 = mdio_read(dev, i, MII_PHYSID1);
1931 if (id1 == 0xffff)
1932 continue;
1933 id2 = mdio_read(dev, i, MII_PHYSID2);
1934 if (id2 == 0xffff)
1935 continue;
1936 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1937 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1938 lp->phycount++;
1939 lp->phymask |= (1 << i);
1940 lp->mii_if.phy_id = i;
1941 if (pcnet32_debug & NETIF_MSG_PROBE)
1942 printk(KERN_INFO PFX
1943 "Found PHY %04x:%04x at address %d.\n",
1944 id1, id2, i);
1945 }
1946 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1947 if (lp->phycount > 1) {
1948 lp->options |= PCNET32_PORT_MII;
1949 }
1950 }
1951
1952 init_timer(&lp->watchdog_timer);
1953 lp->watchdog_timer.data = (unsigned long)dev;
1954 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1955
1956 /* The PCNET32-specific entries in the device structure. */
1957 dev->open = &pcnet32_open;
1958 dev->hard_start_xmit = &pcnet32_start_xmit;
1959 dev->stop = &pcnet32_close;
1960 dev->get_stats = &pcnet32_get_stats;
1961 dev->set_multicast_list = &pcnet32_set_multicast_list;
1962 dev->do_ioctl = &pcnet32_ioctl;
1963 dev->ethtool_ops = &pcnet32_ethtool_ops;
1964 dev->tx_timeout = pcnet32_tx_timeout;
1965 dev->watchdog_timeo = (5 * HZ);
1966
1967 #ifdef CONFIG_NET_POLL_CONTROLLER
1968 dev->poll_controller = pcnet32_poll_controller;
1969 #endif
1970
1971 /* Fill in the generic fields of the device structure. */
1972 if (register_netdev(dev))
1973 goto err_free_ring;
1974
1975 if (pdev) {
1976 pci_set_drvdata(pdev, dev);
1977 } else {
1978 lp->next = pcnet32_dev;
1979 pcnet32_dev = dev;
1980 }
1981
1982 if (pcnet32_debug & NETIF_MSG_PROBE)
1983 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1984 cards_found++;
1985
1986 /* enable LED writes */
1987 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1988
1989 return 0;
1990
1991 err_free_ring:
1992 pcnet32_free_ring(dev);
1993 err_free_consistent:
1994 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
1995 lp->init_block, lp->init_dma_addr);
1996 err_free_netdev:
1997 free_netdev(dev);
1998 err_release_region:
1999 release_region(ioaddr, PCNET32_TOTAL_SIZE);
2000 return ret;
2001 }
2002
2003 /* if any allocation fails, caller must also call pcnet32_free_ring */
2004 static int pcnet32_alloc_ring(struct net_device *dev, char *name)
2005 {
2006 struct pcnet32_private *lp = netdev_priv(dev);
2007
2008 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
2009 sizeof(struct pcnet32_tx_head) *
2010 lp->tx_ring_size,
2011 &lp->tx_ring_dma_addr);
2012 if (lp->tx_ring == NULL) {
2013 if (netif_msg_drv(lp))
2014 printk("\n" KERN_ERR PFX
2015 "%s: Consistent memory allocation failed.\n",
2016 name);
2017 return -ENOMEM;
2018 }
2019
2020 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2021 sizeof(struct pcnet32_rx_head) *
2022 lp->rx_ring_size,
2023 &lp->rx_ring_dma_addr);
2024 if (lp->rx_ring == NULL) {
2025 if (netif_msg_drv(lp))
2026 printk("\n" KERN_ERR PFX
2027 "%s: Consistent memory allocation failed.\n",
2028 name);
2029 return -ENOMEM;
2030 }
2031
2032 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
2033 GFP_ATOMIC);
2034 if (!lp->tx_dma_addr) {
2035 if (netif_msg_drv(lp))
2036 printk("\n" KERN_ERR PFX
2037 "%s: Memory allocation failed.\n", name);
2038 return -ENOMEM;
2039 }
2040
2041 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
2042 GFP_ATOMIC);
2043 if (!lp->rx_dma_addr) {
2044 if (netif_msg_drv(lp))
2045 printk("\n" KERN_ERR PFX
2046 "%s: Memory allocation failed.\n", name);
2047 return -ENOMEM;
2048 }
2049
2050 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2051 GFP_ATOMIC);
2052 if (!lp->tx_skbuff) {
2053 if (netif_msg_drv(lp))
2054 printk("\n" KERN_ERR PFX
2055 "%s: Memory allocation failed.\n", name);
2056 return -ENOMEM;
2057 }
2058
2059 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2060 GFP_ATOMIC);
2061 if (!lp->rx_skbuff) {
2062 if (netif_msg_drv(lp))
2063 printk("\n" KERN_ERR PFX
2064 "%s: Memory allocation failed.\n", name);
2065 return -ENOMEM;
2066 }
2067
2068 return 0;
2069 }
2070
2071 static void pcnet32_free_ring(struct net_device *dev)
2072 {
2073 struct pcnet32_private *lp = netdev_priv(dev);
2074
2075 kfree(lp->tx_skbuff);
2076 lp->tx_skbuff = NULL;
2077
2078 kfree(lp->rx_skbuff);
2079 lp->rx_skbuff = NULL;
2080
2081 kfree(lp->tx_dma_addr);
2082 lp->tx_dma_addr = NULL;
2083
2084 kfree(lp->rx_dma_addr);
2085 lp->rx_dma_addr = NULL;
2086
2087 if (lp->tx_ring) {
2088 pci_free_consistent(lp->pci_dev,
2089 sizeof(struct pcnet32_tx_head) *
2090 lp->tx_ring_size, lp->tx_ring,
2091 lp->tx_ring_dma_addr);
2092 lp->tx_ring = NULL;
2093 }
2094
2095 if (lp->rx_ring) {
2096 pci_free_consistent(lp->pci_dev,
2097 sizeof(struct pcnet32_rx_head) *
2098 lp->rx_ring_size, lp->rx_ring,
2099 lp->rx_ring_dma_addr);
2100 lp->rx_ring = NULL;
2101 }
2102 }
2103
2104 static int pcnet32_open(struct net_device *dev)
2105 {
2106 struct pcnet32_private *lp = netdev_priv(dev);
2107 unsigned long ioaddr = dev->base_addr;
2108 u16 val;
2109 int i;
2110 int rc;
2111 unsigned long flags;
2112
2113 if (request_irq(dev->irq, &pcnet32_interrupt,
2114 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2115 (void *)dev)) {
2116 return -EAGAIN;
2117 }
2118
2119 spin_lock_irqsave(&lp->lock, flags);
2120 /* Check for a valid station address */
2121 if (!is_valid_ether_addr(dev->dev_addr)) {
2122 rc = -EINVAL;
2123 goto err_free_irq;
2124 }
2125
2126 /* Reset the PCNET32 */
2127 lp->a.reset(ioaddr);
2128
2129 /* switch pcnet32 to 32bit mode */
2130 lp->a.write_bcr(ioaddr, 20, 2);
2131
2132 if (netif_msg_ifup(lp))
2133 printk(KERN_DEBUG
2134 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2135 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2136 (u32) (lp->rx_ring_dma_addr),
2137 (u32) (lp->init_dma_addr));
2138
2139 /* set/reset autoselect bit */
2140 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2141 if (lp->options & PCNET32_PORT_ASEL)
2142 val |= 2;
2143 lp->a.write_bcr(ioaddr, 2, val);
2144
2145 /* handle full duplex setting */
2146 if (lp->mii_if.full_duplex) {
2147 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2148 if (lp->options & PCNET32_PORT_FD) {
2149 val |= 1;
2150 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2151 val |= 2;
2152 } else if (lp->options & PCNET32_PORT_ASEL) {
2153 /* workaround of xSeries250, turn on for 79C975 only */
2154 if (lp->chip_version == 0x2627)
2155 val |= 3;
2156 }
2157 lp->a.write_bcr(ioaddr, 9, val);
2158 }
2159
2160 /* set/reset GPSI bit in test register */
2161 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2162 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2163 val |= 0x10;
2164 lp->a.write_csr(ioaddr, 124, val);
2165
2166 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2167 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2168 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2169 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2170 if (lp->options & PCNET32_PORT_ASEL) {
2171 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2172 if (netif_msg_link(lp))
2173 printk(KERN_DEBUG
2174 "%s: Setting 100Mb-Full Duplex.\n",
2175 dev->name);
2176 }
2177 }
2178 if (lp->phycount < 2) {
2179 /*
2180 * 24 Jun 2004 according AMD, in order to change the PHY,
2181 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2182 * duplex, and/or enable auto negotiation, and clear DANAS
2183 */
2184 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2185 lp->a.write_bcr(ioaddr, 32,
2186 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2187 /* disable Auto Negotiation, set 10Mpbs, HD */
2188 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2189 if (lp->options & PCNET32_PORT_FD)
2190 val |= 0x10;
2191 if (lp->options & PCNET32_PORT_100)
2192 val |= 0x08;
2193 lp->a.write_bcr(ioaddr, 32, val);
2194 } else {
2195 if (lp->options & PCNET32_PORT_ASEL) {
2196 lp->a.write_bcr(ioaddr, 32,
2197 lp->a.read_bcr(ioaddr,
2198 32) | 0x0080);
2199 /* enable auto negotiate, setup, disable fd */
2200 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2201 val |= 0x20;
2202 lp->a.write_bcr(ioaddr, 32, val);
2203 }
2204 }
2205 } else {
2206 int first_phy = -1;
2207 u16 bmcr;
2208 u32 bcr9;
2209 struct ethtool_cmd ecmd;
2210
2211 /*
2212 * There is really no good other way to handle multiple PHYs
2213 * other than turning off all automatics
2214 */
2215 val = lp->a.read_bcr(ioaddr, 2);
2216 lp->a.write_bcr(ioaddr, 2, val & ~2);
2217 val = lp->a.read_bcr(ioaddr, 32);
2218 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2219
2220 if (!(lp->options & PCNET32_PORT_ASEL)) {
2221 /* setup ecmd */
2222 ecmd.port = PORT_MII;
2223 ecmd.transceiver = XCVR_INTERNAL;
2224 ecmd.autoneg = AUTONEG_DISABLE;
2225 ecmd.speed =
2226 lp->
2227 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2228 bcr9 = lp->a.read_bcr(ioaddr, 9);
2229
2230 if (lp->options & PCNET32_PORT_FD) {
2231 ecmd.duplex = DUPLEX_FULL;
2232 bcr9 |= (1 << 0);
2233 } else {
2234 ecmd.duplex = DUPLEX_HALF;
2235 bcr9 |= ~(1 << 0);
2236 }
2237 lp->a.write_bcr(ioaddr, 9, bcr9);
2238 }
2239
2240 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2241 if (lp->phymask & (1 << i)) {
2242 /* isolate all but the first PHY */
2243 bmcr = mdio_read(dev, i, MII_BMCR);
2244 if (first_phy == -1) {
2245 first_phy = i;
2246 mdio_write(dev, i, MII_BMCR,
2247 bmcr & ~BMCR_ISOLATE);
2248 } else {
2249 mdio_write(dev, i, MII_BMCR,
2250 bmcr | BMCR_ISOLATE);
2251 }
2252 /* use mii_ethtool_sset to setup PHY */
2253 lp->mii_if.phy_id = i;
2254 ecmd.phy_address = i;
2255 if (lp->options & PCNET32_PORT_ASEL) {
2256 mii_ethtool_gset(&lp->mii_if, &ecmd);
2257 ecmd.autoneg = AUTONEG_ENABLE;
2258 }
2259 mii_ethtool_sset(&lp->mii_if, &ecmd);
2260 }
2261 }
2262 lp->mii_if.phy_id = first_phy;
2263 if (netif_msg_link(lp))
2264 printk(KERN_INFO "%s: Using PHY number %d.\n",
2265 dev->name, first_phy);
2266 }
2267
2268 #ifdef DO_DXSUFLO
2269 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
2270 val = lp->a.read_csr(ioaddr, CSR3);
2271 val |= 0x40;
2272 lp->a.write_csr(ioaddr, CSR3, val);
2273 }
2274 #endif
2275
2276 lp->init_block->mode =
2277 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2278 pcnet32_load_multicast(dev);
2279
2280 if (pcnet32_init_ring(dev)) {
2281 rc = -ENOMEM;
2282 goto err_free_ring;
2283 }
2284
2285 #ifdef CONFIG_PCNET32_NAPI
2286 napi_enable(&lp->napi);
2287 #endif
2288
2289 /* Re-initialize the PCNET32, and start it when done. */
2290 lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2291 lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2292
2293 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2294 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2295
2296 netif_start_queue(dev);
2297
2298 if (lp->chip_version >= PCNET32_79C970A) {
2299 /* Print the link status and start the watchdog */
2300 pcnet32_check_media(dev, 1);
2301 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2302 }
2303
2304 i = 0;
2305 while (i++ < 100)
2306 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2307 break;
2308 /*
2309 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2310 * reports that doing so triggers a bug in the '974.
2311 */
2312 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
2313
2314 if (netif_msg_ifup(lp))
2315 printk(KERN_DEBUG
2316 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2317 dev->name, i,
2318 (u32) (lp->init_dma_addr),
2319 lp->a.read_csr(ioaddr, CSR0));
2320
2321 spin_unlock_irqrestore(&lp->lock, flags);
2322
2323 return 0; /* Always succeed */
2324
2325 err_free_ring:
2326 /* free any allocated skbuffs */
2327 pcnet32_purge_rx_ring(dev);
2328
2329 /*
2330 * Switch back to 16bit mode to avoid problems with dumb
2331 * DOS packet driver after a warm reboot
2332 */
2333 lp->a.write_bcr(ioaddr, 20, 4);
2334
2335 err_free_irq:
2336 spin_unlock_irqrestore(&lp->lock, flags);
2337 free_irq(dev->irq, dev);
2338 return rc;
2339 }
2340
2341 /*
2342 * The LANCE has been halted for one reason or another (busmaster memory
2343 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2344 * etc.). Modern LANCE variants always reload their ring-buffer
2345 * configuration when restarted, so we must reinitialize our ring
2346 * context before restarting. As part of this reinitialization,
2347 * find all packets still on the Tx ring and pretend that they had been
2348 * sent (in effect, drop the packets on the floor) - the higher-level
2349 * protocols will time out and retransmit. It'd be better to shuffle
2350 * these skbs to a temp list and then actually re-Tx them after
2351 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2352 */
2353
2354 static void pcnet32_purge_tx_ring(struct net_device *dev)
2355 {
2356 struct pcnet32_private *lp = netdev_priv(dev);
2357 int i;
2358
2359 for (i = 0; i < lp->tx_ring_size; i++) {
2360 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2361 wmb(); /* Make sure adapter sees owner change */
2362 if (lp->tx_skbuff[i]) {
2363 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2364 lp->tx_skbuff[i]->len,
2365 PCI_DMA_TODEVICE);
2366 dev_kfree_skb_any(lp->tx_skbuff[i]);
2367 }
2368 lp->tx_skbuff[i] = NULL;
2369 lp->tx_dma_addr[i] = 0;
2370 }
2371 }
2372
2373 /* Initialize the PCNET32 Rx and Tx rings. */
2374 static int pcnet32_init_ring(struct net_device *dev)
2375 {
2376 struct pcnet32_private *lp = netdev_priv(dev);
2377 int i;
2378
2379 lp->tx_full = 0;
2380 lp->cur_rx = lp->cur_tx = 0;
2381 lp->dirty_rx = lp->dirty_tx = 0;
2382
2383 for (i = 0; i < lp->rx_ring_size; i++) {
2384 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2385 if (rx_skbuff == NULL) {
2386 if (!
2387 (rx_skbuff = lp->rx_skbuff[i] =
2388 dev_alloc_skb(PKT_BUF_SZ))) {
2389 /* there is not much, we can do at this point */
2390 if (netif_msg_drv(lp))
2391 printk(KERN_ERR
2392 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2393 dev->name);
2394 return -1;
2395 }
2396 skb_reserve(rx_skbuff, 2);
2397 }
2398
2399 rmb();
2400 if (lp->rx_dma_addr[i] == 0)
2401 lp->rx_dma_addr[i] =
2402 pci_map_single(lp->pci_dev, rx_skbuff->data,
2403 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2404 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2405 lp->rx_ring[i].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
2406 wmb(); /* Make sure owner changes after all others are visible */
2407 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2408 }
2409 /* The Tx buffer address is filled in as needed, but we do need to clear
2410 * the upper ownership bit. */
2411 for (i = 0; i < lp->tx_ring_size; i++) {
2412 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2413 wmb(); /* Make sure adapter sees owner change */
2414 lp->tx_ring[i].base = 0;
2415 lp->tx_dma_addr[i] = 0;
2416 }
2417
2418 lp->init_block->tlen_rlen =
2419 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2420 for (i = 0; i < 6; i++)
2421 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2422 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2423 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2424 wmb(); /* Make sure all changes are visible */
2425 return 0;
2426 }
2427
2428 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2429 * then flush the pending transmit operations, re-initialize the ring,
2430 * and tell the chip to initialize.
2431 */
2432 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2433 {
2434 struct pcnet32_private *lp = netdev_priv(dev);
2435 unsigned long ioaddr = dev->base_addr;
2436 int i;
2437
2438 /* wait for stop */
2439 for (i = 0; i < 100; i++)
2440 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
2441 break;
2442
2443 if (i >= 100 && netif_msg_drv(lp))
2444 printk(KERN_ERR
2445 "%s: pcnet32_restart timed out waiting for stop.\n",
2446 dev->name);
2447
2448 pcnet32_purge_tx_ring(dev);
2449 if (pcnet32_init_ring(dev))
2450 return;
2451
2452 /* ReInit Ring */
2453 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2454 i = 0;
2455 while (i++ < 1000)
2456 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2457 break;
2458
2459 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
2460 }
2461
2462 static void pcnet32_tx_timeout(struct net_device *dev)
2463 {
2464 struct pcnet32_private *lp = netdev_priv(dev);
2465 unsigned long ioaddr = dev->base_addr, flags;
2466
2467 spin_lock_irqsave(&lp->lock, flags);
2468 /* Transmitter timeout, serious problems. */
2469 if (pcnet32_debug & NETIF_MSG_DRV)
2470 printk(KERN_ERR
2471 "%s: transmit timed out, status %4.4x, resetting.\n",
2472 dev->name, lp->a.read_csr(ioaddr, CSR0));
2473 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2474 lp->stats.tx_errors++;
2475 if (netif_msg_tx_err(lp)) {
2476 int i;
2477 printk(KERN_DEBUG
2478 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2479 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2480 lp->cur_rx);
2481 for (i = 0; i < lp->rx_ring_size; i++)
2482 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2483 le32_to_cpu(lp->rx_ring[i].base),
2484 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2485 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2486 le16_to_cpu(lp->rx_ring[i].status));
2487 for (i = 0; i < lp->tx_ring_size; i++)
2488 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2489 le32_to_cpu(lp->tx_ring[i].base),
2490 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2491 le32_to_cpu(lp->tx_ring[i].misc),
2492 le16_to_cpu(lp->tx_ring[i].status));
2493 printk("\n");
2494 }
2495 pcnet32_restart(dev, CSR0_NORMAL);
2496
2497 dev->trans_start = jiffies;
2498 netif_wake_queue(dev);
2499
2500 spin_unlock_irqrestore(&lp->lock, flags);
2501 }
2502
2503 static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
2504 {
2505 struct pcnet32_private *lp = netdev_priv(dev);
2506 unsigned long ioaddr = dev->base_addr;
2507 u16 status;
2508 int entry;
2509 unsigned long flags;
2510
2511 spin_lock_irqsave(&lp->lock, flags);
2512
2513 if (netif_msg_tx_queued(lp)) {
2514 printk(KERN_DEBUG
2515 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2516 dev->name, lp->a.read_csr(ioaddr, CSR0));
2517 }
2518
2519 /* Default status -- will not enable Successful-TxDone
2520 * interrupt when that option is available to us.
2521 */
2522 status = 0x8300;
2523
2524 /* Fill in a Tx ring entry */
2525
2526 /* Mask to ring buffer boundary. */
2527 entry = lp->cur_tx & lp->tx_mod_mask;
2528
2529 /* Caution: the write order is important here, set the status
2530 * with the "ownership" bits last. */
2531
2532 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2533
2534 lp->tx_ring[entry].misc = 0x00000000;
2535
2536 lp->tx_skbuff[entry] = skb;
2537 lp->tx_dma_addr[entry] =
2538 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2539 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2540 wmb(); /* Make sure owner changes after all others are visible */
2541 lp->tx_ring[entry].status = cpu_to_le16(status);
2542
2543 lp->cur_tx++;
2544 lp->stats.tx_bytes += skb->len;
2545
2546 /* Trigger an immediate send poll. */
2547 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2548
2549 dev->trans_start = jiffies;
2550
2551 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2552 lp->tx_full = 1;
2553 netif_stop_queue(dev);
2554 }
2555 spin_unlock_irqrestore(&lp->lock, flags);
2556 return 0;
2557 }
2558
2559 /* The PCNET32 interrupt handler. */
2560 static irqreturn_t
2561 pcnet32_interrupt(int irq, void *dev_id)
2562 {
2563 struct net_device *dev = dev_id;
2564 struct pcnet32_private *lp;
2565 unsigned long ioaddr;
2566 u16 csr0;
2567 int boguscnt = max_interrupt_work;
2568
2569 ioaddr = dev->base_addr;
2570 lp = netdev_priv(dev);
2571
2572 spin_lock(&lp->lock);
2573
2574 csr0 = lp->a.read_csr(ioaddr, CSR0);
2575 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2576 if (csr0 == 0xffff) {
2577 break; /* PCMCIA remove happened */
2578 }
2579 /* Acknowledge all of the current interrupt sources ASAP. */
2580 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2581
2582 if (netif_msg_intr(lp))
2583 printk(KERN_DEBUG
2584 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2585 dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
2586
2587 /* Log misc errors. */
2588 if (csr0 & 0x4000)
2589 lp->stats.tx_errors++; /* Tx babble. */
2590 if (csr0 & 0x1000) {
2591 /*
2592 * This happens when our receive ring is full. This
2593 * shouldn't be a problem as we will see normal rx
2594 * interrupts for the frames in the receive ring. But
2595 * there are some PCI chipsets (I can reproduce this
2596 * on SP3G with Intel saturn chipset) which have
2597 * sometimes problems and will fill up the receive
2598 * ring with error descriptors. In this situation we
2599 * don't get a rx interrupt, but a missed frame
2600 * interrupt sooner or later.
2601 */
2602 lp->stats.rx_errors++; /* Missed a Rx frame. */
2603 }
2604 if (csr0 & 0x0800) {
2605 if (netif_msg_drv(lp))
2606 printk(KERN_ERR
2607 "%s: Bus master arbitration failure, status %4.4x.\n",
2608 dev->name, csr0);
2609 /* unlike for the lance, there is no restart needed */
2610 }
2611 #ifdef CONFIG_PCNET32_NAPI
2612 if (netif_rx_schedule_prep(dev, &lp->napi)) {
2613 u16 val;
2614 /* set interrupt masks */
2615 val = lp->a.read_csr(ioaddr, CSR3);
2616 val |= 0x5f00;
2617 lp->a.write_csr(ioaddr, CSR3, val);
2618 mmiowb();
2619 __netif_rx_schedule(dev, &lp->napi);
2620 break;
2621 }
2622 #else
2623 pcnet32_rx(dev, lp->napi.weight);
2624 if (pcnet32_tx(dev)) {
2625 /* reset the chip to clear the error condition, then restart */
2626 lp->a.reset(ioaddr);
2627 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2628 pcnet32_restart(dev, CSR0_START);
2629 netif_wake_queue(dev);
2630 }
2631 #endif
2632 csr0 = lp->a.read_csr(ioaddr, CSR0);
2633 }
2634
2635 #ifndef CONFIG_PCNET32_NAPI
2636 /* Set interrupt enable. */
2637 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
2638 #endif
2639
2640 if (netif_msg_intr(lp))
2641 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2642 dev->name, lp->a.read_csr(ioaddr, CSR0));
2643
2644 spin_unlock(&lp->lock);
2645
2646 return IRQ_HANDLED;
2647 }
2648
2649 static int pcnet32_close(struct net_device *dev)
2650 {
2651 unsigned long ioaddr = dev->base_addr;
2652 struct pcnet32_private *lp = netdev_priv(dev);
2653 unsigned long flags;
2654
2655 del_timer_sync(&lp->watchdog_timer);
2656
2657 netif_stop_queue(dev);
2658 #ifdef CONFIG_PCNET32_NAPI
2659 napi_disable(&lp->napi);
2660 #endif
2661
2662 spin_lock_irqsave(&lp->lock, flags);
2663
2664 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2665
2666 if (netif_msg_ifdown(lp))
2667 printk(KERN_DEBUG
2668 "%s: Shutting down ethercard, status was %2.2x.\n",
2669 dev->name, lp->a.read_csr(ioaddr, CSR0));
2670
2671 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2672 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2673
2674 /*
2675 * Switch back to 16bit mode to avoid problems with dumb
2676 * DOS packet driver after a warm reboot
2677 */
2678 lp->a.write_bcr(ioaddr, 20, 4);
2679
2680 spin_unlock_irqrestore(&lp->lock, flags);
2681
2682 free_irq(dev->irq, dev);
2683
2684 spin_lock_irqsave(&lp->lock, flags);
2685
2686 pcnet32_purge_rx_ring(dev);
2687 pcnet32_purge_tx_ring(dev);
2688
2689 spin_unlock_irqrestore(&lp->lock, flags);
2690
2691 return 0;
2692 }
2693
2694 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2695 {
2696 struct pcnet32_private *lp = netdev_priv(dev);
2697 unsigned long ioaddr = dev->base_addr;
2698 unsigned long flags;
2699
2700 spin_lock_irqsave(&lp->lock, flags);
2701 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2702 spin_unlock_irqrestore(&lp->lock, flags);
2703
2704 return &lp->stats;
2705 }
2706
2707 /* taken from the sunlance driver, which it took from the depca driver */
2708 static void pcnet32_load_multicast(struct net_device *dev)
2709 {
2710 struct pcnet32_private *lp = netdev_priv(dev);
2711 volatile struct pcnet32_init_block *ib = lp->init_block;
2712 volatile __le16 *mcast_table = (__le16 *)ib->filter;
2713 struct dev_mc_list *dmi = dev->mc_list;
2714 unsigned long ioaddr = dev->base_addr;
2715 char *addrs;
2716 int i;
2717 u32 crc;
2718
2719 /* set all multicast bits */
2720 if (dev->flags & IFF_ALLMULTI) {
2721 ib->filter[0] = cpu_to_le32(~0U);
2722 ib->filter[1] = cpu_to_le32(~0U);
2723 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2724 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2725 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2726 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2727 return;
2728 }
2729 /* clear the multicast filter */
2730 ib->filter[0] = 0;
2731 ib->filter[1] = 0;
2732
2733 /* Add addresses */
2734 for (i = 0; i < dev->mc_count; i++) {
2735 addrs = dmi->dmi_addr;
2736 dmi = dmi->next;
2737
2738 /* multicast address? */
2739 if (!(*addrs & 1))
2740 continue;
2741
2742 crc = ether_crc_le(6, addrs);
2743 crc = crc >> 26;
2744 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2745 }
2746 for (i = 0; i < 4; i++)
2747 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2748 le16_to_cpu(mcast_table[i]));
2749 return;
2750 }
2751
2752 /*
2753 * Set or clear the multicast filter for this adaptor.
2754 */
2755 static void pcnet32_set_multicast_list(struct net_device *dev)
2756 {
2757 unsigned long ioaddr = dev->base_addr, flags;
2758 struct pcnet32_private *lp = netdev_priv(dev);
2759 int csr15, suspended;
2760
2761 spin_lock_irqsave(&lp->lock, flags);
2762 suspended = pcnet32_suspend(dev, &flags, 0);
2763 csr15 = lp->a.read_csr(ioaddr, CSR15);
2764 if (dev->flags & IFF_PROMISC) {
2765 /* Log any net taps. */
2766 if (netif_msg_hw(lp))
2767 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2768 dev->name);
2769 lp->init_block->mode =
2770 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2771 7);
2772 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2773 } else {
2774 lp->init_block->mode =
2775 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2776 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2777 pcnet32_load_multicast(dev);
2778 }
2779
2780 if (suspended) {
2781 int csr5;
2782 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2783 csr5 = lp->a.read_csr(ioaddr, CSR5);
2784 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2785 } else {
2786 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2787 pcnet32_restart(dev, CSR0_NORMAL);
2788 netif_wake_queue(dev);
2789 }
2790
2791 spin_unlock_irqrestore(&lp->lock, flags);
2792 }
2793
2794 /* This routine assumes that the lp->lock is held */
2795 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2796 {
2797 struct pcnet32_private *lp = netdev_priv(dev);
2798 unsigned long ioaddr = dev->base_addr;
2799 u16 val_out;
2800
2801 if (!lp->mii)
2802 return 0;
2803
2804 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2805 val_out = lp->a.read_bcr(ioaddr, 34);
2806
2807 return val_out;
2808 }
2809
2810 /* This routine assumes that the lp->lock is held */
2811 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2812 {
2813 struct pcnet32_private *lp = netdev_priv(dev);
2814 unsigned long ioaddr = dev->base_addr;
2815
2816 if (!lp->mii)
2817 return;
2818
2819 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2820 lp->a.write_bcr(ioaddr, 34, val);
2821 }
2822
2823 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2824 {
2825 struct pcnet32_private *lp = netdev_priv(dev);
2826 int rc;
2827 unsigned long flags;
2828
2829 /* SIOC[GS]MIIxxx ioctls */
2830 if (lp->mii) {
2831 spin_lock_irqsave(&lp->lock, flags);
2832 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2833 spin_unlock_irqrestore(&lp->lock, flags);
2834 } else {
2835 rc = -EOPNOTSUPP;
2836 }
2837
2838 return rc;
2839 }
2840
2841 static int pcnet32_check_otherphy(struct net_device *dev)
2842 {
2843 struct pcnet32_private *lp = netdev_priv(dev);
2844 struct mii_if_info mii = lp->mii_if;
2845 u16 bmcr;
2846 int i;
2847
2848 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2849 if (i == lp->mii_if.phy_id)
2850 continue; /* skip active phy */
2851 if (lp->phymask & (1 << i)) {
2852 mii.phy_id = i;
2853 if (mii_link_ok(&mii)) {
2854 /* found PHY with active link */
2855 if (netif_msg_link(lp))
2856 printk(KERN_INFO
2857 "%s: Using PHY number %d.\n",
2858 dev->name, i);
2859
2860 /* isolate inactive phy */
2861 bmcr =
2862 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2863 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2864 bmcr | BMCR_ISOLATE);
2865
2866 /* de-isolate new phy */
2867 bmcr = mdio_read(dev, i, MII_BMCR);
2868 mdio_write(dev, i, MII_BMCR,
2869 bmcr & ~BMCR_ISOLATE);
2870
2871 /* set new phy address */
2872 lp->mii_if.phy_id = i;
2873 return 1;
2874 }
2875 }
2876 }
2877 return 0;
2878 }
2879
2880 /*
2881 * Show the status of the media. Similar to mii_check_media however it
2882 * correctly shows the link speed for all (tested) pcnet32 variants.
2883 * Devices with no mii just report link state without speed.
2884 *
2885 * Caller is assumed to hold and release the lp->lock.
2886 */
2887
2888 static void pcnet32_check_media(struct net_device *dev, int verbose)
2889 {
2890 struct pcnet32_private *lp = netdev_priv(dev);
2891 int curr_link;
2892 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2893 u32 bcr9;
2894
2895 if (lp->mii) {
2896 curr_link = mii_link_ok(&lp->mii_if);
2897 } else {
2898 ulong ioaddr = dev->base_addr; /* card base I/O address */
2899 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2900 }
2901 if (!curr_link) {
2902 if (prev_link || verbose) {
2903 netif_carrier_off(dev);
2904 if (netif_msg_link(lp))
2905 printk(KERN_INFO "%s: link down\n", dev->name);
2906 }
2907 if (lp->phycount > 1) {
2908 curr_link = pcnet32_check_otherphy(dev);
2909 prev_link = 0;
2910 }
2911 } else if (verbose || !prev_link) {
2912 netif_carrier_on(dev);
2913 if (lp->mii) {
2914 if (netif_msg_link(lp)) {
2915 struct ethtool_cmd ecmd;
2916 mii_ethtool_gset(&lp->mii_if, &ecmd);
2917 printk(KERN_INFO
2918 "%s: link up, %sMbps, %s-duplex\n",
2919 dev->name,
2920 (ecmd.speed == SPEED_100) ? "100" : "10",
2921 (ecmd.duplex ==
2922 DUPLEX_FULL) ? "full" : "half");
2923 }
2924 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2925 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2926 if (lp->mii_if.full_duplex)
2927 bcr9 |= (1 << 0);
2928 else
2929 bcr9 &= ~(1 << 0);
2930 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2931 }
2932 } else {
2933 if (netif_msg_link(lp))
2934 printk(KERN_INFO "%s: link up\n", dev->name);
2935 }
2936 }
2937 }
2938
2939 /*
2940 * Check for loss of link and link establishment.
2941 * Can not use mii_check_media because it does nothing if mode is forced.
2942 */
2943
2944 static void pcnet32_watchdog(struct net_device *dev)
2945 {
2946 struct pcnet32_private *lp = netdev_priv(dev);
2947 unsigned long flags;
2948
2949 /* Print the link status if it has changed */
2950 spin_lock_irqsave(&lp->lock, flags);
2951 pcnet32_check_media(dev, 0);
2952 spin_unlock_irqrestore(&lp->lock, flags);
2953
2954 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2955 }
2956
2957 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2958 {
2959 struct net_device *dev = pci_get_drvdata(pdev);
2960
2961 if (netif_running(dev)) {
2962 netif_device_detach(dev);
2963 pcnet32_close(dev);
2964 }
2965 pci_save_state(pdev);
2966 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2967 return 0;
2968 }
2969
2970 static int pcnet32_pm_resume(struct pci_dev *pdev)
2971 {
2972 struct net_device *dev = pci_get_drvdata(pdev);
2973
2974 pci_set_power_state(pdev, PCI_D0);
2975 pci_restore_state(pdev);
2976
2977 if (netif_running(dev)) {
2978 pcnet32_open(dev);
2979 netif_device_attach(dev);
2980 }
2981 return 0;
2982 }
2983
2984 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2985 {
2986 struct net_device *dev = pci_get_drvdata(pdev);
2987
2988 if (dev) {
2989 struct pcnet32_private *lp = netdev_priv(dev);
2990
2991 unregister_netdev(dev);
2992 pcnet32_free_ring(dev);
2993 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2994 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2995 lp->init_block, lp->init_dma_addr);
2996 free_netdev(dev);
2997 pci_disable_device(pdev);
2998 pci_set_drvdata(pdev, NULL);
2999 }
3000 }
3001
3002 static struct pci_driver pcnet32_driver = {
3003 .name = DRV_NAME,
3004 .probe = pcnet32_probe_pci,
3005 .remove = __devexit_p(pcnet32_remove_one),
3006 .id_table = pcnet32_pci_tbl,
3007 .suspend = pcnet32_pm_suspend,
3008 .resume = pcnet32_pm_resume,
3009 };
3010
3011 /* An additional parameter that may be passed in... */
3012 static int debug = -1;
3013 static int tx_start_pt = -1;
3014 static int pcnet32_have_pci;
3015
3016 module_param(debug, int, 0);
3017 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
3018 module_param(max_interrupt_work, int, 0);
3019 MODULE_PARM_DESC(max_interrupt_work,
3020 DRV_NAME " maximum events handled per interrupt");
3021 module_param(rx_copybreak, int, 0);
3022 MODULE_PARM_DESC(rx_copybreak,
3023 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
3024 module_param(tx_start_pt, int, 0);
3025 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
3026 module_param(pcnet32vlb, int, 0);
3027 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
3028 module_param_array(options, int, NULL, 0);
3029 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
3030 module_param_array(full_duplex, int, NULL, 0);
3031 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
3032 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
3033 module_param_array(homepna, int, NULL, 0);
3034 MODULE_PARM_DESC(homepna,
3035 DRV_NAME
3036 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
3037
3038 MODULE_AUTHOR("Thomas Bogendoerfer");
3039 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3040 MODULE_LICENSE("GPL");
3041
3042 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3043
3044 static int __init pcnet32_init_module(void)
3045 {
3046 printk(KERN_INFO "%s", version);
3047
3048 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
3049
3050 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3051 tx_start = tx_start_pt;
3052
3053 /* find the PCI devices */
3054 if (!pci_register_driver(&pcnet32_driver))
3055 pcnet32_have_pci = 1;
3056
3057 /* should we find any remaining VLbus devices ? */
3058 if (pcnet32vlb)
3059 pcnet32_probe_vlbus(pcnet32_portlist);
3060
3061 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3062 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
3063
3064 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
3065 }
3066
3067 static void __exit pcnet32_cleanup_module(void)
3068 {
3069 struct net_device *next_dev;
3070
3071 while (pcnet32_dev) {
3072 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
3073 next_dev = lp->next;
3074 unregister_netdev(pcnet32_dev);
3075 pcnet32_free_ring(pcnet32_dev);
3076 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3077 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3078 lp->init_block, lp->init_dma_addr);
3079 free_netdev(pcnet32_dev);
3080 pcnet32_dev = next_dev;
3081 }
3082
3083 if (pcnet32_have_pci)
3084 pci_unregister_driver(&pcnet32_driver);
3085 }
3086
3087 module_init(pcnet32_init_module);
3088 module_exit(pcnet32_cleanup_module);
3089
3090 /*
3091 * Local variables:
3092 * c-indent-level: 4
3093 * tab-width: 8
3094 * End:
3095 */
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