1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
3 * Copyright 1996-1999 Thomas Bogendoerfer
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
13 * This driver is for PCnet32 and PCnetPCI based ethercards
15 /**************************************************************************
17 * Fixed a few bugs, related to running the controller in 32bit mode.
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
22 *************************************************************************/
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.32"
26 #define DRV_RELDATE "18.Mar.2006"
27 #define PFX DRV_NAME ": "
29 static const char *const version
=
30 DRV_NAME
".c:v" DRV_VERSION
" " DRV_RELDATE
" tsbogend@alpha.franken.de\n";
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/init.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/crc32.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
49 #include <linux/moduleparam.h>
50 #include <linux/bitops.h>
54 #include <asm/uaccess.h>
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
60 static struct pci_device_id pcnet32_pci_tbl
[] = {
61 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_LANCE_HOME
), },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_LANCE
), },
65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
66 * the incorrect vendor id.
68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT
, PCI_DEVICE_ID_AMD_LANCE
),
69 .class = (PCI_CLASS_NETWORK_ETHERNET
<< 8), .class_mask
= 0xffff00, },
71 { } /* terminate list */
74 MODULE_DEVICE_TABLE(pci
, pcnet32_pci_tbl
);
76 static int cards_found
;
81 static unsigned int pcnet32_portlist
[] __initdata
=
82 { 0x300, 0x320, 0x340, 0x360, 0 };
84 static int pcnet32_debug
= 0;
85 static int tx_start
= 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86 static int pcnet32vlb
; /* check for VLB cards ? */
88 static struct net_device
*pcnet32_dev
;
90 static int max_interrupt_work
= 2;
91 static int rx_copybreak
= 200;
93 #define PCNET32_PORT_AUI 0x00
94 #define PCNET32_PORT_10BT 0x01
95 #define PCNET32_PORT_GPSI 0x02
96 #define PCNET32_PORT_MII 0x03
98 #define PCNET32_PORT_PORTSEL 0x03
99 #define PCNET32_PORT_ASEL 0x04
100 #define PCNET32_PORT_100 0x40
101 #define PCNET32_PORT_FD 0x80
103 #define PCNET32_DMA_MASK 0xffffffff
105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
109 * table to translate option values from tulip
110 * to internal options
112 static const unsigned char options_mapping
[] = {
113 PCNET32_PORT_ASEL
, /* 0 Auto-select */
114 PCNET32_PORT_AUI
, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI
, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL
, /* 3 not supported */
117 PCNET32_PORT_10BT
| PCNET32_PORT_FD
, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL
, /* 5 not supported */
119 PCNET32_PORT_ASEL
, /* 6 not supported */
120 PCNET32_PORT_ASEL
, /* 7 not supported */
121 PCNET32_PORT_ASEL
, /* 8 not supported */
122 PCNET32_PORT_MII
, /* 9 MII 10baseT */
123 PCNET32_PORT_MII
| PCNET32_PORT_FD
, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII
, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT
, /* 12 10BaseT */
126 PCNET32_PORT_MII
| PCNET32_PORT_100
, /* 13 MII 100BaseTx */
127 /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_MII
| PCNET32_PORT_100
| PCNET32_PORT_FD
,
129 PCNET32_PORT_ASEL
/* 15 not supported */
132 static const char pcnet32_gstrings_test
[][ETH_GSTRING_LEN
] = {
133 "Loopback test (offline)"
136 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
138 #define PCNET32_NUM_REGS 136
140 #define MAX_UNITS 8 /* More are supported, limit only on options */
141 static int options
[MAX_UNITS
];
142 static int full_duplex
[MAX_UNITS
];
143 static int homepna
[MAX_UNITS
];
146 * Theory of Operation
148 * This driver uses the same software structure as the normal lance
149 * driver. So look for a verbose description in lance.c. The differences
150 * to the normal lance driver is the use of the 32bit mode of PCnet32
151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
152 * 16MB limitation and we don't need bounce buffers.
156 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
160 #ifndef PCNET32_LOG_TX_BUFFERS
161 #define PCNET32_LOG_TX_BUFFERS 4
162 #define PCNET32_LOG_RX_BUFFERS 5
163 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
164 #define PCNET32_LOG_MAX_RX_BUFFERS 9
167 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
168 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
170 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
171 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
173 #define PKT_BUF_SZ 1544
175 /* Offsets from base I/O address. */
176 #define PCNET32_WIO_RDP 0x10
177 #define PCNET32_WIO_RAP 0x12
178 #define PCNET32_WIO_RESET 0x14
179 #define PCNET32_WIO_BDP 0x16
181 #define PCNET32_DWIO_RDP 0x10
182 #define PCNET32_DWIO_RAP 0x14
183 #define PCNET32_DWIO_RESET 0x18
184 #define PCNET32_DWIO_BDP 0x1C
186 #define PCNET32_TOTAL_SIZE 0x20
189 #define CSR0_INIT 0x1
190 #define CSR0_START 0x2
191 #define CSR0_STOP 0x4
192 #define CSR0_TXPOLL 0x8
193 #define CSR0_INTEN 0x40
194 #define CSR0_IDON 0x0100
195 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
196 #define PCNET32_INIT_LOW 1
197 #define PCNET32_INIT_HIGH 2
201 #define CSR5_SUSPEND 0x0001
203 #define PCNET32_MC_FILTER 8
205 /* The PCNET32 Rx and Tx ring descriptors. */
206 struct pcnet32_rx_head
{
214 struct pcnet32_tx_head
{
222 /* The PCNET32 32-Bit initialization block, described in databook. */
223 struct pcnet32_init_block
{
229 /* Receive and transmit ring base, along with extra bits. */
234 /* PCnet32 access functions */
235 struct pcnet32_access
{
236 u16 (*read_csr
) (unsigned long, int);
237 void (*write_csr
) (unsigned long, int, u16
);
238 u16 (*read_bcr
) (unsigned long, int);
239 void (*write_bcr
) (unsigned long, int, u16
);
240 u16 (*read_rap
) (unsigned long);
241 void (*write_rap
) (unsigned long, u16
);
242 void (*reset
) (unsigned long);
246 * The first field of pcnet32_private is read by the ethernet device
247 * so the structure should be allocated using pci_alloc_consistent().
249 struct pcnet32_private
{
250 struct pcnet32_init_block init_block
;
251 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
252 struct pcnet32_rx_head
*rx_ring
;
253 struct pcnet32_tx_head
*tx_ring
;
254 dma_addr_t dma_addr
;/* DMA address of beginning of this
255 object, returned by pci_alloc_consistent */
256 struct pci_dev
*pci_dev
;
258 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
259 struct sk_buff
**tx_skbuff
;
260 struct sk_buff
**rx_skbuff
;
261 dma_addr_t
*tx_dma_addr
;
262 dma_addr_t
*rx_dma_addr
;
263 struct pcnet32_access a
;
264 spinlock_t lock
; /* Guard lock */
265 unsigned int cur_rx
, cur_tx
; /* The next free ring entry */
266 unsigned int rx_ring_size
; /* current rx ring size */
267 unsigned int tx_ring_size
; /* current tx ring size */
268 unsigned int rx_mod_mask
; /* rx ring modular mask */
269 unsigned int tx_mod_mask
; /* tx ring modular mask */
270 unsigned short rx_len_bits
;
271 unsigned short tx_len_bits
;
272 dma_addr_t rx_ring_dma_addr
;
273 dma_addr_t tx_ring_dma_addr
;
274 unsigned int dirty_rx
, /* ring entries to be freed. */
277 struct net_device_stats stats
;
279 char phycount
; /* number of phys found */
281 unsigned int shared_irq
:1, /* shared irq possible */
282 dxsuflo
:1, /* disable transmit stop on uflo */
283 mii
:1; /* mii port available */
284 struct net_device
*next
;
285 struct mii_if_info mii_if
;
286 struct timer_list watchdog_timer
;
287 struct timer_list blink_timer
;
288 u32 msg_enable
; /* debug message level */
290 /* each bit indicates an available PHY */
294 static int pcnet32_probe_pci(struct pci_dev
*, const struct pci_device_id
*);
295 static int pcnet32_probe1(unsigned long, int, struct pci_dev
*);
296 static int pcnet32_open(struct net_device
*);
297 static int pcnet32_init_ring(struct net_device
*);
298 static int pcnet32_start_xmit(struct sk_buff
*, struct net_device
*);
299 static int pcnet32_rx(struct net_device
*);
300 static void pcnet32_tx_timeout(struct net_device
*dev
);
301 static irqreturn_t
pcnet32_interrupt(int, void *, struct pt_regs
*);
302 static int pcnet32_close(struct net_device
*);
303 static struct net_device_stats
*pcnet32_get_stats(struct net_device
*);
304 static void pcnet32_load_multicast(struct net_device
*dev
);
305 static void pcnet32_set_multicast_list(struct net_device
*);
306 static int pcnet32_ioctl(struct net_device
*, struct ifreq
*, int);
307 static void pcnet32_watchdog(struct net_device
*);
308 static int mdio_read(struct net_device
*dev
, int phy_id
, int reg_num
);
309 static void mdio_write(struct net_device
*dev
, int phy_id
, int reg_num
,
311 static void pcnet32_restart(struct net_device
*dev
, unsigned int csr0_bits
);
312 static void pcnet32_ethtool_test(struct net_device
*dev
,
313 struct ethtool_test
*eth_test
, u64
* data
);
314 static int pcnet32_loopback_test(struct net_device
*dev
, uint64_t * data1
);
315 static int pcnet32_phys_id(struct net_device
*dev
, u32 data
);
316 static void pcnet32_led_blink_callback(struct net_device
*dev
);
317 static int pcnet32_get_regs_len(struct net_device
*dev
);
318 static void pcnet32_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
320 static void pcnet32_purge_tx_ring(struct net_device
*dev
);
321 static int pcnet32_alloc_ring(struct net_device
*dev
, char *name
);
322 static void pcnet32_free_ring(struct net_device
*dev
);
323 static void pcnet32_check_media(struct net_device
*dev
, int verbose
);
325 static u16
pcnet32_wio_read_csr(unsigned long addr
, int index
)
327 outw(index
, addr
+ PCNET32_WIO_RAP
);
328 return inw(addr
+ PCNET32_WIO_RDP
);
331 static void pcnet32_wio_write_csr(unsigned long addr
, int index
, u16 val
)
333 outw(index
, addr
+ PCNET32_WIO_RAP
);
334 outw(val
, addr
+ PCNET32_WIO_RDP
);
337 static u16
pcnet32_wio_read_bcr(unsigned long addr
, int index
)
339 outw(index
, addr
+ PCNET32_WIO_RAP
);
340 return inw(addr
+ PCNET32_WIO_BDP
);
343 static void pcnet32_wio_write_bcr(unsigned long addr
, int index
, u16 val
)
345 outw(index
, addr
+ PCNET32_WIO_RAP
);
346 outw(val
, addr
+ PCNET32_WIO_BDP
);
349 static u16
pcnet32_wio_read_rap(unsigned long addr
)
351 return inw(addr
+ PCNET32_WIO_RAP
);
354 static void pcnet32_wio_write_rap(unsigned long addr
, u16 val
)
356 outw(val
, addr
+ PCNET32_WIO_RAP
);
359 static void pcnet32_wio_reset(unsigned long addr
)
361 inw(addr
+ PCNET32_WIO_RESET
);
364 static int pcnet32_wio_check(unsigned long addr
)
366 outw(88, addr
+ PCNET32_WIO_RAP
);
367 return (inw(addr
+ PCNET32_WIO_RAP
) == 88);
370 static struct pcnet32_access pcnet32_wio
= {
371 .read_csr
= pcnet32_wio_read_csr
,
372 .write_csr
= pcnet32_wio_write_csr
,
373 .read_bcr
= pcnet32_wio_read_bcr
,
374 .write_bcr
= pcnet32_wio_write_bcr
,
375 .read_rap
= pcnet32_wio_read_rap
,
376 .write_rap
= pcnet32_wio_write_rap
,
377 .reset
= pcnet32_wio_reset
380 static u16
pcnet32_dwio_read_csr(unsigned long addr
, int index
)
382 outl(index
, addr
+ PCNET32_DWIO_RAP
);
383 return (inl(addr
+ PCNET32_DWIO_RDP
) & 0xffff);
386 static void pcnet32_dwio_write_csr(unsigned long addr
, int index
, u16 val
)
388 outl(index
, addr
+ PCNET32_DWIO_RAP
);
389 outl(val
, addr
+ PCNET32_DWIO_RDP
);
392 static u16
pcnet32_dwio_read_bcr(unsigned long addr
, int index
)
394 outl(index
, addr
+ PCNET32_DWIO_RAP
);
395 return (inl(addr
+ PCNET32_DWIO_BDP
) & 0xffff);
398 static void pcnet32_dwio_write_bcr(unsigned long addr
, int index
, u16 val
)
400 outl(index
, addr
+ PCNET32_DWIO_RAP
);
401 outl(val
, addr
+ PCNET32_DWIO_BDP
);
404 static u16
pcnet32_dwio_read_rap(unsigned long addr
)
406 return (inl(addr
+ PCNET32_DWIO_RAP
) & 0xffff);
409 static void pcnet32_dwio_write_rap(unsigned long addr
, u16 val
)
411 outl(val
, addr
+ PCNET32_DWIO_RAP
);
414 static void pcnet32_dwio_reset(unsigned long addr
)
416 inl(addr
+ PCNET32_DWIO_RESET
);
419 static int pcnet32_dwio_check(unsigned long addr
)
421 outl(88, addr
+ PCNET32_DWIO_RAP
);
422 return ((inl(addr
+ PCNET32_DWIO_RAP
) & 0xffff) == 88);
425 static struct pcnet32_access pcnet32_dwio
= {
426 .read_csr
= pcnet32_dwio_read_csr
,
427 .write_csr
= pcnet32_dwio_write_csr
,
428 .read_bcr
= pcnet32_dwio_read_bcr
,
429 .write_bcr
= pcnet32_dwio_write_bcr
,
430 .read_rap
= pcnet32_dwio_read_rap
,
431 .write_rap
= pcnet32_dwio_write_rap
,
432 .reset
= pcnet32_dwio_reset
435 static void pcnet32_netif_stop(struct net_device
*dev
)
437 dev
->trans_start
= jiffies
;
438 netif_poll_disable(dev
);
439 netif_tx_disable(dev
);
442 static void pcnet32_netif_start(struct net_device
*dev
)
444 netif_wake_queue(dev
);
445 netif_poll_enable(dev
);
449 * Allocate space for the new sized tx ring.
451 * Save new resources.
452 * Any failure keeps old resources.
453 * Must be called with lp->lock held.
455 static void pcnet32_realloc_tx_ring(struct net_device
*dev
,
456 struct pcnet32_private
*lp
,
459 dma_addr_t new_ring_dma_addr
;
460 dma_addr_t
*new_dma_addr_list
;
461 struct pcnet32_tx_head
*new_tx_ring
;
462 struct sk_buff
**new_skb_list
;
464 pcnet32_purge_tx_ring(dev
);
466 new_tx_ring
= pci_alloc_consistent(lp
->pci_dev
,
467 sizeof(struct pcnet32_tx_head
) *
470 if (new_tx_ring
== NULL
) {
471 if (netif_msg_drv(lp
))
473 "%s: Consistent memory allocation failed.\n",
477 memset(new_tx_ring
, 0, sizeof(struct pcnet32_tx_head
) * (1 << size
));
479 new_dma_addr_list
= kcalloc((1 << size
), sizeof(dma_addr_t
),
481 if (!new_dma_addr_list
) {
482 if (netif_msg_drv(lp
))
484 "%s: Memory allocation failed.\n", dev
->name
);
485 goto free_new_tx_ring
;
488 new_skb_list
= kcalloc((1 << size
), sizeof(struct sk_buff
*),
491 if (netif_msg_drv(lp
))
493 "%s: Memory allocation failed.\n", dev
->name
);
497 kfree(lp
->tx_skbuff
);
498 kfree(lp
->tx_dma_addr
);
499 pci_free_consistent(lp
->pci_dev
,
500 sizeof(struct pcnet32_tx_head
) *
501 lp
->tx_ring_size
, lp
->tx_ring
,
502 lp
->tx_ring_dma_addr
);
504 lp
->tx_ring_size
= (1 << size
);
505 lp
->tx_mod_mask
= lp
->tx_ring_size
- 1;
506 lp
->tx_len_bits
= (size
<< 12);
507 lp
->tx_ring
= new_tx_ring
;
508 lp
->tx_ring_dma_addr
= new_ring_dma_addr
;
509 lp
->tx_dma_addr
= new_dma_addr_list
;
510 lp
->tx_skbuff
= new_skb_list
;
514 kfree(new_dma_addr_list
);
516 pci_free_consistent(lp
->pci_dev
,
517 sizeof(struct pcnet32_tx_head
) *
525 * Allocate space for the new sized rx ring.
526 * Re-use old receive buffers.
527 * alloc extra buffers
528 * free unneeded buffers
529 * free unneeded buffers
530 * Save new resources.
531 * Any failure keeps old resources.
532 * Must be called with lp->lock held.
534 static void pcnet32_realloc_rx_ring(struct net_device
*dev
,
535 struct pcnet32_private
*lp
,
538 dma_addr_t new_ring_dma_addr
;
539 dma_addr_t
*new_dma_addr_list
;
540 struct pcnet32_rx_head
*new_rx_ring
;
541 struct sk_buff
**new_skb_list
;
544 new_rx_ring
= pci_alloc_consistent(lp
->pci_dev
,
545 sizeof(struct pcnet32_rx_head
) *
548 if (new_rx_ring
== NULL
) {
549 if (netif_msg_drv(lp
))
551 "%s: Consistent memory allocation failed.\n",
555 memset(new_rx_ring
, 0, sizeof(struct pcnet32_rx_head
) * (1 << size
));
557 new_dma_addr_list
= kcalloc((1 << size
), sizeof(dma_addr_t
),
559 if (!new_dma_addr_list
) {
560 if (netif_msg_drv(lp
))
562 "%s: Memory allocation failed.\n", dev
->name
);
563 goto free_new_rx_ring
;
566 new_skb_list
= kcalloc((1 << size
), sizeof(struct sk_buff
*),
569 if (netif_msg_drv(lp
))
571 "%s: Memory allocation failed.\n", dev
->name
);
575 /* first copy the current receive buffers */
576 overlap
= min(size
, lp
->rx_ring_size
);
577 for (new = 0; new < overlap
; new++) {
578 new_rx_ring
[new] = lp
->rx_ring
[new];
579 new_dma_addr_list
[new] = lp
->rx_dma_addr
[new];
580 new_skb_list
[new] = lp
->rx_skbuff
[new];
582 /* now allocate any new buffers needed */
583 for (; new < size
; new++ ) {
584 struct sk_buff
*rx_skbuff
;
585 new_skb_list
[new] = dev_alloc_skb(PKT_BUF_SZ
);
586 if (!(rx_skbuff
= new_skb_list
[new])) {
587 /* keep the original lists and buffers */
588 if (netif_msg_drv(lp
))
590 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
594 skb_reserve(rx_skbuff
, 2);
596 new_dma_addr_list
[new] =
597 pci_map_single(lp
->pci_dev
, rx_skbuff
->data
,
598 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
599 new_rx_ring
[new].base
= (u32
) le32_to_cpu(new_dma_addr_list
[new]);
600 new_rx_ring
[new].buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
601 new_rx_ring
[new].status
= le16_to_cpu(0x8000);
603 /* and free any unneeded buffers */
604 for (; new < lp
->rx_ring_size
; new++) {
605 if (lp
->rx_skbuff
[new]) {
606 pci_unmap_single(lp
->pci_dev
, lp
->rx_dma_addr
[new],
607 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
608 dev_kfree_skb(lp
->rx_skbuff
[new]);
612 kfree(lp
->rx_skbuff
);
613 kfree(lp
->rx_dma_addr
);
614 pci_free_consistent(lp
->pci_dev
,
615 sizeof(struct pcnet32_rx_head
) *
616 lp
->rx_ring_size
, lp
->rx_ring
,
617 lp
->rx_ring_dma_addr
);
619 lp
->rx_ring_size
= (1 << size
);
620 lp
->rx_mod_mask
= lp
->rx_ring_size
- 1;
621 lp
->rx_len_bits
= (size
<< 4);
622 lp
->rx_ring
= new_rx_ring
;
623 lp
->rx_ring_dma_addr
= new_ring_dma_addr
;
624 lp
->rx_dma_addr
= new_dma_addr_list
;
625 lp
->rx_skbuff
= new_skb_list
;
629 for (; --new >= lp
->rx_ring_size
; ) {
630 if (new_skb_list
[new]) {
631 pci_unmap_single(lp
->pci_dev
, new_dma_addr_list
[new],
632 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
633 dev_kfree_skb(new_skb_list
[new]);
638 kfree(new_dma_addr_list
);
640 pci_free_consistent(lp
->pci_dev
,
641 sizeof(struct pcnet32_rx_head
) *
648 #ifdef CONFIG_NET_POLL_CONTROLLER
649 static void pcnet32_poll_controller(struct net_device
*dev
)
651 disable_irq(dev
->irq
);
652 pcnet32_interrupt(0, dev
, NULL
);
653 enable_irq(dev
->irq
);
657 static int pcnet32_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
659 struct pcnet32_private
*lp
= dev
->priv
;
664 spin_lock_irqsave(&lp
->lock
, flags
);
665 mii_ethtool_gset(&lp
->mii_if
, cmd
);
666 spin_unlock_irqrestore(&lp
->lock
, flags
);
672 static int pcnet32_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
674 struct pcnet32_private
*lp
= dev
->priv
;
679 spin_lock_irqsave(&lp
->lock
, flags
);
680 r
= mii_ethtool_sset(&lp
->mii_if
, cmd
);
681 spin_unlock_irqrestore(&lp
->lock
, flags
);
686 static void pcnet32_get_drvinfo(struct net_device
*dev
,
687 struct ethtool_drvinfo
*info
)
689 struct pcnet32_private
*lp
= dev
->priv
;
691 strcpy(info
->driver
, DRV_NAME
);
692 strcpy(info
->version
, DRV_VERSION
);
694 strcpy(info
->bus_info
, pci_name(lp
->pci_dev
));
696 sprintf(info
->bus_info
, "VLB 0x%lx", dev
->base_addr
);
699 static u32
pcnet32_get_link(struct net_device
*dev
)
701 struct pcnet32_private
*lp
= dev
->priv
;
705 spin_lock_irqsave(&lp
->lock
, flags
);
707 r
= mii_link_ok(&lp
->mii_if
);
709 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
710 r
= (lp
->a
.read_bcr(ioaddr
, 4) != 0xc0);
712 spin_unlock_irqrestore(&lp
->lock
, flags
);
717 static u32
pcnet32_get_msglevel(struct net_device
*dev
)
719 struct pcnet32_private
*lp
= dev
->priv
;
720 return lp
->msg_enable
;
723 static void pcnet32_set_msglevel(struct net_device
*dev
, u32 value
)
725 struct pcnet32_private
*lp
= dev
->priv
;
726 lp
->msg_enable
= value
;
729 static int pcnet32_nway_reset(struct net_device
*dev
)
731 struct pcnet32_private
*lp
= dev
->priv
;
736 spin_lock_irqsave(&lp
->lock
, flags
);
737 r
= mii_nway_restart(&lp
->mii_if
);
738 spin_unlock_irqrestore(&lp
->lock
, flags
);
743 static void pcnet32_get_ringparam(struct net_device
*dev
,
744 struct ethtool_ringparam
*ering
)
746 struct pcnet32_private
*lp
= dev
->priv
;
748 ering
->tx_max_pending
= TX_MAX_RING_SIZE
;
749 ering
->tx_pending
= lp
->tx_ring_size
;
750 ering
->rx_max_pending
= RX_MAX_RING_SIZE
;
751 ering
->rx_pending
= lp
->rx_ring_size
;
754 static int pcnet32_set_ringparam(struct net_device
*dev
,
755 struct ethtool_ringparam
*ering
)
757 struct pcnet32_private
*lp
= dev
->priv
;
760 ulong ioaddr
= dev
->base_addr
;
763 if (ering
->rx_mini_pending
|| ering
->rx_jumbo_pending
)
766 if (netif_running(dev
))
767 pcnet32_netif_stop(dev
);
769 spin_lock_irqsave(&lp
->lock
, flags
);
770 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* stop the chip */
772 size
= min(ering
->tx_pending
, (unsigned int)TX_MAX_RING_SIZE
);
774 /* set the minimum ring size to 4, to allow the loopback test to work
777 for (i
= 2; i
<= PCNET32_LOG_MAX_TX_BUFFERS
; i
++) {
778 if (size
<= (1 << i
))
781 if ((1 << i
) != lp
->tx_ring_size
)
782 pcnet32_realloc_tx_ring(dev
, lp
, i
);
784 size
= min(ering
->rx_pending
, (unsigned int)RX_MAX_RING_SIZE
);
785 for (i
= 2; i
<= PCNET32_LOG_MAX_RX_BUFFERS
; i
++) {
786 if (size
<= (1 << i
))
789 if ((1 << i
) != lp
->rx_ring_size
)
790 pcnet32_realloc_rx_ring(dev
, lp
, i
);
792 dev
->weight
= lp
->rx_ring_size
/ 2;
794 if (netif_running(dev
)) {
795 pcnet32_netif_start(dev
);
796 pcnet32_restart(dev
, CSR0_NORMAL
);
799 spin_unlock_irqrestore(&lp
->lock
, flags
);
801 if (netif_msg_drv(lp
))
803 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev
->name
,
804 lp
->rx_ring_size
, lp
->tx_ring_size
);
809 static void pcnet32_get_strings(struct net_device
*dev
, u32 stringset
,
812 memcpy(data
, pcnet32_gstrings_test
, sizeof(pcnet32_gstrings_test
));
815 static int pcnet32_self_test_count(struct net_device
*dev
)
817 return PCNET32_TEST_LEN
;
820 static void pcnet32_ethtool_test(struct net_device
*dev
,
821 struct ethtool_test
*test
, u64
* data
)
823 struct pcnet32_private
*lp
= dev
->priv
;
826 if (test
->flags
== ETH_TEST_FL_OFFLINE
) {
827 rc
= pcnet32_loopback_test(dev
, data
);
829 if (netif_msg_hw(lp
))
830 printk(KERN_DEBUG
"%s: Loopback test failed.\n",
832 test
->flags
|= ETH_TEST_FL_FAILED
;
833 } else if (netif_msg_hw(lp
))
834 printk(KERN_DEBUG
"%s: Loopback test passed.\n",
836 } else if (netif_msg_hw(lp
))
838 "%s: No tests to run (specify 'Offline' on ethtool).",
840 } /* end pcnet32_ethtool_test */
842 static int pcnet32_loopback_test(struct net_device
*dev
, uint64_t * data1
)
844 struct pcnet32_private
*lp
= dev
->priv
;
845 struct pcnet32_access
*a
= &lp
->a
; /* access to registers */
846 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
847 struct sk_buff
*skb
; /* sk buff */
848 int x
, i
; /* counters */
849 int numbuffs
= 4; /* number of TX/RX buffers and descs */
850 u16 status
= 0x8300; /* TX ring status */
851 u16 teststatus
; /* test of ring status */
852 int rc
; /* return code */
853 int size
; /* size of packets */
854 unsigned char *packet
; /* source packet data */
855 static const int data_len
= 60; /* length of source packets */
859 *data1
= 1; /* status of test, default to fail */
860 rc
= 1; /* default to fail */
862 if (netif_running(dev
))
865 spin_lock_irqsave(&lp
->lock
, flags
);
867 /* Reset the PCNET32 */
870 /* switch pcnet32 to 32bit mode */
871 lp
->a
.write_bcr(ioaddr
, 20, 2);
873 lp
->init_block
.mode
=
874 le16_to_cpu((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
875 lp
->init_block
.filter
[0] = 0;
876 lp
->init_block
.filter
[1] = 0;
878 /* purge & init rings but don't actually restart */
879 pcnet32_restart(dev
, 0x0000);
881 lp
->a
.write_csr(ioaddr
, 0, 0x0004); /* Set STOP bit */
883 /* Initialize Transmit buffers. */
884 size
= data_len
+ 15;
885 for (x
= 0; x
< numbuffs
; x
++) {
886 if (!(skb
= dev_alloc_skb(size
))) {
887 if (netif_msg_hw(lp
))
889 "%s: Cannot allocate skb at line: %d!\n",
890 dev
->name
, __LINE__
);
894 skb_put(skb
, size
); /* create space for data */
895 lp
->tx_skbuff
[x
] = skb
;
896 lp
->tx_ring
[x
].length
= le16_to_cpu(-skb
->len
);
897 lp
->tx_ring
[x
].misc
= 0;
899 /* put DA and SA into the skb */
900 for (i
= 0; i
< 6; i
++)
901 *packet
++ = dev
->dev_addr
[i
];
902 for (i
= 0; i
< 6; i
++)
903 *packet
++ = dev
->dev_addr
[i
];
909 /* fill packet with data */
910 for (i
= 0; i
< data_len
; i
++)
914 pci_map_single(lp
->pci_dev
, skb
->data
, skb
->len
,
916 lp
->tx_ring
[x
].base
=
917 (u32
) le32_to_cpu(lp
->tx_dma_addr
[x
]);
918 wmb(); /* Make sure owner changes after all others are visible */
919 lp
->tx_ring
[x
].status
= le16_to_cpu(status
);
923 x
= a
->read_bcr(ioaddr
, 32); /* set internal loopback in BSR32 */
925 a
->write_bcr(ioaddr
, 32, x
);
927 lp
->a
.write_csr(ioaddr
, 15, 0x0044); /* set int loopback in CSR15 */
929 teststatus
= le16_to_cpu(0x8000);
930 lp
->a
.write_csr(ioaddr
, 0, 0x0002); /* Set STRT bit */
932 /* Check status of descriptors */
933 for (x
= 0; x
< numbuffs
; x
++) {
936 while ((lp
->rx_ring
[x
].status
& teststatus
) && (ticks
< 200)) {
937 spin_unlock_irqrestore(&lp
->lock
, flags
);
939 spin_lock_irqsave(&lp
->lock
, flags
);
944 if (netif_msg_hw(lp
))
945 printk("%s: Desc %d failed to reset!\n",
951 lp
->a
.write_csr(ioaddr
, 0, 0x0004); /* Set STOP bit */
953 if (netif_msg_hw(lp
) && netif_msg_pktdata(lp
)) {
954 printk(KERN_DEBUG
"%s: RX loopback packets:\n", dev
->name
);
956 for (x
= 0; x
< numbuffs
; x
++) {
957 printk(KERN_DEBUG
"%s: Packet %d:\n", dev
->name
, x
);
958 skb
= lp
->rx_skbuff
[x
];
959 for (i
= 0; i
< size
; i
++) {
960 printk("%02x ", *(skb
->data
+ i
));
968 while (x
< numbuffs
&& !rc
) {
969 skb
= lp
->rx_skbuff
[x
];
970 packet
= lp
->tx_skbuff
[x
]->data
;
971 for (i
= 0; i
< size
; i
++) {
972 if (*(skb
->data
+ i
) != packet
[i
]) {
973 if (netif_msg_hw(lp
))
975 "%s: Error in compare! %2x - %02x %02x\n",
976 dev
->name
, i
, *(skb
->data
+ i
),
989 pcnet32_purge_tx_ring(dev
);
990 x
= a
->read_csr(ioaddr
, 15) & 0xFFFF;
991 a
->write_csr(ioaddr
, 15, (x
& ~0x0044)); /* reset bits 6 and 2 */
993 x
= a
->read_bcr(ioaddr
, 32); /* reset internal loopback */
995 a
->write_bcr(ioaddr
, 32, x
);
997 spin_unlock_irqrestore(&lp
->lock
, flags
);
999 if (netif_running(dev
)) {
1002 lp
->a
.write_bcr(ioaddr
, 20, 4); /* return to 16bit mode */
1006 } /* end pcnet32_loopback_test */
1008 static void pcnet32_led_blink_callback(struct net_device
*dev
)
1010 struct pcnet32_private
*lp
= dev
->priv
;
1011 struct pcnet32_access
*a
= &lp
->a
;
1012 ulong ioaddr
= dev
->base_addr
;
1013 unsigned long flags
;
1016 spin_lock_irqsave(&lp
->lock
, flags
);
1017 for (i
= 4; i
< 8; i
++) {
1018 a
->write_bcr(ioaddr
, i
, a
->read_bcr(ioaddr
, i
) ^ 0x4000);
1020 spin_unlock_irqrestore(&lp
->lock
, flags
);
1022 mod_timer(&lp
->blink_timer
, PCNET32_BLINK_TIMEOUT
);
1025 static int pcnet32_phys_id(struct net_device
*dev
, u32 data
)
1027 struct pcnet32_private
*lp
= dev
->priv
;
1028 struct pcnet32_access
*a
= &lp
->a
;
1029 ulong ioaddr
= dev
->base_addr
;
1030 unsigned long flags
;
1033 if (!lp
->blink_timer
.function
) {
1034 init_timer(&lp
->blink_timer
);
1035 lp
->blink_timer
.function
= (void *)pcnet32_led_blink_callback
;
1036 lp
->blink_timer
.data
= (unsigned long)dev
;
1039 /* Save the current value of the bcrs */
1040 spin_lock_irqsave(&lp
->lock
, flags
);
1041 for (i
= 4; i
< 8; i
++) {
1042 regs
[i
- 4] = a
->read_bcr(ioaddr
, i
);
1044 spin_unlock_irqrestore(&lp
->lock
, flags
);
1046 mod_timer(&lp
->blink_timer
, jiffies
);
1047 set_current_state(TASK_INTERRUPTIBLE
);
1049 if ((!data
) || (data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
)))
1050 data
= (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
);
1052 msleep_interruptible(data
* 1000);
1053 del_timer_sync(&lp
->blink_timer
);
1055 /* Restore the original value of the bcrs */
1056 spin_lock_irqsave(&lp
->lock
, flags
);
1057 for (i
= 4; i
< 8; i
++) {
1058 a
->write_bcr(ioaddr
, i
, regs
[i
- 4]);
1060 spin_unlock_irqrestore(&lp
->lock
, flags
);
1066 * lp->lock must be held.
1068 static int pcnet32_suspend(struct net_device
*dev
, unsigned long *flags
,
1072 struct pcnet32_private
*lp
= dev
->priv
;
1073 struct pcnet32_access
*a
= &lp
->a
;
1074 ulong ioaddr
= dev
->base_addr
;
1077 /* set SUSPEND (SPND) - CSR5 bit 0 */
1078 csr5
= a
->read_csr(ioaddr
, CSR5
);
1079 a
->write_csr(ioaddr
, CSR5
, csr5
| CSR5_SUSPEND
);
1081 /* poll waiting for bit to be set */
1083 while (!(a
->read_csr(ioaddr
, CSR5
) & CSR5_SUSPEND
)) {
1084 spin_unlock_irqrestore(&lp
->lock
, *flags
);
1089 spin_lock_irqsave(&lp
->lock
, *flags
);
1092 if (netif_msg_hw(lp
))
1094 "%s: Error getting into suspend!\n",
1102 #define PCNET32_REGS_PER_PHY 32
1103 #define PCNET32_MAX_PHYS 32
1104 static int pcnet32_get_regs_len(struct net_device
*dev
)
1106 struct pcnet32_private
*lp
= dev
->priv
;
1107 int j
= lp
->phycount
* PCNET32_REGS_PER_PHY
;
1109 return ((PCNET32_NUM_REGS
+ j
) * sizeof(u16
));
1112 static void pcnet32_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1117 struct pcnet32_private
*lp
= dev
->priv
;
1118 struct pcnet32_access
*a
= &lp
->a
;
1119 ulong ioaddr
= dev
->base_addr
;
1120 unsigned long flags
;
1122 spin_lock_irqsave(&lp
->lock
, flags
);
1124 csr0
= a
->read_csr(ioaddr
, CSR0
);
1125 if (!(csr0
& CSR0_STOP
)) /* If not stopped */
1126 pcnet32_suspend(dev
, &flags
, 1);
1128 /* read address PROM */
1129 for (i
= 0; i
< 16; i
+= 2)
1130 *buff
++ = inw(ioaddr
+ i
);
1132 /* read control and status registers */
1133 for (i
= 0; i
< 90; i
++) {
1134 *buff
++ = a
->read_csr(ioaddr
, i
);
1137 *buff
++ = a
->read_csr(ioaddr
, 112);
1138 *buff
++ = a
->read_csr(ioaddr
, 114);
1140 /* read bus configuration registers */
1141 for (i
= 0; i
< 30; i
++) {
1142 *buff
++ = a
->read_bcr(ioaddr
, i
);
1144 *buff
++ = 0; /* skip bcr30 so as not to hang 79C976 */
1145 for (i
= 31; i
< 36; i
++) {
1146 *buff
++ = a
->read_bcr(ioaddr
, i
);
1149 /* read mii phy registers */
1152 for (j
= 0; j
< PCNET32_MAX_PHYS
; j
++) {
1153 if (lp
->phymask
& (1 << j
)) {
1154 for (i
= 0; i
< PCNET32_REGS_PER_PHY
; i
++) {
1155 lp
->a
.write_bcr(ioaddr
, 33,
1157 *buff
++ = lp
->a
.read_bcr(ioaddr
, 34);
1163 if (!(csr0
& CSR0_STOP
)) { /* If not stopped */
1166 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1167 csr5
= a
->read_csr(ioaddr
, CSR5
);
1168 a
->write_csr(ioaddr
, CSR5
, csr5
& (~CSR5_SUSPEND
));
1171 spin_unlock_irqrestore(&lp
->lock
, flags
);
1174 static struct ethtool_ops pcnet32_ethtool_ops
= {
1175 .get_settings
= pcnet32_get_settings
,
1176 .set_settings
= pcnet32_set_settings
,
1177 .get_drvinfo
= pcnet32_get_drvinfo
,
1178 .get_msglevel
= pcnet32_get_msglevel
,
1179 .set_msglevel
= pcnet32_set_msglevel
,
1180 .nway_reset
= pcnet32_nway_reset
,
1181 .get_link
= pcnet32_get_link
,
1182 .get_ringparam
= pcnet32_get_ringparam
,
1183 .set_ringparam
= pcnet32_set_ringparam
,
1184 .get_tx_csum
= ethtool_op_get_tx_csum
,
1185 .get_sg
= ethtool_op_get_sg
,
1186 .get_tso
= ethtool_op_get_tso
,
1187 .get_strings
= pcnet32_get_strings
,
1188 .self_test_count
= pcnet32_self_test_count
,
1189 .self_test
= pcnet32_ethtool_test
,
1190 .phys_id
= pcnet32_phys_id
,
1191 .get_regs_len
= pcnet32_get_regs_len
,
1192 .get_regs
= pcnet32_get_regs
,
1193 .get_perm_addr
= ethtool_op_get_perm_addr
,
1196 /* only probes for non-PCI devices, the rest are handled by
1197 * pci_register_driver via pcnet32_probe_pci */
1199 static void __devinit
pcnet32_probe_vlbus(unsigned int *pcnet32_portlist
)
1201 unsigned int *port
, ioaddr
;
1203 /* search for PCnet32 VLB cards at known addresses */
1204 for (port
= pcnet32_portlist
; (ioaddr
= *port
); port
++) {
1206 (ioaddr
, PCNET32_TOTAL_SIZE
, "pcnet32_probe_vlbus")) {
1207 /* check if there is really a pcnet chip on that ioaddr */
1208 if ((inb(ioaddr
+ 14) == 0x57)
1209 && (inb(ioaddr
+ 15) == 0x57)) {
1210 pcnet32_probe1(ioaddr
, 0, NULL
);
1212 release_region(ioaddr
, PCNET32_TOTAL_SIZE
);
1218 static int __devinit
1219 pcnet32_probe_pci(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1221 unsigned long ioaddr
;
1224 err
= pci_enable_device(pdev
);
1226 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1228 "failed to enable device -- err=%d\n", err
);
1231 pci_set_master(pdev
);
1233 ioaddr
= pci_resource_start(pdev
, 0);
1235 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1237 "card has no PCI IO resources, aborting\n");
1241 if (!pci_dma_supported(pdev
, PCNET32_DMA_MASK
)) {
1242 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1244 "architecture does not support 32bit PCI busmaster DMA\n");
1247 if (request_region(ioaddr
, PCNET32_TOTAL_SIZE
, "pcnet32_probe_pci") ==
1249 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1251 "io address range already allocated\n");
1255 err
= pcnet32_probe1(ioaddr
, 1, pdev
);
1257 pci_disable_device(pdev
);
1263 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1264 * pdev will be NULL when called from pcnet32_probe_vlbus.
1266 static int __devinit
1267 pcnet32_probe1(unsigned long ioaddr
, int shared
, struct pci_dev
*pdev
)
1269 struct pcnet32_private
*lp
;
1270 dma_addr_t lp_dma_addr
;
1272 int fdx
, mii
, fset
, dxsuflo
;
1275 struct net_device
*dev
;
1276 struct pcnet32_access
*a
= NULL
;
1280 /* reset the chip */
1281 pcnet32_wio_reset(ioaddr
);
1283 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1284 if (pcnet32_wio_read_csr(ioaddr
, 0) == 4 && pcnet32_wio_check(ioaddr
)) {
1287 pcnet32_dwio_reset(ioaddr
);
1288 if (pcnet32_dwio_read_csr(ioaddr
, 0) == 4
1289 && pcnet32_dwio_check(ioaddr
)) {
1292 goto err_release_region
;
1296 a
->read_csr(ioaddr
, 88) | (a
->read_csr(ioaddr
, 89) << 16);
1297 if ((pcnet32_debug
& NETIF_MSG_PROBE
) && (pcnet32_debug
& NETIF_MSG_HW
))
1298 printk(KERN_INFO
" PCnet chip version is %#x.\n",
1300 if ((chip_version
& 0xfff) != 0x003) {
1301 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1302 printk(KERN_INFO PFX
"Unsupported chip version.\n");
1303 goto err_release_region
;
1306 /* initialize variables */
1307 fdx
= mii
= fset
= dxsuflo
= 0;
1308 chip_version
= (chip_version
>> 12) & 0xffff;
1310 switch (chip_version
) {
1312 chipname
= "PCnet/PCI 79C970"; /* PCI */
1316 chipname
= "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1318 chipname
= "PCnet/32 79C965"; /* 486/VL bus */
1321 chipname
= "PCnet/PCI II 79C970A"; /* PCI */
1325 chipname
= "PCnet/FAST 79C971"; /* PCI */
1331 chipname
= "PCnet/FAST+ 79C972"; /* PCI */
1337 chipname
= "PCnet/FAST III 79C973"; /* PCI */
1342 chipname
= "PCnet/Home 79C978"; /* PCI */
1345 * This is based on specs published at www.amd.com. This section
1346 * assumes that a card with a 79C978 wants to go into standard
1347 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1348 * and the module option homepna=1 can select this instead.
1350 media
= a
->read_bcr(ioaddr
, 49);
1351 media
&= ~3; /* default to 10Mb ethernet */
1352 if (cards_found
< MAX_UNITS
&& homepna
[cards_found
])
1353 media
|= 1; /* switch to home wiring mode */
1354 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1355 printk(KERN_DEBUG PFX
"media set to %sMbit mode.\n",
1356 (media
& 1) ? "1" : "10");
1357 a
->write_bcr(ioaddr
, 49, media
);
1360 chipname
= "PCnet/FAST III 79C975"; /* PCI */
1365 chipname
= "PCnet/PRO 79C976";
1370 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1371 printk(KERN_INFO PFX
1372 "PCnet version %#x, no PCnet32 chip.\n",
1374 goto err_release_region
;
1378 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1379 * starting until the packet is loaded. Strike one for reliability, lose
1380 * one for latency - although on PCI this isnt a big loss. Older chips
1381 * have FIFO's smaller than a packet, so you can't do this.
1382 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1386 a
->write_bcr(ioaddr
, 18, (a
->read_bcr(ioaddr
, 18) | 0x0860));
1387 a
->write_csr(ioaddr
, 80,
1388 (a
->read_csr(ioaddr
, 80) & 0x0C00) | 0x0c00);
1392 dev
= alloc_etherdev(0);
1394 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1395 printk(KERN_ERR PFX
"Memory allocation failed.\n");
1397 goto err_release_region
;
1399 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1401 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1402 printk(KERN_INFO PFX
"%s at %#3lx,", chipname
, ioaddr
);
1404 /* In most chips, after a chip reset, the ethernet address is read from the
1405 * station address PROM at the base address and programmed into the
1406 * "Physical Address Registers" CSR12-14.
1407 * As a precautionary measure, we read the PROM values and complain if
1408 * they disagree with the CSRs. If they miscompare, and the PROM addr
1409 * is valid, then the PROM addr is used.
1411 for (i
= 0; i
< 3; i
++) {
1413 val
= a
->read_csr(ioaddr
, i
+ 12) & 0x0ffff;
1414 /* There may be endianness issues here. */
1415 dev
->dev_addr
[2 * i
] = val
& 0x0ff;
1416 dev
->dev_addr
[2 * i
+ 1] = (val
>> 8) & 0x0ff;
1419 /* read PROM address and compare with CSR address */
1420 for (i
= 0; i
< 6; i
++)
1421 promaddr
[i
] = inb(ioaddr
+ i
);
1423 if (memcmp(promaddr
, dev
->dev_addr
, 6)
1424 || !is_valid_ether_addr(dev
->dev_addr
)) {
1425 if (is_valid_ether_addr(promaddr
)) {
1426 if (pcnet32_debug
& NETIF_MSG_PROBE
) {
1427 printk(" warning: CSR address invalid,\n");
1429 " using instead PROM address of");
1431 memcpy(dev
->dev_addr
, promaddr
, 6);
1434 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
1436 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1437 if (!is_valid_ether_addr(dev
->perm_addr
))
1438 memset(dev
->dev_addr
, 0, sizeof(dev
->dev_addr
));
1440 if (pcnet32_debug
& NETIF_MSG_PROBE
) {
1441 for (i
= 0; i
< 6; i
++)
1442 printk(" %2.2x", dev
->dev_addr
[i
]);
1444 /* Version 0x2623 and 0x2624 */
1445 if (((chip_version
+ 1) & 0xfffe) == 0x2624) {
1446 i
= a
->read_csr(ioaddr
, 80) & 0x0C00; /* Check tx_start_pt */
1447 printk("\n" KERN_INFO
" tx_start_pt(0x%04x):", i
);
1450 printk(" 20 bytes,");
1453 printk(" 64 bytes,");
1456 printk(" 128 bytes,");
1459 printk("~220 bytes,");
1462 i
= a
->read_bcr(ioaddr
, 18); /* Check Burst/Bus control */
1463 printk(" BCR18(%x):", i
& 0xffff);
1465 printk("BurstWrEn ");
1467 printk("BurstRdEn ");
1472 i
= a
->read_bcr(ioaddr
, 25);
1473 printk("\n" KERN_INFO
" SRAMSIZE=0x%04x,", i
<< 8);
1474 i
= a
->read_bcr(ioaddr
, 26);
1475 printk(" SRAM_BND=0x%04x,", i
<< 8);
1476 i
= a
->read_bcr(ioaddr
, 27);
1482 dev
->base_addr
= ioaddr
;
1483 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1485 pci_alloc_consistent(pdev
, sizeof(*lp
), &lp_dma_addr
)) == NULL
) {
1486 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1488 "Consistent memory allocation failed.\n");
1490 goto err_free_netdev
;
1493 memset(lp
, 0, sizeof(*lp
));
1494 lp
->dma_addr
= lp_dma_addr
;
1497 spin_lock_init(&lp
->lock
);
1499 SET_MODULE_OWNER(dev
);
1500 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1502 lp
->name
= chipname
;
1503 lp
->shared_irq
= shared
;
1504 lp
->tx_ring_size
= TX_RING_SIZE
; /* default tx ring size */
1505 lp
->rx_ring_size
= RX_RING_SIZE
; /* default rx ring size */
1506 lp
->tx_mod_mask
= lp
->tx_ring_size
- 1;
1507 lp
->rx_mod_mask
= lp
->rx_ring_size
- 1;
1508 lp
->tx_len_bits
= (PCNET32_LOG_TX_BUFFERS
<< 12);
1509 lp
->rx_len_bits
= (PCNET32_LOG_RX_BUFFERS
<< 4);
1510 lp
->mii_if
.full_duplex
= fdx
;
1511 lp
->mii_if
.phy_id_mask
= 0x1f;
1512 lp
->mii_if
.reg_num_mask
= 0x1f;
1513 lp
->dxsuflo
= dxsuflo
;
1515 lp
->msg_enable
= pcnet32_debug
;
1516 if ((cards_found
>= MAX_UNITS
)
1517 || (options
[cards_found
] > sizeof(options_mapping
)))
1518 lp
->options
= PCNET32_PORT_ASEL
;
1520 lp
->options
= options_mapping
[options
[cards_found
]];
1521 lp
->mii_if
.dev
= dev
;
1522 lp
->mii_if
.mdio_read
= mdio_read
;
1523 lp
->mii_if
.mdio_write
= mdio_write
;
1525 if (fdx
&& !(lp
->options
& PCNET32_PORT_ASEL
) &&
1526 ((cards_found
>= MAX_UNITS
) || full_duplex
[cards_found
]))
1527 lp
->options
|= PCNET32_PORT_FD
;
1530 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1531 printk(KERN_ERR PFX
"No access methods\n");
1533 goto err_free_consistent
;
1537 /* prior to register_netdev, dev->name is not yet correct */
1538 if (pcnet32_alloc_ring(dev
, pci_name(lp
->pci_dev
))) {
1542 /* detect special T1/E1 WAN card by checking for MAC address */
1543 if (dev
->dev_addr
[0] == 0x00 && dev
->dev_addr
[1] == 0xe0
1544 && dev
->dev_addr
[2] == 0x75)
1545 lp
->options
= PCNET32_PORT_FD
| PCNET32_PORT_GPSI
;
1547 lp
->init_block
.mode
= le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1548 lp
->init_block
.tlen_rlen
=
1549 le16_to_cpu(lp
->tx_len_bits
| lp
->rx_len_bits
);
1550 for (i
= 0; i
< 6; i
++)
1551 lp
->init_block
.phys_addr
[i
] = dev
->dev_addr
[i
];
1552 lp
->init_block
.filter
[0] = 0x00000000;
1553 lp
->init_block
.filter
[1] = 0x00000000;
1554 lp
->init_block
.rx_ring
= (u32
) le32_to_cpu(lp
->rx_ring_dma_addr
);
1555 lp
->init_block
.tx_ring
= (u32
) le32_to_cpu(lp
->tx_ring_dma_addr
);
1557 /* switch pcnet32 to 32bit mode */
1558 a
->write_bcr(ioaddr
, 20, 2);
1560 a
->write_csr(ioaddr
, 1, (lp
->dma_addr
+ offsetof(struct pcnet32_private
,
1561 init_block
)) & 0xffff);
1562 a
->write_csr(ioaddr
, 2, (lp
->dma_addr
+ offsetof(struct pcnet32_private
,
1563 init_block
)) >> 16);
1565 if (pdev
) { /* use the IRQ provided by PCI */
1566 dev
->irq
= pdev
->irq
;
1567 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1568 printk(" assigned IRQ %d.\n", dev
->irq
);
1570 unsigned long irq_mask
= probe_irq_on();
1573 * To auto-IRQ we enable the initialization-done and DMA error
1574 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1577 /* Trigger an initialization just for the interrupt. */
1578 a
->write_csr(ioaddr
, 0, 0x41);
1581 dev
->irq
= probe_irq_off(irq_mask
);
1583 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1584 printk(", failed to detect IRQ line.\n");
1588 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1589 printk(", probed IRQ %d.\n", dev
->irq
);
1592 /* Set the mii phy_id so that we can query the link state */
1594 /* lp->phycount and lp->phymask are set to 0 by memset above */
1596 lp
->mii_if
.phy_id
= ((lp
->a
.read_bcr(ioaddr
, 33)) >> 5) & 0x1f;
1598 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
1599 unsigned short id1
, id2
;
1601 id1
= mdio_read(dev
, i
, MII_PHYSID1
);
1604 id2
= mdio_read(dev
, i
, MII_PHYSID2
);
1607 if (i
== 31 && ((chip_version
+ 1) & 0xfffe) == 0x2624)
1608 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1610 lp
->phymask
|= (1 << i
);
1611 lp
->mii_if
.phy_id
= i
;
1612 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1613 printk(KERN_INFO PFX
1614 "Found PHY %04x:%04x at address %d.\n",
1617 lp
->a
.write_bcr(ioaddr
, 33, (lp
->mii_if
.phy_id
) << 5);
1618 if (lp
->phycount
> 1) {
1619 lp
->options
|= PCNET32_PORT_MII
;
1623 init_timer(&lp
->watchdog_timer
);
1624 lp
->watchdog_timer
.data
= (unsigned long)dev
;
1625 lp
->watchdog_timer
.function
= (void *)&pcnet32_watchdog
;
1627 /* The PCNET32-specific entries in the device structure. */
1628 dev
->open
= &pcnet32_open
;
1629 dev
->hard_start_xmit
= &pcnet32_start_xmit
;
1630 dev
->stop
= &pcnet32_close
;
1631 dev
->get_stats
= &pcnet32_get_stats
;
1632 dev
->set_multicast_list
= &pcnet32_set_multicast_list
;
1633 dev
->do_ioctl
= &pcnet32_ioctl
;
1634 dev
->ethtool_ops
= &pcnet32_ethtool_ops
;
1635 dev
->tx_timeout
= pcnet32_tx_timeout
;
1636 dev
->watchdog_timeo
= (5 * HZ
);
1638 #ifdef CONFIG_NET_POLL_CONTROLLER
1639 dev
->poll_controller
= pcnet32_poll_controller
;
1642 /* Fill in the generic fields of the device structure. */
1643 if (register_netdev(dev
))
1647 pci_set_drvdata(pdev
, dev
);
1649 lp
->next
= pcnet32_dev
;
1653 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1654 printk(KERN_INFO
"%s: registered as %s\n", dev
->name
, lp
->name
);
1657 /* enable LED writes */
1658 a
->write_bcr(ioaddr
, 2, a
->read_bcr(ioaddr
, 2) | 0x1000);
1663 pcnet32_free_ring(dev
);
1664 err_free_consistent
:
1665 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
), lp
, lp
->dma_addr
);
1669 release_region(ioaddr
, PCNET32_TOTAL_SIZE
);
1673 /* if any allocation fails, caller must also call pcnet32_free_ring */
1674 static int pcnet32_alloc_ring(struct net_device
*dev
, char *name
)
1676 struct pcnet32_private
*lp
= dev
->priv
;
1678 lp
->tx_ring
= pci_alloc_consistent(lp
->pci_dev
,
1679 sizeof(struct pcnet32_tx_head
) *
1681 &lp
->tx_ring_dma_addr
);
1682 if (lp
->tx_ring
== NULL
) {
1683 if (netif_msg_drv(lp
))
1684 printk("\n" KERN_ERR PFX
1685 "%s: Consistent memory allocation failed.\n",
1690 lp
->rx_ring
= pci_alloc_consistent(lp
->pci_dev
,
1691 sizeof(struct pcnet32_rx_head
) *
1693 &lp
->rx_ring_dma_addr
);
1694 if (lp
->rx_ring
== NULL
) {
1695 if (netif_msg_drv(lp
))
1696 printk("\n" KERN_ERR PFX
1697 "%s: Consistent memory allocation failed.\n",
1702 lp
->tx_dma_addr
= kcalloc(lp
->tx_ring_size
, sizeof(dma_addr_t
),
1704 if (!lp
->tx_dma_addr
) {
1705 if (netif_msg_drv(lp
))
1706 printk("\n" KERN_ERR PFX
1707 "%s: Memory allocation failed.\n", name
);
1711 lp
->rx_dma_addr
= kcalloc(lp
->rx_ring_size
, sizeof(dma_addr_t
),
1713 if (!lp
->rx_dma_addr
) {
1714 if (netif_msg_drv(lp
))
1715 printk("\n" KERN_ERR PFX
1716 "%s: Memory allocation failed.\n", name
);
1720 lp
->tx_skbuff
= kcalloc(lp
->tx_ring_size
, sizeof(struct sk_buff
*),
1722 if (!lp
->tx_skbuff
) {
1723 if (netif_msg_drv(lp
))
1724 printk("\n" KERN_ERR PFX
1725 "%s: Memory allocation failed.\n", name
);
1729 lp
->rx_skbuff
= kcalloc(lp
->rx_ring_size
, sizeof(struct sk_buff
*),
1731 if (!lp
->rx_skbuff
) {
1732 if (netif_msg_drv(lp
))
1733 printk("\n" KERN_ERR PFX
1734 "%s: Memory allocation failed.\n", name
);
1741 static void pcnet32_free_ring(struct net_device
*dev
)
1743 struct pcnet32_private
*lp
= dev
->priv
;
1745 kfree(lp
->tx_skbuff
);
1746 lp
->tx_skbuff
= NULL
;
1748 kfree(lp
->rx_skbuff
);
1749 lp
->rx_skbuff
= NULL
;
1751 kfree(lp
->tx_dma_addr
);
1752 lp
->tx_dma_addr
= NULL
;
1754 kfree(lp
->rx_dma_addr
);
1755 lp
->rx_dma_addr
= NULL
;
1758 pci_free_consistent(lp
->pci_dev
,
1759 sizeof(struct pcnet32_tx_head
) *
1760 lp
->tx_ring_size
, lp
->tx_ring
,
1761 lp
->tx_ring_dma_addr
);
1766 pci_free_consistent(lp
->pci_dev
,
1767 sizeof(struct pcnet32_rx_head
) *
1768 lp
->rx_ring_size
, lp
->rx_ring
,
1769 lp
->rx_ring_dma_addr
);
1774 static int pcnet32_open(struct net_device
*dev
)
1776 struct pcnet32_private
*lp
= dev
->priv
;
1777 unsigned long ioaddr
= dev
->base_addr
;
1781 unsigned long flags
;
1783 if (request_irq(dev
->irq
, &pcnet32_interrupt
,
1784 lp
->shared_irq
? IRQF_SHARED
: 0, dev
->name
,
1789 spin_lock_irqsave(&lp
->lock
, flags
);
1790 /* Check for a valid station address */
1791 if (!is_valid_ether_addr(dev
->dev_addr
)) {
1796 /* Reset the PCNET32 */
1797 lp
->a
.reset(ioaddr
);
1799 /* switch pcnet32 to 32bit mode */
1800 lp
->a
.write_bcr(ioaddr
, 20, 2);
1802 if (netif_msg_ifup(lp
))
1804 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
1805 dev
->name
, dev
->irq
, (u32
) (lp
->tx_ring_dma_addr
),
1806 (u32
) (lp
->rx_ring_dma_addr
),
1807 (u32
) (lp
->dma_addr
+
1808 offsetof(struct pcnet32_private
, init_block
)));
1810 /* set/reset autoselect bit */
1811 val
= lp
->a
.read_bcr(ioaddr
, 2) & ~2;
1812 if (lp
->options
& PCNET32_PORT_ASEL
)
1814 lp
->a
.write_bcr(ioaddr
, 2, val
);
1816 /* handle full duplex setting */
1817 if (lp
->mii_if
.full_duplex
) {
1818 val
= lp
->a
.read_bcr(ioaddr
, 9) & ~3;
1819 if (lp
->options
& PCNET32_PORT_FD
) {
1821 if (lp
->options
== (PCNET32_PORT_FD
| PCNET32_PORT_AUI
))
1823 } else if (lp
->options
& PCNET32_PORT_ASEL
) {
1824 /* workaround of xSeries250, turn on for 79C975 only */
1825 i
= ((lp
->a
.read_csr(ioaddr
, 88) |
1827 read_csr(ioaddr
, 89) << 16)) >> 12) & 0xffff;
1831 lp
->a
.write_bcr(ioaddr
, 9, val
);
1834 /* set/reset GPSI bit in test register */
1835 val
= lp
->a
.read_csr(ioaddr
, 124) & ~0x10;
1836 if ((lp
->options
& PCNET32_PORT_PORTSEL
) == PCNET32_PORT_GPSI
)
1838 lp
->a
.write_csr(ioaddr
, 124, val
);
1840 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
1841 if (lp
->pci_dev
->subsystem_vendor
== PCI_VENDOR_ID_AT
&&
1842 (lp
->pci_dev
->subsystem_device
== PCI_SUBDEVICE_ID_AT_2700FX
||
1843 lp
->pci_dev
->subsystem_device
== PCI_SUBDEVICE_ID_AT_2701FX
)) {
1844 if (lp
->options
& PCNET32_PORT_ASEL
) {
1845 lp
->options
= PCNET32_PORT_FD
| PCNET32_PORT_100
;
1846 if (netif_msg_link(lp
))
1848 "%s: Setting 100Mb-Full Duplex.\n",
1852 if (lp
->phycount
< 2) {
1854 * 24 Jun 2004 according AMD, in order to change the PHY,
1855 * DANAS (or DISPM for 79C976) must be set; then select the speed,
1856 * duplex, and/or enable auto negotiation, and clear DANAS
1858 if (lp
->mii
&& !(lp
->options
& PCNET32_PORT_ASEL
)) {
1859 lp
->a
.write_bcr(ioaddr
, 32,
1860 lp
->a
.read_bcr(ioaddr
, 32) | 0x0080);
1861 /* disable Auto Negotiation, set 10Mpbs, HD */
1862 val
= lp
->a
.read_bcr(ioaddr
, 32) & ~0xb8;
1863 if (lp
->options
& PCNET32_PORT_FD
)
1865 if (lp
->options
& PCNET32_PORT_100
)
1867 lp
->a
.write_bcr(ioaddr
, 32, val
);
1869 if (lp
->options
& PCNET32_PORT_ASEL
) {
1870 lp
->a
.write_bcr(ioaddr
, 32,
1871 lp
->a
.read_bcr(ioaddr
,
1873 /* enable auto negotiate, setup, disable fd */
1874 val
= lp
->a
.read_bcr(ioaddr
, 32) & ~0x98;
1876 lp
->a
.write_bcr(ioaddr
, 32, val
);
1883 struct ethtool_cmd ecmd
;
1886 * There is really no good other way to handle multiple PHYs
1887 * other than turning off all automatics
1889 val
= lp
->a
.read_bcr(ioaddr
, 2);
1890 lp
->a
.write_bcr(ioaddr
, 2, val
& ~2);
1891 val
= lp
->a
.read_bcr(ioaddr
, 32);
1892 lp
->a
.write_bcr(ioaddr
, 32, val
& ~(1 << 7)); /* stop MII manager */
1894 if (!(lp
->options
& PCNET32_PORT_ASEL
)) {
1896 ecmd
.port
= PORT_MII
;
1897 ecmd
.transceiver
= XCVR_INTERNAL
;
1898 ecmd
.autoneg
= AUTONEG_DISABLE
;
1901 options
& PCNET32_PORT_100
? SPEED_100
: SPEED_10
;
1902 bcr9
= lp
->a
.read_bcr(ioaddr
, 9);
1904 if (lp
->options
& PCNET32_PORT_FD
) {
1905 ecmd
.duplex
= DUPLEX_FULL
;
1908 ecmd
.duplex
= DUPLEX_HALF
;
1911 lp
->a
.write_bcr(ioaddr
, 9, bcr9
);
1914 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
1915 if (lp
->phymask
& (1 << i
)) {
1916 /* isolate all but the first PHY */
1917 bmcr
= mdio_read(dev
, i
, MII_BMCR
);
1918 if (first_phy
== -1) {
1920 mdio_write(dev
, i
, MII_BMCR
,
1921 bmcr
& ~BMCR_ISOLATE
);
1923 mdio_write(dev
, i
, MII_BMCR
,
1924 bmcr
| BMCR_ISOLATE
);
1926 /* use mii_ethtool_sset to setup PHY */
1927 lp
->mii_if
.phy_id
= i
;
1928 ecmd
.phy_address
= i
;
1929 if (lp
->options
& PCNET32_PORT_ASEL
) {
1930 mii_ethtool_gset(&lp
->mii_if
, &ecmd
);
1931 ecmd
.autoneg
= AUTONEG_ENABLE
;
1933 mii_ethtool_sset(&lp
->mii_if
, &ecmd
);
1936 lp
->mii_if
.phy_id
= first_phy
;
1937 if (netif_msg_link(lp
))
1938 printk(KERN_INFO
"%s: Using PHY number %d.\n",
1939 dev
->name
, first_phy
);
1943 if (lp
->dxsuflo
) { /* Disable transmit stop on underflow */
1944 val
= lp
->a
.read_csr(ioaddr
, 3);
1946 lp
->a
.write_csr(ioaddr
, 3, val
);
1950 lp
->init_block
.mode
=
1951 le16_to_cpu((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
1952 pcnet32_load_multicast(dev
);
1954 if (pcnet32_init_ring(dev
)) {
1959 /* Re-initialize the PCNET32, and start it when done. */
1960 lp
->a
.write_csr(ioaddr
, 1, (lp
->dma_addr
+
1961 offsetof(struct pcnet32_private
,
1962 init_block
)) & 0xffff);
1963 lp
->a
.write_csr(ioaddr
, 2,
1965 offsetof(struct pcnet32_private
, init_block
)) >> 16);
1967 lp
->a
.write_csr(ioaddr
, 4, 0x0915);
1968 lp
->a
.write_csr(ioaddr
, 0, 0x0001);
1970 netif_start_queue(dev
);
1972 /* Print the link status and start the watchdog */
1973 pcnet32_check_media(dev
, 1);
1974 mod_timer(&(lp
->watchdog_timer
), PCNET32_WATCHDOG_TIMEOUT
);
1978 if (lp
->a
.read_csr(ioaddr
, 0) & 0x0100)
1981 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
1982 * reports that doing so triggers a bug in the '974.
1984 lp
->a
.write_csr(ioaddr
, 0, 0x0042);
1986 if (netif_msg_ifup(lp
))
1988 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
1990 (u32
) (lp
->dma_addr
+
1991 offsetof(struct pcnet32_private
, init_block
)),
1992 lp
->a
.read_csr(ioaddr
, 0));
1994 spin_unlock_irqrestore(&lp
->lock
, flags
);
1996 return 0; /* Always succeed */
1999 /* free any allocated skbuffs */
2000 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
2001 lp
->rx_ring
[i
].status
= 0;
2002 if (lp
->rx_skbuff
[i
]) {
2003 pci_unmap_single(lp
->pci_dev
, lp
->rx_dma_addr
[i
],
2004 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
2005 dev_kfree_skb(lp
->rx_skbuff
[i
]);
2007 lp
->rx_skbuff
[i
] = NULL
;
2008 lp
->rx_dma_addr
[i
] = 0;
2012 * Switch back to 16bit mode to avoid problems with dumb
2013 * DOS packet driver after a warm reboot
2015 lp
->a
.write_bcr(ioaddr
, 20, 4);
2018 spin_unlock_irqrestore(&lp
->lock
, flags
);
2019 free_irq(dev
->irq
, dev
);
2024 * The LANCE has been halted for one reason or another (busmaster memory
2025 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2026 * etc.). Modern LANCE variants always reload their ring-buffer
2027 * configuration when restarted, so we must reinitialize our ring
2028 * context before restarting. As part of this reinitialization,
2029 * find all packets still on the Tx ring and pretend that they had been
2030 * sent (in effect, drop the packets on the floor) - the higher-level
2031 * protocols will time out and retransmit. It'd be better to shuffle
2032 * these skbs to a temp list and then actually re-Tx them after
2033 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2036 static void pcnet32_purge_tx_ring(struct net_device
*dev
)
2038 struct pcnet32_private
*lp
= dev
->priv
;
2041 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
2042 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
2043 wmb(); /* Make sure adapter sees owner change */
2044 if (lp
->tx_skbuff
[i
]) {
2045 pci_unmap_single(lp
->pci_dev
, lp
->tx_dma_addr
[i
],
2046 lp
->tx_skbuff
[i
]->len
,
2048 dev_kfree_skb_any(lp
->tx_skbuff
[i
]);
2050 lp
->tx_skbuff
[i
] = NULL
;
2051 lp
->tx_dma_addr
[i
] = 0;
2055 /* Initialize the PCNET32 Rx and Tx rings. */
2056 static int pcnet32_init_ring(struct net_device
*dev
)
2058 struct pcnet32_private
*lp
= dev
->priv
;
2062 lp
->cur_rx
= lp
->cur_tx
= 0;
2063 lp
->dirty_rx
= lp
->dirty_tx
= 0;
2065 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
2066 struct sk_buff
*rx_skbuff
= lp
->rx_skbuff
[i
];
2067 if (rx_skbuff
== NULL
) {
2069 (rx_skbuff
= lp
->rx_skbuff
[i
] =
2070 dev_alloc_skb(PKT_BUF_SZ
))) {
2071 /* there is not much, we can do at this point */
2072 if (pcnet32_debug
& NETIF_MSG_DRV
)
2074 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2078 skb_reserve(rx_skbuff
, 2);
2082 if (lp
->rx_dma_addr
[i
] == 0)
2083 lp
->rx_dma_addr
[i
] =
2084 pci_map_single(lp
->pci_dev
, rx_skbuff
->data
,
2085 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
2086 lp
->rx_ring
[i
].base
= (u32
) le32_to_cpu(lp
->rx_dma_addr
[i
]);
2087 lp
->rx_ring
[i
].buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
2088 wmb(); /* Make sure owner changes after all others are visible */
2089 lp
->rx_ring
[i
].status
= le16_to_cpu(0x8000);
2091 /* The Tx buffer address is filled in as needed, but we do need to clear
2092 * the upper ownership bit. */
2093 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
2094 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
2095 wmb(); /* Make sure adapter sees owner change */
2096 lp
->tx_ring
[i
].base
= 0;
2097 lp
->tx_dma_addr
[i
] = 0;
2100 lp
->init_block
.tlen_rlen
=
2101 le16_to_cpu(lp
->tx_len_bits
| lp
->rx_len_bits
);
2102 for (i
= 0; i
< 6; i
++)
2103 lp
->init_block
.phys_addr
[i
] = dev
->dev_addr
[i
];
2104 lp
->init_block
.rx_ring
= (u32
) le32_to_cpu(lp
->rx_ring_dma_addr
);
2105 lp
->init_block
.tx_ring
= (u32
) le32_to_cpu(lp
->tx_ring_dma_addr
);
2106 wmb(); /* Make sure all changes are visible */
2110 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2111 * then flush the pending transmit operations, re-initialize the ring,
2112 * and tell the chip to initialize.
2114 static void pcnet32_restart(struct net_device
*dev
, unsigned int csr0_bits
)
2116 struct pcnet32_private
*lp
= dev
->priv
;
2117 unsigned long ioaddr
= dev
->base_addr
;
2121 for (i
= 0; i
< 100; i
++)
2122 if (lp
->a
.read_csr(ioaddr
, 0) & 0x0004)
2125 if (i
>= 100 && netif_msg_drv(lp
))
2127 "%s: pcnet32_restart timed out waiting for stop.\n",
2130 pcnet32_purge_tx_ring(dev
);
2131 if (pcnet32_init_ring(dev
))
2135 lp
->a
.write_csr(ioaddr
, 0, 1);
2138 if (lp
->a
.read_csr(ioaddr
, 0) & 0x0100)
2141 lp
->a
.write_csr(ioaddr
, 0, csr0_bits
);
2144 static void pcnet32_tx_timeout(struct net_device
*dev
)
2146 struct pcnet32_private
*lp
= dev
->priv
;
2147 unsigned long ioaddr
= dev
->base_addr
, flags
;
2149 spin_lock_irqsave(&lp
->lock
, flags
);
2150 /* Transmitter timeout, serious problems. */
2151 if (pcnet32_debug
& NETIF_MSG_DRV
)
2153 "%s: transmit timed out, status %4.4x, resetting.\n",
2154 dev
->name
, lp
->a
.read_csr(ioaddr
, 0));
2155 lp
->a
.write_csr(ioaddr
, 0, 0x0004);
2156 lp
->stats
.tx_errors
++;
2157 if (netif_msg_tx_err(lp
)) {
2160 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2161 lp
->dirty_tx
, lp
->cur_tx
, lp
->tx_full
? " (full)" : "",
2163 for (i
= 0; i
< lp
->rx_ring_size
; i
++)
2164 printk("%s %08x %04x %08x %04x", i
& 1 ? "" : "\n ",
2165 le32_to_cpu(lp
->rx_ring
[i
].base
),
2166 (-le16_to_cpu(lp
->rx_ring
[i
].buf_length
)) &
2167 0xffff, le32_to_cpu(lp
->rx_ring
[i
].msg_length
),
2168 le16_to_cpu(lp
->rx_ring
[i
].status
));
2169 for (i
= 0; i
< lp
->tx_ring_size
; i
++)
2170 printk("%s %08x %04x %08x %04x", i
& 1 ? "" : "\n ",
2171 le32_to_cpu(lp
->tx_ring
[i
].base
),
2172 (-le16_to_cpu(lp
->tx_ring
[i
].length
)) & 0xffff,
2173 le32_to_cpu(lp
->tx_ring
[i
].misc
),
2174 le16_to_cpu(lp
->tx_ring
[i
].status
));
2177 pcnet32_restart(dev
, 0x0042);
2179 dev
->trans_start
= jiffies
;
2180 netif_wake_queue(dev
);
2182 spin_unlock_irqrestore(&lp
->lock
, flags
);
2185 static int pcnet32_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2187 struct pcnet32_private
*lp
= dev
->priv
;
2188 unsigned long ioaddr
= dev
->base_addr
;
2191 unsigned long flags
;
2193 spin_lock_irqsave(&lp
->lock
, flags
);
2195 if (netif_msg_tx_queued(lp
)) {
2197 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2198 dev
->name
, lp
->a
.read_csr(ioaddr
, 0));
2201 /* Default status -- will not enable Successful-TxDone
2202 * interrupt when that option is available to us.
2206 /* Fill in a Tx ring entry */
2208 /* Mask to ring buffer boundary. */
2209 entry
= lp
->cur_tx
& lp
->tx_mod_mask
;
2211 /* Caution: the write order is important here, set the status
2212 * with the "ownership" bits last. */
2214 lp
->tx_ring
[entry
].length
= le16_to_cpu(-skb
->len
);
2216 lp
->tx_ring
[entry
].misc
= 0x00000000;
2218 lp
->tx_skbuff
[entry
] = skb
;
2219 lp
->tx_dma_addr
[entry
] =
2220 pci_map_single(lp
->pci_dev
, skb
->data
, skb
->len
, PCI_DMA_TODEVICE
);
2221 lp
->tx_ring
[entry
].base
= (u32
) le32_to_cpu(lp
->tx_dma_addr
[entry
]);
2222 wmb(); /* Make sure owner changes after all others are visible */
2223 lp
->tx_ring
[entry
].status
= le16_to_cpu(status
);
2226 lp
->stats
.tx_bytes
+= skb
->len
;
2228 /* Trigger an immediate send poll. */
2229 lp
->a
.write_csr(ioaddr
, 0, 0x0048);
2231 dev
->trans_start
= jiffies
;
2233 if (lp
->tx_ring
[(entry
+ 1) & lp
->tx_mod_mask
].base
!= 0) {
2235 netif_stop_queue(dev
);
2237 spin_unlock_irqrestore(&lp
->lock
, flags
);
2241 /* The PCNET32 interrupt handler. */
2243 pcnet32_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
2245 struct net_device
*dev
= dev_id
;
2246 struct pcnet32_private
*lp
;
2247 unsigned long ioaddr
;
2249 int boguscnt
= max_interrupt_work
;
2253 if (pcnet32_debug
& NETIF_MSG_INTR
)
2254 printk(KERN_DEBUG
"%s(): irq %d for unknown device\n",
2259 ioaddr
= dev
->base_addr
;
2262 spin_lock(&lp
->lock
);
2264 rap
= lp
->a
.read_rap(ioaddr
);
2265 while ((csr0
= lp
->a
.read_csr(ioaddr
, 0)) & 0x8f00 && --boguscnt
>= 0) {
2266 if (csr0
== 0xffff) {
2267 break; /* PCMCIA remove happened */
2269 /* Acknowledge all of the current interrupt sources ASAP. */
2270 lp
->a
.write_csr(ioaddr
, 0, csr0
& ~0x004f);
2274 if (netif_msg_intr(lp
))
2276 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2277 dev
->name
, csr0
, lp
->a
.read_csr(ioaddr
, 0));
2279 if (csr0
& 0x0400) /* Rx interrupt */
2282 if (csr0
& 0x0200) { /* Tx-done interrupt */
2283 unsigned int dirty_tx
= lp
->dirty_tx
;
2286 while (dirty_tx
!= lp
->cur_tx
) {
2287 int entry
= dirty_tx
& lp
->tx_mod_mask
;
2289 (short)le16_to_cpu(lp
->tx_ring
[entry
].
2293 break; /* It still hasn't been Txed */
2295 lp
->tx_ring
[entry
].base
= 0;
2297 if (status
& 0x4000) {
2298 /* There was an major error, log it. */
2300 le32_to_cpu(lp
->tx_ring
[entry
].
2302 lp
->stats
.tx_errors
++;
2303 if (netif_msg_tx_err(lp
))
2305 "%s: Tx error status=%04x err_status=%08x\n",
2308 if (err_status
& 0x04000000)
2309 lp
->stats
.tx_aborted_errors
++;
2310 if (err_status
& 0x08000000)
2311 lp
->stats
.tx_carrier_errors
++;
2312 if (err_status
& 0x10000000)
2313 lp
->stats
.tx_window_errors
++;
2315 if (err_status
& 0x40000000) {
2316 lp
->stats
.tx_fifo_errors
++;
2317 /* Ackk! On FIFO errors the Tx unit is turned off! */
2318 /* Remove this verbosity later! */
2319 if (netif_msg_tx_err(lp
))
2321 "%s: Tx FIFO error! CSR0=%4.4x\n",
2326 if (err_status
& 0x40000000) {
2327 lp
->stats
.tx_fifo_errors
++;
2328 if (!lp
->dxsuflo
) { /* If controller doesn't recover ... */
2329 /* Ackk! On FIFO errors the Tx unit is turned off! */
2330 /* Remove this verbosity later! */
2331 if (netif_msg_tx_err
2334 "%s: Tx FIFO error! CSR0=%4.4x\n",
2343 if (status
& 0x1800)
2344 lp
->stats
.collisions
++;
2345 lp
->stats
.tx_packets
++;
2348 /* We must free the original skb */
2349 if (lp
->tx_skbuff
[entry
]) {
2350 pci_unmap_single(lp
->pci_dev
,
2351 lp
->tx_dma_addr
[entry
],
2352 lp
->tx_skbuff
[entry
]->
2353 len
, PCI_DMA_TODEVICE
);
2354 dev_kfree_skb_irq(lp
->tx_skbuff
[entry
]);
2355 lp
->tx_skbuff
[entry
] = NULL
;
2356 lp
->tx_dma_addr
[entry
] = 0;
2362 (lp
->cur_tx
- dirty_tx
) & (lp
->tx_mod_mask
+
2364 if (delta
> lp
->tx_ring_size
) {
2365 if (netif_msg_drv(lp
))
2367 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
2368 dev
->name
, dirty_tx
, lp
->cur_tx
,
2370 dirty_tx
+= lp
->tx_ring_size
;
2371 delta
-= lp
->tx_ring_size
;
2375 netif_queue_stopped(dev
) &&
2376 delta
< lp
->tx_ring_size
- 2) {
2377 /* The ring is no longer full, clear tbusy. */
2379 netif_wake_queue(dev
);
2381 lp
->dirty_tx
= dirty_tx
;
2384 /* Log misc errors. */
2386 lp
->stats
.tx_errors
++; /* Tx babble. */
2387 if (csr0
& 0x1000) {
2389 * this happens when our receive ring is full. This shouldn't
2390 * be a problem as we will see normal rx interrupts for the frames
2391 * in the receive ring. But there are some PCI chipsets (I can
2392 * reproduce this on SP3G with Intel saturn chipset) which have
2393 * sometimes problems and will fill up the receive ring with
2394 * error descriptors. In this situation we don't get a rx
2395 * interrupt, but a missed frame interrupt sooner or later.
2396 * So we try to clean up our receive ring here.
2399 lp
->stats
.rx_errors
++; /* Missed a Rx frame. */
2401 if (csr0
& 0x0800) {
2402 if (netif_msg_drv(lp
))
2404 "%s: Bus master arbitration failure, status %4.4x.\n",
2406 /* unlike for the lance, there is no restart needed */
2410 /* reset the chip to clear the error condition, then restart */
2411 lp
->a
.reset(ioaddr
);
2412 lp
->a
.write_csr(ioaddr
, 4, 0x0915);
2413 pcnet32_restart(dev
, 0x0002);
2414 netif_wake_queue(dev
);
2418 /* Set interrupt enable. */
2419 lp
->a
.write_csr(ioaddr
, 0, 0x0040);
2420 lp
->a
.write_rap(ioaddr
, rap
);
2422 if (netif_msg_intr(lp
))
2423 printk(KERN_DEBUG
"%s: exiting interrupt, csr0=%#4.4x.\n",
2424 dev
->name
, lp
->a
.read_csr(ioaddr
, 0));
2426 spin_unlock(&lp
->lock
);
2431 static int pcnet32_rx(struct net_device
*dev
)
2433 struct pcnet32_private
*lp
= dev
->priv
;
2434 int entry
= lp
->cur_rx
& lp
->rx_mod_mask
;
2435 int boguscnt
= lp
->rx_ring_size
/ 2;
2437 /* If we own the next entry, it's a new packet. Send it up. */
2438 while ((short)le16_to_cpu(lp
->rx_ring
[entry
].status
) >= 0) {
2439 int status
= (short)le16_to_cpu(lp
->rx_ring
[entry
].status
) >> 8;
2441 if (status
!= 0x03) { /* There was an error. */
2443 * There is a tricky error noted by John Murphy,
2444 * <murf@perftech.com> to Russ Nelson: Even with full-sized
2445 * buffers it's possible for a jabber packet to use two
2446 * buffers, with only the last correctly noting the error.
2448 if (status
& 0x01) /* Only count a general error at the */
2449 lp
->stats
.rx_errors
++; /* end of a packet. */
2451 lp
->stats
.rx_frame_errors
++;
2453 lp
->stats
.rx_over_errors
++;
2455 lp
->stats
.rx_crc_errors
++;
2457 lp
->stats
.rx_fifo_errors
++;
2458 lp
->rx_ring
[entry
].status
&= le16_to_cpu(0x03ff);
2460 /* Malloc up new buffer, compatible with net-2e. */
2462 (le32_to_cpu(lp
->rx_ring
[entry
].msg_length
) & 0xfff)
2464 struct sk_buff
*skb
;
2466 /* Discard oversize frames. */
2467 if (unlikely(pkt_len
> PKT_BUF_SZ
- 2)) {
2468 if (netif_msg_drv(lp
))
2470 "%s: Impossible packet size %d!\n",
2471 dev
->name
, pkt_len
);
2472 lp
->stats
.rx_errors
++;
2473 } else if (pkt_len
< 60) {
2474 if (netif_msg_rx_err(lp
))
2475 printk(KERN_ERR
"%s: Runt packet!\n",
2477 lp
->stats
.rx_errors
++;
2479 int rx_in_place
= 0;
2481 if (pkt_len
> rx_copybreak
) {
2482 struct sk_buff
*newskb
;
2485 dev_alloc_skb(PKT_BUF_SZ
))) {
2486 skb_reserve(newskb
, 2);
2487 skb
= lp
->rx_skbuff
[entry
];
2488 pci_unmap_single(lp
->pci_dev
,
2493 PCI_DMA_FROMDEVICE
);
2494 skb_put(skb
, pkt_len
);
2495 lp
->rx_skbuff
[entry
] = newskb
;
2497 lp
->rx_dma_addr
[entry
] =
2498 pci_map_single(lp
->pci_dev
,
2502 PCI_DMA_FROMDEVICE
);
2503 lp
->rx_ring
[entry
].base
=
2511 skb
= dev_alloc_skb(pkt_len
+ 2);
2516 if (netif_msg_drv(lp
))
2518 "%s: Memory squeeze, deferring packet.\n",
2520 for (i
= 0; i
< lp
->rx_ring_size
; i
++)
2530 if (i
> lp
->rx_ring_size
- 2) {
2531 lp
->stats
.rx_dropped
++;
2532 lp
->rx_ring
[entry
].status
|=
2533 le16_to_cpu(0x8000);
2534 wmb(); /* Make sure adapter sees owner change */
2541 skb_reserve(skb
, 2); /* 16 byte align */
2542 skb_put(skb
, pkt_len
); /* Make room */
2543 pci_dma_sync_single_for_cpu(lp
->pci_dev
,
2549 PCI_DMA_FROMDEVICE
);
2550 eth_copy_and_sum(skb
,
2551 (unsigned char *)(lp
->
2556 pci_dma_sync_single_for_device(lp
->
2563 PCI_DMA_FROMDEVICE
);
2565 lp
->stats
.rx_bytes
+= skb
->len
;
2566 skb
->protocol
= eth_type_trans(skb
, dev
);
2568 dev
->last_rx
= jiffies
;
2569 lp
->stats
.rx_packets
++;
2573 * The docs say that the buffer length isn't touched, but Andrew Boyd
2574 * of QNX reports that some revs of the 79C965 clear it.
2576 lp
->rx_ring
[entry
].buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
2577 wmb(); /* Make sure owner changes after all others are visible */
2578 lp
->rx_ring
[entry
].status
|= le16_to_cpu(0x8000);
2579 entry
= (++lp
->cur_rx
) & lp
->rx_mod_mask
;
2580 if (--boguscnt
<= 0)
2581 break; /* don't stay in loop forever */
2587 static int pcnet32_close(struct net_device
*dev
)
2589 unsigned long ioaddr
= dev
->base_addr
;
2590 struct pcnet32_private
*lp
= dev
->priv
;
2592 unsigned long flags
;
2594 del_timer_sync(&lp
->watchdog_timer
);
2596 netif_stop_queue(dev
);
2598 spin_lock_irqsave(&lp
->lock
, flags
);
2600 lp
->stats
.rx_missed_errors
= lp
->a
.read_csr(ioaddr
, 112);
2602 if (netif_msg_ifdown(lp
))
2604 "%s: Shutting down ethercard, status was %2.2x.\n",
2605 dev
->name
, lp
->a
.read_csr(ioaddr
, 0));
2607 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2608 lp
->a
.write_csr(ioaddr
, 0, 0x0004);
2611 * Switch back to 16bit mode to avoid problems with dumb
2612 * DOS packet driver after a warm reboot
2614 lp
->a
.write_bcr(ioaddr
, 20, 4);
2616 spin_unlock_irqrestore(&lp
->lock
, flags
);
2618 free_irq(dev
->irq
, dev
);
2620 spin_lock_irqsave(&lp
->lock
, flags
);
2622 /* free all allocated skbuffs */
2623 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
2624 lp
->rx_ring
[i
].status
= 0;
2625 wmb(); /* Make sure adapter sees owner change */
2626 if (lp
->rx_skbuff
[i
]) {
2627 pci_unmap_single(lp
->pci_dev
, lp
->rx_dma_addr
[i
],
2628 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
2629 dev_kfree_skb(lp
->rx_skbuff
[i
]);
2631 lp
->rx_skbuff
[i
] = NULL
;
2632 lp
->rx_dma_addr
[i
] = 0;
2635 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
2636 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
2637 wmb(); /* Make sure adapter sees owner change */
2638 if (lp
->tx_skbuff
[i
]) {
2639 pci_unmap_single(lp
->pci_dev
, lp
->tx_dma_addr
[i
],
2640 lp
->tx_skbuff
[i
]->len
,
2642 dev_kfree_skb(lp
->tx_skbuff
[i
]);
2644 lp
->tx_skbuff
[i
] = NULL
;
2645 lp
->tx_dma_addr
[i
] = 0;
2648 spin_unlock_irqrestore(&lp
->lock
, flags
);
2653 static struct net_device_stats
*pcnet32_get_stats(struct net_device
*dev
)
2655 struct pcnet32_private
*lp
= dev
->priv
;
2656 unsigned long ioaddr
= dev
->base_addr
;
2658 unsigned long flags
;
2660 spin_lock_irqsave(&lp
->lock
, flags
);
2661 saved_addr
= lp
->a
.read_rap(ioaddr
);
2662 lp
->stats
.rx_missed_errors
= lp
->a
.read_csr(ioaddr
, 112);
2663 lp
->a
.write_rap(ioaddr
, saved_addr
);
2664 spin_unlock_irqrestore(&lp
->lock
, flags
);
2669 /* taken from the sunlance driver, which it took from the depca driver */
2670 static void pcnet32_load_multicast(struct net_device
*dev
)
2672 struct pcnet32_private
*lp
= dev
->priv
;
2673 volatile struct pcnet32_init_block
*ib
= &lp
->init_block
;
2674 volatile u16
*mcast_table
= (u16
*) & ib
->filter
;
2675 struct dev_mc_list
*dmi
= dev
->mc_list
;
2676 unsigned long ioaddr
= dev
->base_addr
;
2681 /* set all multicast bits */
2682 if (dev
->flags
& IFF_ALLMULTI
) {
2683 ib
->filter
[0] = 0xffffffff;
2684 ib
->filter
[1] = 0xffffffff;
2685 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
, 0xffff);
2686 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+1, 0xffff);
2687 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+2, 0xffff);
2688 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+3, 0xffff);
2691 /* clear the multicast filter */
2696 for (i
= 0; i
< dev
->mc_count
; i
++) {
2697 addrs
= dmi
->dmi_addr
;
2700 /* multicast address? */
2704 crc
= ether_crc_le(6, addrs
);
2706 mcast_table
[crc
>> 4] =
2707 le16_to_cpu(le16_to_cpu(mcast_table
[crc
>> 4]) |
2708 (1 << (crc
& 0xf)));
2710 for (i
= 0; i
< 4; i
++)
2711 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+ i
,
2712 le16_to_cpu(mcast_table
[i
]));
2717 * Set or clear the multicast filter for this adaptor.
2719 static void pcnet32_set_multicast_list(struct net_device
*dev
)
2721 unsigned long ioaddr
= dev
->base_addr
, flags
;
2722 struct pcnet32_private
*lp
= dev
->priv
;
2723 int csr15
, suspended
;
2725 spin_lock_irqsave(&lp
->lock
, flags
);
2726 suspended
= pcnet32_suspend(dev
, &flags
, 0);
2727 csr15
= lp
->a
.read_csr(ioaddr
, CSR15
);
2728 if (dev
->flags
& IFF_PROMISC
) {
2729 /* Log any net taps. */
2730 if (netif_msg_hw(lp
))
2731 printk(KERN_INFO
"%s: Promiscuous mode enabled.\n",
2733 lp
->init_block
.mode
=
2734 le16_to_cpu(0x8000 | (lp
->options
& PCNET32_PORT_PORTSEL
) <<
2736 lp
->a
.write_csr(ioaddr
, CSR15
, csr15
| 0x8000);
2738 lp
->init_block
.mode
=
2739 le16_to_cpu((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
2740 lp
->a
.write_csr(ioaddr
, CSR15
, csr15
& 0x7fff);
2741 pcnet32_load_multicast(dev
);
2746 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2747 csr5
= lp
->a
.read_csr(ioaddr
, CSR5
);
2748 lp
->a
.write_csr(ioaddr
, CSR5
, csr5
& (~CSR5_SUSPEND
));
2750 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
);
2751 pcnet32_restart(dev
, CSR0_NORMAL
);
2752 netif_wake_queue(dev
);
2755 spin_unlock_irqrestore(&lp
->lock
, flags
);
2758 /* This routine assumes that the lp->lock is held */
2759 static int mdio_read(struct net_device
*dev
, int phy_id
, int reg_num
)
2761 struct pcnet32_private
*lp
= dev
->priv
;
2762 unsigned long ioaddr
= dev
->base_addr
;
2768 lp
->a
.write_bcr(ioaddr
, 33, ((phy_id
& 0x1f) << 5) | (reg_num
& 0x1f));
2769 val_out
= lp
->a
.read_bcr(ioaddr
, 34);
2774 /* This routine assumes that the lp->lock is held */
2775 static void mdio_write(struct net_device
*dev
, int phy_id
, int reg_num
, int val
)
2777 struct pcnet32_private
*lp
= dev
->priv
;
2778 unsigned long ioaddr
= dev
->base_addr
;
2783 lp
->a
.write_bcr(ioaddr
, 33, ((phy_id
& 0x1f) << 5) | (reg_num
& 0x1f));
2784 lp
->a
.write_bcr(ioaddr
, 34, val
);
2787 static int pcnet32_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2789 struct pcnet32_private
*lp
= dev
->priv
;
2791 unsigned long flags
;
2793 /* SIOC[GS]MIIxxx ioctls */
2795 spin_lock_irqsave(&lp
->lock
, flags
);
2796 rc
= generic_mii_ioctl(&lp
->mii_if
, if_mii(rq
), cmd
, NULL
);
2797 spin_unlock_irqrestore(&lp
->lock
, flags
);
2805 static int pcnet32_check_otherphy(struct net_device
*dev
)
2807 struct pcnet32_private
*lp
= dev
->priv
;
2808 struct mii_if_info mii
= lp
->mii_if
;
2812 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
2813 if (i
== lp
->mii_if
.phy_id
)
2814 continue; /* skip active phy */
2815 if (lp
->phymask
& (1 << i
)) {
2817 if (mii_link_ok(&mii
)) {
2818 /* found PHY with active link */
2819 if (netif_msg_link(lp
))
2821 "%s: Using PHY number %d.\n",
2824 /* isolate inactive phy */
2826 mdio_read(dev
, lp
->mii_if
.phy_id
, MII_BMCR
);
2827 mdio_write(dev
, lp
->mii_if
.phy_id
, MII_BMCR
,
2828 bmcr
| BMCR_ISOLATE
);
2830 /* de-isolate new phy */
2831 bmcr
= mdio_read(dev
, i
, MII_BMCR
);
2832 mdio_write(dev
, i
, MII_BMCR
,
2833 bmcr
& ~BMCR_ISOLATE
);
2835 /* set new phy address */
2836 lp
->mii_if
.phy_id
= i
;
2845 * Show the status of the media. Similar to mii_check_media however it
2846 * correctly shows the link speed for all (tested) pcnet32 variants.
2847 * Devices with no mii just report link state without speed.
2849 * Caller is assumed to hold and release the lp->lock.
2852 static void pcnet32_check_media(struct net_device
*dev
, int verbose
)
2854 struct pcnet32_private
*lp
= dev
->priv
;
2856 int prev_link
= netif_carrier_ok(dev
) ? 1 : 0;
2860 curr_link
= mii_link_ok(&lp
->mii_if
);
2862 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
2863 curr_link
= (lp
->a
.read_bcr(ioaddr
, 4) != 0xc0);
2866 if (prev_link
|| verbose
) {
2867 netif_carrier_off(dev
);
2868 if (netif_msg_link(lp
))
2869 printk(KERN_INFO
"%s: link down\n", dev
->name
);
2871 if (lp
->phycount
> 1) {
2872 curr_link
= pcnet32_check_otherphy(dev
);
2875 } else if (verbose
|| !prev_link
) {
2876 netif_carrier_on(dev
);
2878 if (netif_msg_link(lp
)) {
2879 struct ethtool_cmd ecmd
;
2880 mii_ethtool_gset(&lp
->mii_if
, &ecmd
);
2882 "%s: link up, %sMbps, %s-duplex\n",
2884 (ecmd
.speed
== SPEED_100
) ? "100" : "10",
2886 DUPLEX_FULL
) ? "full" : "half");
2888 bcr9
= lp
->a
.read_bcr(dev
->base_addr
, 9);
2889 if ((bcr9
& (1 << 0)) != lp
->mii_if
.full_duplex
) {
2890 if (lp
->mii_if
.full_duplex
)
2894 lp
->a
.write_bcr(dev
->base_addr
, 9, bcr9
);
2897 if (netif_msg_link(lp
))
2898 printk(KERN_INFO
"%s: link up\n", dev
->name
);
2904 * Check for loss of link and link establishment.
2905 * Can not use mii_check_media because it does nothing if mode is forced.
2908 static void pcnet32_watchdog(struct net_device
*dev
)
2910 struct pcnet32_private
*lp
= dev
->priv
;
2911 unsigned long flags
;
2913 /* Print the link status if it has changed */
2914 spin_lock_irqsave(&lp
->lock
, flags
);
2915 pcnet32_check_media(dev
, 0);
2916 spin_unlock_irqrestore(&lp
->lock
, flags
);
2918 mod_timer(&(lp
->watchdog_timer
), PCNET32_WATCHDOG_TIMEOUT
);
2921 static void __devexit
pcnet32_remove_one(struct pci_dev
*pdev
)
2923 struct net_device
*dev
= pci_get_drvdata(pdev
);
2926 struct pcnet32_private
*lp
= dev
->priv
;
2928 unregister_netdev(dev
);
2929 pcnet32_free_ring(dev
);
2930 release_region(dev
->base_addr
, PCNET32_TOTAL_SIZE
);
2931 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
), lp
, lp
->dma_addr
);
2933 pci_disable_device(pdev
);
2934 pci_set_drvdata(pdev
, NULL
);
2938 static struct pci_driver pcnet32_driver
= {
2940 .probe
= pcnet32_probe_pci
,
2941 .remove
= __devexit_p(pcnet32_remove_one
),
2942 .id_table
= pcnet32_pci_tbl
,
2945 /* An additional parameter that may be passed in... */
2946 static int debug
= -1;
2947 static int tx_start_pt
= -1;
2948 static int pcnet32_have_pci
;
2950 module_param(debug
, int, 0);
2951 MODULE_PARM_DESC(debug
, DRV_NAME
" debug level");
2952 module_param(max_interrupt_work
, int, 0);
2953 MODULE_PARM_DESC(max_interrupt_work
,
2954 DRV_NAME
" maximum events handled per interrupt");
2955 module_param(rx_copybreak
, int, 0);
2956 MODULE_PARM_DESC(rx_copybreak
,
2957 DRV_NAME
" copy breakpoint for copy-only-tiny-frames");
2958 module_param(tx_start_pt
, int, 0);
2959 MODULE_PARM_DESC(tx_start_pt
, DRV_NAME
" transmit start point (0-3)");
2960 module_param(pcnet32vlb
, int, 0);
2961 MODULE_PARM_DESC(pcnet32vlb
, DRV_NAME
" Vesa local bus (VLB) support (0/1)");
2962 module_param_array(options
, int, NULL
, 0);
2963 MODULE_PARM_DESC(options
, DRV_NAME
" initial option setting(s) (0-15)");
2964 module_param_array(full_duplex
, int, NULL
, 0);
2965 MODULE_PARM_DESC(full_duplex
, DRV_NAME
" full duplex setting(s) (1)");
2966 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2967 module_param_array(homepna
, int, NULL
, 0);
2968 MODULE_PARM_DESC(homepna
,
2970 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2972 MODULE_AUTHOR("Thomas Bogendoerfer");
2973 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2974 MODULE_LICENSE("GPL");
2976 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2978 static int __init
pcnet32_init_module(void)
2980 printk(KERN_INFO
"%s", version
);
2982 pcnet32_debug
= netif_msg_init(debug
, PCNET32_MSG_DEFAULT
);
2984 if ((tx_start_pt
>= 0) && (tx_start_pt
<= 3))
2985 tx_start
= tx_start_pt
;
2987 /* find the PCI devices */
2988 if (!pci_module_init(&pcnet32_driver
))
2989 pcnet32_have_pci
= 1;
2991 /* should we find any remaining VLbus devices ? */
2993 pcnet32_probe_vlbus(pcnet32_portlist
);
2995 if (cards_found
&& (pcnet32_debug
& NETIF_MSG_PROBE
))
2996 printk(KERN_INFO PFX
"%d cards_found.\n", cards_found
);
2998 return (pcnet32_have_pci
+ cards_found
) ? 0 : -ENODEV
;
3001 static void __exit
pcnet32_cleanup_module(void)
3003 struct net_device
*next_dev
;
3005 while (pcnet32_dev
) {
3006 struct pcnet32_private
*lp
= pcnet32_dev
->priv
;
3007 next_dev
= lp
->next
;
3008 unregister_netdev(pcnet32_dev
);
3009 pcnet32_free_ring(pcnet32_dev
);
3010 release_region(pcnet32_dev
->base_addr
, PCNET32_TOTAL_SIZE
);
3011 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
), lp
, lp
->dma_addr
);
3012 free_netdev(pcnet32_dev
);
3013 pcnet32_dev
= next_dev
;
3016 if (pcnet32_have_pci
)
3017 pci_unregister_driver(&pcnet32_driver
);
3020 module_init(pcnet32_init_module
);
3021 module_exit(pcnet32_cleanup_module
);