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[mirror_ubuntu-bionic-kernel.git] / drivers / net / phy / amd-xgbe-phy.c
1 /*
2 * AMD 10Gb Ethernet PHY driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 *
25 * License 2: Modified BSD
26 *
27 * Copyright (c) 2014 Advanced Micro Devices, Inc.
28 * All rights reserved.
29 *
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions are met:
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in the
36 * documentation and/or other materials provided with the distribution.
37 * * Neither the name of Advanced Micro Devices, Inc. nor the
38 * names of its contributors may be used to endorse or promote products
39 * derived from this software without specific prior written permission.
40 *
41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
47 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
48 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 */
52
53 #include <linux/kernel.h>
54 #include <linux/device.h>
55 #include <linux/platform_device.h>
56 #include <linux/string.h>
57 #include <linux/errno.h>
58 #include <linux/unistd.h>
59 #include <linux/slab.h>
60 #include <linux/interrupt.h>
61 #include <linux/init.h>
62 #include <linux/delay.h>
63 #include <linux/workqueue.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/skbuff.h>
67 #include <linux/mm.h>
68 #include <linux/module.h>
69 #include <linux/mii.h>
70 #include <linux/ethtool.h>
71 #include <linux/phy.h>
72 #include <linux/mdio.h>
73 #include <linux/io.h>
74 #include <linux/of.h>
75 #include <linux/of_platform.h>
76 #include <linux/of_device.h>
77 #include <linux/uaccess.h>
78 #include <linux/bitops.h>
79 #include <linux/property.h>
80 #include <linux/acpi.h>
81
82 MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
83 MODULE_LICENSE("Dual BSD/GPL");
84 MODULE_VERSION("1.0.0-a");
85 MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
86
87 #define XGBE_PHY_ID 0x000162d0
88 #define XGBE_PHY_MASK 0xfffffff0
89
90 #define XGBE_PHY_SPEEDSET_PROPERTY "amd,speed-set"
91 #define XGBE_PHY_BLWC_PROPERTY "amd,serdes-blwc"
92 #define XGBE_PHY_CDR_RATE_PROPERTY "amd,serdes-cdr-rate"
93 #define XGBE_PHY_PQ_SKEW_PROPERTY "amd,serdes-pq-skew"
94 #define XGBE_PHY_TX_AMP_PROPERTY "amd,serdes-tx-amp"
95 #define XGBE_PHY_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config"
96 #define XGBE_PHY_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable"
97
98 #define XGBE_PHY_SPEEDS 3
99 #define XGBE_PHY_SPEED_1000 0
100 #define XGBE_PHY_SPEED_2500 1
101 #define XGBE_PHY_SPEED_10000 2
102
103 #define XGBE_AN_INT_CMPLT 0x01
104 #define XGBE_AN_INC_LINK 0x02
105 #define XGBE_AN_PG_RCV 0x04
106 #define XGBE_AN_INT_MASK 0x07
107
108 #define XNP_MCF_NULL_MESSAGE 0x001
109 #define XNP_ACK_PROCESSED BIT(12)
110 #define XNP_MP_FORMATTED BIT(13)
111 #define XNP_NP_EXCHANGE BIT(15)
112
113 #define XGBE_PHY_RATECHANGE_COUNT 500
114
115 #define XGBE_PHY_KR_TRAINING_START 0x01
116 #define XGBE_PHY_KR_TRAINING_ENABLE 0x02
117
118 #define XGBE_PHY_FEC_ENABLE 0x01
119 #define XGBE_PHY_FEC_FORWARD 0x02
120 #define XGBE_PHY_FEC_MASK 0x03
121
122 #ifndef MDIO_PMA_10GBR_PMD_CTRL
123 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096
124 #endif
125
126 #ifndef MDIO_PMA_10GBR_FEC_ABILITY
127 #define MDIO_PMA_10GBR_FEC_ABILITY 0x00aa
128 #endif
129
130 #ifndef MDIO_PMA_10GBR_FEC_CTRL
131 #define MDIO_PMA_10GBR_FEC_CTRL 0x00ab
132 #endif
133
134 #ifndef MDIO_AN_XNP
135 #define MDIO_AN_XNP 0x0016
136 #endif
137
138 #ifndef MDIO_AN_LPX
139 #define MDIO_AN_LPX 0x0019
140 #endif
141
142 #ifndef MDIO_AN_INTMASK
143 #define MDIO_AN_INTMASK 0x8001
144 #endif
145
146 #ifndef MDIO_AN_INT
147 #define MDIO_AN_INT 0x8002
148 #endif
149
150 #ifndef MDIO_CTRL1_SPEED1G
151 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
152 #endif
153
154 /* SerDes integration register offsets */
155 #define SIR0_KR_RT_1 0x002c
156 #define SIR0_STATUS 0x0040
157 #define SIR1_SPEED 0x0000
158
159 /* SerDes integration register entry bit positions and sizes */
160 #define SIR0_KR_RT_1_RESET_INDEX 11
161 #define SIR0_KR_RT_1_RESET_WIDTH 1
162 #define SIR0_STATUS_RX_READY_INDEX 0
163 #define SIR0_STATUS_RX_READY_WIDTH 1
164 #define SIR0_STATUS_TX_READY_INDEX 8
165 #define SIR0_STATUS_TX_READY_WIDTH 1
166 #define SIR1_SPEED_CDR_RATE_INDEX 12
167 #define SIR1_SPEED_CDR_RATE_WIDTH 4
168 #define SIR1_SPEED_DATARATE_INDEX 4
169 #define SIR1_SPEED_DATARATE_WIDTH 2
170 #define SIR1_SPEED_PLLSEL_INDEX 3
171 #define SIR1_SPEED_PLLSEL_WIDTH 1
172 #define SIR1_SPEED_RATECHANGE_INDEX 6
173 #define SIR1_SPEED_RATECHANGE_WIDTH 1
174 #define SIR1_SPEED_TXAMP_INDEX 8
175 #define SIR1_SPEED_TXAMP_WIDTH 4
176 #define SIR1_SPEED_WORDMODE_INDEX 0
177 #define SIR1_SPEED_WORDMODE_WIDTH 3
178
179 #define SPEED_10000_BLWC 0
180 #define SPEED_10000_CDR 0x7
181 #define SPEED_10000_PLL 0x1
182 #define SPEED_10000_PQ 0x12
183 #define SPEED_10000_RATE 0x0
184 #define SPEED_10000_TXAMP 0xa
185 #define SPEED_10000_WORD 0x7
186 #define SPEED_10000_DFE_TAP_CONFIG 0x1
187 #define SPEED_10000_DFE_TAP_ENABLE 0x7f
188
189 #define SPEED_2500_BLWC 1
190 #define SPEED_2500_CDR 0x2
191 #define SPEED_2500_PLL 0x0
192 #define SPEED_2500_PQ 0xa
193 #define SPEED_2500_RATE 0x1
194 #define SPEED_2500_TXAMP 0xf
195 #define SPEED_2500_WORD 0x1
196 #define SPEED_2500_DFE_TAP_CONFIG 0x3
197 #define SPEED_2500_DFE_TAP_ENABLE 0x0
198
199 #define SPEED_1000_BLWC 1
200 #define SPEED_1000_CDR 0x2
201 #define SPEED_1000_PLL 0x0
202 #define SPEED_1000_PQ 0xa
203 #define SPEED_1000_RATE 0x3
204 #define SPEED_1000_TXAMP 0xf
205 #define SPEED_1000_WORD 0x1
206 #define SPEED_1000_DFE_TAP_CONFIG 0x3
207 #define SPEED_1000_DFE_TAP_ENABLE 0x0
208
209 /* SerDes RxTx register offsets */
210 #define RXTX_REG6 0x0018
211 #define RXTX_REG20 0x0050
212 #define RXTX_REG22 0x0058
213 #define RXTX_REG114 0x01c8
214 #define RXTX_REG129 0x0204
215
216 /* SerDes RxTx register entry bit positions and sizes */
217 #define RXTX_REG6_RESETB_RXD_INDEX 8
218 #define RXTX_REG6_RESETB_RXD_WIDTH 1
219 #define RXTX_REG20_BLWC_ENA_INDEX 2
220 #define RXTX_REG20_BLWC_ENA_WIDTH 1
221 #define RXTX_REG114_PQ_REG_INDEX 9
222 #define RXTX_REG114_PQ_REG_WIDTH 7
223 #define RXTX_REG129_RXDFE_CONFIG_INDEX 14
224 #define RXTX_REG129_RXDFE_CONFIG_WIDTH 2
225
226 /* Bit setting and getting macros
227 * The get macro will extract the current bit field value from within
228 * the variable
229 *
230 * The set macro will clear the current bit field value within the
231 * variable and then set the bit field of the variable to the
232 * specified value
233 */
234 #define GET_BITS(_var, _index, _width) \
235 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
236
237 #define SET_BITS(_var, _index, _width, _val) \
238 do { \
239 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
240 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
241 } while (0)
242
243 #define XSIR_GET_BITS(_var, _prefix, _field) \
244 GET_BITS((_var), \
245 _prefix##_##_field##_INDEX, \
246 _prefix##_##_field##_WIDTH)
247
248 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \
249 SET_BITS((_var), \
250 _prefix##_##_field##_INDEX, \
251 _prefix##_##_field##_WIDTH, (_val))
252
253 /* Macros for reading or writing SerDes integration registers
254 * The ioread macros will get bit fields or full values using the
255 * register definitions formed using the input names
256 *
257 * The iowrite macros will set bit fields or full values using the
258 * register definitions formed using the input names
259 */
260 #define XSIR0_IOREAD(_priv, _reg) \
261 ioread16((_priv)->sir0_regs + _reg)
262
263 #define XSIR0_IOREAD_BITS(_priv, _reg, _field) \
264 GET_BITS(XSIR0_IOREAD((_priv), _reg), \
265 _reg##_##_field##_INDEX, \
266 _reg##_##_field##_WIDTH)
267
268 #define XSIR0_IOWRITE(_priv, _reg, _val) \
269 iowrite16((_val), (_priv)->sir0_regs + _reg)
270
271 #define XSIR0_IOWRITE_BITS(_priv, _reg, _field, _val) \
272 do { \
273 u16 reg_val = XSIR0_IOREAD((_priv), _reg); \
274 SET_BITS(reg_val, \
275 _reg##_##_field##_INDEX, \
276 _reg##_##_field##_WIDTH, (_val)); \
277 XSIR0_IOWRITE((_priv), _reg, reg_val); \
278 } while (0)
279
280 #define XSIR1_IOREAD(_priv, _reg) \
281 ioread16((_priv)->sir1_regs + _reg)
282
283 #define XSIR1_IOREAD_BITS(_priv, _reg, _field) \
284 GET_BITS(XSIR1_IOREAD((_priv), _reg), \
285 _reg##_##_field##_INDEX, \
286 _reg##_##_field##_WIDTH)
287
288 #define XSIR1_IOWRITE(_priv, _reg, _val) \
289 iowrite16((_val), (_priv)->sir1_regs + _reg)
290
291 #define XSIR1_IOWRITE_BITS(_priv, _reg, _field, _val) \
292 do { \
293 u16 reg_val = XSIR1_IOREAD((_priv), _reg); \
294 SET_BITS(reg_val, \
295 _reg##_##_field##_INDEX, \
296 _reg##_##_field##_WIDTH, (_val)); \
297 XSIR1_IOWRITE((_priv), _reg, reg_val); \
298 } while (0)
299
300 /* Macros for reading or writing SerDes RxTx registers
301 * The ioread macros will get bit fields or full values using the
302 * register definitions formed using the input names
303 *
304 * The iowrite macros will set bit fields or full values using the
305 * register definitions formed using the input names
306 */
307 #define XRXTX_IOREAD(_priv, _reg) \
308 ioread16((_priv)->rxtx_regs + _reg)
309
310 #define XRXTX_IOREAD_BITS(_priv, _reg, _field) \
311 GET_BITS(XRXTX_IOREAD((_priv), _reg), \
312 _reg##_##_field##_INDEX, \
313 _reg##_##_field##_WIDTH)
314
315 #define XRXTX_IOWRITE(_priv, _reg, _val) \
316 iowrite16((_val), (_priv)->rxtx_regs + _reg)
317
318 #define XRXTX_IOWRITE_BITS(_priv, _reg, _field, _val) \
319 do { \
320 u16 reg_val = XRXTX_IOREAD((_priv), _reg); \
321 SET_BITS(reg_val, \
322 _reg##_##_field##_INDEX, \
323 _reg##_##_field##_WIDTH, (_val)); \
324 XRXTX_IOWRITE((_priv), _reg, reg_val); \
325 } while (0)
326
327 static const u32 amd_xgbe_phy_serdes_blwc[] = {
328 SPEED_1000_BLWC,
329 SPEED_2500_BLWC,
330 SPEED_10000_BLWC,
331 };
332
333 static const u32 amd_xgbe_phy_serdes_cdr_rate[] = {
334 SPEED_1000_CDR,
335 SPEED_2500_CDR,
336 SPEED_10000_CDR,
337 };
338
339 static const u32 amd_xgbe_phy_serdes_pq_skew[] = {
340 SPEED_1000_PQ,
341 SPEED_2500_PQ,
342 SPEED_10000_PQ,
343 };
344
345 static const u32 amd_xgbe_phy_serdes_tx_amp[] = {
346 SPEED_1000_TXAMP,
347 SPEED_2500_TXAMP,
348 SPEED_10000_TXAMP,
349 };
350
351 static const u32 amd_xgbe_phy_serdes_dfe_tap_cfg[] = {
352 SPEED_1000_DFE_TAP_CONFIG,
353 SPEED_2500_DFE_TAP_CONFIG,
354 SPEED_10000_DFE_TAP_CONFIG,
355 };
356
357 static const u32 amd_xgbe_phy_serdes_dfe_tap_ena[] = {
358 SPEED_1000_DFE_TAP_ENABLE,
359 SPEED_2500_DFE_TAP_ENABLE,
360 SPEED_10000_DFE_TAP_ENABLE,
361 };
362
363 enum amd_xgbe_phy_an {
364 AMD_XGBE_AN_READY = 0,
365 AMD_XGBE_AN_PAGE_RECEIVED,
366 AMD_XGBE_AN_INCOMPAT_LINK,
367 AMD_XGBE_AN_COMPLETE,
368 AMD_XGBE_AN_NO_LINK,
369 AMD_XGBE_AN_ERROR,
370 };
371
372 enum amd_xgbe_phy_rx {
373 AMD_XGBE_RX_BPA = 0,
374 AMD_XGBE_RX_XNP,
375 AMD_XGBE_RX_COMPLETE,
376 AMD_XGBE_RX_ERROR,
377 };
378
379 enum amd_xgbe_phy_mode {
380 AMD_XGBE_MODE_KR,
381 AMD_XGBE_MODE_KX,
382 };
383
384 enum amd_xgbe_phy_speedset {
385 AMD_XGBE_PHY_SPEEDSET_1000_10000 = 0,
386 AMD_XGBE_PHY_SPEEDSET_2500_10000,
387 };
388
389 struct amd_xgbe_phy_priv {
390 struct platform_device *pdev;
391 struct acpi_device *adev;
392 struct device *dev;
393
394 struct phy_device *phydev;
395
396 /* SerDes related mmio resources */
397 struct resource *rxtx_res;
398 struct resource *sir0_res;
399 struct resource *sir1_res;
400
401 /* SerDes related mmio registers */
402 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
403 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
404 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
405
406 int an_irq;
407 char an_irq_name[IFNAMSIZ + 32];
408 struct work_struct an_irq_work;
409 unsigned int an_irq_allocated;
410
411 unsigned int speed_set;
412
413 /* SerDes UEFI configurable settings.
414 * Switching between modes/speeds requires new values for some
415 * SerDes settings. The values can be supplied as device
416 * properties in array format. The first array entry is for
417 * 1GbE, second for 2.5GbE and third for 10GbE
418 */
419 u32 serdes_blwc[XGBE_PHY_SPEEDS];
420 u32 serdes_cdr_rate[XGBE_PHY_SPEEDS];
421 u32 serdes_pq_skew[XGBE_PHY_SPEEDS];
422 u32 serdes_tx_amp[XGBE_PHY_SPEEDS];
423 u32 serdes_dfe_tap_cfg[XGBE_PHY_SPEEDS];
424 u32 serdes_dfe_tap_ena[XGBE_PHY_SPEEDS];
425
426 /* Auto-negotiation state machine support */
427 struct mutex an_mutex;
428 enum amd_xgbe_phy_an an_result;
429 enum amd_xgbe_phy_an an_state;
430 enum amd_xgbe_phy_rx kr_state;
431 enum amd_xgbe_phy_rx kx_state;
432 struct work_struct an_work;
433 struct workqueue_struct *an_workqueue;
434 unsigned int an_supported;
435 unsigned int parallel_detect;
436 unsigned int fec_ability;
437
438 unsigned int lpm_ctrl; /* CTRL1 for resume */
439 };
440
441 static int amd_xgbe_an_enable_kr_training(struct phy_device *phydev)
442 {
443 int ret;
444
445 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
446 if (ret < 0)
447 return ret;
448
449 ret |= XGBE_PHY_KR_TRAINING_ENABLE;
450 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
451
452 return 0;
453 }
454
455 static int amd_xgbe_an_disable_kr_training(struct phy_device *phydev)
456 {
457 int ret;
458
459 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
460 if (ret < 0)
461 return ret;
462
463 ret &= ~XGBE_PHY_KR_TRAINING_ENABLE;
464 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
465
466 return 0;
467 }
468
469 static int amd_xgbe_phy_pcs_power_cycle(struct phy_device *phydev)
470 {
471 int ret;
472
473 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
474 if (ret < 0)
475 return ret;
476
477 ret |= MDIO_CTRL1_LPOWER;
478 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
479
480 usleep_range(75, 100);
481
482 ret &= ~MDIO_CTRL1_LPOWER;
483 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
484
485 return 0;
486 }
487
488 static void amd_xgbe_phy_serdes_start_ratechange(struct phy_device *phydev)
489 {
490 struct amd_xgbe_phy_priv *priv = phydev->priv;
491
492 /* Assert Rx and Tx ratechange */
493 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 1);
494 }
495
496 static void amd_xgbe_phy_serdes_complete_ratechange(struct phy_device *phydev)
497 {
498 struct amd_xgbe_phy_priv *priv = phydev->priv;
499 unsigned int wait;
500 u16 status;
501
502 /* Release Rx and Tx ratechange */
503 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 0);
504
505 /* Wait for Rx and Tx ready */
506 wait = XGBE_PHY_RATECHANGE_COUNT;
507 while (wait--) {
508 usleep_range(50, 75);
509
510 status = XSIR0_IOREAD(priv, SIR0_STATUS);
511 if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) &&
512 XSIR_GET_BITS(status, SIR0_STATUS, TX_READY))
513 goto rx_reset;
514 }
515
516 netdev_dbg(phydev->attached_dev, "SerDes rx/tx not ready (%#hx)\n",
517 status);
518
519 rx_reset:
520 /* Perform Rx reset for the DFE changes */
521 XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RESETB_RXD, 0);
522 XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RESETB_RXD, 1);
523 }
524
525 static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
526 {
527 struct amd_xgbe_phy_priv *priv = phydev->priv;
528 int ret;
529
530 /* Enable KR training */
531 ret = amd_xgbe_an_enable_kr_training(phydev);
532 if (ret < 0)
533 return ret;
534
535 /* Set PCS to KR/10G speed */
536 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
537 if (ret < 0)
538 return ret;
539
540 ret &= ~MDIO_PCS_CTRL2_TYPE;
541 ret |= MDIO_PCS_CTRL2_10GBR;
542 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
543
544 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
545 if (ret < 0)
546 return ret;
547
548 ret &= ~MDIO_CTRL1_SPEEDSEL;
549 ret |= MDIO_CTRL1_SPEED10G;
550 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
551
552 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
553 if (ret < 0)
554 return ret;
555
556 /* Set SerDes to 10G speed */
557 amd_xgbe_phy_serdes_start_ratechange(phydev);
558
559 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_10000_RATE);
560 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_10000_WORD);
561 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_10000_PLL);
562
563 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE,
564 priv->serdes_cdr_rate[XGBE_PHY_SPEED_10000]);
565 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP,
566 priv->serdes_tx_amp[XGBE_PHY_SPEED_10000]);
567 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA,
568 priv->serdes_blwc[XGBE_PHY_SPEED_10000]);
569 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG,
570 priv->serdes_pq_skew[XGBE_PHY_SPEED_10000]);
571 XRXTX_IOWRITE_BITS(priv, RXTX_REG129, RXDFE_CONFIG,
572 priv->serdes_dfe_tap_cfg[XGBE_PHY_SPEED_10000]);
573 XRXTX_IOWRITE(priv, RXTX_REG22,
574 priv->serdes_dfe_tap_ena[XGBE_PHY_SPEED_10000]);
575
576 amd_xgbe_phy_serdes_complete_ratechange(phydev);
577
578 return 0;
579 }
580
581 static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev)
582 {
583 struct amd_xgbe_phy_priv *priv = phydev->priv;
584 int ret;
585
586 /* Disable KR training */
587 ret = amd_xgbe_an_disable_kr_training(phydev);
588 if (ret < 0)
589 return ret;
590
591 /* Set PCS to KX/1G speed */
592 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
593 if (ret < 0)
594 return ret;
595
596 ret &= ~MDIO_PCS_CTRL2_TYPE;
597 ret |= MDIO_PCS_CTRL2_10GBX;
598 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
599
600 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
601 if (ret < 0)
602 return ret;
603
604 ret &= ~MDIO_CTRL1_SPEEDSEL;
605 ret |= MDIO_CTRL1_SPEED1G;
606 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
607
608 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
609 if (ret < 0)
610 return ret;
611
612 /* Set SerDes to 2.5G speed */
613 amd_xgbe_phy_serdes_start_ratechange(phydev);
614
615 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_2500_RATE);
616 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_2500_WORD);
617 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_2500_PLL);
618
619 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE,
620 priv->serdes_cdr_rate[XGBE_PHY_SPEED_2500]);
621 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP,
622 priv->serdes_tx_amp[XGBE_PHY_SPEED_2500]);
623 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA,
624 priv->serdes_blwc[XGBE_PHY_SPEED_2500]);
625 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG,
626 priv->serdes_pq_skew[XGBE_PHY_SPEED_2500]);
627 XRXTX_IOWRITE_BITS(priv, RXTX_REG129, RXDFE_CONFIG,
628 priv->serdes_dfe_tap_cfg[XGBE_PHY_SPEED_2500]);
629 XRXTX_IOWRITE(priv, RXTX_REG22,
630 priv->serdes_dfe_tap_ena[XGBE_PHY_SPEED_2500]);
631
632 amd_xgbe_phy_serdes_complete_ratechange(phydev);
633
634 return 0;
635 }
636
637 static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev)
638 {
639 struct amd_xgbe_phy_priv *priv = phydev->priv;
640 int ret;
641
642 /* Disable KR training */
643 ret = amd_xgbe_an_disable_kr_training(phydev);
644 if (ret < 0)
645 return ret;
646
647 /* Set PCS to KX/1G speed */
648 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
649 if (ret < 0)
650 return ret;
651
652 ret &= ~MDIO_PCS_CTRL2_TYPE;
653 ret |= MDIO_PCS_CTRL2_10GBX;
654 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
655
656 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
657 if (ret < 0)
658 return ret;
659
660 ret &= ~MDIO_CTRL1_SPEEDSEL;
661 ret |= MDIO_CTRL1_SPEED1G;
662 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
663
664 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
665 if (ret < 0)
666 return ret;
667
668 /* Set SerDes to 1G speed */
669 amd_xgbe_phy_serdes_start_ratechange(phydev);
670
671 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_1000_RATE);
672 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_1000_WORD);
673 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_1000_PLL);
674
675 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE,
676 priv->serdes_cdr_rate[XGBE_PHY_SPEED_1000]);
677 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP,
678 priv->serdes_tx_amp[XGBE_PHY_SPEED_1000]);
679 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA,
680 priv->serdes_blwc[XGBE_PHY_SPEED_1000]);
681 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG,
682 priv->serdes_pq_skew[XGBE_PHY_SPEED_1000]);
683 XRXTX_IOWRITE_BITS(priv, RXTX_REG129, RXDFE_CONFIG,
684 priv->serdes_dfe_tap_cfg[XGBE_PHY_SPEED_1000]);
685 XRXTX_IOWRITE(priv, RXTX_REG22,
686 priv->serdes_dfe_tap_ena[XGBE_PHY_SPEED_1000]);
687
688 amd_xgbe_phy_serdes_complete_ratechange(phydev);
689
690 return 0;
691 }
692
693 static int amd_xgbe_phy_cur_mode(struct phy_device *phydev,
694 enum amd_xgbe_phy_mode *mode)
695 {
696 int ret;
697
698 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
699 if (ret < 0)
700 return ret;
701
702 if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
703 *mode = AMD_XGBE_MODE_KR;
704 else
705 *mode = AMD_XGBE_MODE_KX;
706
707 return 0;
708 }
709
710 static bool amd_xgbe_phy_in_kr_mode(struct phy_device *phydev)
711 {
712 enum amd_xgbe_phy_mode mode;
713
714 if (amd_xgbe_phy_cur_mode(phydev, &mode))
715 return false;
716
717 return (mode == AMD_XGBE_MODE_KR);
718 }
719
720 static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
721 {
722 struct amd_xgbe_phy_priv *priv = phydev->priv;
723 int ret;
724
725 /* If we are in KR switch to KX, and vice-versa */
726 if (amd_xgbe_phy_in_kr_mode(phydev)) {
727 if (priv->speed_set == AMD_XGBE_PHY_SPEEDSET_1000_10000)
728 ret = amd_xgbe_phy_gmii_mode(phydev);
729 else
730 ret = amd_xgbe_phy_gmii_2500_mode(phydev);
731 } else {
732 ret = amd_xgbe_phy_xgmii_mode(phydev);
733 }
734
735 return ret;
736 }
737
738 static int amd_xgbe_phy_set_mode(struct phy_device *phydev,
739 enum amd_xgbe_phy_mode mode)
740 {
741 enum amd_xgbe_phy_mode cur_mode;
742 int ret;
743
744 ret = amd_xgbe_phy_cur_mode(phydev, &cur_mode);
745 if (ret)
746 return ret;
747
748 if (mode != cur_mode)
749 ret = amd_xgbe_phy_switch_mode(phydev);
750
751 return ret;
752 }
753
754 static int amd_xgbe_phy_set_an(struct phy_device *phydev, bool enable,
755 bool restart)
756 {
757 int ret;
758
759 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
760 if (ret < 0)
761 return ret;
762
763 ret &= ~MDIO_AN_CTRL1_ENABLE;
764
765 if (enable)
766 ret |= MDIO_AN_CTRL1_ENABLE;
767
768 if (restart)
769 ret |= MDIO_AN_CTRL1_RESTART;
770
771 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
772
773 return 0;
774 }
775
776 static int amd_xgbe_phy_restart_an(struct phy_device *phydev)
777 {
778 return amd_xgbe_phy_set_an(phydev, true, true);
779 }
780
781 static int amd_xgbe_phy_disable_an(struct phy_device *phydev)
782 {
783 return amd_xgbe_phy_set_an(phydev, false, false);
784 }
785
786 static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
787 enum amd_xgbe_phy_rx *state)
788 {
789 struct amd_xgbe_phy_priv *priv = phydev->priv;
790 int ad_reg, lp_reg, ret;
791
792 *state = AMD_XGBE_RX_COMPLETE;
793
794 /* If we're not in KR mode then we're done */
795 if (!amd_xgbe_phy_in_kr_mode(phydev))
796 return AMD_XGBE_AN_PAGE_RECEIVED;
797
798 /* Enable/Disable FEC */
799 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
800 if (ad_reg < 0)
801 return AMD_XGBE_AN_ERROR;
802
803 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 2);
804 if (lp_reg < 0)
805 return AMD_XGBE_AN_ERROR;
806
807 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL);
808 if (ret < 0)
809 return AMD_XGBE_AN_ERROR;
810
811 ret &= ~XGBE_PHY_FEC_MASK;
812 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
813 ret |= priv->fec_ability;
814
815 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL, ret);
816
817 /* Start KR training */
818 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
819 if (ret < 0)
820 return AMD_XGBE_AN_ERROR;
821
822 if (ret & XGBE_PHY_KR_TRAINING_ENABLE) {
823 XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 1);
824
825 ret |= XGBE_PHY_KR_TRAINING_START;
826 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
827 ret);
828
829 XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 0);
830 }
831
832 return AMD_XGBE_AN_PAGE_RECEIVED;
833 }
834
835 static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev,
836 enum amd_xgbe_phy_rx *state)
837 {
838 u16 msg;
839
840 *state = AMD_XGBE_RX_XNP;
841
842 msg = XNP_MCF_NULL_MESSAGE;
843 msg |= XNP_MP_FORMATTED;
844
845 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
846 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
847 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP, msg);
848
849 return AMD_XGBE_AN_PAGE_RECEIVED;
850 }
851
852 static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev,
853 enum amd_xgbe_phy_rx *state)
854 {
855 unsigned int link_support;
856 int ret, ad_reg, lp_reg;
857
858 /* Read Base Ability register 2 first */
859 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);
860 if (ret < 0)
861 return AMD_XGBE_AN_ERROR;
862
863 /* Check for a supported mode, otherwise restart in a different one */
864 link_support = amd_xgbe_phy_in_kr_mode(phydev) ? 0x80 : 0x20;
865 if (!(ret & link_support))
866 return AMD_XGBE_AN_INCOMPAT_LINK;
867
868 /* Check Extended Next Page support */
869 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
870 if (ad_reg < 0)
871 return AMD_XGBE_AN_ERROR;
872
873 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
874 if (lp_reg < 0)
875 return AMD_XGBE_AN_ERROR;
876
877 return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ?
878 amd_xgbe_an_tx_xnp(phydev, state) :
879 amd_xgbe_an_tx_training(phydev, state);
880 }
881
882 static enum amd_xgbe_phy_an amd_xgbe_an_rx_xnp(struct phy_device *phydev,
883 enum amd_xgbe_phy_rx *state)
884 {
885 int ad_reg, lp_reg;
886
887 /* Check Extended Next Page support */
888 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP);
889 if (ad_reg < 0)
890 return AMD_XGBE_AN_ERROR;
891
892 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPX);
893 if (lp_reg < 0)
894 return AMD_XGBE_AN_ERROR;
895
896 return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ?
897 amd_xgbe_an_tx_xnp(phydev, state) :
898 amd_xgbe_an_tx_training(phydev, state);
899 }
900
901 static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
902 {
903 struct amd_xgbe_phy_priv *priv = phydev->priv;
904 enum amd_xgbe_phy_rx *state;
905 int ret;
906
907 state = amd_xgbe_phy_in_kr_mode(phydev) ? &priv->kr_state
908 : &priv->kx_state;
909
910 switch (*state) {
911 case AMD_XGBE_RX_BPA:
912 ret = amd_xgbe_an_rx_bpa(phydev, state);
913 break;
914
915 case AMD_XGBE_RX_XNP:
916 ret = amd_xgbe_an_rx_xnp(phydev, state);
917 break;
918
919 default:
920 ret = AMD_XGBE_AN_ERROR;
921 }
922
923 return ret;
924 }
925
926 static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev)
927 {
928 struct amd_xgbe_phy_priv *priv = phydev->priv;
929 int ret;
930
931 /* Be sure we aren't looping trying to negotiate */
932 if (amd_xgbe_phy_in_kr_mode(phydev)) {
933 priv->kr_state = AMD_XGBE_RX_ERROR;
934
935 if (!(phydev->supported & SUPPORTED_1000baseKX_Full) &&
936 !(phydev->supported & SUPPORTED_2500baseX_Full))
937 return AMD_XGBE_AN_NO_LINK;
938
939 if (priv->kx_state != AMD_XGBE_RX_BPA)
940 return AMD_XGBE_AN_NO_LINK;
941 } else {
942 priv->kx_state = AMD_XGBE_RX_ERROR;
943
944 if (!(phydev->supported & SUPPORTED_10000baseKR_Full))
945 return AMD_XGBE_AN_NO_LINK;
946
947 if (priv->kr_state != AMD_XGBE_RX_BPA)
948 return AMD_XGBE_AN_NO_LINK;
949 }
950
951 ret = amd_xgbe_phy_disable_an(phydev);
952 if (ret)
953 return AMD_XGBE_AN_ERROR;
954
955 ret = amd_xgbe_phy_switch_mode(phydev);
956 if (ret)
957 return AMD_XGBE_AN_ERROR;
958
959 ret = amd_xgbe_phy_restart_an(phydev);
960 if (ret)
961 return AMD_XGBE_AN_ERROR;
962
963 return AMD_XGBE_AN_INCOMPAT_LINK;
964 }
965
966 static irqreturn_t amd_xgbe_an_isr(int irq, void *data)
967 {
968 struct amd_xgbe_phy_priv *priv = (struct amd_xgbe_phy_priv *)data;
969
970 /* Interrupt reason must be read and cleared outside of IRQ context */
971 disable_irq_nosync(priv->an_irq);
972
973 queue_work(priv->an_workqueue, &priv->an_irq_work);
974
975 return IRQ_HANDLED;
976 }
977
978 static void amd_xgbe_an_irq_work(struct work_struct *work)
979 {
980 struct amd_xgbe_phy_priv *priv = container_of(work,
981 struct amd_xgbe_phy_priv,
982 an_irq_work);
983
984 /* Avoid a race between enabling the IRQ and exiting the work by
985 * waiting for the work to finish and then queueing it
986 */
987 flush_work(&priv->an_work);
988 queue_work(priv->an_workqueue, &priv->an_work);
989 }
990
991 static void amd_xgbe_an_state_machine(struct work_struct *work)
992 {
993 struct amd_xgbe_phy_priv *priv = container_of(work,
994 struct amd_xgbe_phy_priv,
995 an_work);
996 struct phy_device *phydev = priv->phydev;
997 enum amd_xgbe_phy_an cur_state = priv->an_state;
998 int int_reg, int_mask;
999
1000 mutex_lock(&priv->an_mutex);
1001
1002 /* Read the interrupt */
1003 int_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT);
1004 if (!int_reg)
1005 goto out;
1006
1007 next_int:
1008 if (int_reg < 0) {
1009 priv->an_state = AMD_XGBE_AN_ERROR;
1010 int_mask = XGBE_AN_INT_MASK;
1011 } else if (int_reg & XGBE_AN_PG_RCV) {
1012 priv->an_state = AMD_XGBE_AN_PAGE_RECEIVED;
1013 int_mask = XGBE_AN_PG_RCV;
1014 } else if (int_reg & XGBE_AN_INC_LINK) {
1015 priv->an_state = AMD_XGBE_AN_INCOMPAT_LINK;
1016 int_mask = XGBE_AN_INC_LINK;
1017 } else if (int_reg & XGBE_AN_INT_CMPLT) {
1018 priv->an_state = AMD_XGBE_AN_COMPLETE;
1019 int_mask = XGBE_AN_INT_CMPLT;
1020 } else {
1021 priv->an_state = AMD_XGBE_AN_ERROR;
1022 int_mask = 0;
1023 }
1024
1025 /* Clear the interrupt to be processed */
1026 int_reg &= ~int_mask;
1027 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, int_reg);
1028
1029 priv->an_result = priv->an_state;
1030
1031 again:
1032 cur_state = priv->an_state;
1033
1034 switch (priv->an_state) {
1035 case AMD_XGBE_AN_READY:
1036 priv->an_supported = 0;
1037 break;
1038
1039 case AMD_XGBE_AN_PAGE_RECEIVED:
1040 priv->an_state = amd_xgbe_an_page_received(phydev);
1041 priv->an_supported++;
1042 break;
1043
1044 case AMD_XGBE_AN_INCOMPAT_LINK:
1045 priv->an_supported = 0;
1046 priv->parallel_detect = 0;
1047 priv->an_state = amd_xgbe_an_incompat_link(phydev);
1048 break;
1049
1050 case AMD_XGBE_AN_COMPLETE:
1051 priv->parallel_detect = priv->an_supported ? 0 : 1;
1052 netdev_dbg(phydev->attached_dev, "%s successful\n",
1053 priv->an_supported ? "Auto negotiation"
1054 : "Parallel detection");
1055 break;
1056
1057 case AMD_XGBE_AN_NO_LINK:
1058 break;
1059
1060 default:
1061 priv->an_state = AMD_XGBE_AN_ERROR;
1062 }
1063
1064 if (priv->an_state == AMD_XGBE_AN_NO_LINK) {
1065 int_reg = 0;
1066 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
1067 } else if (priv->an_state == AMD_XGBE_AN_ERROR) {
1068 netdev_err(phydev->attached_dev,
1069 "error during auto-negotiation, state=%u\n",
1070 cur_state);
1071
1072 int_reg = 0;
1073 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
1074 }
1075
1076 if (priv->an_state >= AMD_XGBE_AN_COMPLETE) {
1077 priv->an_result = priv->an_state;
1078 priv->an_state = AMD_XGBE_AN_READY;
1079 priv->kr_state = AMD_XGBE_RX_BPA;
1080 priv->kx_state = AMD_XGBE_RX_BPA;
1081 }
1082
1083 if (cur_state != priv->an_state)
1084 goto again;
1085
1086 if (int_reg)
1087 goto next_int;
1088
1089 out:
1090 enable_irq(priv->an_irq);
1091
1092 mutex_unlock(&priv->an_mutex);
1093 }
1094
1095 static int amd_xgbe_an_init(struct phy_device *phydev)
1096 {
1097 int ret;
1098
1099 /* Set up Advertisement register 3 first */
1100 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1101 if (ret < 0)
1102 return ret;
1103
1104 if (phydev->supported & SUPPORTED_10000baseR_FEC)
1105 ret |= 0xc000;
1106 else
1107 ret &= ~0xc000;
1108
1109 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret);
1110
1111 /* Set up Advertisement register 2 next */
1112 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1113 if (ret < 0)
1114 return ret;
1115
1116 if (phydev->supported & SUPPORTED_10000baseKR_Full)
1117 ret |= 0x80;
1118 else
1119 ret &= ~0x80;
1120
1121 if ((phydev->supported & SUPPORTED_1000baseKX_Full) ||
1122 (phydev->supported & SUPPORTED_2500baseX_Full))
1123 ret |= 0x20;
1124 else
1125 ret &= ~0x20;
1126
1127 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret);
1128
1129 /* Set up Advertisement register 1 last */
1130 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1131 if (ret < 0)
1132 return ret;
1133
1134 if (phydev->supported & SUPPORTED_Pause)
1135 ret |= 0x400;
1136 else
1137 ret &= ~0x400;
1138
1139 if (phydev->supported & SUPPORTED_Asym_Pause)
1140 ret |= 0x800;
1141 else
1142 ret &= ~0x800;
1143
1144 /* We don't intend to perform XNP */
1145 ret &= ~XNP_NP_EXCHANGE;
1146
1147 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret);
1148
1149 return 0;
1150 }
1151
1152 static int amd_xgbe_phy_soft_reset(struct phy_device *phydev)
1153 {
1154 int count, ret;
1155
1156 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
1157 if (ret < 0)
1158 return ret;
1159
1160 ret |= MDIO_CTRL1_RESET;
1161 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
1162
1163 count = 50;
1164 do {
1165 msleep(20);
1166 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
1167 if (ret < 0)
1168 return ret;
1169 } while ((ret & MDIO_CTRL1_RESET) && --count);
1170
1171 if (ret & MDIO_CTRL1_RESET)
1172 return -ETIMEDOUT;
1173
1174 /* Disable auto-negotiation for now */
1175 ret = amd_xgbe_phy_disable_an(phydev);
1176 if (ret < 0)
1177 return ret;
1178
1179 /* Clear auto-negotiation interrupts */
1180 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
1181
1182 return 0;
1183 }
1184
1185 static int amd_xgbe_phy_config_init(struct phy_device *phydev)
1186 {
1187 struct amd_xgbe_phy_priv *priv = phydev->priv;
1188 struct net_device *netdev = phydev->attached_dev;
1189 int ret;
1190
1191 if (!priv->an_irq_allocated) {
1192 /* Allocate the auto-negotiation workqueue and interrupt */
1193 snprintf(priv->an_irq_name, sizeof(priv->an_irq_name) - 1,
1194 "%s-pcs", netdev_name(netdev));
1195
1196 priv->an_workqueue =
1197 create_singlethread_workqueue(priv->an_irq_name);
1198 if (!priv->an_workqueue) {
1199 netdev_err(netdev, "phy workqueue creation failed\n");
1200 return -ENOMEM;
1201 }
1202
1203 ret = devm_request_irq(priv->dev, priv->an_irq,
1204 amd_xgbe_an_isr, 0, priv->an_irq_name,
1205 priv);
1206 if (ret) {
1207 netdev_err(netdev, "phy irq request failed\n");
1208 destroy_workqueue(priv->an_workqueue);
1209 return ret;
1210 }
1211
1212 priv->an_irq_allocated = 1;
1213 }
1214
1215 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_ABILITY);
1216 if (ret < 0)
1217 return ret;
1218 priv->fec_ability = ret & XGBE_PHY_FEC_MASK;
1219
1220 /* Initialize supported features */
1221 phydev->supported = SUPPORTED_Autoneg;
1222 phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1223 phydev->supported |= SUPPORTED_Backplane;
1224 phydev->supported |= SUPPORTED_10000baseKR_Full;
1225 switch (priv->speed_set) {
1226 case AMD_XGBE_PHY_SPEEDSET_1000_10000:
1227 phydev->supported |= SUPPORTED_1000baseKX_Full;
1228 break;
1229 case AMD_XGBE_PHY_SPEEDSET_2500_10000:
1230 phydev->supported |= SUPPORTED_2500baseX_Full;
1231 break;
1232 }
1233
1234 if (priv->fec_ability & XGBE_PHY_FEC_ENABLE)
1235 phydev->supported |= SUPPORTED_10000baseR_FEC;
1236
1237 phydev->advertising = phydev->supported;
1238
1239 /* Set initial mode - call the mode setting routines
1240 * directly to insure we are properly configured
1241 */
1242 if (phydev->supported & SUPPORTED_10000baseKR_Full)
1243 ret = amd_xgbe_phy_xgmii_mode(phydev);
1244 else if (phydev->supported & SUPPORTED_1000baseKX_Full)
1245 ret = amd_xgbe_phy_gmii_mode(phydev);
1246 else if (phydev->supported & SUPPORTED_2500baseX_Full)
1247 ret = amd_xgbe_phy_gmii_2500_mode(phydev);
1248 else
1249 ret = -EINVAL;
1250 if (ret < 0)
1251 return ret;
1252
1253 /* Set up advertisement registers based on current settings */
1254 ret = amd_xgbe_an_init(phydev);
1255 if (ret)
1256 return ret;
1257
1258 /* Enable auto-negotiation interrupts */
1259 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07);
1260
1261 return 0;
1262 }
1263
1264 static int amd_xgbe_phy_setup_forced(struct phy_device *phydev)
1265 {
1266 int ret;
1267
1268 /* Disable auto-negotiation */
1269 ret = amd_xgbe_phy_disable_an(phydev);
1270 if (ret < 0)
1271 return ret;
1272
1273 /* Validate/Set specified speed */
1274 switch (phydev->speed) {
1275 case SPEED_10000:
1276 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
1277 break;
1278
1279 case SPEED_2500:
1280 case SPEED_1000:
1281 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
1282 break;
1283
1284 default:
1285 ret = -EINVAL;
1286 }
1287
1288 if (ret < 0)
1289 return ret;
1290
1291 /* Validate duplex mode */
1292 if (phydev->duplex != DUPLEX_FULL)
1293 return -EINVAL;
1294
1295 phydev->pause = 0;
1296 phydev->asym_pause = 0;
1297
1298 return 0;
1299 }
1300
1301 static int __amd_xgbe_phy_config_aneg(struct phy_device *phydev)
1302 {
1303 struct amd_xgbe_phy_priv *priv = phydev->priv;
1304 u32 mmd_mask = phydev->c45_ids.devices_in_package;
1305 int ret;
1306
1307 if (phydev->autoneg != AUTONEG_ENABLE)
1308 return amd_xgbe_phy_setup_forced(phydev);
1309
1310 /* Make sure we have the AN MMD present */
1311 if (!(mmd_mask & MDIO_DEVS_AN))
1312 return -EINVAL;
1313
1314 /* Disable auto-negotiation interrupt */
1315 disable_irq(priv->an_irq);
1316
1317 /* Start auto-negotiation in a supported mode */
1318 if (phydev->supported & SUPPORTED_10000baseKR_Full)
1319 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
1320 else if ((phydev->supported & SUPPORTED_1000baseKX_Full) ||
1321 (phydev->supported & SUPPORTED_2500baseX_Full))
1322 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
1323 else
1324 ret = -EINVAL;
1325 if (ret < 0) {
1326 enable_irq(priv->an_irq);
1327 return ret;
1328 }
1329
1330 /* Disable and stop any in progress auto-negotiation */
1331 ret = amd_xgbe_phy_disable_an(phydev);
1332 if (ret < 0)
1333 return ret;
1334
1335 /* Clear any auto-negotitation interrupts */
1336 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
1337
1338 priv->an_result = AMD_XGBE_AN_READY;
1339 priv->an_state = AMD_XGBE_AN_READY;
1340 priv->kr_state = AMD_XGBE_RX_BPA;
1341 priv->kx_state = AMD_XGBE_RX_BPA;
1342
1343 /* Re-enable auto-negotiation interrupt */
1344 enable_irq(priv->an_irq);
1345
1346 /* Set up advertisement registers based on current settings */
1347 ret = amd_xgbe_an_init(phydev);
1348 if (ret)
1349 return ret;
1350
1351 /* Enable and start auto-negotiation */
1352 return amd_xgbe_phy_restart_an(phydev);
1353 }
1354
1355 static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
1356 {
1357 struct amd_xgbe_phy_priv *priv = phydev->priv;
1358 int ret;
1359
1360 mutex_lock(&priv->an_mutex);
1361
1362 ret = __amd_xgbe_phy_config_aneg(phydev);
1363
1364 mutex_unlock(&priv->an_mutex);
1365
1366 return ret;
1367 }
1368
1369 static int amd_xgbe_phy_aneg_done(struct phy_device *phydev)
1370 {
1371 struct amd_xgbe_phy_priv *priv = phydev->priv;
1372
1373 return (priv->an_result == AMD_XGBE_AN_COMPLETE);
1374 }
1375
1376 static int amd_xgbe_phy_update_link(struct phy_device *phydev)
1377 {
1378 struct amd_xgbe_phy_priv *priv = phydev->priv;
1379 int ret;
1380
1381 /* If we're doing auto-negotiation don't report link down */
1382 if (priv->an_state != AMD_XGBE_AN_READY) {
1383 phydev->link = 1;
1384 return 0;
1385 }
1386
1387 /* Link status is latched low, so read once to clear
1388 * and then read again to get current state
1389 */
1390 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
1391 if (ret < 0)
1392 return ret;
1393
1394 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
1395 if (ret < 0)
1396 return ret;
1397
1398 phydev->link = (ret & MDIO_STAT1_LSTATUS) ? 1 : 0;
1399
1400 return 0;
1401 }
1402
1403 static int amd_xgbe_phy_read_status(struct phy_device *phydev)
1404 {
1405 struct amd_xgbe_phy_priv *priv = phydev->priv;
1406 u32 mmd_mask = phydev->c45_ids.devices_in_package;
1407 int ret, ad_ret, lp_ret;
1408
1409 ret = amd_xgbe_phy_update_link(phydev);
1410 if (ret)
1411 return ret;
1412
1413 if ((phydev->autoneg == AUTONEG_ENABLE) &&
1414 !priv->parallel_detect) {
1415 if (!(mmd_mask & MDIO_DEVS_AN))
1416 return -EINVAL;
1417
1418 if (!amd_xgbe_phy_aneg_done(phydev))
1419 return 0;
1420
1421 /* Compare Advertisement and Link Partner register 1 */
1422 ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1423 if (ad_ret < 0)
1424 return ad_ret;
1425 lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
1426 if (lp_ret < 0)
1427 return lp_ret;
1428
1429 ad_ret &= lp_ret;
1430 phydev->pause = (ad_ret & 0x400) ? 1 : 0;
1431 phydev->asym_pause = (ad_ret & 0x800) ? 1 : 0;
1432
1433 /* Compare Advertisement and Link Partner register 2 */
1434 ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN,
1435 MDIO_AN_ADVERTISE + 1);
1436 if (ad_ret < 0)
1437 return ad_ret;
1438 lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1439 if (lp_ret < 0)
1440 return lp_ret;
1441
1442 ad_ret &= lp_ret;
1443 if (ad_ret & 0x80) {
1444 phydev->speed = SPEED_10000;
1445 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
1446 if (ret)
1447 return ret;
1448 } else {
1449 switch (priv->speed_set) {
1450 case AMD_XGBE_PHY_SPEEDSET_1000_10000:
1451 phydev->speed = SPEED_1000;
1452 break;
1453
1454 case AMD_XGBE_PHY_SPEEDSET_2500_10000:
1455 phydev->speed = SPEED_2500;
1456 break;
1457 }
1458
1459 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
1460 if (ret)
1461 return ret;
1462 }
1463
1464 phydev->duplex = DUPLEX_FULL;
1465 } else {
1466 if (amd_xgbe_phy_in_kr_mode(phydev)) {
1467 phydev->speed = SPEED_10000;
1468 } else {
1469 switch (priv->speed_set) {
1470 case AMD_XGBE_PHY_SPEEDSET_1000_10000:
1471 phydev->speed = SPEED_1000;
1472 break;
1473
1474 case AMD_XGBE_PHY_SPEEDSET_2500_10000:
1475 phydev->speed = SPEED_2500;
1476 break;
1477 }
1478 }
1479 phydev->duplex = DUPLEX_FULL;
1480 phydev->pause = 0;
1481 phydev->asym_pause = 0;
1482 }
1483
1484 return 0;
1485 }
1486
1487 static int amd_xgbe_phy_suspend(struct phy_device *phydev)
1488 {
1489 struct amd_xgbe_phy_priv *priv = phydev->priv;
1490 int ret;
1491
1492 mutex_lock(&phydev->lock);
1493
1494 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
1495 if (ret < 0)
1496 goto unlock;
1497
1498 priv->lpm_ctrl = ret;
1499
1500 ret |= MDIO_CTRL1_LPOWER;
1501 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
1502
1503 ret = 0;
1504
1505 unlock:
1506 mutex_unlock(&phydev->lock);
1507
1508 return ret;
1509 }
1510
1511 static int amd_xgbe_phy_resume(struct phy_device *phydev)
1512 {
1513 struct amd_xgbe_phy_priv *priv = phydev->priv;
1514
1515 mutex_lock(&phydev->lock);
1516
1517 priv->lpm_ctrl &= ~MDIO_CTRL1_LPOWER;
1518 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, priv->lpm_ctrl);
1519
1520 mutex_unlock(&phydev->lock);
1521
1522 return 0;
1523 }
1524
1525 static unsigned int amd_xgbe_phy_resource_count(struct platform_device *pdev,
1526 unsigned int type)
1527 {
1528 unsigned int count;
1529 int i;
1530
1531 for (i = 0, count = 0; i < pdev->num_resources; i++) {
1532 struct resource *r = &pdev->resource[i];
1533
1534 if (type == resource_type(r))
1535 count++;
1536 }
1537
1538 return count;
1539 }
1540
1541 static int amd_xgbe_phy_probe(struct phy_device *phydev)
1542 {
1543 struct amd_xgbe_phy_priv *priv;
1544 struct platform_device *phy_pdev;
1545 struct device *dev, *phy_dev;
1546 unsigned int phy_resnum, phy_irqnum;
1547 int ret;
1548
1549 if (!phydev->bus || !phydev->bus->parent)
1550 return -EINVAL;
1551
1552 dev = phydev->bus->parent;
1553
1554 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1555 if (!priv)
1556 return -ENOMEM;
1557
1558 priv->pdev = to_platform_device(dev);
1559 priv->adev = ACPI_COMPANION(dev);
1560 priv->dev = dev;
1561 priv->phydev = phydev;
1562 mutex_init(&priv->an_mutex);
1563 INIT_WORK(&priv->an_irq_work, amd_xgbe_an_irq_work);
1564 INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine);
1565
1566 if (!priv->adev || acpi_disabled) {
1567 struct device_node *bus_node;
1568 struct device_node *phy_node;
1569
1570 bus_node = priv->dev->of_node;
1571 phy_node = of_parse_phandle(bus_node, "phy-handle", 0);
1572 if (!phy_node) {
1573 dev_err(dev, "unable to parse phy-handle\n");
1574 ret = -EINVAL;
1575 goto err_priv;
1576 }
1577
1578 phy_pdev = of_find_device_by_node(phy_node);
1579 of_node_put(phy_node);
1580
1581 if (!phy_pdev) {
1582 dev_err(dev, "unable to obtain phy device\n");
1583 ret = -EINVAL;
1584 goto err_priv;
1585 }
1586
1587 phy_resnum = 0;
1588 phy_irqnum = 0;
1589 } else {
1590 /* In ACPI, the XGBE and PHY resources are the grouped
1591 * together with the PHY resources at the end
1592 */
1593 phy_pdev = priv->pdev;
1594 phy_resnum = amd_xgbe_phy_resource_count(phy_pdev,
1595 IORESOURCE_MEM) - 3;
1596 phy_irqnum = amd_xgbe_phy_resource_count(phy_pdev,
1597 IORESOURCE_IRQ) - 1;
1598 }
1599 phy_dev = &phy_pdev->dev;
1600
1601 /* Get the device mmio areas */
1602 priv->rxtx_res = platform_get_resource(phy_pdev, IORESOURCE_MEM,
1603 phy_resnum++);
1604 priv->rxtx_regs = devm_ioremap_resource(dev, priv->rxtx_res);
1605 if (IS_ERR(priv->rxtx_regs)) {
1606 dev_err(dev, "rxtx ioremap failed\n");
1607 ret = PTR_ERR(priv->rxtx_regs);
1608 goto err_put;
1609 }
1610
1611 priv->sir0_res = platform_get_resource(phy_pdev, IORESOURCE_MEM,
1612 phy_resnum++);
1613 priv->sir0_regs = devm_ioremap_resource(dev, priv->sir0_res);
1614 if (IS_ERR(priv->sir0_regs)) {
1615 dev_err(dev, "sir0 ioremap failed\n");
1616 ret = PTR_ERR(priv->sir0_regs);
1617 goto err_rxtx;
1618 }
1619
1620 priv->sir1_res = platform_get_resource(phy_pdev, IORESOURCE_MEM,
1621 phy_resnum++);
1622 priv->sir1_regs = devm_ioremap_resource(dev, priv->sir1_res);
1623 if (IS_ERR(priv->sir1_regs)) {
1624 dev_err(dev, "sir1 ioremap failed\n");
1625 ret = PTR_ERR(priv->sir1_regs);
1626 goto err_sir0;
1627 }
1628
1629 /* Get the auto-negotiation interrupt */
1630 ret = platform_get_irq(phy_pdev, phy_irqnum);
1631 if (ret < 0) {
1632 dev_err(dev, "platform_get_irq failed\n");
1633 goto err_sir1;
1634 }
1635 priv->an_irq = ret;
1636
1637 /* Get the device speed set property */
1638 ret = device_property_read_u32(phy_dev, XGBE_PHY_SPEEDSET_PROPERTY,
1639 &priv->speed_set);
1640 if (ret) {
1641 dev_err(dev, "invalid %s property\n",
1642 XGBE_PHY_SPEEDSET_PROPERTY);
1643 goto err_sir1;
1644 }
1645
1646 switch (priv->speed_set) {
1647 case AMD_XGBE_PHY_SPEEDSET_1000_10000:
1648 case AMD_XGBE_PHY_SPEEDSET_2500_10000:
1649 break;
1650 default:
1651 dev_err(dev, "invalid %s property\n",
1652 XGBE_PHY_SPEEDSET_PROPERTY);
1653 ret = -EINVAL;
1654 goto err_sir1;
1655 }
1656
1657 if (device_property_present(phy_dev, XGBE_PHY_BLWC_PROPERTY)) {
1658 ret = device_property_read_u32_array(phy_dev,
1659 XGBE_PHY_BLWC_PROPERTY,
1660 priv->serdes_blwc,
1661 XGBE_PHY_SPEEDS);
1662 if (ret) {
1663 dev_err(dev, "invalid %s property\n",
1664 XGBE_PHY_BLWC_PROPERTY);
1665 goto err_sir1;
1666 }
1667 } else {
1668 memcpy(priv->serdes_blwc, amd_xgbe_phy_serdes_blwc,
1669 sizeof(priv->serdes_blwc));
1670 }
1671
1672 if (device_property_present(phy_dev, XGBE_PHY_CDR_RATE_PROPERTY)) {
1673 ret = device_property_read_u32_array(phy_dev,
1674 XGBE_PHY_CDR_RATE_PROPERTY,
1675 priv->serdes_cdr_rate,
1676 XGBE_PHY_SPEEDS);
1677 if (ret) {
1678 dev_err(dev, "invalid %s property\n",
1679 XGBE_PHY_CDR_RATE_PROPERTY);
1680 goto err_sir1;
1681 }
1682 } else {
1683 memcpy(priv->serdes_cdr_rate, amd_xgbe_phy_serdes_cdr_rate,
1684 sizeof(priv->serdes_cdr_rate));
1685 }
1686
1687 if (device_property_present(phy_dev, XGBE_PHY_PQ_SKEW_PROPERTY)) {
1688 ret = device_property_read_u32_array(phy_dev,
1689 XGBE_PHY_PQ_SKEW_PROPERTY,
1690 priv->serdes_pq_skew,
1691 XGBE_PHY_SPEEDS);
1692 if (ret) {
1693 dev_err(dev, "invalid %s property\n",
1694 XGBE_PHY_PQ_SKEW_PROPERTY);
1695 goto err_sir1;
1696 }
1697 } else {
1698 memcpy(priv->serdes_pq_skew, amd_xgbe_phy_serdes_pq_skew,
1699 sizeof(priv->serdes_pq_skew));
1700 }
1701
1702 if (device_property_present(phy_dev, XGBE_PHY_TX_AMP_PROPERTY)) {
1703 ret = device_property_read_u32_array(phy_dev,
1704 XGBE_PHY_TX_AMP_PROPERTY,
1705 priv->serdes_tx_amp,
1706 XGBE_PHY_SPEEDS);
1707 if (ret) {
1708 dev_err(dev, "invalid %s property\n",
1709 XGBE_PHY_TX_AMP_PROPERTY);
1710 goto err_sir1;
1711 }
1712 } else {
1713 memcpy(priv->serdes_tx_amp, amd_xgbe_phy_serdes_tx_amp,
1714 sizeof(priv->serdes_tx_amp));
1715 }
1716
1717 if (device_property_present(phy_dev, XGBE_PHY_DFE_CFG_PROPERTY)) {
1718 ret = device_property_read_u32_array(phy_dev,
1719 XGBE_PHY_DFE_CFG_PROPERTY,
1720 priv->serdes_dfe_tap_cfg,
1721 XGBE_PHY_SPEEDS);
1722 if (ret) {
1723 dev_err(dev, "invalid %s property\n",
1724 XGBE_PHY_DFE_CFG_PROPERTY);
1725 goto err_sir1;
1726 }
1727 } else {
1728 memcpy(priv->serdes_dfe_tap_cfg,
1729 amd_xgbe_phy_serdes_dfe_tap_cfg,
1730 sizeof(priv->serdes_dfe_tap_cfg));
1731 }
1732
1733 if (device_property_present(phy_dev, XGBE_PHY_DFE_ENA_PROPERTY)) {
1734 ret = device_property_read_u32_array(phy_dev,
1735 XGBE_PHY_DFE_ENA_PROPERTY,
1736 priv->serdes_dfe_tap_ena,
1737 XGBE_PHY_SPEEDS);
1738 if (ret) {
1739 dev_err(dev, "invalid %s property\n",
1740 XGBE_PHY_DFE_ENA_PROPERTY);
1741 goto err_sir1;
1742 }
1743 } else {
1744 memcpy(priv->serdes_dfe_tap_ena,
1745 amd_xgbe_phy_serdes_dfe_tap_ena,
1746 sizeof(priv->serdes_dfe_tap_ena));
1747 }
1748
1749 phydev->priv = priv;
1750
1751 if (!priv->adev || acpi_disabled)
1752 platform_device_put(phy_pdev);
1753
1754 return 0;
1755
1756 err_sir1:
1757 devm_iounmap(dev, priv->sir1_regs);
1758 devm_release_mem_region(dev, priv->sir1_res->start,
1759 resource_size(priv->sir1_res));
1760
1761 err_sir0:
1762 devm_iounmap(dev, priv->sir0_regs);
1763 devm_release_mem_region(dev, priv->sir0_res->start,
1764 resource_size(priv->sir0_res));
1765
1766 err_rxtx:
1767 devm_iounmap(dev, priv->rxtx_regs);
1768 devm_release_mem_region(dev, priv->rxtx_res->start,
1769 resource_size(priv->rxtx_res));
1770
1771 err_put:
1772 if (!priv->adev || acpi_disabled)
1773 platform_device_put(phy_pdev);
1774
1775 err_priv:
1776 devm_kfree(dev, priv);
1777
1778 return ret;
1779 }
1780
1781 static void amd_xgbe_phy_remove(struct phy_device *phydev)
1782 {
1783 struct amd_xgbe_phy_priv *priv = phydev->priv;
1784 struct device *dev = priv->dev;
1785
1786 if (priv->an_irq_allocated) {
1787 devm_free_irq(dev, priv->an_irq, priv);
1788
1789 flush_workqueue(priv->an_workqueue);
1790 destroy_workqueue(priv->an_workqueue);
1791 }
1792
1793 /* Release resources */
1794 devm_iounmap(dev, priv->sir1_regs);
1795 devm_release_mem_region(dev, priv->sir1_res->start,
1796 resource_size(priv->sir1_res));
1797
1798 devm_iounmap(dev, priv->sir0_regs);
1799 devm_release_mem_region(dev, priv->sir0_res->start,
1800 resource_size(priv->sir0_res));
1801
1802 devm_iounmap(dev, priv->rxtx_regs);
1803 devm_release_mem_region(dev, priv->rxtx_res->start,
1804 resource_size(priv->rxtx_res));
1805
1806 devm_kfree(dev, priv);
1807 }
1808
1809 static int amd_xgbe_match_phy_device(struct phy_device *phydev)
1810 {
1811 return phydev->c45_ids.device_ids[MDIO_MMD_PCS] == XGBE_PHY_ID;
1812 }
1813
1814 static struct phy_driver amd_xgbe_phy_driver[] = {
1815 {
1816 .phy_id = XGBE_PHY_ID,
1817 .phy_id_mask = XGBE_PHY_MASK,
1818 .name = "AMD XGBE PHY",
1819 .features = 0,
1820 .probe = amd_xgbe_phy_probe,
1821 .remove = amd_xgbe_phy_remove,
1822 .soft_reset = amd_xgbe_phy_soft_reset,
1823 .config_init = amd_xgbe_phy_config_init,
1824 .suspend = amd_xgbe_phy_suspend,
1825 .resume = amd_xgbe_phy_resume,
1826 .config_aneg = amd_xgbe_phy_config_aneg,
1827 .aneg_done = amd_xgbe_phy_aneg_done,
1828 .read_status = amd_xgbe_phy_read_status,
1829 .match_phy_device = amd_xgbe_match_phy_device,
1830 .driver = {
1831 .owner = THIS_MODULE,
1832 },
1833 },
1834 };
1835
1836 module_phy_driver(amd_xgbe_phy_driver);
1837
1838 static struct mdio_device_id __maybe_unused amd_xgbe_phy_ids[] = {
1839 { XGBE_PHY_ID, XGBE_PHY_MASK },
1840 { }
1841 };
1842 MODULE_DEVICE_TABLE(mdio, amd_xgbe_phy_ids);
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