2 * AMD 10Gb Ethernet PHY driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 * License 2: Modified BSD
27 * Copyright (c) 2014 Advanced Micro Devices, Inc.
28 * All rights reserved.
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions are met:
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in the
36 * documentation and/or other materials provided with the distribution.
37 * * Neither the name of Advanced Micro Devices, Inc. nor the
38 * names of its contributors may be used to endorse or promote products
39 * derived from this software without specific prior written permission.
41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
47 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
48 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53 #include <linux/kernel.h>
54 #include <linux/device.h>
55 #include <linux/platform_device.h>
56 #include <linux/string.h>
57 #include <linux/errno.h>
58 #include <linux/unistd.h>
59 #include <linux/slab.h>
60 #include <linux/interrupt.h>
61 #include <linux/init.h>
62 #include <linux/delay.h>
63 #include <linux/workqueue.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/skbuff.h>
68 #include <linux/module.h>
69 #include <linux/mii.h>
70 #include <linux/ethtool.h>
71 #include <linux/phy.h>
72 #include <linux/mdio.h>
75 #include <linux/of_platform.h>
76 #include <linux/of_device.h>
77 #include <linux/uaccess.h>
78 #include <linux/bitops.h>
79 #include <linux/property.h>
80 #include <linux/acpi.h>
82 MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
83 MODULE_LICENSE("Dual BSD/GPL");
84 MODULE_VERSION("1.0.0-a");
85 MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
87 #define XGBE_PHY_ID 0x000162d0
88 #define XGBE_PHY_MASK 0xfffffff0
90 #define XGBE_PHY_SPEEDSET_PROPERTY "amd,speed-set"
91 #define XGBE_PHY_BLWC_PROPERTY "amd,serdes-blwc"
92 #define XGBE_PHY_CDR_RATE_PROPERTY "amd,serdes-cdr-rate"
93 #define XGBE_PHY_PQ_SKEW_PROPERTY "amd,serdes-pq-skew"
94 #define XGBE_PHY_TX_AMP_PROPERTY "amd,serdes-tx-amp"
96 #define XGBE_PHY_SPEEDS 3
97 #define XGBE_PHY_SPEED_1000 0
98 #define XGBE_PHY_SPEED_2500 1
99 #define XGBE_PHY_SPEED_10000 2
101 #define XGBE_AN_INT_CMPLT 0x01
102 #define XGBE_AN_INC_LINK 0x02
103 #define XGBE_AN_PG_RCV 0x04
104 #define XGBE_AN_INT_MASK 0x07
106 #define XNP_MCF_NULL_MESSAGE 0x001
107 #define XNP_ACK_PROCESSED BIT(12)
108 #define XNP_MP_FORMATTED BIT(13)
109 #define XNP_NP_EXCHANGE BIT(15)
111 #define XGBE_PHY_RATECHANGE_COUNT 500
113 #define XGBE_PHY_KR_TRAINING_START 0x01
114 #define XGBE_PHY_KR_TRAINING_ENABLE 0x02
116 #define XGBE_PHY_FEC_ENABLE 0x01
117 #define XGBE_PHY_FEC_FORWARD 0x02
118 #define XGBE_PHY_FEC_MASK 0x03
120 #ifndef MDIO_PMA_10GBR_PMD_CTRL
121 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096
124 #ifndef MDIO_PMA_10GBR_FEC_ABILITY
125 #define MDIO_PMA_10GBR_FEC_ABILITY 0x00aa
128 #ifndef MDIO_PMA_10GBR_FEC_CTRL
129 #define MDIO_PMA_10GBR_FEC_CTRL 0x00ab
133 #define MDIO_AN_XNP 0x0016
137 #define MDIO_AN_LPX 0x0019
140 #ifndef MDIO_AN_INTMASK
141 #define MDIO_AN_INTMASK 0x8001
145 #define MDIO_AN_INT 0x8002
148 #ifndef MDIO_CTRL1_SPEED1G
149 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
152 /* SerDes integration register offsets */
153 #define SIR0_KR_RT_1 0x002c
154 #define SIR0_STATUS 0x0040
155 #define SIR1_SPEED 0x0000
157 /* SerDes integration register entry bit positions and sizes */
158 #define SIR0_KR_RT_1_RESET_INDEX 11
159 #define SIR0_KR_RT_1_RESET_WIDTH 1
160 #define SIR0_STATUS_RX_READY_INDEX 0
161 #define SIR0_STATUS_RX_READY_WIDTH 1
162 #define SIR0_STATUS_TX_READY_INDEX 8
163 #define SIR0_STATUS_TX_READY_WIDTH 1
164 #define SIR1_SPEED_CDR_RATE_INDEX 12
165 #define SIR1_SPEED_CDR_RATE_WIDTH 4
166 #define SIR1_SPEED_DATARATE_INDEX 4
167 #define SIR1_SPEED_DATARATE_WIDTH 2
168 #define SIR1_SPEED_PLLSEL_INDEX 3
169 #define SIR1_SPEED_PLLSEL_WIDTH 1
170 #define SIR1_SPEED_RATECHANGE_INDEX 6
171 #define SIR1_SPEED_RATECHANGE_WIDTH 1
172 #define SIR1_SPEED_TXAMP_INDEX 8
173 #define SIR1_SPEED_TXAMP_WIDTH 4
174 #define SIR1_SPEED_WORDMODE_INDEX 0
175 #define SIR1_SPEED_WORDMODE_WIDTH 3
177 #define SPEED_10000_BLWC 0
178 #define SPEED_10000_CDR 0x7
179 #define SPEED_10000_PLL 0x1
180 #define SPEED_10000_PQ 0x1e
181 #define SPEED_10000_RATE 0x0
182 #define SPEED_10000_TXAMP 0xa
183 #define SPEED_10000_WORD 0x7
185 #define SPEED_2500_BLWC 1
186 #define SPEED_2500_CDR 0x2
187 #define SPEED_2500_PLL 0x0
188 #define SPEED_2500_PQ 0xa
189 #define SPEED_2500_RATE 0x1
190 #define SPEED_2500_TXAMP 0xf
191 #define SPEED_2500_WORD 0x1
193 #define SPEED_1000_BLWC 1
194 #define SPEED_1000_CDR 0x2
195 #define SPEED_1000_PLL 0x0
196 #define SPEED_1000_PQ 0xa
197 #define SPEED_1000_RATE 0x3
198 #define SPEED_1000_TXAMP 0xf
199 #define SPEED_1000_WORD 0x1
201 /* SerDes RxTx register offsets */
202 #define RXTX_REG20 0x0050
203 #define RXTX_REG114 0x01c8
205 /* SerDes RxTx register entry bit positions and sizes */
206 #define RXTX_REG20_BLWC_ENA_INDEX 2
207 #define RXTX_REG20_BLWC_ENA_WIDTH 1
208 #define RXTX_REG114_PQ_REG_INDEX 9
209 #define RXTX_REG114_PQ_REG_WIDTH 7
211 /* Bit setting and getting macros
212 * The get macro will extract the current bit field value from within
215 * The set macro will clear the current bit field value within the
216 * variable and then set the bit field of the variable to the
219 #define GET_BITS(_var, _index, _width) \
220 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
222 #define SET_BITS(_var, _index, _width, _val) \
224 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
225 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
228 #define XSIR_GET_BITS(_var, _prefix, _field) \
230 _prefix##_##_field##_INDEX, \
231 _prefix##_##_field##_WIDTH)
233 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \
235 _prefix##_##_field##_INDEX, \
236 _prefix##_##_field##_WIDTH, (_val))
238 /* Macros for reading or writing SerDes integration registers
239 * The ioread macros will get bit fields or full values using the
240 * register definitions formed using the input names
242 * The iowrite macros will set bit fields or full values using the
243 * register definitions formed using the input names
245 #define XSIR0_IOREAD(_priv, _reg) \
246 ioread16((_priv)->sir0_regs + _reg)
248 #define XSIR0_IOREAD_BITS(_priv, _reg, _field) \
249 GET_BITS(XSIR0_IOREAD((_priv), _reg), \
250 _reg##_##_field##_INDEX, \
251 _reg##_##_field##_WIDTH)
253 #define XSIR0_IOWRITE(_priv, _reg, _val) \
254 iowrite16((_val), (_priv)->sir0_regs + _reg)
256 #define XSIR0_IOWRITE_BITS(_priv, _reg, _field, _val) \
258 u16 reg_val = XSIR0_IOREAD((_priv), _reg); \
260 _reg##_##_field##_INDEX, \
261 _reg##_##_field##_WIDTH, (_val)); \
262 XSIR0_IOWRITE((_priv), _reg, reg_val); \
265 #define XSIR1_IOREAD(_priv, _reg) \
266 ioread16((_priv)->sir1_regs + _reg)
268 #define XSIR1_IOREAD_BITS(_priv, _reg, _field) \
269 GET_BITS(XSIR1_IOREAD((_priv), _reg), \
270 _reg##_##_field##_INDEX, \
271 _reg##_##_field##_WIDTH)
273 #define XSIR1_IOWRITE(_priv, _reg, _val) \
274 iowrite16((_val), (_priv)->sir1_regs + _reg)
276 #define XSIR1_IOWRITE_BITS(_priv, _reg, _field, _val) \
278 u16 reg_val = XSIR1_IOREAD((_priv), _reg); \
280 _reg##_##_field##_INDEX, \
281 _reg##_##_field##_WIDTH, (_val)); \
282 XSIR1_IOWRITE((_priv), _reg, reg_val); \
285 /* Macros for reading or writing SerDes RxTx registers
286 * The ioread macros will get bit fields or full values using the
287 * register definitions formed using the input names
289 * The iowrite macros will set bit fields or full values using the
290 * register definitions formed using the input names
292 #define XRXTX_IOREAD(_priv, _reg) \
293 ioread16((_priv)->rxtx_regs + _reg)
295 #define XRXTX_IOREAD_BITS(_priv, _reg, _field) \
296 GET_BITS(XRXTX_IOREAD((_priv), _reg), \
297 _reg##_##_field##_INDEX, \
298 _reg##_##_field##_WIDTH)
300 #define XRXTX_IOWRITE(_priv, _reg, _val) \
301 iowrite16((_val), (_priv)->rxtx_regs + _reg)
303 #define XRXTX_IOWRITE_BITS(_priv, _reg, _field, _val) \
305 u16 reg_val = XRXTX_IOREAD((_priv), _reg); \
307 _reg##_##_field##_INDEX, \
308 _reg##_##_field##_WIDTH, (_val)); \
309 XRXTX_IOWRITE((_priv), _reg, reg_val); \
312 static const u32 amd_xgbe_phy_serdes_blwc
[] = {
318 static const u32 amd_xgbe_phy_serdes_cdr_rate
[] = {
324 static const u32 amd_xgbe_phy_serdes_pq_skew
[] = {
330 static const u32 amd_xgbe_phy_serdes_tx_amp
[] = {
336 enum amd_xgbe_phy_an
{
337 AMD_XGBE_AN_READY
= 0,
338 AMD_XGBE_AN_PAGE_RECEIVED
,
339 AMD_XGBE_AN_INCOMPAT_LINK
,
340 AMD_XGBE_AN_COMPLETE
,
345 enum amd_xgbe_phy_rx
{
348 AMD_XGBE_RX_COMPLETE
,
352 enum amd_xgbe_phy_mode
{
357 enum amd_xgbe_phy_speedset
{
358 AMD_XGBE_PHY_SPEEDSET_1000_10000
= 0,
359 AMD_XGBE_PHY_SPEEDSET_2500_10000
,
362 struct amd_xgbe_phy_priv
{
363 struct platform_device
*pdev
;
364 struct acpi_device
*adev
;
367 struct phy_device
*phydev
;
369 /* SerDes related mmio resources */
370 struct resource
*rxtx_res
;
371 struct resource
*sir0_res
;
372 struct resource
*sir1_res
;
374 /* SerDes related mmio registers */
375 void __iomem
*rxtx_regs
; /* SerDes Rx/Tx CSRs */
376 void __iomem
*sir0_regs
; /* SerDes integration registers (1/2) */
377 void __iomem
*sir1_regs
; /* SerDes integration registers (2/2) */
380 char an_irq_name
[IFNAMSIZ
+ 32];
381 struct work_struct an_irq_work
;
382 unsigned int an_irq_allocated
;
384 unsigned int speed_set
;
386 /* SerDes UEFI configurable settings.
387 * Switching between modes/speeds requires new values for some
388 * SerDes settings. The values can be supplied as device
389 * properties in array format. The first array entry is for
390 * 1GbE, second for 2.5GbE and third for 10GbE
392 u32 serdes_blwc
[XGBE_PHY_SPEEDS
];
393 u32 serdes_cdr_rate
[XGBE_PHY_SPEEDS
];
394 u32 serdes_pq_skew
[XGBE_PHY_SPEEDS
];
395 u32 serdes_tx_amp
[XGBE_PHY_SPEEDS
];
397 /* Auto-negotiation state machine support */
398 struct mutex an_mutex
;
399 enum amd_xgbe_phy_an an_result
;
400 enum amd_xgbe_phy_an an_state
;
401 enum amd_xgbe_phy_rx kr_state
;
402 enum amd_xgbe_phy_rx kx_state
;
403 struct work_struct an_work
;
404 struct workqueue_struct
*an_workqueue
;
405 unsigned int an_supported
;
406 unsigned int parallel_detect
;
407 unsigned int fec_ability
;
409 unsigned int lpm_ctrl
; /* CTRL1 for resume */
412 static int amd_xgbe_an_enable_kr_training(struct phy_device
*phydev
)
416 ret
= phy_read_mmd(phydev
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_PMD_CTRL
);
420 ret
|= XGBE_PHY_KR_TRAINING_ENABLE
;
421 phy_write_mmd(phydev
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_PMD_CTRL
, ret
);
426 static int amd_xgbe_an_disable_kr_training(struct phy_device
*phydev
)
430 ret
= phy_read_mmd(phydev
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_PMD_CTRL
);
434 ret
&= ~XGBE_PHY_KR_TRAINING_ENABLE
;
435 phy_write_mmd(phydev
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_PMD_CTRL
, ret
);
440 static int amd_xgbe_phy_pcs_power_cycle(struct phy_device
*phydev
)
444 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
);
448 ret
|= MDIO_CTRL1_LPOWER
;
449 phy_write_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
, ret
);
451 usleep_range(75, 100);
453 ret
&= ~MDIO_CTRL1_LPOWER
;
454 phy_write_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
, ret
);
459 static void amd_xgbe_phy_serdes_start_ratechange(struct phy_device
*phydev
)
461 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
463 /* Assert Rx and Tx ratechange */
464 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, RATECHANGE
, 1);
467 static void amd_xgbe_phy_serdes_complete_ratechange(struct phy_device
*phydev
)
469 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
473 /* Release Rx and Tx ratechange */
474 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, RATECHANGE
, 0);
476 /* Wait for Rx and Tx ready */
477 wait
= XGBE_PHY_RATECHANGE_COUNT
;
479 usleep_range(50, 75);
481 status
= XSIR0_IOREAD(priv
, SIR0_STATUS
);
482 if (XSIR_GET_BITS(status
, SIR0_STATUS
, RX_READY
) &&
483 XSIR_GET_BITS(status
, SIR0_STATUS
, TX_READY
))
487 netdev_dbg(phydev
->attached_dev
, "SerDes rx/tx not ready (%#hx)\n",
491 static int amd_xgbe_phy_xgmii_mode(struct phy_device
*phydev
)
493 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
496 /* Enable KR training */
497 ret
= amd_xgbe_an_enable_kr_training(phydev
);
501 /* Set PCS to KR/10G speed */
502 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL2
);
506 ret
&= ~MDIO_PCS_CTRL2_TYPE
;
507 ret
|= MDIO_PCS_CTRL2_10GBR
;
508 phy_write_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL2
, ret
);
510 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
);
514 ret
&= ~MDIO_CTRL1_SPEEDSEL
;
515 ret
|= MDIO_CTRL1_SPEED10G
;
516 phy_write_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
, ret
);
518 ret
= amd_xgbe_phy_pcs_power_cycle(phydev
);
522 /* Set SerDes to 10G speed */
523 amd_xgbe_phy_serdes_start_ratechange(phydev
);
525 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, DATARATE
, SPEED_10000_RATE
);
526 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, WORDMODE
, SPEED_10000_WORD
);
527 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, PLLSEL
, SPEED_10000_PLL
);
529 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, CDR_RATE
,
530 priv
->serdes_cdr_rate
[XGBE_PHY_SPEED_10000
]);
531 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, TXAMP
,
532 priv
->serdes_tx_amp
[XGBE_PHY_SPEED_10000
]);
533 XRXTX_IOWRITE_BITS(priv
, RXTX_REG20
, BLWC_ENA
,
534 priv
->serdes_blwc
[XGBE_PHY_SPEED_10000
]);
535 XRXTX_IOWRITE_BITS(priv
, RXTX_REG114
, PQ_REG
,
536 priv
->serdes_pq_skew
[XGBE_PHY_SPEED_10000
]);
538 amd_xgbe_phy_serdes_complete_ratechange(phydev
);
543 static int amd_xgbe_phy_gmii_2500_mode(struct phy_device
*phydev
)
545 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
548 /* Disable KR training */
549 ret
= amd_xgbe_an_disable_kr_training(phydev
);
553 /* Set PCS to KX/1G speed */
554 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL2
);
558 ret
&= ~MDIO_PCS_CTRL2_TYPE
;
559 ret
|= MDIO_PCS_CTRL2_10GBX
;
560 phy_write_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL2
, ret
);
562 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
);
566 ret
&= ~MDIO_CTRL1_SPEEDSEL
;
567 ret
|= MDIO_CTRL1_SPEED1G
;
568 phy_write_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
, ret
);
570 ret
= amd_xgbe_phy_pcs_power_cycle(phydev
);
574 /* Set SerDes to 2.5G speed */
575 amd_xgbe_phy_serdes_start_ratechange(phydev
);
577 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, DATARATE
, SPEED_2500_RATE
);
578 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, WORDMODE
, SPEED_2500_WORD
);
579 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, PLLSEL
, SPEED_2500_PLL
);
581 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, CDR_RATE
,
582 priv
->serdes_cdr_rate
[XGBE_PHY_SPEED_2500
]);
583 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, TXAMP
,
584 priv
->serdes_tx_amp
[XGBE_PHY_SPEED_2500
]);
585 XRXTX_IOWRITE_BITS(priv
, RXTX_REG20
, BLWC_ENA
,
586 priv
->serdes_blwc
[XGBE_PHY_SPEED_2500
]);
587 XRXTX_IOWRITE_BITS(priv
, RXTX_REG114
, PQ_REG
,
588 priv
->serdes_pq_skew
[XGBE_PHY_SPEED_2500
]);
590 amd_xgbe_phy_serdes_complete_ratechange(phydev
);
595 static int amd_xgbe_phy_gmii_mode(struct phy_device
*phydev
)
597 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
600 /* Disable KR training */
601 ret
= amd_xgbe_an_disable_kr_training(phydev
);
605 /* Set PCS to KX/1G speed */
606 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL2
);
610 ret
&= ~MDIO_PCS_CTRL2_TYPE
;
611 ret
|= MDIO_PCS_CTRL2_10GBX
;
612 phy_write_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL2
, ret
);
614 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
);
618 ret
&= ~MDIO_CTRL1_SPEEDSEL
;
619 ret
|= MDIO_CTRL1_SPEED1G
;
620 phy_write_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
, ret
);
622 ret
= amd_xgbe_phy_pcs_power_cycle(phydev
);
626 /* Set SerDes to 1G speed */
627 amd_xgbe_phy_serdes_start_ratechange(phydev
);
629 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, DATARATE
, SPEED_1000_RATE
);
630 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, WORDMODE
, SPEED_1000_WORD
);
631 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, PLLSEL
, SPEED_1000_PLL
);
633 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, CDR_RATE
,
634 priv
->serdes_cdr_rate
[XGBE_PHY_SPEED_1000
]);
635 XSIR1_IOWRITE_BITS(priv
, SIR1_SPEED
, TXAMP
,
636 priv
->serdes_tx_amp
[XGBE_PHY_SPEED_1000
]);
637 XRXTX_IOWRITE_BITS(priv
, RXTX_REG20
, BLWC_ENA
,
638 priv
->serdes_blwc
[XGBE_PHY_SPEED_1000
]);
639 XRXTX_IOWRITE_BITS(priv
, RXTX_REG114
, PQ_REG
,
640 priv
->serdes_pq_skew
[XGBE_PHY_SPEED_1000
]);
642 amd_xgbe_phy_serdes_complete_ratechange(phydev
);
647 static int amd_xgbe_phy_cur_mode(struct phy_device
*phydev
,
648 enum amd_xgbe_phy_mode
*mode
)
652 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL2
);
656 if ((ret
& MDIO_PCS_CTRL2_TYPE
) == MDIO_PCS_CTRL2_10GBR
)
657 *mode
= AMD_XGBE_MODE_KR
;
659 *mode
= AMD_XGBE_MODE_KX
;
664 static bool amd_xgbe_phy_in_kr_mode(struct phy_device
*phydev
)
666 enum amd_xgbe_phy_mode mode
;
668 if (amd_xgbe_phy_cur_mode(phydev
, &mode
))
671 return (mode
== AMD_XGBE_MODE_KR
);
674 static int amd_xgbe_phy_switch_mode(struct phy_device
*phydev
)
676 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
679 /* If we are in KR switch to KX, and vice-versa */
680 if (amd_xgbe_phy_in_kr_mode(phydev
)) {
681 if (priv
->speed_set
== AMD_XGBE_PHY_SPEEDSET_1000_10000
)
682 ret
= amd_xgbe_phy_gmii_mode(phydev
);
684 ret
= amd_xgbe_phy_gmii_2500_mode(phydev
);
686 ret
= amd_xgbe_phy_xgmii_mode(phydev
);
692 static int amd_xgbe_phy_set_mode(struct phy_device
*phydev
,
693 enum amd_xgbe_phy_mode mode
)
695 enum amd_xgbe_phy_mode cur_mode
;
698 ret
= amd_xgbe_phy_cur_mode(phydev
, &cur_mode
);
702 if (mode
!= cur_mode
)
703 ret
= amd_xgbe_phy_switch_mode(phydev
);
708 static int amd_xgbe_phy_set_an(struct phy_device
*phydev
, bool enable
,
713 ret
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_CTRL1
);
717 ret
&= ~MDIO_AN_CTRL1_ENABLE
;
720 ret
|= MDIO_AN_CTRL1_ENABLE
;
723 ret
|= MDIO_AN_CTRL1_RESTART
;
725 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_CTRL1
, ret
);
730 static int amd_xgbe_phy_restart_an(struct phy_device
*phydev
)
732 return amd_xgbe_phy_set_an(phydev
, true, true);
735 static int amd_xgbe_phy_disable_an(struct phy_device
*phydev
)
737 return amd_xgbe_phy_set_an(phydev
, false, false);
740 static enum amd_xgbe_phy_an
amd_xgbe_an_tx_training(struct phy_device
*phydev
,
741 enum amd_xgbe_phy_rx
*state
)
743 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
744 int ad_reg
, lp_reg
, ret
;
746 *state
= AMD_XGBE_RX_COMPLETE
;
748 /* If we're not in KR mode then we're done */
749 if (!amd_xgbe_phy_in_kr_mode(phydev
))
750 return AMD_XGBE_AN_PAGE_RECEIVED
;
752 /* Enable/Disable FEC */
753 ad_reg
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
+ 2);
755 return AMD_XGBE_AN_ERROR
;
757 lp_reg
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_LPA
+ 2);
759 return AMD_XGBE_AN_ERROR
;
761 ret
= phy_read_mmd(phydev
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_FEC_CTRL
);
763 return AMD_XGBE_AN_ERROR
;
765 ret
&= ~XGBE_PHY_FEC_MASK
;
766 if ((ad_reg
& 0xc000) && (lp_reg
& 0xc000))
767 ret
|= priv
->fec_ability
;
769 phy_write_mmd(phydev
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_FEC_CTRL
, ret
);
771 /* Start KR training */
772 ret
= phy_read_mmd(phydev
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_PMD_CTRL
);
774 return AMD_XGBE_AN_ERROR
;
776 if (ret
& XGBE_PHY_KR_TRAINING_ENABLE
) {
777 XSIR0_IOWRITE_BITS(priv
, SIR0_KR_RT_1
, RESET
, 1);
779 ret
|= XGBE_PHY_KR_TRAINING_START
;
780 phy_write_mmd(phydev
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_PMD_CTRL
,
783 XSIR0_IOWRITE_BITS(priv
, SIR0_KR_RT_1
, RESET
, 0);
786 return AMD_XGBE_AN_PAGE_RECEIVED
;
789 static enum amd_xgbe_phy_an
amd_xgbe_an_tx_xnp(struct phy_device
*phydev
,
790 enum amd_xgbe_phy_rx
*state
)
794 *state
= AMD_XGBE_RX_XNP
;
796 msg
= XNP_MCF_NULL_MESSAGE
;
797 msg
|= XNP_MP_FORMATTED
;
799 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_XNP
+ 2, 0);
800 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_XNP
+ 1, 0);
801 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_XNP
, msg
);
803 return AMD_XGBE_AN_PAGE_RECEIVED
;
806 static enum amd_xgbe_phy_an
amd_xgbe_an_rx_bpa(struct phy_device
*phydev
,
807 enum amd_xgbe_phy_rx
*state
)
809 unsigned int link_support
;
810 int ret
, ad_reg
, lp_reg
;
812 /* Read Base Ability register 2 first */
813 ret
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_LPA
+ 1);
815 return AMD_XGBE_AN_ERROR
;
817 /* Check for a supported mode, otherwise restart in a different one */
818 link_support
= amd_xgbe_phy_in_kr_mode(phydev
) ? 0x80 : 0x20;
819 if (!(ret
& link_support
))
820 return AMD_XGBE_AN_INCOMPAT_LINK
;
822 /* Check Extended Next Page support */
823 ad_reg
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
);
825 return AMD_XGBE_AN_ERROR
;
827 lp_reg
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_LPA
);
829 return AMD_XGBE_AN_ERROR
;
831 return ((ad_reg
& XNP_NP_EXCHANGE
) || (lp_reg
& XNP_NP_EXCHANGE
)) ?
832 amd_xgbe_an_tx_xnp(phydev
, state
) :
833 amd_xgbe_an_tx_training(phydev
, state
);
836 static enum amd_xgbe_phy_an
amd_xgbe_an_rx_xnp(struct phy_device
*phydev
,
837 enum amd_xgbe_phy_rx
*state
)
841 /* Check Extended Next Page support */
842 ad_reg
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_XNP
);
844 return AMD_XGBE_AN_ERROR
;
846 lp_reg
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_LPX
);
848 return AMD_XGBE_AN_ERROR
;
850 return ((ad_reg
& XNP_NP_EXCHANGE
) || (lp_reg
& XNP_NP_EXCHANGE
)) ?
851 amd_xgbe_an_tx_xnp(phydev
, state
) :
852 amd_xgbe_an_tx_training(phydev
, state
);
855 static enum amd_xgbe_phy_an
amd_xgbe_an_page_received(struct phy_device
*phydev
)
857 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
858 enum amd_xgbe_phy_rx
*state
;
861 state
= amd_xgbe_phy_in_kr_mode(phydev
) ? &priv
->kr_state
865 case AMD_XGBE_RX_BPA
:
866 ret
= amd_xgbe_an_rx_bpa(phydev
, state
);
869 case AMD_XGBE_RX_XNP
:
870 ret
= amd_xgbe_an_rx_xnp(phydev
, state
);
874 ret
= AMD_XGBE_AN_ERROR
;
880 static enum amd_xgbe_phy_an
amd_xgbe_an_incompat_link(struct phy_device
*phydev
)
882 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
885 /* Be sure we aren't looping trying to negotiate */
886 if (amd_xgbe_phy_in_kr_mode(phydev
)) {
887 priv
->kr_state
= AMD_XGBE_RX_ERROR
;
889 if (!(phydev
->supported
& SUPPORTED_1000baseKX_Full
) &&
890 !(phydev
->supported
& SUPPORTED_2500baseX_Full
))
891 return AMD_XGBE_AN_NO_LINK
;
893 if (priv
->kx_state
!= AMD_XGBE_RX_BPA
)
894 return AMD_XGBE_AN_NO_LINK
;
896 priv
->kx_state
= AMD_XGBE_RX_ERROR
;
898 if (!(phydev
->supported
& SUPPORTED_10000baseKR_Full
))
899 return AMD_XGBE_AN_NO_LINK
;
901 if (priv
->kr_state
!= AMD_XGBE_RX_BPA
)
902 return AMD_XGBE_AN_NO_LINK
;
905 ret
= amd_xgbe_phy_disable_an(phydev
);
907 return AMD_XGBE_AN_ERROR
;
909 ret
= amd_xgbe_phy_switch_mode(phydev
);
911 return AMD_XGBE_AN_ERROR
;
913 ret
= amd_xgbe_phy_restart_an(phydev
);
915 return AMD_XGBE_AN_ERROR
;
917 return AMD_XGBE_AN_INCOMPAT_LINK
;
920 static irqreturn_t
amd_xgbe_an_isr(int irq
, void *data
)
922 struct amd_xgbe_phy_priv
*priv
= (struct amd_xgbe_phy_priv
*)data
;
924 /* Interrupt reason must be read and cleared outside of IRQ context */
925 disable_irq_nosync(priv
->an_irq
);
927 queue_work(priv
->an_workqueue
, &priv
->an_irq_work
);
932 static void amd_xgbe_an_irq_work(struct work_struct
*work
)
934 struct amd_xgbe_phy_priv
*priv
= container_of(work
,
935 struct amd_xgbe_phy_priv
,
938 /* Avoid a race between enabling the IRQ and exiting the work by
939 * waiting for the work to finish and then queueing it
941 flush_work(&priv
->an_work
);
942 queue_work(priv
->an_workqueue
, &priv
->an_work
);
945 static void amd_xgbe_an_state_machine(struct work_struct
*work
)
947 struct amd_xgbe_phy_priv
*priv
= container_of(work
,
948 struct amd_xgbe_phy_priv
,
950 struct phy_device
*phydev
= priv
->phydev
;
951 enum amd_xgbe_phy_an cur_state
= priv
->an_state
;
952 int int_reg
, int_mask
;
954 mutex_lock(&priv
->an_mutex
);
956 /* Read the interrupt */
957 int_reg
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_INT
);
963 priv
->an_state
= AMD_XGBE_AN_ERROR
;
964 int_mask
= XGBE_AN_INT_MASK
;
965 } else if (int_reg
& XGBE_AN_PG_RCV
) {
966 priv
->an_state
= AMD_XGBE_AN_PAGE_RECEIVED
;
967 int_mask
= XGBE_AN_PG_RCV
;
968 } else if (int_reg
& XGBE_AN_INC_LINK
) {
969 priv
->an_state
= AMD_XGBE_AN_INCOMPAT_LINK
;
970 int_mask
= XGBE_AN_INC_LINK
;
971 } else if (int_reg
& XGBE_AN_INT_CMPLT
) {
972 priv
->an_state
= AMD_XGBE_AN_COMPLETE
;
973 int_mask
= XGBE_AN_INT_CMPLT
;
975 priv
->an_state
= AMD_XGBE_AN_ERROR
;
979 /* Clear the interrupt to be processed */
980 int_reg
&= ~int_mask
;
981 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_INT
, int_reg
);
983 priv
->an_result
= priv
->an_state
;
986 cur_state
= priv
->an_state
;
988 switch (priv
->an_state
) {
989 case AMD_XGBE_AN_READY
:
990 priv
->an_supported
= 0;
993 case AMD_XGBE_AN_PAGE_RECEIVED
:
994 priv
->an_state
= amd_xgbe_an_page_received(phydev
);
995 priv
->an_supported
++;
998 case AMD_XGBE_AN_INCOMPAT_LINK
:
999 priv
->an_supported
= 0;
1000 priv
->parallel_detect
= 0;
1001 priv
->an_state
= amd_xgbe_an_incompat_link(phydev
);
1004 case AMD_XGBE_AN_COMPLETE
:
1005 priv
->parallel_detect
= priv
->an_supported
? 0 : 1;
1006 netdev_dbg(phydev
->attached_dev
, "%s successful\n",
1007 priv
->an_supported
? "Auto negotiation"
1008 : "Parallel detection");
1011 case AMD_XGBE_AN_NO_LINK
:
1015 priv
->an_state
= AMD_XGBE_AN_ERROR
;
1018 if (priv
->an_state
== AMD_XGBE_AN_NO_LINK
) {
1020 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_INT
, 0);
1021 } else if (priv
->an_state
== AMD_XGBE_AN_ERROR
) {
1022 netdev_err(phydev
->attached_dev
,
1023 "error during auto-negotiation, state=%u\n",
1027 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_INT
, 0);
1030 if (priv
->an_state
>= AMD_XGBE_AN_COMPLETE
) {
1031 priv
->an_result
= priv
->an_state
;
1032 priv
->an_state
= AMD_XGBE_AN_READY
;
1033 priv
->kr_state
= AMD_XGBE_RX_BPA
;
1034 priv
->kx_state
= AMD_XGBE_RX_BPA
;
1037 if (cur_state
!= priv
->an_state
)
1044 enable_irq(priv
->an_irq
);
1046 mutex_unlock(&priv
->an_mutex
);
1049 static int amd_xgbe_an_init(struct phy_device
*phydev
)
1053 /* Set up Advertisement register 3 first */
1054 ret
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
+ 2);
1058 if (phydev
->supported
& SUPPORTED_10000baseR_FEC
)
1063 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
+ 2, ret
);
1065 /* Set up Advertisement register 2 next */
1066 ret
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
+ 1);
1070 if (phydev
->supported
& SUPPORTED_10000baseKR_Full
)
1075 if ((phydev
->supported
& SUPPORTED_1000baseKX_Full
) ||
1076 (phydev
->supported
& SUPPORTED_2500baseX_Full
))
1081 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
+ 1, ret
);
1083 /* Set up Advertisement register 1 last */
1084 ret
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
);
1088 if (phydev
->supported
& SUPPORTED_Pause
)
1093 if (phydev
->supported
& SUPPORTED_Asym_Pause
)
1098 /* We don't intend to perform XNP */
1099 ret
&= ~XNP_NP_EXCHANGE
;
1101 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
, ret
);
1106 static int amd_xgbe_phy_soft_reset(struct phy_device
*phydev
)
1110 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
);
1114 ret
|= MDIO_CTRL1_RESET
;
1115 phy_write_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
, ret
);
1120 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
);
1123 } while ((ret
& MDIO_CTRL1_RESET
) && --count
);
1125 if (ret
& MDIO_CTRL1_RESET
)
1128 /* Disable auto-negotiation for now */
1129 ret
= amd_xgbe_phy_disable_an(phydev
);
1133 /* Clear auto-negotiation interrupts */
1134 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_INT
, 0);
1139 static int amd_xgbe_phy_config_init(struct phy_device
*phydev
)
1141 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
1142 struct net_device
*netdev
= phydev
->attached_dev
;
1145 if (!priv
->an_irq_allocated
) {
1146 /* Allocate the auto-negotiation workqueue and interrupt */
1147 snprintf(priv
->an_irq_name
, sizeof(priv
->an_irq_name
) - 1,
1148 "%s-pcs", netdev_name(netdev
));
1150 priv
->an_workqueue
=
1151 create_singlethread_workqueue(priv
->an_irq_name
);
1152 if (!priv
->an_workqueue
) {
1153 netdev_err(netdev
, "phy workqueue creation failed\n");
1157 ret
= devm_request_irq(priv
->dev
, priv
->an_irq
,
1158 amd_xgbe_an_isr
, 0, priv
->an_irq_name
,
1161 netdev_err(netdev
, "phy irq request failed\n");
1162 destroy_workqueue(priv
->an_workqueue
);
1166 priv
->an_irq_allocated
= 1;
1169 ret
= phy_read_mmd(phydev
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_FEC_ABILITY
);
1172 priv
->fec_ability
= ret
& XGBE_PHY_FEC_MASK
;
1174 /* Initialize supported features */
1175 phydev
->supported
= SUPPORTED_Autoneg
;
1176 phydev
->supported
|= SUPPORTED_Pause
| SUPPORTED_Asym_Pause
;
1177 phydev
->supported
|= SUPPORTED_Backplane
;
1178 phydev
->supported
|= SUPPORTED_10000baseKR_Full
;
1179 switch (priv
->speed_set
) {
1180 case AMD_XGBE_PHY_SPEEDSET_1000_10000
:
1181 phydev
->supported
|= SUPPORTED_1000baseKX_Full
;
1183 case AMD_XGBE_PHY_SPEEDSET_2500_10000
:
1184 phydev
->supported
|= SUPPORTED_2500baseX_Full
;
1188 if (priv
->fec_ability
& XGBE_PHY_FEC_ENABLE
)
1189 phydev
->supported
|= SUPPORTED_10000baseR_FEC
;
1191 phydev
->advertising
= phydev
->supported
;
1193 /* Set initial mode - call the mode setting routines
1194 * directly to insure we are properly configured
1196 if (phydev
->supported
& SUPPORTED_10000baseKR_Full
)
1197 ret
= amd_xgbe_phy_xgmii_mode(phydev
);
1198 else if (phydev
->supported
& SUPPORTED_1000baseKX_Full
)
1199 ret
= amd_xgbe_phy_gmii_mode(phydev
);
1200 else if (phydev
->supported
& SUPPORTED_2500baseX_Full
)
1201 ret
= amd_xgbe_phy_gmii_2500_mode(phydev
);
1207 /* Set up advertisement registers based on current settings */
1208 ret
= amd_xgbe_an_init(phydev
);
1212 /* Enable auto-negotiation interrupts */
1213 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_INTMASK
, 0x07);
1218 static int amd_xgbe_phy_setup_forced(struct phy_device
*phydev
)
1222 /* Disable auto-negotiation */
1223 ret
= amd_xgbe_phy_disable_an(phydev
);
1227 /* Validate/Set specified speed */
1228 switch (phydev
->speed
) {
1230 ret
= amd_xgbe_phy_set_mode(phydev
, AMD_XGBE_MODE_KR
);
1235 ret
= amd_xgbe_phy_set_mode(phydev
, AMD_XGBE_MODE_KX
);
1245 /* Validate duplex mode */
1246 if (phydev
->duplex
!= DUPLEX_FULL
)
1250 phydev
->asym_pause
= 0;
1255 static int __amd_xgbe_phy_config_aneg(struct phy_device
*phydev
)
1257 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
1258 u32 mmd_mask
= phydev
->c45_ids
.devices_in_package
;
1261 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
1262 return amd_xgbe_phy_setup_forced(phydev
);
1264 /* Make sure we have the AN MMD present */
1265 if (!(mmd_mask
& MDIO_DEVS_AN
))
1268 /* Disable auto-negotiation interrupt */
1269 disable_irq(priv
->an_irq
);
1271 /* Start auto-negotiation in a supported mode */
1272 if (phydev
->supported
& SUPPORTED_10000baseKR_Full
)
1273 ret
= amd_xgbe_phy_set_mode(phydev
, AMD_XGBE_MODE_KR
);
1274 else if ((phydev
->supported
& SUPPORTED_1000baseKX_Full
) ||
1275 (phydev
->supported
& SUPPORTED_2500baseX_Full
))
1276 ret
= amd_xgbe_phy_set_mode(phydev
, AMD_XGBE_MODE_KX
);
1280 enable_irq(priv
->an_irq
);
1284 /* Disable and stop any in progress auto-negotiation */
1285 ret
= amd_xgbe_phy_disable_an(phydev
);
1289 /* Clear any auto-negotitation interrupts */
1290 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_INT
, 0);
1292 priv
->an_result
= AMD_XGBE_AN_READY
;
1293 priv
->an_state
= AMD_XGBE_AN_READY
;
1294 priv
->kr_state
= AMD_XGBE_RX_BPA
;
1295 priv
->kx_state
= AMD_XGBE_RX_BPA
;
1297 /* Re-enable auto-negotiation interrupt */
1298 enable_irq(priv
->an_irq
);
1300 /* Set up advertisement registers based on current settings */
1301 ret
= amd_xgbe_an_init(phydev
);
1305 /* Enable and start auto-negotiation */
1306 return amd_xgbe_phy_restart_an(phydev
);
1309 static int amd_xgbe_phy_config_aneg(struct phy_device
*phydev
)
1311 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
1314 mutex_lock(&priv
->an_mutex
);
1316 ret
= __amd_xgbe_phy_config_aneg(phydev
);
1318 mutex_unlock(&priv
->an_mutex
);
1323 static int amd_xgbe_phy_aneg_done(struct phy_device
*phydev
)
1325 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
1327 return (priv
->an_result
== AMD_XGBE_AN_COMPLETE
);
1330 static int amd_xgbe_phy_update_link(struct phy_device
*phydev
)
1332 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
1335 /* If we're doing auto-negotiation don't report link down */
1336 if (priv
->an_state
!= AMD_XGBE_AN_READY
) {
1341 /* Link status is latched low, so read once to clear
1342 * and then read again to get current state
1344 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_STAT1
);
1348 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_STAT1
);
1352 phydev
->link
= (ret
& MDIO_STAT1_LSTATUS
) ? 1 : 0;
1357 static int amd_xgbe_phy_read_status(struct phy_device
*phydev
)
1359 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
1360 u32 mmd_mask
= phydev
->c45_ids
.devices_in_package
;
1361 int ret
, ad_ret
, lp_ret
;
1363 ret
= amd_xgbe_phy_update_link(phydev
);
1367 if ((phydev
->autoneg
== AUTONEG_ENABLE
) &&
1368 !priv
->parallel_detect
) {
1369 if (!(mmd_mask
& MDIO_DEVS_AN
))
1372 if (!amd_xgbe_phy_aneg_done(phydev
))
1375 /* Compare Advertisement and Link Partner register 1 */
1376 ad_ret
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
);
1379 lp_ret
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_LPA
);
1384 phydev
->pause
= (ad_ret
& 0x400) ? 1 : 0;
1385 phydev
->asym_pause
= (ad_ret
& 0x800) ? 1 : 0;
1387 /* Compare Advertisement and Link Partner register 2 */
1388 ad_ret
= phy_read_mmd(phydev
, MDIO_MMD_AN
,
1389 MDIO_AN_ADVERTISE
+ 1);
1392 lp_ret
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_LPA
+ 1);
1397 if (ad_ret
& 0x80) {
1398 phydev
->speed
= SPEED_10000
;
1399 ret
= amd_xgbe_phy_set_mode(phydev
, AMD_XGBE_MODE_KR
);
1403 switch (priv
->speed_set
) {
1404 case AMD_XGBE_PHY_SPEEDSET_1000_10000
:
1405 phydev
->speed
= SPEED_1000
;
1408 case AMD_XGBE_PHY_SPEEDSET_2500_10000
:
1409 phydev
->speed
= SPEED_2500
;
1413 ret
= amd_xgbe_phy_set_mode(phydev
, AMD_XGBE_MODE_KX
);
1418 phydev
->duplex
= DUPLEX_FULL
;
1420 if (amd_xgbe_phy_in_kr_mode(phydev
)) {
1421 phydev
->speed
= SPEED_10000
;
1423 switch (priv
->speed_set
) {
1424 case AMD_XGBE_PHY_SPEEDSET_1000_10000
:
1425 phydev
->speed
= SPEED_1000
;
1428 case AMD_XGBE_PHY_SPEEDSET_2500_10000
:
1429 phydev
->speed
= SPEED_2500
;
1433 phydev
->duplex
= DUPLEX_FULL
;
1435 phydev
->asym_pause
= 0;
1441 static int amd_xgbe_phy_suspend(struct phy_device
*phydev
)
1443 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
1446 mutex_lock(&phydev
->lock
);
1448 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
);
1452 priv
->lpm_ctrl
= ret
;
1454 ret
|= MDIO_CTRL1_LPOWER
;
1455 phy_write_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
, ret
);
1460 mutex_unlock(&phydev
->lock
);
1465 static int amd_xgbe_phy_resume(struct phy_device
*phydev
)
1467 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
1469 mutex_lock(&phydev
->lock
);
1471 priv
->lpm_ctrl
&= ~MDIO_CTRL1_LPOWER
;
1472 phy_write_mmd(phydev
, MDIO_MMD_PCS
, MDIO_CTRL1
, priv
->lpm_ctrl
);
1474 mutex_unlock(&phydev
->lock
);
1479 static unsigned int amd_xgbe_phy_resource_count(struct platform_device
*pdev
,
1485 for (i
= 0, count
= 0; i
< pdev
->num_resources
; i
++) {
1486 struct resource
*r
= &pdev
->resource
[i
];
1488 if (type
== resource_type(r
))
1495 static int amd_xgbe_phy_probe(struct phy_device
*phydev
)
1497 struct amd_xgbe_phy_priv
*priv
;
1498 struct platform_device
*phy_pdev
;
1499 struct device
*dev
, *phy_dev
;
1500 unsigned int phy_resnum
, phy_irqnum
;
1503 if (!phydev
->bus
|| !phydev
->bus
->parent
)
1506 dev
= phydev
->bus
->parent
;
1508 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1512 priv
->pdev
= to_platform_device(dev
);
1513 priv
->adev
= ACPI_COMPANION(dev
);
1515 priv
->phydev
= phydev
;
1516 mutex_init(&priv
->an_mutex
);
1517 INIT_WORK(&priv
->an_irq_work
, amd_xgbe_an_irq_work
);
1518 INIT_WORK(&priv
->an_work
, amd_xgbe_an_state_machine
);
1520 if (!priv
->adev
|| acpi_disabled
) {
1521 struct device_node
*bus_node
;
1522 struct device_node
*phy_node
;
1524 bus_node
= priv
->dev
->of_node
;
1525 phy_node
= of_parse_phandle(bus_node
, "phy-handle", 0);
1527 dev_err(dev
, "unable to parse phy-handle\n");
1532 phy_pdev
= of_find_device_by_node(phy_node
);
1533 of_node_put(phy_node
);
1536 dev_err(dev
, "unable to obtain phy device\n");
1544 /* In ACPI, the XGBE and PHY resources are the grouped
1545 * together with the PHY resources at the end
1547 phy_pdev
= priv
->pdev
;
1548 phy_resnum
= amd_xgbe_phy_resource_count(phy_pdev
,
1549 IORESOURCE_MEM
) - 3;
1550 phy_irqnum
= amd_xgbe_phy_resource_count(phy_pdev
,
1551 IORESOURCE_IRQ
) - 1;
1553 phy_dev
= &phy_pdev
->dev
;
1555 /* Get the device mmio areas */
1556 priv
->rxtx_res
= platform_get_resource(phy_pdev
, IORESOURCE_MEM
,
1558 priv
->rxtx_regs
= devm_ioremap_resource(dev
, priv
->rxtx_res
);
1559 if (IS_ERR(priv
->rxtx_regs
)) {
1560 dev_err(dev
, "rxtx ioremap failed\n");
1561 ret
= PTR_ERR(priv
->rxtx_regs
);
1565 priv
->sir0_res
= platform_get_resource(phy_pdev
, IORESOURCE_MEM
,
1567 priv
->sir0_regs
= devm_ioremap_resource(dev
, priv
->sir0_res
);
1568 if (IS_ERR(priv
->sir0_regs
)) {
1569 dev_err(dev
, "sir0 ioremap failed\n");
1570 ret
= PTR_ERR(priv
->sir0_regs
);
1574 priv
->sir1_res
= platform_get_resource(phy_pdev
, IORESOURCE_MEM
,
1576 priv
->sir1_regs
= devm_ioremap_resource(dev
, priv
->sir1_res
);
1577 if (IS_ERR(priv
->sir1_regs
)) {
1578 dev_err(dev
, "sir1 ioremap failed\n");
1579 ret
= PTR_ERR(priv
->sir1_regs
);
1583 /* Get the auto-negotiation interrupt */
1584 ret
= platform_get_irq(phy_pdev
, phy_irqnum
);
1586 dev_err(dev
, "platform_get_irq failed\n");
1591 /* Get the device speed set property */
1592 ret
= device_property_read_u32(phy_dev
, XGBE_PHY_SPEEDSET_PROPERTY
,
1595 dev_err(dev
, "invalid %s property\n",
1596 XGBE_PHY_SPEEDSET_PROPERTY
);
1600 switch (priv
->speed_set
) {
1601 case AMD_XGBE_PHY_SPEEDSET_1000_10000
:
1602 case AMD_XGBE_PHY_SPEEDSET_2500_10000
:
1605 dev_err(dev
, "invalid %s property\n",
1606 XGBE_PHY_SPEEDSET_PROPERTY
);
1611 if (device_property_present(phy_dev
, XGBE_PHY_BLWC_PROPERTY
)) {
1612 ret
= device_property_read_u32_array(phy_dev
,
1613 XGBE_PHY_BLWC_PROPERTY
,
1617 dev_err(dev
, "invalid %s property\n",
1618 XGBE_PHY_BLWC_PROPERTY
);
1622 memcpy(priv
->serdes_blwc
, amd_xgbe_phy_serdes_blwc
,
1623 sizeof(priv
->serdes_blwc
));
1626 if (device_property_present(phy_dev
, XGBE_PHY_CDR_RATE_PROPERTY
)) {
1627 ret
= device_property_read_u32_array(phy_dev
,
1628 XGBE_PHY_CDR_RATE_PROPERTY
,
1629 priv
->serdes_cdr_rate
,
1632 dev_err(dev
, "invalid %s property\n",
1633 XGBE_PHY_CDR_RATE_PROPERTY
);
1637 memcpy(priv
->serdes_cdr_rate
, amd_xgbe_phy_serdes_cdr_rate
,
1638 sizeof(priv
->serdes_cdr_rate
));
1641 if (device_property_present(phy_dev
, XGBE_PHY_PQ_SKEW_PROPERTY
)) {
1642 ret
= device_property_read_u32_array(phy_dev
,
1643 XGBE_PHY_PQ_SKEW_PROPERTY
,
1644 priv
->serdes_pq_skew
,
1647 dev_err(dev
, "invalid %s property\n",
1648 XGBE_PHY_PQ_SKEW_PROPERTY
);
1652 memcpy(priv
->serdes_pq_skew
, amd_xgbe_phy_serdes_pq_skew
,
1653 sizeof(priv
->serdes_pq_skew
));
1656 if (device_property_present(phy_dev
, XGBE_PHY_TX_AMP_PROPERTY
)) {
1657 ret
= device_property_read_u32_array(phy_dev
,
1658 XGBE_PHY_TX_AMP_PROPERTY
,
1659 priv
->serdes_tx_amp
,
1662 dev_err(dev
, "invalid %s property\n",
1663 XGBE_PHY_TX_AMP_PROPERTY
);
1667 memcpy(priv
->serdes_tx_amp
, amd_xgbe_phy_serdes_tx_amp
,
1668 sizeof(priv
->serdes_tx_amp
));
1671 phydev
->priv
= priv
;
1673 if (!priv
->adev
|| acpi_disabled
)
1674 platform_device_put(phy_pdev
);
1679 devm_iounmap(dev
, priv
->sir1_regs
);
1680 devm_release_mem_region(dev
, priv
->sir1_res
->start
,
1681 resource_size(priv
->sir1_res
));
1684 devm_iounmap(dev
, priv
->sir0_regs
);
1685 devm_release_mem_region(dev
, priv
->sir0_res
->start
,
1686 resource_size(priv
->sir0_res
));
1689 devm_iounmap(dev
, priv
->rxtx_regs
);
1690 devm_release_mem_region(dev
, priv
->rxtx_res
->start
,
1691 resource_size(priv
->rxtx_res
));
1694 if (!priv
->adev
|| acpi_disabled
)
1695 platform_device_put(phy_pdev
);
1698 devm_kfree(dev
, priv
);
1703 static void amd_xgbe_phy_remove(struct phy_device
*phydev
)
1705 struct amd_xgbe_phy_priv
*priv
= phydev
->priv
;
1706 struct device
*dev
= priv
->dev
;
1708 if (priv
->an_irq_allocated
) {
1709 devm_free_irq(dev
, priv
->an_irq
, priv
);
1711 flush_workqueue(priv
->an_workqueue
);
1712 destroy_workqueue(priv
->an_workqueue
);
1715 /* Release resources */
1716 devm_iounmap(dev
, priv
->sir1_regs
);
1717 devm_release_mem_region(dev
, priv
->sir1_res
->start
,
1718 resource_size(priv
->sir1_res
));
1720 devm_iounmap(dev
, priv
->sir0_regs
);
1721 devm_release_mem_region(dev
, priv
->sir0_res
->start
,
1722 resource_size(priv
->sir0_res
));
1724 devm_iounmap(dev
, priv
->rxtx_regs
);
1725 devm_release_mem_region(dev
, priv
->rxtx_res
->start
,
1726 resource_size(priv
->rxtx_res
));
1728 devm_kfree(dev
, priv
);
1731 static int amd_xgbe_match_phy_device(struct phy_device
*phydev
)
1733 return phydev
->c45_ids
.device_ids
[MDIO_MMD_PCS
] == XGBE_PHY_ID
;
1736 static struct phy_driver amd_xgbe_phy_driver
[] = {
1738 .phy_id
= XGBE_PHY_ID
,
1739 .phy_id_mask
= XGBE_PHY_MASK
,
1740 .name
= "AMD XGBE PHY",
1742 .probe
= amd_xgbe_phy_probe
,
1743 .remove
= amd_xgbe_phy_remove
,
1744 .soft_reset
= amd_xgbe_phy_soft_reset
,
1745 .config_init
= amd_xgbe_phy_config_init
,
1746 .suspend
= amd_xgbe_phy_suspend
,
1747 .resume
= amd_xgbe_phy_resume
,
1748 .config_aneg
= amd_xgbe_phy_config_aneg
,
1749 .aneg_done
= amd_xgbe_phy_aneg_done
,
1750 .read_status
= amd_xgbe_phy_read_status
,
1751 .match_phy_device
= amd_xgbe_match_phy_device
,
1753 .owner
= THIS_MODULE
,
1758 module_phy_driver(amd_xgbe_phy_driver
);
1760 static struct mdio_device_id __maybe_unused amd_xgbe_phy_ids
[] = {
1761 { XGBE_PHY_ID
, XGBE_PHY_MASK
},
1764 MODULE_DEVICE_TABLE(mdio
, amd_xgbe_phy_ids
);