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Merge tag 'omap-for-v5.0/fixes-rc7-signed' of git://git.kernel.org/pub/scm/linux...
[mirror_ubuntu-eoan-kernel.git] / drivers / net / phy / dp83640.c
1 /*
2 * Driver for the National Semiconductor DP83640 PHYTER
3 *
4 * Copyright (C) 2010 OMICRON electronics GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22
23 #include <linux/crc32.h>
24 #include <linux/ethtool.h>
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/mii.h>
28 #include <linux/module.h>
29 #include <linux/net_tstamp.h>
30 #include <linux/netdevice.h>
31 #include <linux/if_vlan.h>
32 #include <linux/phy.h>
33 #include <linux/ptp_classify.h>
34 #include <linux/ptp_clock_kernel.h>
35
36 #include "dp83640_reg.h"
37
38 #define DP83640_PHY_ID 0x20005ce1
39 #define PAGESEL 0x13
40 #define MAX_RXTS 64
41 #define N_EXT_TS 6
42 #define N_PER_OUT 7
43 #define PSF_PTPVER 2
44 #define PSF_EVNT 0x4000
45 #define PSF_RX 0x2000
46 #define PSF_TX 0x1000
47 #define EXT_EVENT 1
48 #define CAL_EVENT 7
49 #define CAL_TRIGGER 1
50 #define DP83640_N_PINS 12
51
52 #define MII_DP83640_MICR 0x11
53 #define MII_DP83640_MISR 0x12
54
55 #define MII_DP83640_MICR_OE 0x1
56 #define MII_DP83640_MICR_IE 0x2
57
58 #define MII_DP83640_MISR_RHF_INT_EN 0x01
59 #define MII_DP83640_MISR_FHF_INT_EN 0x02
60 #define MII_DP83640_MISR_ANC_INT_EN 0x04
61 #define MII_DP83640_MISR_DUP_INT_EN 0x08
62 #define MII_DP83640_MISR_SPD_INT_EN 0x10
63 #define MII_DP83640_MISR_LINK_INT_EN 0x20
64 #define MII_DP83640_MISR_ED_INT_EN 0x40
65 #define MII_DP83640_MISR_LQ_INT_EN 0x80
66
67 /* phyter seems to miss the mark by 16 ns */
68 #define ADJTIME_FIX 16
69
70 #define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */
71
72 #if defined(__BIG_ENDIAN)
73 #define ENDIAN_FLAG 0
74 #elif defined(__LITTLE_ENDIAN)
75 #define ENDIAN_FLAG PSF_ENDIAN
76 #endif
77
78 struct dp83640_skb_info {
79 int ptp_type;
80 unsigned long tmo;
81 };
82
83 struct phy_rxts {
84 u16 ns_lo; /* ns[15:0] */
85 u16 ns_hi; /* overflow[1:0], ns[29:16] */
86 u16 sec_lo; /* sec[15:0] */
87 u16 sec_hi; /* sec[31:16] */
88 u16 seqid; /* sequenceId[15:0] */
89 u16 msgtype; /* messageType[3:0], hash[11:0] */
90 };
91
92 struct phy_txts {
93 u16 ns_lo; /* ns[15:0] */
94 u16 ns_hi; /* overflow[1:0], ns[29:16] */
95 u16 sec_lo; /* sec[15:0] */
96 u16 sec_hi; /* sec[31:16] */
97 };
98
99 struct rxts {
100 struct list_head list;
101 unsigned long tmo;
102 u64 ns;
103 u16 seqid;
104 u8 msgtype;
105 u16 hash;
106 };
107
108 struct dp83640_clock;
109
110 struct dp83640_private {
111 struct list_head list;
112 struct dp83640_clock *clock;
113 struct phy_device *phydev;
114 struct delayed_work ts_work;
115 int hwts_tx_en;
116 int hwts_rx_en;
117 int layer;
118 int version;
119 /* remember state of cfg0 during calibration */
120 int cfg0;
121 /* remember the last event time stamp */
122 struct phy_txts edata;
123 /* list of rx timestamps */
124 struct list_head rxts;
125 struct list_head rxpool;
126 struct rxts rx_pool_data[MAX_RXTS];
127 /* protects above three fields from concurrent access */
128 spinlock_t rx_lock;
129 /* queues of incoming and outgoing packets */
130 struct sk_buff_head rx_queue;
131 struct sk_buff_head tx_queue;
132 };
133
134 struct dp83640_clock {
135 /* keeps the instance in the 'phyter_clocks' list */
136 struct list_head list;
137 /* we create one clock instance per MII bus */
138 struct mii_bus *bus;
139 /* protects extended registers from concurrent access */
140 struct mutex extreg_lock;
141 /* remembers which page was last selected */
142 int page;
143 /* our advertised capabilities */
144 struct ptp_clock_info caps;
145 /* protects the three fields below from concurrent access */
146 struct mutex clock_lock;
147 /* the one phyter from which we shall read */
148 struct dp83640_private *chosen;
149 /* list of the other attached phyters, not chosen */
150 struct list_head phylist;
151 /* reference to our PTP hardware clock */
152 struct ptp_clock *ptp_clock;
153 };
154
155 /* globals */
156
157 enum {
158 CALIBRATE_GPIO,
159 PEROUT_GPIO,
160 EXTTS0_GPIO,
161 EXTTS1_GPIO,
162 EXTTS2_GPIO,
163 EXTTS3_GPIO,
164 EXTTS4_GPIO,
165 EXTTS5_GPIO,
166 GPIO_TABLE_SIZE
167 };
168
169 static int chosen_phy = -1;
170 static ushort gpio_tab[GPIO_TABLE_SIZE] = {
171 1, 2, 3, 4, 8, 9, 10, 11
172 };
173
174 module_param(chosen_phy, int, 0444);
175 module_param_array(gpio_tab, ushort, NULL, 0444);
176
177 MODULE_PARM_DESC(chosen_phy, \
178 "The address of the PHY to use for the ancillary clock features");
179 MODULE_PARM_DESC(gpio_tab, \
180 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
181
182 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
183 {
184 int i, index;
185
186 for (i = 0; i < DP83640_N_PINS; i++) {
187 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
188 pd[i].index = i;
189 }
190
191 for (i = 0; i < GPIO_TABLE_SIZE; i++) {
192 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
193 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
194 return;
195 }
196 }
197
198 index = gpio_tab[CALIBRATE_GPIO] - 1;
199 pd[index].func = PTP_PF_PHYSYNC;
200 pd[index].chan = 0;
201
202 index = gpio_tab[PEROUT_GPIO] - 1;
203 pd[index].func = PTP_PF_PEROUT;
204 pd[index].chan = 0;
205
206 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
207 index = gpio_tab[i] - 1;
208 pd[index].func = PTP_PF_EXTTS;
209 pd[index].chan = i - EXTTS0_GPIO;
210 }
211 }
212
213 /* a list of clocks and a mutex to protect it */
214 static LIST_HEAD(phyter_clocks);
215 static DEFINE_MUTEX(phyter_clocks_lock);
216
217 static void rx_timestamp_work(struct work_struct *work);
218
219 /* extended register access functions */
220
221 #define BROADCAST_ADDR 31
222
223 static inline int broadcast_write(struct phy_device *phydev, u32 regnum,
224 u16 val)
225 {
226 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);
227 }
228
229 /* Caller must hold extreg_lock. */
230 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
231 {
232 struct dp83640_private *dp83640 = phydev->priv;
233 int val;
234
235 if (dp83640->clock->page != page) {
236 broadcast_write(phydev, PAGESEL, page);
237 dp83640->clock->page = page;
238 }
239 val = phy_read(phydev, regnum);
240
241 return val;
242 }
243
244 /* Caller must hold extreg_lock. */
245 static void ext_write(int broadcast, struct phy_device *phydev,
246 int page, u32 regnum, u16 val)
247 {
248 struct dp83640_private *dp83640 = phydev->priv;
249
250 if (dp83640->clock->page != page) {
251 broadcast_write(phydev, PAGESEL, page);
252 dp83640->clock->page = page;
253 }
254 if (broadcast)
255 broadcast_write(phydev, regnum, val);
256 else
257 phy_write(phydev, regnum, val);
258 }
259
260 /* Caller must hold extreg_lock. */
261 static int tdr_write(int bc, struct phy_device *dev,
262 const struct timespec64 *ts, u16 cmd)
263 {
264 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
265 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
266 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
267 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
268
269 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
270
271 return 0;
272 }
273
274 /* convert phy timestamps into driver timestamps */
275
276 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
277 {
278 u32 sec;
279
280 sec = p->sec_lo;
281 sec |= p->sec_hi << 16;
282
283 rxts->ns = p->ns_lo;
284 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
285 rxts->ns += ((u64)sec) * 1000000000ULL;
286 rxts->seqid = p->seqid;
287 rxts->msgtype = (p->msgtype >> 12) & 0xf;
288 rxts->hash = p->msgtype & 0x0fff;
289 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
290 }
291
292 static u64 phy2txts(struct phy_txts *p)
293 {
294 u64 ns;
295 u32 sec;
296
297 sec = p->sec_lo;
298 sec |= p->sec_hi << 16;
299
300 ns = p->ns_lo;
301 ns |= (p->ns_hi & 0x3fff) << 16;
302 ns += ((u64)sec) * 1000000000ULL;
303
304 return ns;
305 }
306
307 static int periodic_output(struct dp83640_clock *clock,
308 struct ptp_clock_request *clkreq, bool on,
309 int trigger)
310 {
311 struct dp83640_private *dp83640 = clock->chosen;
312 struct phy_device *phydev = dp83640->phydev;
313 u32 sec, nsec, pwidth;
314 u16 gpio, ptp_trig, val;
315
316 if (on) {
317 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
318 trigger);
319 if (gpio < 1)
320 return -EINVAL;
321 } else {
322 gpio = 0;
323 }
324
325 ptp_trig = TRIG_WR |
326 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
327 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
328 TRIG_PER |
329 TRIG_PULSE;
330
331 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
332
333 if (!on) {
334 val |= TRIG_DIS;
335 mutex_lock(&clock->extreg_lock);
336 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
337 ext_write(0, phydev, PAGE4, PTP_CTL, val);
338 mutex_unlock(&clock->extreg_lock);
339 return 0;
340 }
341
342 sec = clkreq->perout.start.sec;
343 nsec = clkreq->perout.start.nsec;
344 pwidth = clkreq->perout.period.sec * 1000000000UL;
345 pwidth += clkreq->perout.period.nsec;
346 pwidth /= 2;
347
348 mutex_lock(&clock->extreg_lock);
349
350 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
351
352 /*load trigger*/
353 val |= TRIG_LOAD;
354 ext_write(0, phydev, PAGE4, PTP_CTL, val);
355 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */
356 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
357 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
358 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
359 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
360 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
361 /* Triggers 0 and 1 has programmable pulsewidth2 */
362 if (trigger < 2) {
363 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
364 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
365 }
366
367 /*enable trigger*/
368 val &= ~TRIG_LOAD;
369 val |= TRIG_EN;
370 ext_write(0, phydev, PAGE4, PTP_CTL, val);
371
372 mutex_unlock(&clock->extreg_lock);
373 return 0;
374 }
375
376 /* ptp clock methods */
377
378 static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
379 {
380 struct dp83640_clock *clock =
381 container_of(ptp, struct dp83640_clock, caps);
382 struct phy_device *phydev = clock->chosen->phydev;
383 u64 rate;
384 int neg_adj = 0;
385 u16 hi, lo;
386
387 if (scaled_ppm < 0) {
388 neg_adj = 1;
389 scaled_ppm = -scaled_ppm;
390 }
391 rate = scaled_ppm;
392 rate <<= 13;
393 rate = div_u64(rate, 15625);
394
395 hi = (rate >> 16) & PTP_RATE_HI_MASK;
396 if (neg_adj)
397 hi |= PTP_RATE_DIR;
398
399 lo = rate & 0xffff;
400
401 mutex_lock(&clock->extreg_lock);
402
403 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
404 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
405
406 mutex_unlock(&clock->extreg_lock);
407
408 return 0;
409 }
410
411 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
412 {
413 struct dp83640_clock *clock =
414 container_of(ptp, struct dp83640_clock, caps);
415 struct phy_device *phydev = clock->chosen->phydev;
416 struct timespec64 ts;
417 int err;
418
419 delta += ADJTIME_FIX;
420
421 ts = ns_to_timespec64(delta);
422
423 mutex_lock(&clock->extreg_lock);
424
425 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
426
427 mutex_unlock(&clock->extreg_lock);
428
429 return err;
430 }
431
432 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
433 struct timespec64 *ts)
434 {
435 struct dp83640_clock *clock =
436 container_of(ptp, struct dp83640_clock, caps);
437 struct phy_device *phydev = clock->chosen->phydev;
438 unsigned int val[4];
439
440 mutex_lock(&clock->extreg_lock);
441
442 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
443
444 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
445 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
446 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
447 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
448
449 mutex_unlock(&clock->extreg_lock);
450
451 ts->tv_nsec = val[0] | (val[1] << 16);
452 ts->tv_sec = val[2] | (val[3] << 16);
453
454 return 0;
455 }
456
457 static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
458 const struct timespec64 *ts)
459 {
460 struct dp83640_clock *clock =
461 container_of(ptp, struct dp83640_clock, caps);
462 struct phy_device *phydev = clock->chosen->phydev;
463 int err;
464
465 mutex_lock(&clock->extreg_lock);
466
467 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
468
469 mutex_unlock(&clock->extreg_lock);
470
471 return err;
472 }
473
474 static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
475 struct ptp_clock_request *rq, int on)
476 {
477 struct dp83640_clock *clock =
478 container_of(ptp, struct dp83640_clock, caps);
479 struct phy_device *phydev = clock->chosen->phydev;
480 unsigned int index;
481 u16 evnt, event_num, gpio_num;
482
483 switch (rq->type) {
484 case PTP_CLK_REQ_EXTTS:
485 index = rq->extts.index;
486 if (index >= N_EXT_TS)
487 return -EINVAL;
488 event_num = EXT_EVENT + index;
489 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
490 if (on) {
491 gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
492 PTP_PF_EXTTS, index);
493 if (gpio_num < 1)
494 return -EINVAL;
495 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
496 if (rq->extts.flags & PTP_FALLING_EDGE)
497 evnt |= EVNT_FALL;
498 else
499 evnt |= EVNT_RISE;
500 }
501 mutex_lock(&clock->extreg_lock);
502 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
503 mutex_unlock(&clock->extreg_lock);
504 return 0;
505
506 case PTP_CLK_REQ_PEROUT:
507 if (rq->perout.index >= N_PER_OUT)
508 return -EINVAL;
509 return periodic_output(clock, rq, on, rq->perout.index);
510
511 default:
512 break;
513 }
514
515 return -EOPNOTSUPP;
516 }
517
518 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
519 enum ptp_pin_function func, unsigned int chan)
520 {
521 struct dp83640_clock *clock =
522 container_of(ptp, struct dp83640_clock, caps);
523
524 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
525 !list_empty(&clock->phylist))
526 return 1;
527
528 if (func == PTP_PF_PHYSYNC)
529 return 1;
530
531 return 0;
532 }
533
534 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
535 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
536
537 static void enable_status_frames(struct phy_device *phydev, bool on)
538 {
539 struct dp83640_private *dp83640 = phydev->priv;
540 struct dp83640_clock *clock = dp83640->clock;
541 u16 cfg0 = 0, ver;
542
543 if (on)
544 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
545
546 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
547
548 mutex_lock(&clock->extreg_lock);
549
550 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
551 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
552
553 mutex_unlock(&clock->extreg_lock);
554
555 if (!phydev->attached_dev) {
556 phydev_warn(phydev,
557 "expected to find an attached netdevice\n");
558 return;
559 }
560
561 if (on) {
562 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
563 phydev_warn(phydev, "failed to add mc address\n");
564 } else {
565 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
566 phydev_warn(phydev, "failed to delete mc address\n");
567 }
568 }
569
570 static bool is_status_frame(struct sk_buff *skb, int type)
571 {
572 struct ethhdr *h = eth_hdr(skb);
573
574 if (PTP_CLASS_V2_L2 == type &&
575 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
576 return true;
577 else
578 return false;
579 }
580
581 static int expired(struct rxts *rxts)
582 {
583 return time_after(jiffies, rxts->tmo);
584 }
585
586 /* Caller must hold rx_lock. */
587 static void prune_rx_ts(struct dp83640_private *dp83640)
588 {
589 struct list_head *this, *next;
590 struct rxts *rxts;
591
592 list_for_each_safe(this, next, &dp83640->rxts) {
593 rxts = list_entry(this, struct rxts, list);
594 if (expired(rxts)) {
595 list_del_init(&rxts->list);
596 list_add(&rxts->list, &dp83640->rxpool);
597 }
598 }
599 }
600
601 /* synchronize the phyters so they act as one clock */
602
603 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
604 {
605 int val;
606 phy_write(phydev, PAGESEL, 0);
607 val = phy_read(phydev, PHYCR2);
608 if (on)
609 val |= BC_WRITE;
610 else
611 val &= ~BC_WRITE;
612 phy_write(phydev, PHYCR2, val);
613 phy_write(phydev, PAGESEL, init_page);
614 }
615
616 static void recalibrate(struct dp83640_clock *clock)
617 {
618 s64 now, diff;
619 struct phy_txts event_ts;
620 struct timespec64 ts;
621 struct list_head *this;
622 struct dp83640_private *tmp;
623 struct phy_device *master = clock->chosen->phydev;
624 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
625
626 trigger = CAL_TRIGGER;
627 cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
628 if (cal_gpio < 1) {
629 pr_err("PHY calibration pin not available - PHY is not calibrated.");
630 return;
631 }
632
633 mutex_lock(&clock->extreg_lock);
634
635 /*
636 * enable broadcast, disable status frames, enable ptp clock
637 */
638 list_for_each(this, &clock->phylist) {
639 tmp = list_entry(this, struct dp83640_private, list);
640 enable_broadcast(tmp->phydev, clock->page, 1);
641 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
642 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
643 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
644 }
645 enable_broadcast(master, clock->page, 1);
646 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
647 ext_write(0, master, PAGE5, PSF_CFG0, 0);
648 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
649
650 /*
651 * enable an event timestamp
652 */
653 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
654 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
655 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
656
657 list_for_each(this, &clock->phylist) {
658 tmp = list_entry(this, struct dp83640_private, list);
659 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
660 }
661 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
662
663 /*
664 * configure a trigger
665 */
666 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
667 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
668 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
669 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
670
671 /* load trigger */
672 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
673 val |= TRIG_LOAD;
674 ext_write(0, master, PAGE4, PTP_CTL, val);
675
676 /* enable trigger */
677 val &= ~TRIG_LOAD;
678 val |= TRIG_EN;
679 ext_write(0, master, PAGE4, PTP_CTL, val);
680
681 /* disable trigger */
682 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
683 val |= TRIG_DIS;
684 ext_write(0, master, PAGE4, PTP_CTL, val);
685
686 /*
687 * read out and correct offsets
688 */
689 val = ext_read(master, PAGE4, PTP_STS);
690 phydev_info(master, "master PTP_STS 0x%04hx\n", val);
691 val = ext_read(master, PAGE4, PTP_ESTS);
692 phydev_info(master, "master PTP_ESTS 0x%04hx\n", val);
693 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
694 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
695 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
696 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
697 now = phy2txts(&event_ts);
698
699 list_for_each(this, &clock->phylist) {
700 tmp = list_entry(this, struct dp83640_private, list);
701 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
702 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val);
703 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
704 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val);
705 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
706 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
707 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
708 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
709 diff = now - (s64) phy2txts(&event_ts);
710 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n",
711 diff);
712 diff += ADJTIME_FIX;
713 ts = ns_to_timespec64(diff);
714 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
715 }
716
717 /*
718 * restore status frames
719 */
720 list_for_each(this, &clock->phylist) {
721 tmp = list_entry(this, struct dp83640_private, list);
722 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
723 }
724 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
725
726 mutex_unlock(&clock->extreg_lock);
727 }
728
729 /* time stamping methods */
730
731 static inline u16 exts_chan_to_edata(int ch)
732 {
733 return 1 << ((ch + EXT_EVENT) * 2);
734 }
735
736 static int decode_evnt(struct dp83640_private *dp83640,
737 void *data, int len, u16 ests)
738 {
739 struct phy_txts *phy_txts;
740 struct ptp_clock_event event;
741 int i, parsed;
742 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
743 u16 ext_status = 0;
744
745 /* calculate length of the event timestamp status message */
746 if (ests & MULT_EVNT)
747 parsed = (words + 2) * sizeof(u16);
748 else
749 parsed = (words + 1) * sizeof(u16);
750
751 /* check if enough data is available */
752 if (len < parsed)
753 return len;
754
755 if (ests & MULT_EVNT) {
756 ext_status = *(u16 *) data;
757 data += sizeof(ext_status);
758 }
759
760 phy_txts = data;
761
762 switch (words) {
763 case 3:
764 dp83640->edata.sec_hi = phy_txts->sec_hi;
765 /* fall through */
766 case 2:
767 dp83640->edata.sec_lo = phy_txts->sec_lo;
768 /* fall through */
769 case 1:
770 dp83640->edata.ns_hi = phy_txts->ns_hi;
771 /* fall through */
772 case 0:
773 dp83640->edata.ns_lo = phy_txts->ns_lo;
774 }
775
776 if (!ext_status) {
777 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
778 ext_status = exts_chan_to_edata(i);
779 }
780
781 event.type = PTP_CLOCK_EXTTS;
782 event.timestamp = phy2txts(&dp83640->edata);
783
784 /* Compensate for input path and synchronization delays */
785 event.timestamp -= 35;
786
787 for (i = 0; i < N_EXT_TS; i++) {
788 if (ext_status & exts_chan_to_edata(i)) {
789 event.index = i;
790 ptp_clock_event(dp83640->clock->ptp_clock, &event);
791 }
792 }
793
794 return parsed;
795 }
796
797 #define DP83640_PACKET_HASH_OFFSET 20
798 #define DP83640_PACKET_HASH_LEN 10
799
800 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
801 {
802 u16 *seqid, hash;
803 unsigned int offset = 0;
804 u8 *msgtype, *data = skb_mac_header(skb);
805
806 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
807
808 if (type & PTP_CLASS_VLAN)
809 offset += VLAN_HLEN;
810
811 switch (type & PTP_CLASS_PMASK) {
812 case PTP_CLASS_IPV4:
813 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
814 break;
815 case PTP_CLASS_IPV6:
816 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
817 break;
818 case PTP_CLASS_L2:
819 offset += ETH_HLEN;
820 break;
821 default:
822 return 0;
823 }
824
825 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
826 return 0;
827
828 if (unlikely(type & PTP_CLASS_V1))
829 msgtype = data + offset + OFF_PTP_CONTROL;
830 else
831 msgtype = data + offset;
832 if (rxts->msgtype != (*msgtype & 0xf))
833 return 0;
834
835 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
836 if (rxts->seqid != ntohs(*seqid))
837 return 0;
838
839 hash = ether_crc(DP83640_PACKET_HASH_LEN,
840 data + offset + DP83640_PACKET_HASH_OFFSET) >> 20;
841 if (rxts->hash != hash)
842 return 0;
843
844 return 1;
845 }
846
847 static void decode_rxts(struct dp83640_private *dp83640,
848 struct phy_rxts *phy_rxts)
849 {
850 struct rxts *rxts;
851 struct skb_shared_hwtstamps *shhwtstamps = NULL;
852 struct sk_buff *skb;
853 unsigned long flags;
854 u8 overflow;
855
856 overflow = (phy_rxts->ns_hi >> 14) & 0x3;
857 if (overflow)
858 pr_debug("rx timestamp queue overflow, count %d\n", overflow);
859
860 spin_lock_irqsave(&dp83640->rx_lock, flags);
861
862 prune_rx_ts(dp83640);
863
864 if (list_empty(&dp83640->rxpool)) {
865 pr_debug("rx timestamp pool is empty\n");
866 goto out;
867 }
868 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
869 list_del_init(&rxts->list);
870 phy2rxts(phy_rxts, rxts);
871
872 spin_lock(&dp83640->rx_queue.lock);
873 skb_queue_walk(&dp83640->rx_queue, skb) {
874 struct dp83640_skb_info *skb_info;
875
876 skb_info = (struct dp83640_skb_info *)skb->cb;
877 if (match(skb, skb_info->ptp_type, rxts)) {
878 __skb_unlink(skb, &dp83640->rx_queue);
879 shhwtstamps = skb_hwtstamps(skb);
880 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
881 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
882 list_add(&rxts->list, &dp83640->rxpool);
883 break;
884 }
885 }
886 spin_unlock(&dp83640->rx_queue.lock);
887
888 if (!shhwtstamps)
889 list_add_tail(&rxts->list, &dp83640->rxts);
890 out:
891 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
892
893 if (shhwtstamps)
894 netif_rx_ni(skb);
895 }
896
897 static void decode_txts(struct dp83640_private *dp83640,
898 struct phy_txts *phy_txts)
899 {
900 struct skb_shared_hwtstamps shhwtstamps;
901 struct dp83640_skb_info *skb_info;
902 struct sk_buff *skb;
903 u8 overflow;
904 u64 ns;
905
906 /* We must already have the skb that triggered this. */
907 again:
908 skb = skb_dequeue(&dp83640->tx_queue);
909 if (!skb) {
910 pr_debug("have timestamp but tx_queue empty\n");
911 return;
912 }
913
914 overflow = (phy_txts->ns_hi >> 14) & 0x3;
915 if (overflow) {
916 pr_debug("tx timestamp queue overflow, count %d\n", overflow);
917 while (skb) {
918 kfree_skb(skb);
919 skb = skb_dequeue(&dp83640->tx_queue);
920 }
921 return;
922 }
923 skb_info = (struct dp83640_skb_info *)skb->cb;
924 if (time_after(jiffies, skb_info->tmo)) {
925 kfree_skb(skb);
926 goto again;
927 }
928
929 ns = phy2txts(phy_txts);
930 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
931 shhwtstamps.hwtstamp = ns_to_ktime(ns);
932 skb_complete_tx_timestamp(skb, &shhwtstamps);
933 }
934
935 static void decode_status_frame(struct dp83640_private *dp83640,
936 struct sk_buff *skb)
937 {
938 struct phy_rxts *phy_rxts;
939 struct phy_txts *phy_txts;
940 u8 *ptr;
941 int len, size;
942 u16 ests, type;
943
944 ptr = skb->data + 2;
945
946 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
947
948 type = *(u16 *)ptr;
949 ests = type & 0x0fff;
950 type = type & 0xf000;
951 len -= sizeof(type);
952 ptr += sizeof(type);
953
954 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
955
956 phy_rxts = (struct phy_rxts *) ptr;
957 decode_rxts(dp83640, phy_rxts);
958 size = sizeof(*phy_rxts);
959
960 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
961
962 phy_txts = (struct phy_txts *) ptr;
963 decode_txts(dp83640, phy_txts);
964 size = sizeof(*phy_txts);
965
966 } else if (PSF_EVNT == type) {
967
968 size = decode_evnt(dp83640, ptr, len, ests);
969
970 } else {
971 size = 0;
972 break;
973 }
974 ptr += size;
975 }
976 }
977
978 static int is_sync(struct sk_buff *skb, int type)
979 {
980 u8 *data = skb->data, *msgtype;
981 unsigned int offset = 0;
982
983 if (type & PTP_CLASS_VLAN)
984 offset += VLAN_HLEN;
985
986 switch (type & PTP_CLASS_PMASK) {
987 case PTP_CLASS_IPV4:
988 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
989 break;
990 case PTP_CLASS_IPV6:
991 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
992 break;
993 case PTP_CLASS_L2:
994 offset += ETH_HLEN;
995 break;
996 default:
997 return 0;
998 }
999
1000 if (type & PTP_CLASS_V1)
1001 offset += OFF_PTP_CONTROL;
1002
1003 if (skb->len < offset + 1)
1004 return 0;
1005
1006 msgtype = data + offset;
1007
1008 return (*msgtype & 0xf) == 0;
1009 }
1010
1011 static void dp83640_free_clocks(void)
1012 {
1013 struct dp83640_clock *clock;
1014 struct list_head *this, *next;
1015
1016 mutex_lock(&phyter_clocks_lock);
1017
1018 list_for_each_safe(this, next, &phyter_clocks) {
1019 clock = list_entry(this, struct dp83640_clock, list);
1020 if (!list_empty(&clock->phylist)) {
1021 pr_warn("phy list non-empty while unloading\n");
1022 BUG();
1023 }
1024 list_del(&clock->list);
1025 mutex_destroy(&clock->extreg_lock);
1026 mutex_destroy(&clock->clock_lock);
1027 put_device(&clock->bus->dev);
1028 kfree(clock->caps.pin_config);
1029 kfree(clock);
1030 }
1031
1032 mutex_unlock(&phyter_clocks_lock);
1033 }
1034
1035 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
1036 {
1037 INIT_LIST_HEAD(&clock->list);
1038 clock->bus = bus;
1039 mutex_init(&clock->extreg_lock);
1040 mutex_init(&clock->clock_lock);
1041 INIT_LIST_HEAD(&clock->phylist);
1042 clock->caps.owner = THIS_MODULE;
1043 sprintf(clock->caps.name, "dp83640 timer");
1044 clock->caps.max_adj = 1953124;
1045 clock->caps.n_alarm = 0;
1046 clock->caps.n_ext_ts = N_EXT_TS;
1047 clock->caps.n_per_out = N_PER_OUT;
1048 clock->caps.n_pins = DP83640_N_PINS;
1049 clock->caps.pps = 0;
1050 clock->caps.adjfine = ptp_dp83640_adjfine;
1051 clock->caps.adjtime = ptp_dp83640_adjtime;
1052 clock->caps.gettime64 = ptp_dp83640_gettime;
1053 clock->caps.settime64 = ptp_dp83640_settime;
1054 clock->caps.enable = ptp_dp83640_enable;
1055 clock->caps.verify = ptp_dp83640_verify;
1056 /*
1057 * Convert the module param defaults into a dynamic pin configuration.
1058 */
1059 dp83640_gpio_defaults(clock->caps.pin_config);
1060 /*
1061 * Get a reference to this bus instance.
1062 */
1063 get_device(&bus->dev);
1064 }
1065
1066 static int choose_this_phy(struct dp83640_clock *clock,
1067 struct phy_device *phydev)
1068 {
1069 if (chosen_phy == -1 && !clock->chosen)
1070 return 1;
1071
1072 if (chosen_phy == phydev->mdio.addr)
1073 return 1;
1074
1075 return 0;
1076 }
1077
1078 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1079 {
1080 if (clock)
1081 mutex_lock(&clock->clock_lock);
1082 return clock;
1083 }
1084
1085 /*
1086 * Look up and lock a clock by bus instance.
1087 * If there is no clock for this bus, then create it first.
1088 */
1089 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1090 {
1091 struct dp83640_clock *clock = NULL, *tmp;
1092 struct list_head *this;
1093
1094 mutex_lock(&phyter_clocks_lock);
1095
1096 list_for_each(this, &phyter_clocks) {
1097 tmp = list_entry(this, struct dp83640_clock, list);
1098 if (tmp->bus == bus) {
1099 clock = tmp;
1100 break;
1101 }
1102 }
1103 if (clock)
1104 goto out;
1105
1106 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1107 if (!clock)
1108 goto out;
1109
1110 clock->caps.pin_config = kcalloc(DP83640_N_PINS,
1111 sizeof(struct ptp_pin_desc),
1112 GFP_KERNEL);
1113 if (!clock->caps.pin_config) {
1114 kfree(clock);
1115 clock = NULL;
1116 goto out;
1117 }
1118 dp83640_clock_init(clock, bus);
1119 list_add_tail(&phyter_clocks, &clock->list);
1120 out:
1121 mutex_unlock(&phyter_clocks_lock);
1122
1123 return dp83640_clock_get(clock);
1124 }
1125
1126 static void dp83640_clock_put(struct dp83640_clock *clock)
1127 {
1128 mutex_unlock(&clock->clock_lock);
1129 }
1130
1131 static int dp83640_probe(struct phy_device *phydev)
1132 {
1133 struct dp83640_clock *clock;
1134 struct dp83640_private *dp83640;
1135 int err = -ENOMEM, i;
1136
1137 if (phydev->mdio.addr == BROADCAST_ADDR)
1138 return 0;
1139
1140 clock = dp83640_clock_get_bus(phydev->mdio.bus);
1141 if (!clock)
1142 goto no_clock;
1143
1144 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1145 if (!dp83640)
1146 goto no_memory;
1147
1148 dp83640->phydev = phydev;
1149 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
1150
1151 INIT_LIST_HEAD(&dp83640->rxts);
1152 INIT_LIST_HEAD(&dp83640->rxpool);
1153 for (i = 0; i < MAX_RXTS; i++)
1154 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1155
1156 phydev->priv = dp83640;
1157
1158 spin_lock_init(&dp83640->rx_lock);
1159 skb_queue_head_init(&dp83640->rx_queue);
1160 skb_queue_head_init(&dp83640->tx_queue);
1161
1162 dp83640->clock = clock;
1163
1164 if (choose_this_phy(clock, phydev)) {
1165 clock->chosen = dp83640;
1166 clock->ptp_clock = ptp_clock_register(&clock->caps,
1167 &phydev->mdio.dev);
1168 if (IS_ERR(clock->ptp_clock)) {
1169 err = PTR_ERR(clock->ptp_clock);
1170 goto no_register;
1171 }
1172 } else
1173 list_add_tail(&dp83640->list, &clock->phylist);
1174
1175 dp83640_clock_put(clock);
1176 return 0;
1177
1178 no_register:
1179 clock->chosen = NULL;
1180 kfree(dp83640);
1181 no_memory:
1182 dp83640_clock_put(clock);
1183 no_clock:
1184 return err;
1185 }
1186
1187 static void dp83640_remove(struct phy_device *phydev)
1188 {
1189 struct dp83640_clock *clock;
1190 struct list_head *this, *next;
1191 struct dp83640_private *tmp, *dp83640 = phydev->priv;
1192
1193 if (phydev->mdio.addr == BROADCAST_ADDR)
1194 return;
1195
1196 enable_status_frames(phydev, false);
1197 cancel_delayed_work_sync(&dp83640->ts_work);
1198
1199 skb_queue_purge(&dp83640->rx_queue);
1200 skb_queue_purge(&dp83640->tx_queue);
1201
1202 clock = dp83640_clock_get(dp83640->clock);
1203
1204 if (dp83640 == clock->chosen) {
1205 ptp_clock_unregister(clock->ptp_clock);
1206 clock->chosen = NULL;
1207 } else {
1208 list_for_each_safe(this, next, &clock->phylist) {
1209 tmp = list_entry(this, struct dp83640_private, list);
1210 if (tmp == dp83640) {
1211 list_del_init(&tmp->list);
1212 break;
1213 }
1214 }
1215 }
1216
1217 dp83640_clock_put(clock);
1218 kfree(dp83640);
1219 }
1220
1221 static int dp83640_soft_reset(struct phy_device *phydev)
1222 {
1223 int ret;
1224
1225 ret = genphy_soft_reset(phydev);
1226 if (ret < 0)
1227 return ret;
1228
1229 /* From DP83640 datasheet: "Software driver code must wait 3 us
1230 * following a software reset before allowing further serial MII
1231 * operations with the DP83640."
1232 */
1233 udelay(10); /* Taking udelay inaccuracy into account */
1234
1235 return 0;
1236 }
1237
1238 static int dp83640_config_init(struct phy_device *phydev)
1239 {
1240 struct dp83640_private *dp83640 = phydev->priv;
1241 struct dp83640_clock *clock = dp83640->clock;
1242
1243 if (clock->chosen && !list_empty(&clock->phylist))
1244 recalibrate(clock);
1245 else {
1246 mutex_lock(&clock->extreg_lock);
1247 enable_broadcast(phydev, clock->page, 1);
1248 mutex_unlock(&clock->extreg_lock);
1249 }
1250
1251 enable_status_frames(phydev, true);
1252
1253 mutex_lock(&clock->extreg_lock);
1254 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1255 mutex_unlock(&clock->extreg_lock);
1256
1257 return 0;
1258 }
1259
1260 static int dp83640_ack_interrupt(struct phy_device *phydev)
1261 {
1262 int err = phy_read(phydev, MII_DP83640_MISR);
1263
1264 if (err < 0)
1265 return err;
1266
1267 return 0;
1268 }
1269
1270 static int dp83640_config_intr(struct phy_device *phydev)
1271 {
1272 int micr;
1273 int misr;
1274 int err;
1275
1276 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1277 misr = phy_read(phydev, MII_DP83640_MISR);
1278 if (misr < 0)
1279 return misr;
1280 misr |=
1281 (MII_DP83640_MISR_ANC_INT_EN |
1282 MII_DP83640_MISR_DUP_INT_EN |
1283 MII_DP83640_MISR_SPD_INT_EN |
1284 MII_DP83640_MISR_LINK_INT_EN);
1285 err = phy_write(phydev, MII_DP83640_MISR, misr);
1286 if (err < 0)
1287 return err;
1288
1289 micr = phy_read(phydev, MII_DP83640_MICR);
1290 if (micr < 0)
1291 return micr;
1292 micr |=
1293 (MII_DP83640_MICR_OE |
1294 MII_DP83640_MICR_IE);
1295 return phy_write(phydev, MII_DP83640_MICR, micr);
1296 } else {
1297 micr = phy_read(phydev, MII_DP83640_MICR);
1298 if (micr < 0)
1299 return micr;
1300 micr &=
1301 ~(MII_DP83640_MICR_OE |
1302 MII_DP83640_MICR_IE);
1303 err = phy_write(phydev, MII_DP83640_MICR, micr);
1304 if (err < 0)
1305 return err;
1306
1307 misr = phy_read(phydev, MII_DP83640_MISR);
1308 if (misr < 0)
1309 return misr;
1310 misr &=
1311 ~(MII_DP83640_MISR_ANC_INT_EN |
1312 MII_DP83640_MISR_DUP_INT_EN |
1313 MII_DP83640_MISR_SPD_INT_EN |
1314 MII_DP83640_MISR_LINK_INT_EN);
1315 return phy_write(phydev, MII_DP83640_MISR, misr);
1316 }
1317 }
1318
1319 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1320 {
1321 struct dp83640_private *dp83640 = phydev->priv;
1322 struct hwtstamp_config cfg;
1323 u16 txcfg0, rxcfg0;
1324
1325 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1326 return -EFAULT;
1327
1328 if (cfg.flags) /* reserved for future extensions */
1329 return -EINVAL;
1330
1331 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1332 return -ERANGE;
1333
1334 dp83640->hwts_tx_en = cfg.tx_type;
1335
1336 switch (cfg.rx_filter) {
1337 case HWTSTAMP_FILTER_NONE:
1338 dp83640->hwts_rx_en = 0;
1339 dp83640->layer = 0;
1340 dp83640->version = 0;
1341 break;
1342 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1343 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1344 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1345 dp83640->hwts_rx_en = 1;
1346 dp83640->layer = PTP_CLASS_L4;
1347 dp83640->version = PTP_CLASS_V1;
1348 break;
1349 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1350 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1351 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1352 dp83640->hwts_rx_en = 1;
1353 dp83640->layer = PTP_CLASS_L4;
1354 dp83640->version = PTP_CLASS_V2;
1355 break;
1356 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1357 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1358 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1359 dp83640->hwts_rx_en = 1;
1360 dp83640->layer = PTP_CLASS_L2;
1361 dp83640->version = PTP_CLASS_V2;
1362 break;
1363 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1364 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1365 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1366 dp83640->hwts_rx_en = 1;
1367 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
1368 dp83640->version = PTP_CLASS_V2;
1369 break;
1370 default:
1371 return -ERANGE;
1372 }
1373
1374 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1375 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1376
1377 if (dp83640->layer & PTP_CLASS_L2) {
1378 txcfg0 |= TX_L2_EN;
1379 rxcfg0 |= RX_L2_EN;
1380 }
1381 if (dp83640->layer & PTP_CLASS_L4) {
1382 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1383 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1384 }
1385
1386 if (dp83640->hwts_tx_en)
1387 txcfg0 |= TX_TS_EN;
1388
1389 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1390 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1391
1392 if (dp83640->hwts_rx_en)
1393 rxcfg0 |= RX_TS_EN;
1394
1395 mutex_lock(&dp83640->clock->extreg_lock);
1396
1397 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
1398 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1399
1400 mutex_unlock(&dp83640->clock->extreg_lock);
1401
1402 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1403 }
1404
1405 static void rx_timestamp_work(struct work_struct *work)
1406 {
1407 struct dp83640_private *dp83640 =
1408 container_of(work, struct dp83640_private, ts_work.work);
1409 struct sk_buff *skb;
1410
1411 /* Deliver expired packets. */
1412 while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1413 struct dp83640_skb_info *skb_info;
1414
1415 skb_info = (struct dp83640_skb_info *)skb->cb;
1416 if (!time_after(jiffies, skb_info->tmo)) {
1417 skb_queue_head(&dp83640->rx_queue, skb);
1418 break;
1419 }
1420
1421 netif_rx_ni(skb);
1422 }
1423
1424 if (!skb_queue_empty(&dp83640->rx_queue))
1425 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1426 }
1427
1428 static bool dp83640_rxtstamp(struct phy_device *phydev,
1429 struct sk_buff *skb, int type)
1430 {
1431 struct dp83640_private *dp83640 = phydev->priv;
1432 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1433 struct list_head *this, *next;
1434 struct rxts *rxts;
1435 struct skb_shared_hwtstamps *shhwtstamps = NULL;
1436 unsigned long flags;
1437
1438 if (is_status_frame(skb, type)) {
1439 decode_status_frame(dp83640, skb);
1440 kfree_skb(skb);
1441 return true;
1442 }
1443
1444 if (!dp83640->hwts_rx_en)
1445 return false;
1446
1447 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)
1448 return false;
1449
1450 spin_lock_irqsave(&dp83640->rx_lock, flags);
1451 prune_rx_ts(dp83640);
1452 list_for_each_safe(this, next, &dp83640->rxts) {
1453 rxts = list_entry(this, struct rxts, list);
1454 if (match(skb, type, rxts)) {
1455 shhwtstamps = skb_hwtstamps(skb);
1456 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1457 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1458 list_del_init(&rxts->list);
1459 list_add(&rxts->list, &dp83640->rxpool);
1460 break;
1461 }
1462 }
1463 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1464
1465 if (!shhwtstamps) {
1466 skb_info->ptp_type = type;
1467 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1468 skb_queue_tail(&dp83640->rx_queue, skb);
1469 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1470 } else {
1471 netif_rx_ni(skb);
1472 }
1473
1474 return true;
1475 }
1476
1477 static void dp83640_txtstamp(struct phy_device *phydev,
1478 struct sk_buff *skb, int type)
1479 {
1480 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1481 struct dp83640_private *dp83640 = phydev->priv;
1482
1483 switch (dp83640->hwts_tx_en) {
1484
1485 case HWTSTAMP_TX_ONESTEP_SYNC:
1486 if (is_sync(skb, type)) {
1487 kfree_skb(skb);
1488 return;
1489 }
1490 /* fall through */
1491 case HWTSTAMP_TX_ON:
1492 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1493 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1494 skb_queue_tail(&dp83640->tx_queue, skb);
1495 break;
1496
1497 case HWTSTAMP_TX_OFF:
1498 default:
1499 kfree_skb(skb);
1500 break;
1501 }
1502 }
1503
1504 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info)
1505 {
1506 struct dp83640_private *dp83640 = dev->priv;
1507
1508 info->so_timestamping =
1509 SOF_TIMESTAMPING_TX_HARDWARE |
1510 SOF_TIMESTAMPING_RX_HARDWARE |
1511 SOF_TIMESTAMPING_RAW_HARDWARE;
1512 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1513 info->tx_types =
1514 (1 << HWTSTAMP_TX_OFF) |
1515 (1 << HWTSTAMP_TX_ON) |
1516 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1517 info->rx_filters =
1518 (1 << HWTSTAMP_FILTER_NONE) |
1519 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1520 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1521 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1522 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1523 return 0;
1524 }
1525
1526 static struct phy_driver dp83640_driver = {
1527 .phy_id = DP83640_PHY_ID,
1528 .phy_id_mask = 0xfffffff0,
1529 .name = "NatSemi DP83640",
1530 .features = PHY_BASIC_FEATURES,
1531 .probe = dp83640_probe,
1532 .remove = dp83640_remove,
1533 .soft_reset = dp83640_soft_reset,
1534 .config_init = dp83640_config_init,
1535 .ack_interrupt = dp83640_ack_interrupt,
1536 .config_intr = dp83640_config_intr,
1537 .ts_info = dp83640_ts_info,
1538 .hwtstamp = dp83640_hwtstamp,
1539 .rxtstamp = dp83640_rxtstamp,
1540 .txtstamp = dp83640_txtstamp,
1541 };
1542
1543 static int __init dp83640_init(void)
1544 {
1545 return phy_driver_register(&dp83640_driver, THIS_MODULE);
1546 }
1547
1548 static void __exit dp83640_exit(void)
1549 {
1550 dp83640_free_clocks();
1551 phy_driver_unregister(&dp83640_driver);
1552 }
1553
1554 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1555 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1556 MODULE_LICENSE("GPL");
1557
1558 module_init(dp83640_init);
1559 module_exit(dp83640_exit);
1560
1561 static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1562 { DP83640_PHY_ID, 0xfffffff0 },
1563 { }
1564 };
1565
1566 MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
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